1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 40 #ifdef CONFIG_X86 41 /* for snoop control */ 42 #include <asm/pgtable.h> 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* Define VIA HD Audio Device ID*/ 90 #define VIA_HDAC_DEVICE_ID 0x3288 91 92 /* max number of SDs */ 93 /* ICH, ATI and VIA have 4 playback and 4 capture */ 94 #define ICH6_NUM_CAPTURE 4 95 #define ICH6_NUM_PLAYBACK 4 96 97 /* ULI has 6 playback and 5 capture */ 98 #define ULI_NUM_CAPTURE 5 99 #define ULI_NUM_PLAYBACK 6 100 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 102 #define ATIHDMI_NUM_CAPTURE 0 103 #define ATIHDMI_NUM_PLAYBACK 8 104 105 /* TERA has 4 playback and 3 capture */ 106 #define TERA_NUM_CAPTURE 3 107 #define TERA_NUM_PLAYBACK 4 108 109 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113 static char *model[SNDRV_CARDS]; 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117 static int probe_only[SNDRV_CARDS]; 118 static int jackpoll_ms[SNDRV_CARDS]; 119 static int single_cmd = -1; 120 static int enable_msi = -1; 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER 122 static char *patch[SNDRV_CARDS]; 123 #endif 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127 #endif 128 static bool dsp_driver = 1; 129 130 module_param_array(index, int, NULL, 0444); 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132 module_param_array(id, charp, NULL, 0444); 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134 module_param_array(enable, bool, NULL, 0444); 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136 module_param_array(model, charp, NULL, 0444); 137 MODULE_PARM_DESC(model, "Use the given board model."); 138 module_param_array(position_fix, int, NULL, 0444); 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141 module_param_array(bdl_pos_adj, int, NULL, 0644); 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143 module_param_array(probe_mask, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145 module_param_array(probe_only, int, NULL, 0444); 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147 module_param_array(jackpoll_ms, int, NULL, 0444); 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149 module_param(single_cmd, bint, 0444); 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152 module_param(enable_msi, bint, 0444); 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER 155 module_param_array(patch, charp, NULL, 0444); 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157 #endif 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP 159 module_param_array(beep_mode, bool, NULL, 0444); 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162 #endif 163 module_param(dsp_driver, bool, 0444); 164 MODULE_PARM_DESC(dsp_driver, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1)"); 166 167 #ifdef CONFIG_PM 168 static int param_set_xint(const char *val, const struct kernel_param *kp); 169 static const struct kernel_param_ops param_ops_xint = { 170 .set = param_set_xint, 171 .get = param_get_int, 172 }; 173 #define param_check_xint param_check_int 174 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 176 module_param(power_save, xint, 0644); 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 178 "(in second, 0 = disable)."); 179 180 static bool pm_blacklist = true; 181 module_param(pm_blacklist, bool, 0644); 182 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 183 184 /* reset the HD-audio controller in power save mode. 185 * this may give more power-saving, but will take longer time to 186 * wake up. 187 */ 188 static bool power_save_controller = 1; 189 module_param(power_save_controller, bool, 0644); 190 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 191 #else 192 #define power_save 0 193 #endif /* CONFIG_PM */ 194 195 static int align_buffer_size = -1; 196 module_param(align_buffer_size, bint, 0644); 197 MODULE_PARM_DESC(align_buffer_size, 198 "Force buffer and period sizes to be multiple of 128 bytes."); 199 200 #ifdef CONFIG_X86 201 static int hda_snoop = -1; 202 module_param_named(snoop, hda_snoop, bint, 0444); 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 204 #else 205 #define hda_snoop true 206 #endif 207 208 209 MODULE_LICENSE("GPL"); 210 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 211 "{Intel, ICH6M}," 212 "{Intel, ICH7}," 213 "{Intel, ESB2}," 214 "{Intel, ICH8}," 215 "{Intel, ICH9}," 216 "{Intel, ICH10}," 217 "{Intel, PCH}," 218 "{Intel, CPT}," 219 "{Intel, PPT}," 220 "{Intel, LPT}," 221 "{Intel, LPT_LP}," 222 "{Intel, WPT_LP}," 223 "{Intel, SPT}," 224 "{Intel, SPT_LP}," 225 "{Intel, HPT}," 226 "{Intel, PBG}," 227 "{Intel, SCH}," 228 "{ATI, SB450}," 229 "{ATI, SB600}," 230 "{ATI, RS600}," 231 "{ATI, RS690}," 232 "{ATI, RS780}," 233 "{ATI, R600}," 234 "{ATI, RV630}," 235 "{ATI, RV610}," 236 "{ATI, RV670}," 237 "{ATI, RV635}," 238 "{ATI, RV620}," 239 "{ATI, RV770}," 240 "{VIA, VT8251}," 241 "{VIA, VT8237A}," 242 "{SiS, SIS966}," 243 "{ULI, M5461}}"); 244 MODULE_DESCRIPTION("Intel HDA driver"); 245 246 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 247 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 248 #define SUPPORT_VGA_SWITCHEROO 249 #endif 250 #endif 251 252 253 /* 254 */ 255 256 /* driver types */ 257 enum { 258 AZX_DRIVER_ICH, 259 AZX_DRIVER_PCH, 260 AZX_DRIVER_SCH, 261 AZX_DRIVER_SKL, 262 AZX_DRIVER_HDMI, 263 AZX_DRIVER_ATI, 264 AZX_DRIVER_ATIHDMI, 265 AZX_DRIVER_ATIHDMI_NS, 266 AZX_DRIVER_VIA, 267 AZX_DRIVER_SIS, 268 AZX_DRIVER_ULI, 269 AZX_DRIVER_NVIDIA, 270 AZX_DRIVER_TERA, 271 AZX_DRIVER_CTX, 272 AZX_DRIVER_CTHDA, 273 AZX_DRIVER_CMEDIA, 274 AZX_DRIVER_ZHAOXIN, 275 AZX_DRIVER_GENERIC, 276 AZX_NUM_DRIVERS, /* keep this as last entry */ 277 }; 278 279 #define azx_get_snoop_type(chip) \ 280 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 281 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 282 283 /* quirks for old Intel chipsets */ 284 #define AZX_DCAPS_INTEL_ICH \ 285 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\ 286 AZX_DCAPS_SYNC_WRITE) 287 288 /* quirks for Intel PCH */ 289 #define AZX_DCAPS_INTEL_PCH_BASE \ 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 292 293 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 294 #define AZX_DCAPS_INTEL_PCH_NOPM \ 295 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 296 297 /* PCH for HSW/BDW; with runtime PM */ 298 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 299 #define AZX_DCAPS_INTEL_PCH \ 300 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 301 302 /* HSW HDMI */ 303 #define AZX_DCAPS_INTEL_HASWELL \ 304 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 305 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 306 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 307 308 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 309 #define AZX_DCAPS_INTEL_BROADWELL \ 310 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 311 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 312 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 313 314 #define AZX_DCAPS_INTEL_BAYTRAIL \ 315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 316 317 #define AZX_DCAPS_INTEL_BRASWELL \ 318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 319 AZX_DCAPS_I915_COMPONENT) 320 321 #define AZX_DCAPS_INTEL_SKYLAKE \ 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 323 AZX_DCAPS_SYNC_WRITE |\ 324 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 325 326 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 327 328 /* quirks for ATI SB / AMD Hudson */ 329 #define AZX_DCAPS_PRESET_ATI_SB \ 330 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 331 AZX_DCAPS_SNOOP_TYPE(ATI)) 332 333 /* quirks for ATI/AMD HDMI */ 334 #define AZX_DCAPS_PRESET_ATI_HDMI \ 335 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 336 AZX_DCAPS_NO_MSI64) 337 338 /* quirks for ATI HDMI with snoop off */ 339 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 340 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 341 342 /* quirks for AMD SB */ 343 #define AZX_DCAPS_PRESET_AMD_SB \ 344 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\ 345 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) 346 347 /* quirks for Nvidia */ 348 #define AZX_DCAPS_PRESET_NVIDIA \ 349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 350 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 351 352 #define AZX_DCAPS_PRESET_CTHDA \ 353 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 354 AZX_DCAPS_NO_64BIT |\ 355 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 356 357 /* 358 * vga_switcheroo support 359 */ 360 #ifdef SUPPORT_VGA_SWITCHEROO 361 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 362 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 363 #else 364 #define use_vga_switcheroo(chip) 0 365 #define needs_eld_notify_link(chip) false 366 #endif 367 368 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 369 ((pci)->device == 0x0c0c) || \ 370 ((pci)->device == 0x0d0c) || \ 371 ((pci)->device == 0x160c)) 372 373 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 374 375 static char *driver_short_names[] = { 376 [AZX_DRIVER_ICH] = "HDA Intel", 377 [AZX_DRIVER_PCH] = "HDA Intel PCH", 378 [AZX_DRIVER_SCH] = "HDA Intel MID", 379 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 380 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 381 [AZX_DRIVER_ATI] = "HDA ATI SB", 382 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 383 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 384 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 385 [AZX_DRIVER_SIS] = "HDA SIS966", 386 [AZX_DRIVER_ULI] = "HDA ULI M5461", 387 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 388 [AZX_DRIVER_TERA] = "HDA Teradici", 389 [AZX_DRIVER_CTX] = "HDA Creative", 390 [AZX_DRIVER_CTHDA] = "HDA Creative", 391 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 392 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 393 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 394 }; 395 396 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 397 static void set_default_power_save(struct azx *chip); 398 399 /* 400 * initialize the PCI registers 401 */ 402 /* update bits in a PCI register byte */ 403 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 404 unsigned char mask, unsigned char val) 405 { 406 unsigned char data; 407 408 pci_read_config_byte(pci, reg, &data); 409 data &= ~mask; 410 data |= (val & mask); 411 pci_write_config_byte(pci, reg, data); 412 } 413 414 static void azx_init_pci(struct azx *chip) 415 { 416 int snoop_type = azx_get_snoop_type(chip); 417 418 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 419 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 420 * Ensuring these bits are 0 clears playback static on some HD Audio 421 * codecs. 422 * The PCI register TCSEL is defined in the Intel manuals. 423 */ 424 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 425 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 426 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 427 } 428 429 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 430 * we need to enable snoop. 431 */ 432 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 433 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 434 azx_snoop(chip)); 435 update_pci_byte(chip->pci, 436 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 437 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 438 } 439 440 /* For NVIDIA HDA, enable snoop */ 441 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 442 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 443 azx_snoop(chip)); 444 update_pci_byte(chip->pci, 445 NVIDIA_HDA_TRANSREG_ADDR, 446 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 447 update_pci_byte(chip->pci, 448 NVIDIA_HDA_ISTRM_COH, 449 0x01, NVIDIA_HDA_ENABLE_COHBIT); 450 update_pci_byte(chip->pci, 451 NVIDIA_HDA_OSTRM_COH, 452 0x01, NVIDIA_HDA_ENABLE_COHBIT); 453 } 454 455 /* Enable SCH/PCH snoop if needed */ 456 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 457 unsigned short snoop; 458 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 459 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 460 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 461 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 462 if (!azx_snoop(chip)) 463 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 464 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 465 pci_read_config_word(chip->pci, 466 INTEL_SCH_HDA_DEVC, &snoop); 467 } 468 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 469 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 470 "Disabled" : "Enabled"); 471 } 472 } 473 474 /* 475 * In BXT-P A0, HD-Audio DMA requests is later than expected, 476 * and makes an audio stream sensitive to system latencies when 477 * 24/32 bits are playing. 478 * Adjusting threshold of DMA fifo to force the DMA request 479 * sooner to improve latency tolerance at the expense of power. 480 */ 481 static void bxt_reduce_dma_latency(struct azx *chip) 482 { 483 u32 val; 484 485 val = azx_readl(chip, VS_EM4L); 486 val &= (0x3 << 20); 487 azx_writel(chip, VS_EM4L, val); 488 } 489 490 /* 491 * ML_LCAP bits: 492 * bit 0: 6 MHz Supported 493 * bit 1: 12 MHz Supported 494 * bit 2: 24 MHz Supported 495 * bit 3: 48 MHz Supported 496 * bit 4: 96 MHz Supported 497 * bit 5: 192 MHz Supported 498 */ 499 static int intel_get_lctl_scf(struct azx *chip) 500 { 501 struct hdac_bus *bus = azx_bus(chip); 502 static int preferred_bits[] = { 2, 3, 1, 4, 5 }; 503 u32 val, t; 504 int i; 505 506 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 507 508 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 509 t = preferred_bits[i]; 510 if (val & (1 << t)) 511 return t; 512 } 513 514 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 515 return 0; 516 } 517 518 static int intel_ml_lctl_set_power(struct azx *chip, int state) 519 { 520 struct hdac_bus *bus = azx_bus(chip); 521 u32 val; 522 int timeout; 523 524 /* 525 * the codecs are sharing the first link setting by default 526 * If other links are enabled for stream, they need similar fix 527 */ 528 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 529 val &= ~AZX_MLCTL_SPA; 530 val |= state << AZX_MLCTL_SPA_SHIFT; 531 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 532 /* wait for CPA */ 533 timeout = 50; 534 while (timeout) { 535 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 536 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 537 return 0; 538 timeout--; 539 udelay(10); 540 } 541 542 return -1; 543 } 544 545 static void intel_init_lctl(struct azx *chip) 546 { 547 struct hdac_bus *bus = azx_bus(chip); 548 u32 val; 549 int ret; 550 551 /* 0. check lctl register value is correct or not */ 552 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 553 /* if SCF is already set, let's use it */ 554 if ((val & ML_LCTL_SCF_MASK) != 0) 555 return; 556 557 /* 558 * Before operating on SPA, CPA must match SPA. 559 * Any deviation may result in undefined behavior. 560 */ 561 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 562 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 563 return; 564 565 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 566 ret = intel_ml_lctl_set_power(chip, 0); 567 udelay(100); 568 if (ret) 569 goto set_spa; 570 571 /* 2. update SCF to select a properly audio clock*/ 572 val &= ~ML_LCTL_SCF_MASK; 573 val |= intel_get_lctl_scf(chip); 574 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 575 576 set_spa: 577 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 578 intel_ml_lctl_set_power(chip, 1); 579 udelay(100); 580 } 581 582 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 583 { 584 struct hdac_bus *bus = azx_bus(chip); 585 struct pci_dev *pci = chip->pci; 586 u32 val; 587 588 snd_hdac_set_codec_wakeup(bus, true); 589 if (chip->driver_type == AZX_DRIVER_SKL) { 590 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 591 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 592 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 593 } 594 azx_init_chip(chip, full_reset); 595 if (chip->driver_type == AZX_DRIVER_SKL) { 596 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 597 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 598 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 599 } 600 601 snd_hdac_set_codec_wakeup(bus, false); 602 603 /* reduce dma latency to avoid noise */ 604 if (IS_BXT(pci)) 605 bxt_reduce_dma_latency(chip); 606 607 if (bus->mlcap != NULL) 608 intel_init_lctl(chip); 609 } 610 611 /* calculate runtime delay from LPIB */ 612 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 613 unsigned int pos) 614 { 615 struct snd_pcm_substream *substream = azx_dev->core.substream; 616 int stream = substream->stream; 617 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 618 int delay; 619 620 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 621 delay = pos - lpib_pos; 622 else 623 delay = lpib_pos - pos; 624 if (delay < 0) { 625 if (delay >= azx_dev->core.delay_negative_threshold) 626 delay = 0; 627 else 628 delay += azx_dev->core.bufsize; 629 } 630 631 if (delay >= azx_dev->core.period_bytes) { 632 dev_info(chip->card->dev, 633 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 634 delay, azx_dev->core.period_bytes); 635 delay = 0; 636 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 637 chip->get_delay[stream] = NULL; 638 } 639 640 return bytes_to_frames(substream->runtime, delay); 641 } 642 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 644 645 /* called from IRQ */ 646 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 647 { 648 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 649 int ok; 650 651 ok = azx_position_ok(chip, azx_dev); 652 if (ok == 1) { 653 azx_dev->irq_pending = 0; 654 return ok; 655 } else if (ok == 0) { 656 /* bogus IRQ, process it later */ 657 azx_dev->irq_pending = 1; 658 schedule_work(&hda->irq_pending_work); 659 } 660 return 0; 661 } 662 663 #define display_power(chip, enable) \ 664 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 665 666 /* 667 * Check whether the current DMA position is acceptable for updating 668 * periods. Returns non-zero if it's OK. 669 * 670 * Many HD-audio controllers appear pretty inaccurate about 671 * the update-IRQ timing. The IRQ is issued before actually the 672 * data is processed. So, we need to process it afterwords in a 673 * workqueue. 674 */ 675 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 676 { 677 struct snd_pcm_substream *substream = azx_dev->core.substream; 678 int stream = substream->stream; 679 u32 wallclk; 680 unsigned int pos; 681 682 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 683 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 684 return -1; /* bogus (too early) interrupt */ 685 686 if (chip->get_position[stream]) 687 pos = chip->get_position[stream](chip, azx_dev); 688 else { /* use the position buffer as default */ 689 pos = azx_get_pos_posbuf(chip, azx_dev); 690 if (!pos || pos == (u32)-1) { 691 dev_info(chip->card->dev, 692 "Invalid position buffer, using LPIB read method instead.\n"); 693 chip->get_position[stream] = azx_get_pos_lpib; 694 if (chip->get_position[0] == azx_get_pos_lpib && 695 chip->get_position[1] == azx_get_pos_lpib) 696 azx_bus(chip)->use_posbuf = false; 697 pos = azx_get_pos_lpib(chip, azx_dev); 698 chip->get_delay[stream] = NULL; 699 } else { 700 chip->get_position[stream] = azx_get_pos_posbuf; 701 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 702 chip->get_delay[stream] = azx_get_delay_from_lpib; 703 } 704 } 705 706 if (pos >= azx_dev->core.bufsize) 707 pos = 0; 708 709 if (WARN_ONCE(!azx_dev->core.period_bytes, 710 "hda-intel: zero azx_dev->period_bytes")) 711 return -1; /* this shouldn't happen! */ 712 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 713 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 714 /* NG - it's below the first next period boundary */ 715 return chip->bdl_pos_adj ? 0 : -1; 716 azx_dev->core.start_wallclk += wallclk; 717 return 1; /* OK, it's fine */ 718 } 719 720 /* 721 * The work for pending PCM period updates. 722 */ 723 static void azx_irq_pending_work(struct work_struct *work) 724 { 725 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 726 struct azx *chip = &hda->chip; 727 struct hdac_bus *bus = azx_bus(chip); 728 struct hdac_stream *s; 729 int pending, ok; 730 731 if (!hda->irq_pending_warned) { 732 dev_info(chip->card->dev, 733 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 734 chip->card->number); 735 hda->irq_pending_warned = 1; 736 } 737 738 for (;;) { 739 pending = 0; 740 spin_lock_irq(&bus->reg_lock); 741 list_for_each_entry(s, &bus->stream_list, list) { 742 struct azx_dev *azx_dev = stream_to_azx_dev(s); 743 if (!azx_dev->irq_pending || 744 !s->substream || 745 !s->running) 746 continue; 747 ok = azx_position_ok(chip, azx_dev); 748 if (ok > 0) { 749 azx_dev->irq_pending = 0; 750 spin_unlock(&bus->reg_lock); 751 snd_pcm_period_elapsed(s->substream); 752 spin_lock(&bus->reg_lock); 753 } else if (ok < 0) { 754 pending = 0; /* too early */ 755 } else 756 pending++; 757 } 758 spin_unlock_irq(&bus->reg_lock); 759 if (!pending) 760 return; 761 msleep(1); 762 } 763 } 764 765 /* clear irq_pending flags and assure no on-going workq */ 766 static void azx_clear_irq_pending(struct azx *chip) 767 { 768 struct hdac_bus *bus = azx_bus(chip); 769 struct hdac_stream *s; 770 771 spin_lock_irq(&bus->reg_lock); 772 list_for_each_entry(s, &bus->stream_list, list) { 773 struct azx_dev *azx_dev = stream_to_azx_dev(s); 774 azx_dev->irq_pending = 0; 775 } 776 spin_unlock_irq(&bus->reg_lock); 777 } 778 779 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 780 { 781 struct hdac_bus *bus = azx_bus(chip); 782 783 if (request_irq(chip->pci->irq, azx_interrupt, 784 chip->msi ? 0 : IRQF_SHARED, 785 chip->card->irq_descr, chip)) { 786 dev_err(chip->card->dev, 787 "unable to grab IRQ %d, disabling device\n", 788 chip->pci->irq); 789 if (do_disconnect) 790 snd_card_disconnect(chip->card); 791 return -1; 792 } 793 bus->irq = chip->pci->irq; 794 pci_intx(chip->pci, !chip->msi); 795 return 0; 796 } 797 798 /* get the current DMA position with correction on VIA chips */ 799 static unsigned int azx_via_get_position(struct azx *chip, 800 struct azx_dev *azx_dev) 801 { 802 unsigned int link_pos, mini_pos, bound_pos; 803 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 804 unsigned int fifo_size; 805 806 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 807 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 808 /* Playback, no problem using link position */ 809 return link_pos; 810 } 811 812 /* Capture */ 813 /* For new chipset, 814 * use mod to get the DMA position just like old chipset 815 */ 816 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 817 mod_dma_pos %= azx_dev->core.period_bytes; 818 819 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 820 821 if (azx_dev->insufficient) { 822 /* Link position never gather than FIFO size */ 823 if (link_pos <= fifo_size) 824 return 0; 825 826 azx_dev->insufficient = 0; 827 } 828 829 if (link_pos <= fifo_size) 830 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 831 else 832 mini_pos = link_pos - fifo_size; 833 834 /* Find nearest previous boudary */ 835 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 836 mod_link_pos = link_pos % azx_dev->core.period_bytes; 837 if (mod_link_pos >= fifo_size) 838 bound_pos = link_pos - mod_link_pos; 839 else if (mod_dma_pos >= mod_mini_pos) 840 bound_pos = mini_pos - mod_mini_pos; 841 else { 842 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 843 if (bound_pos >= azx_dev->core.bufsize) 844 bound_pos = 0; 845 } 846 847 /* Calculate real DMA position we want */ 848 return bound_pos + mod_dma_pos; 849 } 850 851 #define AMD_FIFO_SIZE 32 852 853 /* get the current DMA position with FIFO size correction */ 854 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 855 { 856 struct snd_pcm_substream *substream = azx_dev->core.substream; 857 struct snd_pcm_runtime *runtime = substream->runtime; 858 unsigned int pos, delay; 859 860 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 861 if (!runtime) 862 return pos; 863 864 runtime->delay = AMD_FIFO_SIZE; 865 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 866 if (azx_dev->insufficient) { 867 if (pos < delay) { 868 delay = pos; 869 runtime->delay = bytes_to_frames(runtime, pos); 870 } else { 871 azx_dev->insufficient = 0; 872 } 873 } 874 875 /* correct the DMA position for capture stream */ 876 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 877 if (pos < delay) 878 pos += azx_dev->core.bufsize; 879 pos -= delay; 880 } 881 882 return pos; 883 } 884 885 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 886 unsigned int pos) 887 { 888 struct snd_pcm_substream *substream = azx_dev->core.substream; 889 890 /* just read back the calculated value in the above */ 891 return substream->runtime->delay; 892 } 893 894 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 895 struct azx_dev *azx_dev) 896 { 897 return _snd_hdac_chip_readl(azx_bus(chip), 898 AZX_REG_VS_SDXDPIB_XBASE + 899 (AZX_REG_VS_SDXDPIB_XINTERVAL * 900 azx_dev->core.index)); 901 } 902 903 /* get the current DMA position with correction on SKL+ chips */ 904 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 905 { 906 /* DPIB register gives a more accurate position for playback */ 907 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 908 return azx_skl_get_dpib_pos(chip, azx_dev); 909 910 /* For capture, we need to read posbuf, but it requires a delay 911 * for the possible boundary overlap; the read of DPIB fetches the 912 * actual posbuf 913 */ 914 udelay(20); 915 azx_skl_get_dpib_pos(chip, azx_dev); 916 return azx_get_pos_posbuf(chip, azx_dev); 917 } 918 919 #ifdef CONFIG_PM 920 static DEFINE_MUTEX(card_list_lock); 921 static LIST_HEAD(card_list); 922 923 static void azx_add_card_list(struct azx *chip) 924 { 925 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 926 mutex_lock(&card_list_lock); 927 list_add(&hda->list, &card_list); 928 mutex_unlock(&card_list_lock); 929 } 930 931 static void azx_del_card_list(struct azx *chip) 932 { 933 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 934 mutex_lock(&card_list_lock); 935 list_del_init(&hda->list); 936 mutex_unlock(&card_list_lock); 937 } 938 939 /* trigger power-save check at writing parameter */ 940 static int param_set_xint(const char *val, const struct kernel_param *kp) 941 { 942 struct hda_intel *hda; 943 struct azx *chip; 944 int prev = power_save; 945 int ret = param_set_int(val, kp); 946 947 if (ret || prev == power_save) 948 return ret; 949 950 mutex_lock(&card_list_lock); 951 list_for_each_entry(hda, &card_list, list) { 952 chip = &hda->chip; 953 if (!hda->probe_continued || chip->disabled) 954 continue; 955 snd_hda_set_power_save(&chip->bus, power_save * 1000); 956 } 957 mutex_unlock(&card_list_lock); 958 return 0; 959 } 960 961 /* 962 * power management 963 */ 964 static bool azx_is_pm_ready(struct snd_card *card) 965 { 966 struct azx *chip; 967 struct hda_intel *hda; 968 969 if (!card) 970 return false; 971 chip = card->private_data; 972 hda = container_of(chip, struct hda_intel, chip); 973 if (chip->disabled || hda->init_failed || !chip->running) 974 return false; 975 return true; 976 } 977 978 static void __azx_runtime_suspend(struct azx *chip) 979 { 980 azx_stop_chip(chip); 981 azx_enter_link_reset(chip); 982 azx_clear_irq_pending(chip); 983 display_power(chip, false); 984 } 985 986 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 987 { 988 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 989 struct hdac_bus *bus = azx_bus(chip); 990 struct hda_codec *codec; 991 int status; 992 993 display_power(chip, true); 994 if (hda->need_i915_power) 995 snd_hdac_i915_set_bclk(bus); 996 997 /* Read STATESTS before controller reset */ 998 status = azx_readw(chip, STATESTS); 999 1000 azx_init_pci(chip); 1001 hda_intel_init_chip(chip, true); 1002 1003 if (status && from_rt) { 1004 list_for_each_codec(codec, &chip->bus) 1005 if (status & (1 << codec->addr)) 1006 schedule_delayed_work(&codec->jackpoll_work, 1007 codec->jackpoll_interval); 1008 } 1009 1010 /* power down again for link-controlled chips */ 1011 if (!hda->need_i915_power) 1012 display_power(chip, false); 1013 } 1014 1015 #ifdef CONFIG_PM_SLEEP 1016 static int azx_suspend(struct device *dev) 1017 { 1018 struct snd_card *card = dev_get_drvdata(dev); 1019 struct azx *chip; 1020 struct hdac_bus *bus; 1021 1022 if (!azx_is_pm_ready(card)) 1023 return 0; 1024 1025 chip = card->private_data; 1026 bus = azx_bus(chip); 1027 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1028 __azx_runtime_suspend(chip); 1029 if (bus->irq >= 0) { 1030 free_irq(bus->irq, chip); 1031 bus->irq = -1; 1032 } 1033 1034 if (chip->msi) 1035 pci_disable_msi(chip->pci); 1036 1037 trace_azx_suspend(chip); 1038 return 0; 1039 } 1040 1041 static int azx_resume(struct device *dev) 1042 { 1043 struct snd_card *card = dev_get_drvdata(dev); 1044 struct azx *chip; 1045 1046 if (!azx_is_pm_ready(card)) 1047 return 0; 1048 1049 chip = card->private_data; 1050 if (chip->msi) 1051 if (pci_enable_msi(chip->pci) < 0) 1052 chip->msi = 0; 1053 if (azx_acquire_irq(chip, 1) < 0) 1054 return -EIO; 1055 __azx_runtime_resume(chip, false); 1056 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1057 1058 trace_azx_resume(chip); 1059 return 0; 1060 } 1061 1062 /* put codec down to D3 at hibernation for Intel SKL+; 1063 * otherwise BIOS may still access the codec and screw up the driver 1064 */ 1065 static int azx_freeze_noirq(struct device *dev) 1066 { 1067 struct snd_card *card = dev_get_drvdata(dev); 1068 struct azx *chip = card->private_data; 1069 struct pci_dev *pci = to_pci_dev(dev); 1070 1071 if (chip->driver_type == AZX_DRIVER_SKL) 1072 pci_set_power_state(pci, PCI_D3hot); 1073 1074 return 0; 1075 } 1076 1077 static int azx_thaw_noirq(struct device *dev) 1078 { 1079 struct snd_card *card = dev_get_drvdata(dev); 1080 struct azx *chip = card->private_data; 1081 struct pci_dev *pci = to_pci_dev(dev); 1082 1083 if (chip->driver_type == AZX_DRIVER_SKL) 1084 pci_set_power_state(pci, PCI_D0); 1085 1086 return 0; 1087 } 1088 #endif /* CONFIG_PM_SLEEP */ 1089 1090 static int azx_runtime_suspend(struct device *dev) 1091 { 1092 struct snd_card *card = dev_get_drvdata(dev); 1093 struct azx *chip; 1094 1095 if (!azx_is_pm_ready(card)) 1096 return 0; 1097 chip = card->private_data; 1098 if (!azx_has_pm_runtime(chip)) 1099 return 0; 1100 1101 /* enable controller wake up event */ 1102 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1103 STATESTS_INT_MASK); 1104 1105 __azx_runtime_suspend(chip); 1106 trace_azx_runtime_suspend(chip); 1107 return 0; 1108 } 1109 1110 static int azx_runtime_resume(struct device *dev) 1111 { 1112 struct snd_card *card = dev_get_drvdata(dev); 1113 struct azx *chip; 1114 1115 if (!azx_is_pm_ready(card)) 1116 return 0; 1117 chip = card->private_data; 1118 if (!azx_has_pm_runtime(chip)) 1119 return 0; 1120 __azx_runtime_resume(chip, true); 1121 1122 /* disable controller Wake Up event*/ 1123 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1124 ~STATESTS_INT_MASK); 1125 1126 trace_azx_runtime_resume(chip); 1127 return 0; 1128 } 1129 1130 static int azx_runtime_idle(struct device *dev) 1131 { 1132 struct snd_card *card = dev_get_drvdata(dev); 1133 struct azx *chip; 1134 struct hda_intel *hda; 1135 1136 if (!card) 1137 return 0; 1138 1139 chip = card->private_data; 1140 hda = container_of(chip, struct hda_intel, chip); 1141 if (chip->disabled || hda->init_failed) 1142 return 0; 1143 1144 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1145 azx_bus(chip)->codec_powered || !chip->running) 1146 return -EBUSY; 1147 1148 /* ELD notification gets broken when HD-audio bus is off */ 1149 if (needs_eld_notify_link(chip)) 1150 return -EBUSY; 1151 1152 return 0; 1153 } 1154 1155 static const struct dev_pm_ops azx_pm = { 1156 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1157 #ifdef CONFIG_PM_SLEEP 1158 .freeze_noirq = azx_freeze_noirq, 1159 .thaw_noirq = azx_thaw_noirq, 1160 #endif 1161 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1162 }; 1163 1164 #define AZX_PM_OPS &azx_pm 1165 #else 1166 #define azx_add_card_list(chip) /* NOP */ 1167 #define azx_del_card_list(chip) /* NOP */ 1168 #define AZX_PM_OPS NULL 1169 #endif /* CONFIG_PM */ 1170 1171 1172 static int azx_probe_continue(struct azx *chip); 1173 1174 #ifdef SUPPORT_VGA_SWITCHEROO 1175 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1176 1177 static void azx_vs_set_state(struct pci_dev *pci, 1178 enum vga_switcheroo_state state) 1179 { 1180 struct snd_card *card = pci_get_drvdata(pci); 1181 struct azx *chip = card->private_data; 1182 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1183 struct hda_codec *codec; 1184 bool disabled; 1185 1186 wait_for_completion(&hda->probe_wait); 1187 if (hda->init_failed) 1188 return; 1189 1190 disabled = (state == VGA_SWITCHEROO_OFF); 1191 if (chip->disabled == disabled) 1192 return; 1193 1194 if (!hda->probe_continued) { 1195 chip->disabled = disabled; 1196 if (!disabled) { 1197 dev_info(chip->card->dev, 1198 "Start delayed initialization\n"); 1199 if (azx_probe_continue(chip) < 0) { 1200 dev_err(chip->card->dev, "initialization error\n"); 1201 hda->init_failed = true; 1202 } 1203 } 1204 } else { 1205 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1206 disabled ? "Disabling" : "Enabling"); 1207 if (disabled) { 1208 list_for_each_codec(codec, &chip->bus) { 1209 pm_runtime_suspend(hda_codec_dev(codec)); 1210 pm_runtime_disable(hda_codec_dev(codec)); 1211 } 1212 pm_runtime_suspend(card->dev); 1213 pm_runtime_disable(card->dev); 1214 /* when we get suspended by vga_switcheroo we end up in D3cold, 1215 * however we have no ACPI handle, so pci/acpi can't put us there, 1216 * put ourselves there */ 1217 pci->current_state = PCI_D3cold; 1218 chip->disabled = true; 1219 if (snd_hda_lock_devices(&chip->bus)) 1220 dev_warn(chip->card->dev, 1221 "Cannot lock devices!\n"); 1222 } else { 1223 snd_hda_unlock_devices(&chip->bus); 1224 chip->disabled = false; 1225 pm_runtime_enable(card->dev); 1226 list_for_each_codec(codec, &chip->bus) { 1227 pm_runtime_enable(hda_codec_dev(codec)); 1228 pm_runtime_resume(hda_codec_dev(codec)); 1229 } 1230 } 1231 } 1232 } 1233 1234 static bool azx_vs_can_switch(struct pci_dev *pci) 1235 { 1236 struct snd_card *card = pci_get_drvdata(pci); 1237 struct azx *chip = card->private_data; 1238 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1239 1240 wait_for_completion(&hda->probe_wait); 1241 if (hda->init_failed) 1242 return false; 1243 if (chip->disabled || !hda->probe_continued) 1244 return true; 1245 if (snd_hda_lock_devices(&chip->bus)) 1246 return false; 1247 snd_hda_unlock_devices(&chip->bus); 1248 return true; 1249 } 1250 1251 /* 1252 * The discrete GPU cannot power down unless the HDA controller runtime 1253 * suspends, so activate runtime PM on codecs even if power_save == 0. 1254 */ 1255 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1256 { 1257 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1258 struct hda_codec *codec; 1259 1260 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1261 list_for_each_codec(codec, &chip->bus) 1262 codec->auto_runtime_pm = 1; 1263 /* reset the power save setup */ 1264 if (chip->running) 1265 set_default_power_save(chip); 1266 } 1267 } 1268 1269 static void azx_vs_gpu_bound(struct pci_dev *pci, 1270 enum vga_switcheroo_client_id client_id) 1271 { 1272 struct snd_card *card = pci_get_drvdata(pci); 1273 struct azx *chip = card->private_data; 1274 1275 if (client_id == VGA_SWITCHEROO_DIS) 1276 chip->bus.keep_power = 0; 1277 setup_vga_switcheroo_runtime_pm(chip); 1278 } 1279 1280 static void init_vga_switcheroo(struct azx *chip) 1281 { 1282 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1283 struct pci_dev *p = get_bound_vga(chip->pci); 1284 struct pci_dev *parent; 1285 if (p) { 1286 dev_info(chip->card->dev, 1287 "Handle vga_switcheroo audio client\n"); 1288 hda->use_vga_switcheroo = 1; 1289 1290 /* cleared in either gpu_bound op or codec probe, or when its 1291 * upstream port has _PR3 (i.e. dGPU). 1292 */ 1293 parent = pci_upstream_bridge(p); 1294 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1295 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1296 pci_dev_put(p); 1297 } 1298 } 1299 1300 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1301 .set_gpu_state = azx_vs_set_state, 1302 .can_switch = azx_vs_can_switch, 1303 .gpu_bound = azx_vs_gpu_bound, 1304 }; 1305 1306 static int register_vga_switcheroo(struct azx *chip) 1307 { 1308 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1309 struct pci_dev *p; 1310 int err; 1311 1312 if (!hda->use_vga_switcheroo) 1313 return 0; 1314 1315 p = get_bound_vga(chip->pci); 1316 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1317 pci_dev_put(p); 1318 1319 if (err < 0) 1320 return err; 1321 hda->vga_switcheroo_registered = 1; 1322 1323 return 0; 1324 } 1325 #else 1326 #define init_vga_switcheroo(chip) /* NOP */ 1327 #define register_vga_switcheroo(chip) 0 1328 #define check_hdmi_disabled(pci) false 1329 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1330 #endif /* SUPPORT_VGA_SWITCHER */ 1331 1332 /* 1333 * destructor 1334 */ 1335 static int azx_free(struct azx *chip) 1336 { 1337 struct pci_dev *pci = chip->pci; 1338 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1339 struct hdac_bus *bus = azx_bus(chip); 1340 1341 if (azx_has_pm_runtime(chip) && chip->running) 1342 pm_runtime_get_noresume(&pci->dev); 1343 chip->running = 0; 1344 1345 azx_del_card_list(chip); 1346 1347 hda->init_failed = 1; /* to be sure */ 1348 complete_all(&hda->probe_wait); 1349 1350 if (use_vga_switcheroo(hda)) { 1351 if (chip->disabled && hda->probe_continued) 1352 snd_hda_unlock_devices(&chip->bus); 1353 if (hda->vga_switcheroo_registered) 1354 vga_switcheroo_unregister_client(chip->pci); 1355 } 1356 1357 if (bus->chip_init) { 1358 azx_clear_irq_pending(chip); 1359 azx_stop_all_streams(chip); 1360 azx_stop_chip(chip); 1361 } 1362 1363 if (bus->irq >= 0) 1364 free_irq(bus->irq, (void*)chip); 1365 if (chip->msi) 1366 pci_disable_msi(chip->pci); 1367 iounmap(bus->remap_addr); 1368 1369 azx_free_stream_pages(chip); 1370 azx_free_streams(chip); 1371 snd_hdac_bus_exit(bus); 1372 1373 if (chip->region_requested) 1374 pci_release_regions(chip->pci); 1375 1376 pci_disable_device(chip->pci); 1377 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1378 release_firmware(chip->fw); 1379 #endif 1380 display_power(chip, false); 1381 1382 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1383 snd_hdac_i915_exit(bus); 1384 kfree(hda); 1385 1386 return 0; 1387 } 1388 1389 static int azx_dev_disconnect(struct snd_device *device) 1390 { 1391 struct azx *chip = device->device_data; 1392 struct hdac_bus *bus = azx_bus(chip); 1393 1394 chip->bus.shutdown = 1; 1395 cancel_work_sync(&bus->unsol_work); 1396 1397 return 0; 1398 } 1399 1400 static int azx_dev_free(struct snd_device *device) 1401 { 1402 return azx_free(device->device_data); 1403 } 1404 1405 #ifdef SUPPORT_VGA_SWITCHEROO 1406 #ifdef CONFIG_ACPI 1407 /* ATPX is in the integrated GPU's namespace */ 1408 static bool atpx_present(void) 1409 { 1410 struct pci_dev *pdev = NULL; 1411 acpi_handle dhandle, atpx_handle; 1412 acpi_status status; 1413 1414 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1415 dhandle = ACPI_HANDLE(&pdev->dev); 1416 if (dhandle) { 1417 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1418 if (!ACPI_FAILURE(status)) { 1419 pci_dev_put(pdev); 1420 return true; 1421 } 1422 } 1423 } 1424 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1425 dhandle = ACPI_HANDLE(&pdev->dev); 1426 if (dhandle) { 1427 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1428 if (!ACPI_FAILURE(status)) { 1429 pci_dev_put(pdev); 1430 return true; 1431 } 1432 } 1433 } 1434 return false; 1435 } 1436 #else 1437 static bool atpx_present(void) 1438 { 1439 return false; 1440 } 1441 #endif 1442 1443 /* 1444 * Check of disabled HDMI controller by vga_switcheroo 1445 */ 1446 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1447 { 1448 struct pci_dev *p; 1449 1450 /* check only discrete GPU */ 1451 switch (pci->vendor) { 1452 case PCI_VENDOR_ID_ATI: 1453 case PCI_VENDOR_ID_AMD: 1454 if (pci->devfn == 1) { 1455 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1456 pci->bus->number, 0); 1457 if (p) { 1458 /* ATPX is in the integrated GPU's ACPI namespace 1459 * rather than the dGPU's namespace. However, 1460 * the dGPU is the one who is involved in 1461 * vgaswitcheroo. 1462 */ 1463 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1464 atpx_present()) 1465 return p; 1466 pci_dev_put(p); 1467 } 1468 } 1469 break; 1470 case PCI_VENDOR_ID_NVIDIA: 1471 if (pci->devfn == 1) { 1472 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1473 pci->bus->number, 0); 1474 if (p) { 1475 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1476 return p; 1477 pci_dev_put(p); 1478 } 1479 } 1480 break; 1481 } 1482 return NULL; 1483 } 1484 1485 static bool check_hdmi_disabled(struct pci_dev *pci) 1486 { 1487 bool vga_inactive = false; 1488 struct pci_dev *p = get_bound_vga(pci); 1489 1490 if (p) { 1491 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1492 vga_inactive = true; 1493 pci_dev_put(p); 1494 } 1495 return vga_inactive; 1496 } 1497 #endif /* SUPPORT_VGA_SWITCHEROO */ 1498 1499 /* 1500 * white/black-listing for position_fix 1501 */ 1502 static struct snd_pci_quirk position_fix_list[] = { 1503 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1504 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1505 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1506 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1507 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1508 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1510 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1511 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1512 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1516 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1517 {} 1518 }; 1519 1520 static int check_position_fix(struct azx *chip, int fix) 1521 { 1522 const struct snd_pci_quirk *q; 1523 1524 switch (fix) { 1525 case POS_FIX_AUTO: 1526 case POS_FIX_LPIB: 1527 case POS_FIX_POSBUF: 1528 case POS_FIX_VIACOMBO: 1529 case POS_FIX_COMBO: 1530 case POS_FIX_SKL: 1531 case POS_FIX_FIFO: 1532 return fix; 1533 } 1534 1535 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1536 if (q) { 1537 dev_info(chip->card->dev, 1538 "position_fix set to %d for device %04x:%04x\n", 1539 q->value, q->subvendor, q->subdevice); 1540 return q->value; 1541 } 1542 1543 /* Check VIA/ATI HD Audio Controller exist */ 1544 if (chip->driver_type == AZX_DRIVER_VIA) { 1545 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1546 return POS_FIX_VIACOMBO; 1547 } 1548 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1549 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1550 return POS_FIX_FIFO; 1551 } 1552 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1553 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1554 return POS_FIX_LPIB; 1555 } 1556 if (chip->driver_type == AZX_DRIVER_SKL) { 1557 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1558 return POS_FIX_SKL; 1559 } 1560 return POS_FIX_AUTO; 1561 } 1562 1563 static void assign_position_fix(struct azx *chip, int fix) 1564 { 1565 static azx_get_pos_callback_t callbacks[] = { 1566 [POS_FIX_AUTO] = NULL, 1567 [POS_FIX_LPIB] = azx_get_pos_lpib, 1568 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1569 [POS_FIX_VIACOMBO] = azx_via_get_position, 1570 [POS_FIX_COMBO] = azx_get_pos_lpib, 1571 [POS_FIX_SKL] = azx_get_pos_skl, 1572 [POS_FIX_FIFO] = azx_get_pos_fifo, 1573 }; 1574 1575 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1576 1577 /* combo mode uses LPIB only for playback */ 1578 if (fix == POS_FIX_COMBO) 1579 chip->get_position[1] = NULL; 1580 1581 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1582 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1583 chip->get_delay[0] = chip->get_delay[1] = 1584 azx_get_delay_from_lpib; 1585 } 1586 1587 if (fix == POS_FIX_FIFO) 1588 chip->get_delay[0] = chip->get_delay[1] = 1589 azx_get_delay_from_fifo; 1590 } 1591 1592 /* 1593 * black-lists for probe_mask 1594 */ 1595 static struct snd_pci_quirk probe_mask_list[] = { 1596 /* Thinkpad often breaks the controller communication when accessing 1597 * to the non-working (or non-existing) modem codec slot. 1598 */ 1599 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1600 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1601 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1602 /* broken BIOS */ 1603 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1604 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1605 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1606 /* forced codec slots */ 1607 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1608 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1609 /* WinFast VP200 H (Teradici) user reported broken communication */ 1610 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1611 {} 1612 }; 1613 1614 #define AZX_FORCE_CODEC_MASK 0x100 1615 1616 static void check_probe_mask(struct azx *chip, int dev) 1617 { 1618 const struct snd_pci_quirk *q; 1619 1620 chip->codec_probe_mask = probe_mask[dev]; 1621 if (chip->codec_probe_mask == -1) { 1622 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1623 if (q) { 1624 dev_info(chip->card->dev, 1625 "probe_mask set to 0x%x for device %04x:%04x\n", 1626 q->value, q->subvendor, q->subdevice); 1627 chip->codec_probe_mask = q->value; 1628 } 1629 } 1630 1631 /* check forced option */ 1632 if (chip->codec_probe_mask != -1 && 1633 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1634 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1635 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1636 (int)azx_bus(chip)->codec_mask); 1637 } 1638 } 1639 1640 /* 1641 * white/black-list for enable_msi 1642 */ 1643 static struct snd_pci_quirk msi_black_list[] = { 1644 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1645 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1646 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1647 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1648 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1649 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1650 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1651 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1652 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1653 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1654 {} 1655 }; 1656 1657 static void check_msi(struct azx *chip) 1658 { 1659 const struct snd_pci_quirk *q; 1660 1661 if (enable_msi >= 0) { 1662 chip->msi = !!enable_msi; 1663 return; 1664 } 1665 chip->msi = 1; /* enable MSI as default */ 1666 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1667 if (q) { 1668 dev_info(chip->card->dev, 1669 "msi for device %04x:%04x set to %d\n", 1670 q->subvendor, q->subdevice, q->value); 1671 chip->msi = q->value; 1672 return; 1673 } 1674 1675 /* NVidia chipsets seem to cause troubles with MSI */ 1676 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1677 dev_info(chip->card->dev, "Disabling MSI\n"); 1678 chip->msi = 0; 1679 } 1680 } 1681 1682 /* check the snoop mode availability */ 1683 static void azx_check_snoop_available(struct azx *chip) 1684 { 1685 int snoop = hda_snoop; 1686 1687 if (snoop >= 0) { 1688 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1689 snoop ? "snoop" : "non-snoop"); 1690 chip->snoop = snoop; 1691 chip->uc_buffer = !snoop; 1692 return; 1693 } 1694 1695 snoop = true; 1696 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1697 chip->driver_type == AZX_DRIVER_VIA) { 1698 /* force to non-snoop mode for a new VIA controller 1699 * when BIOS is set 1700 */ 1701 u8 val; 1702 pci_read_config_byte(chip->pci, 0x42, &val); 1703 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1704 chip->pci->revision == 0x20)) 1705 snoop = false; 1706 } 1707 1708 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1709 snoop = false; 1710 1711 chip->snoop = snoop; 1712 if (!snoop) { 1713 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1714 /* C-Media requires non-cached pages only for CORB/RIRB */ 1715 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1716 chip->uc_buffer = true; 1717 } 1718 } 1719 1720 static void azx_probe_work(struct work_struct *work) 1721 { 1722 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1723 azx_probe_continue(&hda->chip); 1724 } 1725 1726 static int default_bdl_pos_adj(struct azx *chip) 1727 { 1728 /* some exceptions: Atoms seem problematic with value 1 */ 1729 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1730 switch (chip->pci->device) { 1731 case 0x0f04: /* Baytrail */ 1732 case 0x2284: /* Braswell */ 1733 return 32; 1734 } 1735 } 1736 1737 switch (chip->driver_type) { 1738 case AZX_DRIVER_ICH: 1739 case AZX_DRIVER_PCH: 1740 return 1; 1741 default: 1742 return 32; 1743 } 1744 } 1745 1746 /* 1747 * constructor 1748 */ 1749 static const struct hda_controller_ops pci_hda_ops; 1750 1751 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1752 int dev, unsigned int driver_caps, 1753 struct azx **rchip) 1754 { 1755 static struct snd_device_ops ops = { 1756 .dev_disconnect = azx_dev_disconnect, 1757 .dev_free = azx_dev_free, 1758 }; 1759 struct hda_intel *hda; 1760 struct azx *chip; 1761 int err; 1762 1763 *rchip = NULL; 1764 1765 err = pci_enable_device(pci); 1766 if (err < 0) 1767 return err; 1768 1769 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1770 if (!hda) { 1771 pci_disable_device(pci); 1772 return -ENOMEM; 1773 } 1774 1775 chip = &hda->chip; 1776 mutex_init(&chip->open_mutex); 1777 chip->card = card; 1778 chip->pci = pci; 1779 chip->ops = &pci_hda_ops; 1780 chip->driver_caps = driver_caps; 1781 chip->driver_type = driver_caps & 0xff; 1782 check_msi(chip); 1783 chip->dev_index = dev; 1784 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1785 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1786 INIT_LIST_HEAD(&chip->pcm_list); 1787 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1788 INIT_LIST_HEAD(&hda->list); 1789 init_vga_switcheroo(chip); 1790 init_completion(&hda->probe_wait); 1791 1792 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1793 1794 check_probe_mask(chip, dev); 1795 1796 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1797 chip->fallback_to_single_cmd = 1; 1798 else /* explicitly set to single_cmd or not */ 1799 chip->single_cmd = single_cmd; 1800 1801 azx_check_snoop_available(chip); 1802 1803 if (bdl_pos_adj[dev] < 0) 1804 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1805 else 1806 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1807 1808 err = azx_bus_init(chip, model[dev]); 1809 if (err < 0) { 1810 kfree(hda); 1811 pci_disable_device(pci); 1812 return err; 1813 } 1814 1815 /* use the non-cached pages in non-snoop mode */ 1816 if (!azx_snoop(chip)) 1817 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1818 1819 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1820 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1821 chip->bus.needs_damn_long_delay = 1; 1822 } 1823 1824 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1825 if (err < 0) { 1826 dev_err(card->dev, "Error creating device [card]!\n"); 1827 azx_free(chip); 1828 return err; 1829 } 1830 1831 /* continue probing in work context as may trigger request module */ 1832 INIT_WORK(&hda->probe_work, azx_probe_work); 1833 1834 *rchip = chip; 1835 1836 return 0; 1837 } 1838 1839 static int azx_first_init(struct azx *chip) 1840 { 1841 int dev = chip->dev_index; 1842 struct pci_dev *pci = chip->pci; 1843 struct snd_card *card = chip->card; 1844 struct hdac_bus *bus = azx_bus(chip); 1845 int err; 1846 unsigned short gcap; 1847 unsigned int dma_bits = 64; 1848 1849 #if BITS_PER_LONG != 64 1850 /* Fix up base address on ULI M5461 */ 1851 if (chip->driver_type == AZX_DRIVER_ULI) { 1852 u16 tmp3; 1853 pci_read_config_word(pci, 0x40, &tmp3); 1854 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1855 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1856 } 1857 #endif 1858 1859 err = pci_request_regions(pci, "ICH HD audio"); 1860 if (err < 0) 1861 return err; 1862 chip->region_requested = 1; 1863 1864 bus->addr = pci_resource_start(pci, 0); 1865 bus->remap_addr = pci_ioremap_bar(pci, 0); 1866 if (bus->remap_addr == NULL) { 1867 dev_err(card->dev, "ioremap error\n"); 1868 return -ENXIO; 1869 } 1870 1871 if (chip->driver_type == AZX_DRIVER_SKL) 1872 snd_hdac_bus_parse_capabilities(bus); 1873 1874 /* 1875 * Some Intel CPUs has always running timer (ART) feature and 1876 * controller may have Global time sync reporting capability, so 1877 * check both of these before declaring synchronized time reporting 1878 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1879 */ 1880 chip->gts_present = false; 1881 1882 #ifdef CONFIG_X86 1883 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1884 chip->gts_present = true; 1885 #endif 1886 1887 if (chip->msi) { 1888 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1889 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1890 pci->no_64bit_msi = true; 1891 } 1892 if (pci_enable_msi(pci) < 0) 1893 chip->msi = 0; 1894 } 1895 1896 pci_set_master(pci); 1897 synchronize_irq(bus->irq); 1898 1899 gcap = azx_readw(chip, GCAP); 1900 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1901 1902 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1903 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1904 dma_bits = 40; 1905 1906 /* disable SB600 64bit support for safety */ 1907 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1908 struct pci_dev *p_smbus; 1909 dma_bits = 40; 1910 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1911 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1912 NULL); 1913 if (p_smbus) { 1914 if (p_smbus->revision < 0x30) 1915 gcap &= ~AZX_GCAP_64OK; 1916 pci_dev_put(p_smbus); 1917 } 1918 } 1919 1920 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1921 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1922 dma_bits = 40; 1923 1924 /* disable 64bit DMA address on some devices */ 1925 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1926 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1927 gcap &= ~AZX_GCAP_64OK; 1928 } 1929 1930 /* disable buffer size rounding to 128-byte multiples if supported */ 1931 if (align_buffer_size >= 0) 1932 chip->align_buffer_size = !!align_buffer_size; 1933 else { 1934 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1935 chip->align_buffer_size = 0; 1936 else 1937 chip->align_buffer_size = 1; 1938 } 1939 1940 /* allow 64bit DMA address if supported by H/W */ 1941 if (!(gcap & AZX_GCAP_64OK)) 1942 dma_bits = 32; 1943 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1944 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1945 } else { 1946 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1947 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1948 } 1949 1950 /* read number of streams from GCAP register instead of using 1951 * hardcoded value 1952 */ 1953 chip->capture_streams = (gcap >> 8) & 0x0f; 1954 chip->playback_streams = (gcap >> 12) & 0x0f; 1955 if (!chip->playback_streams && !chip->capture_streams) { 1956 /* gcap didn't give any info, switching to old method */ 1957 1958 switch (chip->driver_type) { 1959 case AZX_DRIVER_ULI: 1960 chip->playback_streams = ULI_NUM_PLAYBACK; 1961 chip->capture_streams = ULI_NUM_CAPTURE; 1962 break; 1963 case AZX_DRIVER_ATIHDMI: 1964 case AZX_DRIVER_ATIHDMI_NS: 1965 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1966 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1967 break; 1968 case AZX_DRIVER_GENERIC: 1969 default: 1970 chip->playback_streams = ICH6_NUM_PLAYBACK; 1971 chip->capture_streams = ICH6_NUM_CAPTURE; 1972 break; 1973 } 1974 } 1975 chip->capture_index_offset = 0; 1976 chip->playback_index_offset = chip->capture_streams; 1977 chip->num_streams = chip->playback_streams + chip->capture_streams; 1978 1979 /* sanity check for the SDxCTL.STRM field overflow */ 1980 if (chip->num_streams > 15 && 1981 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1982 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1983 "forcing separate stream tags", chip->num_streams); 1984 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1985 } 1986 1987 /* initialize streams */ 1988 err = azx_init_streams(chip); 1989 if (err < 0) 1990 return err; 1991 1992 err = azx_alloc_stream_pages(chip); 1993 if (err < 0) 1994 return err; 1995 1996 /* initialize chip */ 1997 azx_init_pci(chip); 1998 1999 snd_hdac_i915_set_bclk(bus); 2000 2001 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2002 2003 /* codec detection */ 2004 if (!azx_bus(chip)->codec_mask) { 2005 dev_err(card->dev, "no codecs found!\n"); 2006 return -ENODEV; 2007 } 2008 2009 if (azx_acquire_irq(chip, 0) < 0) 2010 return -EBUSY; 2011 2012 strcpy(card->driver, "HDA-Intel"); 2013 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2014 sizeof(card->shortname)); 2015 snprintf(card->longname, sizeof(card->longname), 2016 "%s at 0x%lx irq %i", 2017 card->shortname, bus->addr, bus->irq); 2018 2019 return 0; 2020 } 2021 2022 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2023 /* callback from request_firmware_nowait() */ 2024 static void azx_firmware_cb(const struct firmware *fw, void *context) 2025 { 2026 struct snd_card *card = context; 2027 struct azx *chip = card->private_data; 2028 struct pci_dev *pci = chip->pci; 2029 2030 if (!fw) { 2031 dev_err(card->dev, "Cannot load firmware, aborting\n"); 2032 goto error; 2033 } 2034 2035 chip->fw = fw; 2036 if (!chip->disabled) { 2037 /* continue probing */ 2038 if (azx_probe_continue(chip)) 2039 goto error; 2040 } 2041 return; /* OK */ 2042 2043 error: 2044 snd_card_free(card); 2045 pci_set_drvdata(pci, NULL); 2046 } 2047 #endif 2048 2049 static int disable_msi_reset_irq(struct azx *chip) 2050 { 2051 struct hdac_bus *bus = azx_bus(chip); 2052 int err; 2053 2054 free_irq(bus->irq, chip); 2055 bus->irq = -1; 2056 pci_disable_msi(chip->pci); 2057 chip->msi = 0; 2058 err = azx_acquire_irq(chip, 1); 2059 if (err < 0) 2060 return err; 2061 2062 return 0; 2063 } 2064 2065 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2066 struct vm_area_struct *area) 2067 { 2068 #ifdef CONFIG_X86 2069 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2070 struct azx *chip = apcm->chip; 2071 if (chip->uc_buffer) 2072 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2073 #endif 2074 } 2075 2076 static const struct hda_controller_ops pci_hda_ops = { 2077 .disable_msi_reset_irq = disable_msi_reset_irq, 2078 .pcm_mmap_prepare = pcm_mmap_prepare, 2079 .position_check = azx_position_check, 2080 }; 2081 2082 static int azx_probe(struct pci_dev *pci, 2083 const struct pci_device_id *pci_id) 2084 { 2085 static int dev; 2086 struct snd_card *card; 2087 struct hda_intel *hda; 2088 struct azx *chip; 2089 bool schedule_probe; 2090 int err; 2091 2092 if (dev >= SNDRV_CARDS) 2093 return -ENODEV; 2094 if (!enable[dev]) { 2095 dev++; 2096 return -ENOENT; 2097 } 2098 2099 /* 2100 * stop probe if another Intel's DSP driver should be activated 2101 */ 2102 if (dsp_driver) { 2103 err = snd_intel_dsp_driver_probe(pci); 2104 if (err != SND_INTEL_DSP_DRIVER_ANY && 2105 err != SND_INTEL_DSP_DRIVER_LEGACY) 2106 return -ENODEV; 2107 } 2108 2109 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2110 0, &card); 2111 if (err < 0) { 2112 dev_err(&pci->dev, "Error creating card!\n"); 2113 return err; 2114 } 2115 2116 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2117 if (err < 0) 2118 goto out_free; 2119 card->private_data = chip; 2120 hda = container_of(chip, struct hda_intel, chip); 2121 2122 pci_set_drvdata(pci, card); 2123 2124 err = register_vga_switcheroo(chip); 2125 if (err < 0) { 2126 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2127 goto out_free; 2128 } 2129 2130 if (check_hdmi_disabled(pci)) { 2131 dev_info(card->dev, "VGA controller is disabled\n"); 2132 dev_info(card->dev, "Delaying initialization\n"); 2133 chip->disabled = true; 2134 } 2135 2136 schedule_probe = !chip->disabled; 2137 2138 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2139 if (patch[dev] && *patch[dev]) { 2140 dev_info(card->dev, "Applying patch firmware '%s'\n", 2141 patch[dev]); 2142 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2143 &pci->dev, GFP_KERNEL, card, 2144 azx_firmware_cb); 2145 if (err < 0) 2146 goto out_free; 2147 schedule_probe = false; /* continued in azx_firmware_cb() */ 2148 } 2149 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2150 2151 #ifndef CONFIG_SND_HDA_I915 2152 if (CONTROLLER_IN_GPU(pci)) 2153 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2154 #endif 2155 2156 if (schedule_probe) 2157 schedule_work(&hda->probe_work); 2158 2159 dev++; 2160 if (chip->disabled) 2161 complete_all(&hda->probe_wait); 2162 return 0; 2163 2164 out_free: 2165 snd_card_free(card); 2166 return err; 2167 } 2168 2169 #ifdef CONFIG_PM 2170 /* On some boards setting power_save to a non 0 value leads to clicking / 2171 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2172 * figure out how to avoid these sounds, but that is not always feasible. 2173 * So we keep a list of devices where we disable powersaving as its known 2174 * to causes problems on these devices. 2175 */ 2176 static struct snd_pci_quirk power_save_blacklist[] = { 2177 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2178 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2179 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2180 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2181 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2182 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2183 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2184 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2185 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2186 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2187 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2188 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2189 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2190 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2191 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2192 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2193 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2194 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2195 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2196 /* https://bugs.launchpad.net/bugs/1821663 */ 2197 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2198 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2199 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2200 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2201 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2202 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2203 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2204 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2205 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2206 /* https://bugs.launchpad.net/bugs/1821663 */ 2207 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2208 {} 2209 }; 2210 #endif /* CONFIG_PM */ 2211 2212 static void set_default_power_save(struct azx *chip) 2213 { 2214 int val = power_save; 2215 2216 #ifdef CONFIG_PM 2217 if (pm_blacklist) { 2218 const struct snd_pci_quirk *q; 2219 2220 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2221 if (q && val) { 2222 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2223 q->subvendor, q->subdevice); 2224 val = 0; 2225 } 2226 } 2227 #endif /* CONFIG_PM */ 2228 snd_hda_set_power_save(&chip->bus, val * 1000); 2229 } 2230 2231 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2232 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2233 [AZX_DRIVER_NVIDIA] = 8, 2234 [AZX_DRIVER_TERA] = 1, 2235 }; 2236 2237 static int azx_probe_continue(struct azx *chip) 2238 { 2239 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2240 struct hdac_bus *bus = azx_bus(chip); 2241 struct pci_dev *pci = chip->pci; 2242 int dev = chip->dev_index; 2243 int err; 2244 2245 to_hda_bus(bus)->bus_probing = 1; 2246 hda->probe_continued = 1; 2247 2248 /* bind with i915 if needed */ 2249 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2250 err = snd_hdac_i915_init(bus); 2251 if (err < 0) { 2252 /* if the controller is bound only with HDMI/DP 2253 * (for HSW and BDW), we need to abort the probe; 2254 * for other chips, still continue probing as other 2255 * codecs can be on the same link. 2256 */ 2257 if (CONTROLLER_IN_GPU(pci)) { 2258 dev_err(chip->card->dev, 2259 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2260 goto out_free; 2261 } else { 2262 /* don't bother any longer */ 2263 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2264 } 2265 } 2266 2267 /* HSW/BDW controllers need this power */ 2268 if (CONTROLLER_IN_GPU(pci)) 2269 hda->need_i915_power = 1; 2270 } 2271 2272 /* Request display power well for the HDA controller or codec. For 2273 * Haswell/Broadwell, both the display HDA controller and codec need 2274 * this power. For other platforms, like Baytrail/Braswell, only the 2275 * display codec needs the power and it can be released after probe. 2276 */ 2277 display_power(chip, true); 2278 2279 err = azx_first_init(chip); 2280 if (err < 0) 2281 goto out_free; 2282 2283 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2284 chip->beep_mode = beep_mode[dev]; 2285 #endif 2286 2287 /* create codec instances */ 2288 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2289 if (err < 0) 2290 goto out_free; 2291 2292 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2293 if (chip->fw) { 2294 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2295 chip->fw->data); 2296 if (err < 0) 2297 goto out_free; 2298 #ifndef CONFIG_PM 2299 release_firmware(chip->fw); /* no longer needed */ 2300 chip->fw = NULL; 2301 #endif 2302 } 2303 #endif 2304 if ((probe_only[dev] & 1) == 0) { 2305 err = azx_codec_configure(chip); 2306 if (err < 0) 2307 goto out_free; 2308 } 2309 2310 err = snd_card_register(chip->card); 2311 if (err < 0) 2312 goto out_free; 2313 2314 setup_vga_switcheroo_runtime_pm(chip); 2315 2316 chip->running = 1; 2317 azx_add_card_list(chip); 2318 2319 set_default_power_save(chip); 2320 2321 if (azx_has_pm_runtime(chip)) 2322 pm_runtime_put_autosuspend(&pci->dev); 2323 2324 out_free: 2325 if (err < 0 || !hda->need_i915_power) 2326 display_power(chip, false); 2327 if (err < 0) 2328 hda->init_failed = 1; 2329 complete_all(&hda->probe_wait); 2330 to_hda_bus(bus)->bus_probing = 0; 2331 return err; 2332 } 2333 2334 static void azx_remove(struct pci_dev *pci) 2335 { 2336 struct snd_card *card = pci_get_drvdata(pci); 2337 struct azx *chip; 2338 struct hda_intel *hda; 2339 2340 if (card) { 2341 /* cancel the pending probing work */ 2342 chip = card->private_data; 2343 hda = container_of(chip, struct hda_intel, chip); 2344 /* FIXME: below is an ugly workaround. 2345 * Both device_release_driver() and driver_probe_device() 2346 * take *both* the device's and its parent's lock before 2347 * calling the remove() and probe() callbacks. The codec 2348 * probe takes the locks of both the codec itself and its 2349 * parent, i.e. the PCI controller dev. Meanwhile, when 2350 * the PCI controller is unbound, it takes its lock, too 2351 * ==> ouch, a deadlock! 2352 * As a workaround, we unlock temporarily here the controller 2353 * device during cancel_work_sync() call. 2354 */ 2355 device_unlock(&pci->dev); 2356 cancel_work_sync(&hda->probe_work); 2357 device_lock(&pci->dev); 2358 2359 snd_card_free(card); 2360 } 2361 } 2362 2363 static void azx_shutdown(struct pci_dev *pci) 2364 { 2365 struct snd_card *card = pci_get_drvdata(pci); 2366 struct azx *chip; 2367 2368 if (!card) 2369 return; 2370 chip = card->private_data; 2371 if (chip && chip->running) 2372 azx_stop_chip(chip); 2373 } 2374 2375 /* PCI IDs */ 2376 static const struct pci_device_id azx_ids[] = { 2377 /* CPT */ 2378 { PCI_DEVICE(0x8086, 0x1c20), 2379 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2380 /* PBG */ 2381 { PCI_DEVICE(0x8086, 0x1d20), 2382 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2383 /* Panther Point */ 2384 { PCI_DEVICE(0x8086, 0x1e20), 2385 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2386 /* Lynx Point */ 2387 { PCI_DEVICE(0x8086, 0x8c20), 2388 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2389 /* 9 Series */ 2390 { PCI_DEVICE(0x8086, 0x8ca0), 2391 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2392 /* Wellsburg */ 2393 { PCI_DEVICE(0x8086, 0x8d20), 2394 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2395 { PCI_DEVICE(0x8086, 0x8d21), 2396 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2397 /* Lewisburg */ 2398 { PCI_DEVICE(0x8086, 0xa1f0), 2399 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2400 { PCI_DEVICE(0x8086, 0xa270), 2401 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2402 /* Lynx Point-LP */ 2403 { PCI_DEVICE(0x8086, 0x9c20), 2404 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2405 /* Lynx Point-LP */ 2406 { PCI_DEVICE(0x8086, 0x9c21), 2407 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2408 /* Wildcat Point-LP */ 2409 { PCI_DEVICE(0x8086, 0x9ca0), 2410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2411 /* Sunrise Point */ 2412 { PCI_DEVICE(0x8086, 0xa170), 2413 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2414 /* Sunrise Point-LP */ 2415 { PCI_DEVICE(0x8086, 0x9d70), 2416 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2417 /* Kabylake */ 2418 { PCI_DEVICE(0x8086, 0xa171), 2419 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2420 /* Kabylake-LP */ 2421 { PCI_DEVICE(0x8086, 0x9d71), 2422 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2423 /* Kabylake-H */ 2424 { PCI_DEVICE(0x8086, 0xa2f0), 2425 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2426 /* Coffelake */ 2427 { PCI_DEVICE(0x8086, 0xa348), 2428 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2429 /* Cannonlake */ 2430 { PCI_DEVICE(0x8086, 0x9dc8), 2431 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2432 /* CometLake-LP */ 2433 { PCI_DEVICE(0x8086, 0x02C8), 2434 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2435 /* CometLake-H */ 2436 { PCI_DEVICE(0x8086, 0x06C8), 2437 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2438 /* CometLake-S */ 2439 { PCI_DEVICE(0x8086, 0xa3f0), 2440 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2441 /* Icelake */ 2442 { PCI_DEVICE(0x8086, 0x34c8), 2443 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2444 /* Jasperlake */ 2445 { PCI_DEVICE(0x8086, 0x38c8), 2446 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2447 /* Tigerlake */ 2448 { PCI_DEVICE(0x8086, 0xa0c8), 2449 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2450 /* Elkhart Lake */ 2451 { PCI_DEVICE(0x8086, 0x4b55), 2452 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2453 /* Broxton-P(Apollolake) */ 2454 { PCI_DEVICE(0x8086, 0x5a98), 2455 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2456 /* Broxton-T */ 2457 { PCI_DEVICE(0x8086, 0x1a98), 2458 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2459 /* Gemini-Lake */ 2460 { PCI_DEVICE(0x8086, 0x3198), 2461 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2462 /* Haswell */ 2463 { PCI_DEVICE(0x8086, 0x0a0c), 2464 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2465 { PCI_DEVICE(0x8086, 0x0c0c), 2466 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2467 { PCI_DEVICE(0x8086, 0x0d0c), 2468 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2469 /* Broadwell */ 2470 { PCI_DEVICE(0x8086, 0x160c), 2471 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2472 /* 5 Series/3400 */ 2473 { PCI_DEVICE(0x8086, 0x3b56), 2474 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2475 /* Poulsbo */ 2476 { PCI_DEVICE(0x8086, 0x811b), 2477 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2478 /* Oaktrail */ 2479 { PCI_DEVICE(0x8086, 0x080a), 2480 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2481 /* BayTrail */ 2482 { PCI_DEVICE(0x8086, 0x0f04), 2483 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2484 /* Braswell */ 2485 { PCI_DEVICE(0x8086, 0x2284), 2486 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2487 /* ICH6 */ 2488 { PCI_DEVICE(0x8086, 0x2668), 2489 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2490 /* ICH7 */ 2491 { PCI_DEVICE(0x8086, 0x27d8), 2492 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2493 /* ESB2 */ 2494 { PCI_DEVICE(0x8086, 0x269a), 2495 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2496 /* ICH8 */ 2497 { PCI_DEVICE(0x8086, 0x284b), 2498 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2499 /* ICH9 */ 2500 { PCI_DEVICE(0x8086, 0x293e), 2501 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2502 /* ICH9 */ 2503 { PCI_DEVICE(0x8086, 0x293f), 2504 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2505 /* ICH10 */ 2506 { PCI_DEVICE(0x8086, 0x3a3e), 2507 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2508 /* ICH10 */ 2509 { PCI_DEVICE(0x8086, 0x3a6e), 2510 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2511 /* Generic Intel */ 2512 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2513 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2514 .class_mask = 0xffffff, 2515 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2516 /* ATI SB 450/600/700/800/900 */ 2517 { PCI_DEVICE(0x1002, 0x437b), 2518 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2519 { PCI_DEVICE(0x1002, 0x4383), 2520 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2521 /* AMD Hudson */ 2522 { PCI_DEVICE(0x1022, 0x780d), 2523 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2524 /* AMD, X370 & co */ 2525 { PCI_DEVICE(0x1022, 0x1457), 2526 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2527 /* AMD, X570 & co */ 2528 { PCI_DEVICE(0x1022, 0x1487), 2529 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2530 /* AMD Stoney */ 2531 { PCI_DEVICE(0x1022, 0x157a), 2532 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2533 AZX_DCAPS_PM_RUNTIME }, 2534 /* AMD Raven */ 2535 { PCI_DEVICE(0x1022, 0x15e3), 2536 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2537 /* ATI HDMI */ 2538 { PCI_DEVICE(0x1002, 0x0002), 2539 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2540 { PCI_DEVICE(0x1002, 0x1308), 2541 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2542 { PCI_DEVICE(0x1002, 0x157a), 2543 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2544 { PCI_DEVICE(0x1002, 0x15b3), 2545 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2546 { PCI_DEVICE(0x1002, 0x793b), 2547 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2548 { PCI_DEVICE(0x1002, 0x7919), 2549 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2550 { PCI_DEVICE(0x1002, 0x960f), 2551 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2552 { PCI_DEVICE(0x1002, 0x970f), 2553 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2554 { PCI_DEVICE(0x1002, 0x9840), 2555 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2556 { PCI_DEVICE(0x1002, 0xaa00), 2557 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2558 { PCI_DEVICE(0x1002, 0xaa08), 2559 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2560 { PCI_DEVICE(0x1002, 0xaa10), 2561 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2562 { PCI_DEVICE(0x1002, 0xaa18), 2563 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2564 { PCI_DEVICE(0x1002, 0xaa20), 2565 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2566 { PCI_DEVICE(0x1002, 0xaa28), 2567 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2568 { PCI_DEVICE(0x1002, 0xaa30), 2569 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2570 { PCI_DEVICE(0x1002, 0xaa38), 2571 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2572 { PCI_DEVICE(0x1002, 0xaa40), 2573 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2574 { PCI_DEVICE(0x1002, 0xaa48), 2575 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2576 { PCI_DEVICE(0x1002, 0xaa50), 2577 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2578 { PCI_DEVICE(0x1002, 0xaa58), 2579 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2580 { PCI_DEVICE(0x1002, 0xaa60), 2581 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2582 { PCI_DEVICE(0x1002, 0xaa68), 2583 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2584 { PCI_DEVICE(0x1002, 0xaa80), 2585 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2586 { PCI_DEVICE(0x1002, 0xaa88), 2587 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2588 { PCI_DEVICE(0x1002, 0xaa90), 2589 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2590 { PCI_DEVICE(0x1002, 0xaa98), 2591 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2592 { PCI_DEVICE(0x1002, 0x9902), 2593 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2594 { PCI_DEVICE(0x1002, 0xaaa0), 2595 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2596 { PCI_DEVICE(0x1002, 0xaaa8), 2597 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2598 { PCI_DEVICE(0x1002, 0xaab0), 2599 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2600 { PCI_DEVICE(0x1002, 0xaac0), 2601 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2602 { PCI_DEVICE(0x1002, 0xaac8), 2603 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2604 { PCI_DEVICE(0x1002, 0xaad8), 2605 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2606 AZX_DCAPS_PM_RUNTIME }, 2607 { PCI_DEVICE(0x1002, 0xaae0), 2608 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2609 AZX_DCAPS_PM_RUNTIME }, 2610 { PCI_DEVICE(0x1002, 0xaae8), 2611 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2612 AZX_DCAPS_PM_RUNTIME }, 2613 { PCI_DEVICE(0x1002, 0xaaf0), 2614 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2615 AZX_DCAPS_PM_RUNTIME }, 2616 { PCI_DEVICE(0x1002, 0xaaf8), 2617 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2618 AZX_DCAPS_PM_RUNTIME }, 2619 { PCI_DEVICE(0x1002, 0xab00), 2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2621 AZX_DCAPS_PM_RUNTIME }, 2622 { PCI_DEVICE(0x1002, 0xab08), 2623 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2624 AZX_DCAPS_PM_RUNTIME }, 2625 { PCI_DEVICE(0x1002, 0xab10), 2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2627 AZX_DCAPS_PM_RUNTIME }, 2628 { PCI_DEVICE(0x1002, 0xab18), 2629 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2630 AZX_DCAPS_PM_RUNTIME }, 2631 { PCI_DEVICE(0x1002, 0xab20), 2632 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2633 AZX_DCAPS_PM_RUNTIME }, 2634 { PCI_DEVICE(0x1002, 0xab38), 2635 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2636 AZX_DCAPS_PM_RUNTIME }, 2637 /* VIA VT8251/VT8237A */ 2638 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2639 /* VIA GFX VT7122/VX900 */ 2640 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2641 /* VIA GFX VT6122/VX11 */ 2642 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2643 /* SIS966 */ 2644 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2645 /* ULI M5461 */ 2646 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2647 /* NVIDIA MCP */ 2648 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2649 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2650 .class_mask = 0xffffff, 2651 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2652 /* Teradici */ 2653 { PCI_DEVICE(0x6549, 0x1200), 2654 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2655 { PCI_DEVICE(0x6549, 0x2200), 2656 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2657 /* Creative X-Fi (CA0110-IBG) */ 2658 /* CTHDA chips */ 2659 { PCI_DEVICE(0x1102, 0x0010), 2660 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2661 { PCI_DEVICE(0x1102, 0x0012), 2662 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2663 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2664 /* the following entry conflicts with snd-ctxfi driver, 2665 * as ctxfi driver mutates from HD-audio to native mode with 2666 * a special command sequence. 2667 */ 2668 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2669 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2670 .class_mask = 0xffffff, 2671 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2672 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2673 #else 2674 /* this entry seems still valid -- i.e. without emu20kx chip */ 2675 { PCI_DEVICE(0x1102, 0x0009), 2676 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2677 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2678 #endif 2679 /* CM8888 */ 2680 { PCI_DEVICE(0x13f6, 0x5011), 2681 .driver_data = AZX_DRIVER_CMEDIA | 2682 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2683 /* Vortex86MX */ 2684 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2685 /* VMware HDAudio */ 2686 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2687 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2688 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2689 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2690 .class_mask = 0xffffff, 2691 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2692 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2693 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2694 .class_mask = 0xffffff, 2695 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2696 /* Zhaoxin */ 2697 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2698 { 0, } 2699 }; 2700 MODULE_DEVICE_TABLE(pci, azx_ids); 2701 2702 /* pci_driver definition */ 2703 static struct pci_driver azx_driver = { 2704 .name = KBUILD_MODNAME, 2705 .id_table = azx_ids, 2706 .probe = azx_probe, 2707 .remove = azx_remove, 2708 .shutdown = azx_shutdown, 2709 .driver = { 2710 .pm = AZX_PM_OPS, 2711 }, 2712 }; 2713 2714 module_pci_driver(azx_driver); 2715