1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/set_memory.h> 57 #include <asm/cpufeature.h> 58 #endif 59 #include <sound/core.h> 60 #include <sound/initval.h> 61 #include <sound/hdaudio.h> 62 #include <sound/hda_i915.h> 63 #include <linux/vgaarb.h> 64 #include <linux/vga_switcheroo.h> 65 #include <linux/firmware.h> 66 #include "hda_codec.h" 67 #include "hda_controller.h" 68 #include "hda_intel.h" 69 70 #define CREATE_TRACE_POINTS 71 #include "hda_intel_trace.h" 72 73 /* position fix mode */ 74 enum { 75 POS_FIX_AUTO, 76 POS_FIX_LPIB, 77 POS_FIX_POSBUF, 78 POS_FIX_VIACOMBO, 79 POS_FIX_COMBO, 80 POS_FIX_SKL, 81 }; 82 83 /* Defines for ATI HD Audio support in SB450 south bridge */ 84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 86 87 /* Defines for Nvidia HDA support */ 88 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 89 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 90 #define NVIDIA_HDA_ISTRM_COH 0x4d 91 #define NVIDIA_HDA_OSTRM_COH 0x4c 92 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 93 94 /* Defines for Intel SCH HDA snoop control */ 95 #define INTEL_HDA_CGCTL 0x48 96 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 97 #define INTEL_SCH_HDA_DEVC 0x78 98 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 99 100 /* Define IN stream 0 FIFO size offset in VIA controller */ 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 102 /* Define VIA HD Audio Device ID*/ 103 #define VIA_HDAC_DEVICE_ID 0x3288 104 105 /* max number of SDs */ 106 /* ICH, ATI and VIA have 4 playback and 4 capture */ 107 #define ICH6_NUM_CAPTURE 4 108 #define ICH6_NUM_PLAYBACK 4 109 110 /* ULI has 6 playback and 5 capture */ 111 #define ULI_NUM_CAPTURE 5 112 #define ULI_NUM_PLAYBACK 6 113 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 115 #define ATIHDMI_NUM_CAPTURE 0 116 #define ATIHDMI_NUM_PLAYBACK 8 117 118 /* TERA has 4 playback and 3 capture */ 119 #define TERA_NUM_CAPTURE 3 120 #define TERA_NUM_PLAYBACK 4 121 122 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 126 static char *model[SNDRV_CARDS]; 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 130 static int probe_only[SNDRV_CARDS]; 131 static int jackpoll_ms[SNDRV_CARDS]; 132 static int single_cmd = -1; 133 static int enable_msi = -1; 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER 135 static char *patch[SNDRV_CARDS]; 136 #endif 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 139 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 140 #endif 141 142 module_param_array(index, int, NULL, 0444); 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 144 module_param_array(id, charp, NULL, 0444); 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 146 module_param_array(enable, bool, NULL, 0444); 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 148 module_param_array(model, charp, NULL, 0444); 149 MODULE_PARM_DESC(model, "Use the given board model."); 150 module_param_array(position_fix, int, NULL, 0444); 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+)."); 153 module_param_array(bdl_pos_adj, int, NULL, 0644); 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 155 module_param_array(probe_mask, int, NULL, 0444); 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 157 module_param_array(probe_only, int, NULL, 0444); 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 159 module_param_array(jackpoll_ms, int, NULL, 0444); 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 161 module_param(single_cmd, bint, 0444); 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 163 "(for debugging only)."); 164 module_param(enable_msi, bint, 0444); 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER 167 module_param_array(patch, charp, NULL, 0444); 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 169 #endif 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP 171 module_param_array(beep_mode, bool, NULL, 0444); 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 173 "(0=off, 1=on) (default=1)."); 174 #endif 175 176 #ifdef CONFIG_PM 177 static int param_set_xint(const char *val, const struct kernel_param *kp); 178 static const struct kernel_param_ops param_ops_xint = { 179 .set = param_set_xint, 180 .get = param_get_int, 181 }; 182 #define param_check_xint param_check_int 183 184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 185 module_param(power_save, xint, 0644); 186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 187 "(in second, 0 = disable)."); 188 189 static bool pm_blacklist = true; 190 module_param(pm_blacklist, bool, 0644); 191 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 192 193 /* reset the HD-audio controller in power save mode. 194 * this may give more power-saving, but will take longer time to 195 * wake up. 196 */ 197 static bool power_save_controller = 1; 198 module_param(power_save_controller, bool, 0644); 199 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 200 #else 201 #define power_save 0 202 #endif /* CONFIG_PM */ 203 204 static int align_buffer_size = -1; 205 module_param(align_buffer_size, bint, 0644); 206 MODULE_PARM_DESC(align_buffer_size, 207 "Force buffer and period sizes to be multiple of 128 bytes."); 208 209 #ifdef CONFIG_X86 210 static int hda_snoop = -1; 211 module_param_named(snoop, hda_snoop, bint, 0444); 212 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 213 #else 214 #define hda_snoop true 215 #endif 216 217 218 MODULE_LICENSE("GPL"); 219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 220 "{Intel, ICH6M}," 221 "{Intel, ICH7}," 222 "{Intel, ESB2}," 223 "{Intel, ICH8}," 224 "{Intel, ICH9}," 225 "{Intel, ICH10}," 226 "{Intel, PCH}," 227 "{Intel, CPT}," 228 "{Intel, PPT}," 229 "{Intel, LPT}," 230 "{Intel, LPT_LP}," 231 "{Intel, WPT_LP}," 232 "{Intel, SPT}," 233 "{Intel, SPT_LP}," 234 "{Intel, HPT}," 235 "{Intel, PBG}," 236 "{Intel, SCH}," 237 "{ATI, SB450}," 238 "{ATI, SB600}," 239 "{ATI, RS600}," 240 "{ATI, RS690}," 241 "{ATI, RS780}," 242 "{ATI, R600}," 243 "{ATI, RV630}," 244 "{ATI, RV610}," 245 "{ATI, RV670}," 246 "{ATI, RV635}," 247 "{ATI, RV620}," 248 "{ATI, RV770}," 249 "{VIA, VT8251}," 250 "{VIA, VT8237A}," 251 "{SiS, SIS966}," 252 "{ULI, M5461}}"); 253 MODULE_DESCRIPTION("Intel HDA driver"); 254 255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 257 #define SUPPORT_VGA_SWITCHEROO 258 #endif 259 #endif 260 261 262 /* 263 */ 264 265 /* driver types */ 266 enum { 267 AZX_DRIVER_ICH, 268 AZX_DRIVER_PCH, 269 AZX_DRIVER_SCH, 270 AZX_DRIVER_SKL, 271 AZX_DRIVER_HDMI, 272 AZX_DRIVER_ATI, 273 AZX_DRIVER_ATIHDMI, 274 AZX_DRIVER_ATIHDMI_NS, 275 AZX_DRIVER_VIA, 276 AZX_DRIVER_SIS, 277 AZX_DRIVER_ULI, 278 AZX_DRIVER_NVIDIA, 279 AZX_DRIVER_TERA, 280 AZX_DRIVER_CTX, 281 AZX_DRIVER_CTHDA, 282 AZX_DRIVER_CMEDIA, 283 AZX_DRIVER_GENERIC, 284 AZX_NUM_DRIVERS, /* keep this as last entry */ 285 }; 286 287 #define azx_get_snoop_type(chip) \ 288 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 290 291 /* quirks for old Intel chipsets */ 292 #define AZX_DCAPS_INTEL_ICH \ 293 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 294 295 /* quirks for Intel PCH */ 296 #define AZX_DCAPS_INTEL_PCH_BASE \ 297 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 298 AZX_DCAPS_SNOOP_TYPE(SCH)) 299 300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 301 #define AZX_DCAPS_INTEL_PCH_NOPM \ 302 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 303 304 /* PCH for HSW/BDW; with runtime PM */ 305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 306 #define AZX_DCAPS_INTEL_PCH \ 307 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 308 309 /* HSW HDMI */ 310 #define AZX_DCAPS_INTEL_HASWELL \ 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 313 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH)) 314 315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 316 #define AZX_DCAPS_INTEL_BROADWELL \ 317 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 318 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 319 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH)) 320 321 #define AZX_DCAPS_INTEL_BAYTRAIL \ 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\ 323 AZX_DCAPS_I915_POWERWELL) 324 325 #define AZX_DCAPS_INTEL_BRASWELL \ 326 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 327 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL) 328 329 #define AZX_DCAPS_INTEL_SKYLAKE \ 330 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 331 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\ 332 AZX_DCAPS_I915_POWERWELL) 333 334 #define AZX_DCAPS_INTEL_BROXTON \ 335 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 336 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\ 337 AZX_DCAPS_I915_POWERWELL) 338 339 /* quirks for ATI SB / AMD Hudson */ 340 #define AZX_DCAPS_PRESET_ATI_SB \ 341 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 342 AZX_DCAPS_SNOOP_TYPE(ATI)) 343 344 /* quirks for ATI/AMD HDMI */ 345 #define AZX_DCAPS_PRESET_ATI_HDMI \ 346 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 347 AZX_DCAPS_NO_MSI64) 348 349 /* quirks for ATI HDMI with snoop off */ 350 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 351 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 352 353 /* quirks for Nvidia */ 354 #define AZX_DCAPS_PRESET_NVIDIA \ 355 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 356 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 357 358 #define AZX_DCAPS_PRESET_CTHDA \ 359 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 360 AZX_DCAPS_NO_64BIT |\ 361 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 362 363 /* 364 * vga_switcheroo support 365 */ 366 #ifdef SUPPORT_VGA_SWITCHEROO 367 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 368 #define needs_eld_notify_link(chip) ((chip)->need_eld_notify_link) 369 #else 370 #define use_vga_switcheroo(chip) 0 371 #define needs_eld_notify_link(chip) false 372 #endif 373 374 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 375 ((pci)->device == 0x0c0c) || \ 376 ((pci)->device == 0x0d0c) || \ 377 ((pci)->device == 0x160c)) 378 379 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 380 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348) 381 382 static char *driver_short_names[] = { 383 [AZX_DRIVER_ICH] = "HDA Intel", 384 [AZX_DRIVER_PCH] = "HDA Intel PCH", 385 [AZX_DRIVER_SCH] = "HDA Intel MID", 386 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 387 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 388 [AZX_DRIVER_ATI] = "HDA ATI SB", 389 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 390 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 391 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 392 [AZX_DRIVER_SIS] = "HDA SIS966", 393 [AZX_DRIVER_ULI] = "HDA ULI M5461", 394 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 395 [AZX_DRIVER_TERA] = "HDA Teradici", 396 [AZX_DRIVER_CTX] = "HDA Creative", 397 [AZX_DRIVER_CTHDA] = "HDA Creative", 398 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 399 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 400 }; 401 402 #ifdef CONFIG_X86 403 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 404 { 405 int pages; 406 407 if (azx_snoop(chip)) 408 return; 409 if (!dmab || !dmab->area || !dmab->bytes) 410 return; 411 412 #ifdef CONFIG_SND_DMA_SGBUF 413 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 414 struct snd_sg_buf *sgbuf = dmab->private_data; 415 if (chip->driver_type == AZX_DRIVER_CMEDIA) 416 return; /* deal with only CORB/RIRB buffers */ 417 if (on) 418 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 419 else 420 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 421 return; 422 } 423 #endif 424 425 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 426 if (on) 427 set_memory_wc((unsigned long)dmab->area, pages); 428 else 429 set_memory_wb((unsigned long)dmab->area, pages); 430 } 431 432 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 433 bool on) 434 { 435 __mark_pages_wc(chip, buf, on); 436 } 437 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 438 struct snd_pcm_substream *substream, bool on) 439 { 440 if (azx_dev->wc_marked != on) { 441 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 442 azx_dev->wc_marked = on; 443 } 444 } 445 #else 446 /* NOP for other archs */ 447 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 448 bool on) 449 { 450 } 451 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 452 struct snd_pcm_substream *substream, bool on) 453 { 454 } 455 #endif 456 457 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 458 static void set_default_power_save(struct azx *chip); 459 460 /* 461 * initialize the PCI registers 462 */ 463 /* update bits in a PCI register byte */ 464 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 465 unsigned char mask, unsigned char val) 466 { 467 unsigned char data; 468 469 pci_read_config_byte(pci, reg, &data); 470 data &= ~mask; 471 data |= (val & mask); 472 pci_write_config_byte(pci, reg, data); 473 } 474 475 static void azx_init_pci(struct azx *chip) 476 { 477 int snoop_type = azx_get_snoop_type(chip); 478 479 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 480 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 481 * Ensuring these bits are 0 clears playback static on some HD Audio 482 * codecs. 483 * The PCI register TCSEL is defined in the Intel manuals. 484 */ 485 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 486 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 487 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 488 } 489 490 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 491 * we need to enable snoop. 492 */ 493 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 494 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 495 azx_snoop(chip)); 496 update_pci_byte(chip->pci, 497 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 498 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 499 } 500 501 /* For NVIDIA HDA, enable snoop */ 502 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 503 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 504 azx_snoop(chip)); 505 update_pci_byte(chip->pci, 506 NVIDIA_HDA_TRANSREG_ADDR, 507 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 508 update_pci_byte(chip->pci, 509 NVIDIA_HDA_ISTRM_COH, 510 0x01, NVIDIA_HDA_ENABLE_COHBIT); 511 update_pci_byte(chip->pci, 512 NVIDIA_HDA_OSTRM_COH, 513 0x01, NVIDIA_HDA_ENABLE_COHBIT); 514 } 515 516 /* Enable SCH/PCH snoop if needed */ 517 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 518 unsigned short snoop; 519 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 520 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 521 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 522 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 523 if (!azx_snoop(chip)) 524 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 525 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 526 pci_read_config_word(chip->pci, 527 INTEL_SCH_HDA_DEVC, &snoop); 528 } 529 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 530 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 531 "Disabled" : "Enabled"); 532 } 533 } 534 535 /* 536 * In BXT-P A0, HD-Audio DMA requests is later than expected, 537 * and makes an audio stream sensitive to system latencies when 538 * 24/32 bits are playing. 539 * Adjusting threshold of DMA fifo to force the DMA request 540 * sooner to improve latency tolerance at the expense of power. 541 */ 542 static void bxt_reduce_dma_latency(struct azx *chip) 543 { 544 u32 val; 545 546 val = azx_readl(chip, VS_EM4L); 547 val &= (0x3 << 20); 548 azx_writel(chip, VS_EM4L, val); 549 } 550 551 /* 552 * ML_LCAP bits: 553 * bit 0: 6 MHz Supported 554 * bit 1: 12 MHz Supported 555 * bit 2: 24 MHz Supported 556 * bit 3: 48 MHz Supported 557 * bit 4: 96 MHz Supported 558 * bit 5: 192 MHz Supported 559 */ 560 static int intel_get_lctl_scf(struct azx *chip) 561 { 562 struct hdac_bus *bus = azx_bus(chip); 563 static int preferred_bits[] = { 2, 3, 1, 4, 5 }; 564 u32 val, t; 565 int i; 566 567 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 568 569 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 570 t = preferred_bits[i]; 571 if (val & (1 << t)) 572 return t; 573 } 574 575 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 576 return 0; 577 } 578 579 static int intel_ml_lctl_set_power(struct azx *chip, int state) 580 { 581 struct hdac_bus *bus = azx_bus(chip); 582 u32 val; 583 int timeout; 584 585 /* 586 * the codecs are sharing the first link setting by default 587 * If other links are enabled for stream, they need similar fix 588 */ 589 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 590 val &= ~AZX_MLCTL_SPA; 591 val |= state << AZX_MLCTL_SPA_SHIFT; 592 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 593 /* wait for CPA */ 594 timeout = 50; 595 while (timeout) { 596 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 597 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 598 return 0; 599 timeout--; 600 udelay(10); 601 } 602 603 return -1; 604 } 605 606 static void intel_init_lctl(struct azx *chip) 607 { 608 struct hdac_bus *bus = azx_bus(chip); 609 u32 val; 610 int ret; 611 612 /* 0. check lctl register value is correct or not */ 613 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 614 /* if SCF is already set, let's use it */ 615 if ((val & ML_LCTL_SCF_MASK) != 0) 616 return; 617 618 /* 619 * Before operating on SPA, CPA must match SPA. 620 * Any deviation may result in undefined behavior. 621 */ 622 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 623 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 624 return; 625 626 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 627 ret = intel_ml_lctl_set_power(chip, 0); 628 udelay(100); 629 if (ret) 630 goto set_spa; 631 632 /* 2. update SCF to select a properly audio clock*/ 633 val &= ~ML_LCTL_SCF_MASK; 634 val |= intel_get_lctl_scf(chip); 635 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 636 637 set_spa: 638 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 639 intel_ml_lctl_set_power(chip, 1); 640 udelay(100); 641 } 642 643 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 644 { 645 struct hdac_bus *bus = azx_bus(chip); 646 struct pci_dev *pci = chip->pci; 647 u32 val; 648 649 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 650 snd_hdac_set_codec_wakeup(bus, true); 651 if (chip->driver_type == AZX_DRIVER_SKL) { 652 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 653 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 654 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 655 } 656 azx_init_chip(chip, full_reset); 657 if (chip->driver_type == AZX_DRIVER_SKL) { 658 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 659 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 660 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 661 } 662 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 663 snd_hdac_set_codec_wakeup(bus, false); 664 665 /* reduce dma latency to avoid noise */ 666 if (IS_BXT(pci)) 667 bxt_reduce_dma_latency(chip); 668 669 if (bus->mlcap != NULL) 670 intel_init_lctl(chip); 671 } 672 673 /* calculate runtime delay from LPIB */ 674 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 675 unsigned int pos) 676 { 677 struct snd_pcm_substream *substream = azx_dev->core.substream; 678 int stream = substream->stream; 679 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 680 int delay; 681 682 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 683 delay = pos - lpib_pos; 684 else 685 delay = lpib_pos - pos; 686 if (delay < 0) { 687 if (delay >= azx_dev->core.delay_negative_threshold) 688 delay = 0; 689 else 690 delay += azx_dev->core.bufsize; 691 } 692 693 if (delay >= azx_dev->core.period_bytes) { 694 dev_info(chip->card->dev, 695 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 696 delay, azx_dev->core.period_bytes); 697 delay = 0; 698 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 699 chip->get_delay[stream] = NULL; 700 } 701 702 return bytes_to_frames(substream->runtime, delay); 703 } 704 705 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 706 707 /* called from IRQ */ 708 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 709 { 710 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 711 int ok; 712 713 ok = azx_position_ok(chip, azx_dev); 714 if (ok == 1) { 715 azx_dev->irq_pending = 0; 716 return ok; 717 } else if (ok == 0) { 718 /* bogus IRQ, process it later */ 719 azx_dev->irq_pending = 1; 720 schedule_work(&hda->irq_pending_work); 721 } 722 return 0; 723 } 724 725 /* Enable/disable i915 display power for the link */ 726 static int azx_intel_link_power(struct azx *chip, bool enable) 727 { 728 struct hdac_bus *bus = azx_bus(chip); 729 730 return snd_hdac_display_power(bus, enable); 731 } 732 733 /* 734 * Check whether the current DMA position is acceptable for updating 735 * periods. Returns non-zero if it's OK. 736 * 737 * Many HD-audio controllers appear pretty inaccurate about 738 * the update-IRQ timing. The IRQ is issued before actually the 739 * data is processed. So, we need to process it afterwords in a 740 * workqueue. 741 */ 742 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 743 { 744 struct snd_pcm_substream *substream = azx_dev->core.substream; 745 int stream = substream->stream; 746 u32 wallclk; 747 unsigned int pos; 748 749 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 750 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 751 return -1; /* bogus (too early) interrupt */ 752 753 if (chip->get_position[stream]) 754 pos = chip->get_position[stream](chip, azx_dev); 755 else { /* use the position buffer as default */ 756 pos = azx_get_pos_posbuf(chip, azx_dev); 757 if (!pos || pos == (u32)-1) { 758 dev_info(chip->card->dev, 759 "Invalid position buffer, using LPIB read method instead.\n"); 760 chip->get_position[stream] = azx_get_pos_lpib; 761 if (chip->get_position[0] == azx_get_pos_lpib && 762 chip->get_position[1] == azx_get_pos_lpib) 763 azx_bus(chip)->use_posbuf = false; 764 pos = azx_get_pos_lpib(chip, azx_dev); 765 chip->get_delay[stream] = NULL; 766 } else { 767 chip->get_position[stream] = azx_get_pos_posbuf; 768 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 769 chip->get_delay[stream] = azx_get_delay_from_lpib; 770 } 771 } 772 773 if (pos >= azx_dev->core.bufsize) 774 pos = 0; 775 776 if (WARN_ONCE(!azx_dev->core.period_bytes, 777 "hda-intel: zero azx_dev->period_bytes")) 778 return -1; /* this shouldn't happen! */ 779 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 780 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 781 /* NG - it's below the first next period boundary */ 782 return chip->bdl_pos_adj ? 0 : -1; 783 azx_dev->core.start_wallclk += wallclk; 784 return 1; /* OK, it's fine */ 785 } 786 787 /* 788 * The work for pending PCM period updates. 789 */ 790 static void azx_irq_pending_work(struct work_struct *work) 791 { 792 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 793 struct azx *chip = &hda->chip; 794 struct hdac_bus *bus = azx_bus(chip); 795 struct hdac_stream *s; 796 int pending, ok; 797 798 if (!hda->irq_pending_warned) { 799 dev_info(chip->card->dev, 800 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 801 chip->card->number); 802 hda->irq_pending_warned = 1; 803 } 804 805 for (;;) { 806 pending = 0; 807 spin_lock_irq(&bus->reg_lock); 808 list_for_each_entry(s, &bus->stream_list, list) { 809 struct azx_dev *azx_dev = stream_to_azx_dev(s); 810 if (!azx_dev->irq_pending || 811 !s->substream || 812 !s->running) 813 continue; 814 ok = azx_position_ok(chip, azx_dev); 815 if (ok > 0) { 816 azx_dev->irq_pending = 0; 817 spin_unlock(&bus->reg_lock); 818 snd_pcm_period_elapsed(s->substream); 819 spin_lock(&bus->reg_lock); 820 } else if (ok < 0) { 821 pending = 0; /* too early */ 822 } else 823 pending++; 824 } 825 spin_unlock_irq(&bus->reg_lock); 826 if (!pending) 827 return; 828 msleep(1); 829 } 830 } 831 832 /* clear irq_pending flags and assure no on-going workq */ 833 static void azx_clear_irq_pending(struct azx *chip) 834 { 835 struct hdac_bus *bus = azx_bus(chip); 836 struct hdac_stream *s; 837 838 spin_lock_irq(&bus->reg_lock); 839 list_for_each_entry(s, &bus->stream_list, list) { 840 struct azx_dev *azx_dev = stream_to_azx_dev(s); 841 azx_dev->irq_pending = 0; 842 } 843 spin_unlock_irq(&bus->reg_lock); 844 } 845 846 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 847 { 848 struct hdac_bus *bus = azx_bus(chip); 849 850 if (request_irq(chip->pci->irq, azx_interrupt, 851 chip->msi ? 0 : IRQF_SHARED, 852 chip->card->irq_descr, chip)) { 853 dev_err(chip->card->dev, 854 "unable to grab IRQ %d, disabling device\n", 855 chip->pci->irq); 856 if (do_disconnect) 857 snd_card_disconnect(chip->card); 858 return -1; 859 } 860 bus->irq = chip->pci->irq; 861 pci_intx(chip->pci, !chip->msi); 862 return 0; 863 } 864 865 /* get the current DMA position with correction on VIA chips */ 866 static unsigned int azx_via_get_position(struct azx *chip, 867 struct azx_dev *azx_dev) 868 { 869 unsigned int link_pos, mini_pos, bound_pos; 870 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 871 unsigned int fifo_size; 872 873 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 874 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 875 /* Playback, no problem using link position */ 876 return link_pos; 877 } 878 879 /* Capture */ 880 /* For new chipset, 881 * use mod to get the DMA position just like old chipset 882 */ 883 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 884 mod_dma_pos %= azx_dev->core.period_bytes; 885 886 /* azx_dev->fifo_size can't get FIFO size of in stream. 887 * Get from base address + offset. 888 */ 889 fifo_size = readw(azx_bus(chip)->remap_addr + 890 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 891 892 if (azx_dev->insufficient) { 893 /* Link position never gather than FIFO size */ 894 if (link_pos <= fifo_size) 895 return 0; 896 897 azx_dev->insufficient = 0; 898 } 899 900 if (link_pos <= fifo_size) 901 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 902 else 903 mini_pos = link_pos - fifo_size; 904 905 /* Find nearest previous boudary */ 906 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 907 mod_link_pos = link_pos % azx_dev->core.period_bytes; 908 if (mod_link_pos >= fifo_size) 909 bound_pos = link_pos - mod_link_pos; 910 else if (mod_dma_pos >= mod_mini_pos) 911 bound_pos = mini_pos - mod_mini_pos; 912 else { 913 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 914 if (bound_pos >= azx_dev->core.bufsize) 915 bound_pos = 0; 916 } 917 918 /* Calculate real DMA position we want */ 919 return bound_pos + mod_dma_pos; 920 } 921 922 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 923 struct azx_dev *azx_dev) 924 { 925 return _snd_hdac_chip_readl(azx_bus(chip), 926 AZX_REG_VS_SDXDPIB_XBASE + 927 (AZX_REG_VS_SDXDPIB_XINTERVAL * 928 azx_dev->core.index)); 929 } 930 931 /* get the current DMA position with correction on SKL+ chips */ 932 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 933 { 934 /* DPIB register gives a more accurate position for playback */ 935 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 936 return azx_skl_get_dpib_pos(chip, azx_dev); 937 938 /* For capture, we need to read posbuf, but it requires a delay 939 * for the possible boundary overlap; the read of DPIB fetches the 940 * actual posbuf 941 */ 942 udelay(20); 943 azx_skl_get_dpib_pos(chip, azx_dev); 944 return azx_get_pos_posbuf(chip, azx_dev); 945 } 946 947 #ifdef CONFIG_PM 948 static DEFINE_MUTEX(card_list_lock); 949 static LIST_HEAD(card_list); 950 951 static void azx_add_card_list(struct azx *chip) 952 { 953 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 954 mutex_lock(&card_list_lock); 955 list_add(&hda->list, &card_list); 956 mutex_unlock(&card_list_lock); 957 } 958 959 static void azx_del_card_list(struct azx *chip) 960 { 961 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 962 mutex_lock(&card_list_lock); 963 list_del_init(&hda->list); 964 mutex_unlock(&card_list_lock); 965 } 966 967 /* trigger power-save check at writing parameter */ 968 static int param_set_xint(const char *val, const struct kernel_param *kp) 969 { 970 struct hda_intel *hda; 971 struct azx *chip; 972 int prev = power_save; 973 int ret = param_set_int(val, kp); 974 975 if (ret || prev == power_save) 976 return ret; 977 978 mutex_lock(&card_list_lock); 979 list_for_each_entry(hda, &card_list, list) { 980 chip = &hda->chip; 981 if (!hda->probe_continued || chip->disabled) 982 continue; 983 snd_hda_set_power_save(&chip->bus, power_save * 1000); 984 } 985 mutex_unlock(&card_list_lock); 986 return 0; 987 } 988 #else 989 #define azx_add_card_list(chip) /* NOP */ 990 #define azx_del_card_list(chip) /* NOP */ 991 #endif /* CONFIG_PM */ 992 993 #ifdef CONFIG_PM_SLEEP 994 /* 995 * power management 996 */ 997 static int azx_suspend(struct device *dev) 998 { 999 struct snd_card *card = dev_get_drvdata(dev); 1000 struct azx *chip; 1001 struct hda_intel *hda; 1002 struct hdac_bus *bus; 1003 1004 if (!card) 1005 return 0; 1006 1007 chip = card->private_data; 1008 hda = container_of(chip, struct hda_intel, chip); 1009 if (chip->disabled || hda->init_failed || !chip->running) 1010 return 0; 1011 1012 bus = azx_bus(chip); 1013 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1014 azx_clear_irq_pending(chip); 1015 azx_stop_chip(chip); 1016 azx_enter_link_reset(chip); 1017 if (bus->irq >= 0) { 1018 free_irq(bus->irq, chip); 1019 bus->irq = -1; 1020 } 1021 1022 if (chip->msi) 1023 pci_disable_msi(chip->pci); 1024 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1025 && hda->need_i915_power) 1026 snd_hdac_display_power(bus, false); 1027 1028 trace_azx_suspend(chip); 1029 return 0; 1030 } 1031 1032 static int azx_resume(struct device *dev) 1033 { 1034 struct pci_dev *pci = to_pci_dev(dev); 1035 struct snd_card *card = dev_get_drvdata(dev); 1036 struct azx *chip; 1037 struct hda_intel *hda; 1038 struct hdac_bus *bus; 1039 1040 if (!card) 1041 return 0; 1042 1043 chip = card->private_data; 1044 hda = container_of(chip, struct hda_intel, chip); 1045 bus = azx_bus(chip); 1046 if (chip->disabled || hda->init_failed || !chip->running) 1047 return 0; 1048 1049 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1050 snd_hdac_display_power(bus, true); 1051 if (hda->need_i915_power) 1052 snd_hdac_i915_set_bclk(bus); 1053 } 1054 1055 if (chip->msi) 1056 if (pci_enable_msi(pci) < 0) 1057 chip->msi = 0; 1058 if (azx_acquire_irq(chip, 1) < 0) 1059 return -EIO; 1060 azx_init_pci(chip); 1061 1062 hda_intel_init_chip(chip, true); 1063 1064 /* power down again for link-controlled chips */ 1065 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) && 1066 !hda->need_i915_power) 1067 snd_hdac_display_power(bus, false); 1068 1069 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1070 1071 trace_azx_resume(chip); 1072 return 0; 1073 } 1074 1075 /* put codec down to D3 at hibernation for Intel SKL+; 1076 * otherwise BIOS may still access the codec and screw up the driver 1077 */ 1078 static int azx_freeze_noirq(struct device *dev) 1079 { 1080 struct snd_card *card = dev_get_drvdata(dev); 1081 struct azx *chip = card->private_data; 1082 struct pci_dev *pci = to_pci_dev(dev); 1083 1084 if (chip->driver_type == AZX_DRIVER_SKL) 1085 pci_set_power_state(pci, PCI_D3hot); 1086 1087 return 0; 1088 } 1089 1090 static int azx_thaw_noirq(struct device *dev) 1091 { 1092 struct snd_card *card = dev_get_drvdata(dev); 1093 struct azx *chip = card->private_data; 1094 struct pci_dev *pci = to_pci_dev(dev); 1095 1096 if (chip->driver_type == AZX_DRIVER_SKL) 1097 pci_set_power_state(pci, PCI_D0); 1098 1099 return 0; 1100 } 1101 #endif /* CONFIG_PM_SLEEP */ 1102 1103 #ifdef CONFIG_PM 1104 static int azx_runtime_suspend(struct device *dev) 1105 { 1106 struct snd_card *card = dev_get_drvdata(dev); 1107 struct azx *chip; 1108 struct hda_intel *hda; 1109 1110 if (!card) 1111 return 0; 1112 1113 chip = card->private_data; 1114 hda = container_of(chip, struct hda_intel, chip); 1115 if (chip->disabled || hda->init_failed) 1116 return 0; 1117 1118 if (!azx_has_pm_runtime(chip)) 1119 return 0; 1120 1121 /* enable controller wake up event */ 1122 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1123 STATESTS_INT_MASK); 1124 1125 azx_stop_chip(chip); 1126 azx_enter_link_reset(chip); 1127 azx_clear_irq_pending(chip); 1128 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1129 && hda->need_i915_power) 1130 snd_hdac_display_power(azx_bus(chip), false); 1131 1132 trace_azx_runtime_suspend(chip); 1133 return 0; 1134 } 1135 1136 static int azx_runtime_resume(struct device *dev) 1137 { 1138 struct snd_card *card = dev_get_drvdata(dev); 1139 struct azx *chip; 1140 struct hda_intel *hda; 1141 struct hdac_bus *bus; 1142 struct hda_codec *codec; 1143 int status; 1144 1145 if (!card) 1146 return 0; 1147 1148 chip = card->private_data; 1149 hda = container_of(chip, struct hda_intel, chip); 1150 bus = azx_bus(chip); 1151 if (chip->disabled || hda->init_failed) 1152 return 0; 1153 1154 if (!azx_has_pm_runtime(chip)) 1155 return 0; 1156 1157 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1158 snd_hdac_display_power(bus, true); 1159 if (hda->need_i915_power) 1160 snd_hdac_i915_set_bclk(bus); 1161 } 1162 1163 /* Read STATESTS before controller reset */ 1164 status = azx_readw(chip, STATESTS); 1165 1166 azx_init_pci(chip); 1167 hda_intel_init_chip(chip, true); 1168 1169 if (status) { 1170 list_for_each_codec(codec, &chip->bus) 1171 if (status & (1 << codec->addr)) 1172 schedule_delayed_work(&codec->jackpoll_work, 1173 codec->jackpoll_interval); 1174 } 1175 1176 /* disable controller Wake Up event*/ 1177 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1178 ~STATESTS_INT_MASK); 1179 1180 /* power down again for link-controlled chips */ 1181 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) && 1182 !hda->need_i915_power) 1183 snd_hdac_display_power(bus, false); 1184 1185 trace_azx_runtime_resume(chip); 1186 return 0; 1187 } 1188 1189 static int azx_runtime_idle(struct device *dev) 1190 { 1191 struct snd_card *card = dev_get_drvdata(dev); 1192 struct azx *chip; 1193 struct hda_intel *hda; 1194 1195 if (!card) 1196 return 0; 1197 1198 chip = card->private_data; 1199 hda = container_of(chip, struct hda_intel, chip); 1200 if (chip->disabled || hda->init_failed) 1201 return 0; 1202 1203 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1204 azx_bus(chip)->codec_powered || !chip->running) 1205 return -EBUSY; 1206 1207 /* ELD notification gets broken when HD-audio bus is off */ 1208 if (needs_eld_notify_link(hda)) 1209 return -EBUSY; 1210 1211 return 0; 1212 } 1213 1214 static const struct dev_pm_ops azx_pm = { 1215 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1216 #ifdef CONFIG_PM_SLEEP 1217 .freeze_noirq = azx_freeze_noirq, 1218 .thaw_noirq = azx_thaw_noirq, 1219 #endif 1220 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1221 }; 1222 1223 #define AZX_PM_OPS &azx_pm 1224 #else 1225 #define AZX_PM_OPS NULL 1226 #endif /* CONFIG_PM */ 1227 1228 1229 static int azx_probe_continue(struct azx *chip); 1230 1231 #ifdef SUPPORT_VGA_SWITCHEROO 1232 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1233 1234 static void azx_vs_set_state(struct pci_dev *pci, 1235 enum vga_switcheroo_state state) 1236 { 1237 struct snd_card *card = pci_get_drvdata(pci); 1238 struct azx *chip = card->private_data; 1239 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1240 struct hda_codec *codec; 1241 bool disabled; 1242 1243 wait_for_completion(&hda->probe_wait); 1244 if (hda->init_failed) 1245 return; 1246 1247 disabled = (state == VGA_SWITCHEROO_OFF); 1248 if (chip->disabled == disabled) 1249 return; 1250 1251 if (!hda->probe_continued) { 1252 chip->disabled = disabled; 1253 if (!disabled) { 1254 dev_info(chip->card->dev, 1255 "Start delayed initialization\n"); 1256 if (azx_probe_continue(chip) < 0) { 1257 dev_err(chip->card->dev, "initialization error\n"); 1258 hda->init_failed = true; 1259 } 1260 } 1261 } else { 1262 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1263 disabled ? "Disabling" : "Enabling"); 1264 if (disabled) { 1265 list_for_each_codec(codec, &chip->bus) { 1266 pm_runtime_suspend(hda_codec_dev(codec)); 1267 pm_runtime_disable(hda_codec_dev(codec)); 1268 } 1269 pm_runtime_suspend(card->dev); 1270 pm_runtime_disable(card->dev); 1271 /* when we get suspended by vga_switcheroo we end up in D3cold, 1272 * however we have no ACPI handle, so pci/acpi can't put us there, 1273 * put ourselves there */ 1274 pci->current_state = PCI_D3cold; 1275 chip->disabled = true; 1276 if (snd_hda_lock_devices(&chip->bus)) 1277 dev_warn(chip->card->dev, 1278 "Cannot lock devices!\n"); 1279 } else { 1280 snd_hda_unlock_devices(&chip->bus); 1281 chip->disabled = false; 1282 pm_runtime_enable(card->dev); 1283 list_for_each_codec(codec, &chip->bus) { 1284 pm_runtime_enable(hda_codec_dev(codec)); 1285 pm_runtime_resume(hda_codec_dev(codec)); 1286 } 1287 } 1288 } 1289 } 1290 1291 static bool azx_vs_can_switch(struct pci_dev *pci) 1292 { 1293 struct snd_card *card = pci_get_drvdata(pci); 1294 struct azx *chip = card->private_data; 1295 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1296 1297 wait_for_completion(&hda->probe_wait); 1298 if (hda->init_failed) 1299 return false; 1300 if (chip->disabled || !hda->probe_continued) 1301 return true; 1302 if (snd_hda_lock_devices(&chip->bus)) 1303 return false; 1304 snd_hda_unlock_devices(&chip->bus); 1305 return true; 1306 } 1307 1308 /* 1309 * The discrete GPU cannot power down unless the HDA controller runtime 1310 * suspends, so activate runtime PM on codecs even if power_save == 0. 1311 */ 1312 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1313 { 1314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1315 struct hda_codec *codec; 1316 1317 if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) { 1318 list_for_each_codec(codec, &chip->bus) 1319 codec->auto_runtime_pm = 1; 1320 /* reset the power save setup */ 1321 if (chip->running) 1322 set_default_power_save(chip); 1323 } 1324 } 1325 1326 static void azx_vs_gpu_bound(struct pci_dev *pci, 1327 enum vga_switcheroo_client_id client_id) 1328 { 1329 struct snd_card *card = pci_get_drvdata(pci); 1330 struct azx *chip = card->private_data; 1331 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1332 1333 if (client_id == VGA_SWITCHEROO_DIS) 1334 hda->need_eld_notify_link = 0; 1335 setup_vga_switcheroo_runtime_pm(chip); 1336 } 1337 1338 static void init_vga_switcheroo(struct azx *chip) 1339 { 1340 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1341 struct pci_dev *p = get_bound_vga(chip->pci); 1342 if (p) { 1343 dev_info(chip->card->dev, 1344 "Handle vga_switcheroo audio client\n"); 1345 hda->use_vga_switcheroo = 1; 1346 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */ 1347 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1348 pci_dev_put(p); 1349 } 1350 } 1351 1352 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1353 .set_gpu_state = azx_vs_set_state, 1354 .can_switch = azx_vs_can_switch, 1355 .gpu_bound = azx_vs_gpu_bound, 1356 }; 1357 1358 static int register_vga_switcheroo(struct azx *chip) 1359 { 1360 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1361 struct pci_dev *p; 1362 int err; 1363 1364 if (!hda->use_vga_switcheroo) 1365 return 0; 1366 1367 p = get_bound_vga(chip->pci); 1368 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1369 pci_dev_put(p); 1370 1371 if (err < 0) 1372 return err; 1373 hda->vga_switcheroo_registered = 1; 1374 1375 return 0; 1376 } 1377 #else 1378 #define init_vga_switcheroo(chip) /* NOP */ 1379 #define register_vga_switcheroo(chip) 0 1380 #define check_hdmi_disabled(pci) false 1381 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1382 #endif /* SUPPORT_VGA_SWITCHER */ 1383 1384 /* 1385 * destructor 1386 */ 1387 static int azx_free(struct azx *chip) 1388 { 1389 struct pci_dev *pci = chip->pci; 1390 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1391 struct hdac_bus *bus = azx_bus(chip); 1392 1393 if (azx_has_pm_runtime(chip) && chip->running) 1394 pm_runtime_get_noresume(&pci->dev); 1395 chip->running = 0; 1396 1397 azx_del_card_list(chip); 1398 1399 hda->init_failed = 1; /* to be sure */ 1400 complete_all(&hda->probe_wait); 1401 1402 if (use_vga_switcheroo(hda)) { 1403 if (chip->disabled && hda->probe_continued) 1404 snd_hda_unlock_devices(&chip->bus); 1405 if (hda->vga_switcheroo_registered) 1406 vga_switcheroo_unregister_client(chip->pci); 1407 } 1408 1409 if (bus->chip_init) { 1410 azx_clear_irq_pending(chip); 1411 azx_stop_all_streams(chip); 1412 azx_stop_chip(chip); 1413 } 1414 1415 if (bus->irq >= 0) 1416 free_irq(bus->irq, (void*)chip); 1417 if (chip->msi) 1418 pci_disable_msi(chip->pci); 1419 iounmap(bus->remap_addr); 1420 1421 azx_free_stream_pages(chip); 1422 azx_free_streams(chip); 1423 snd_hdac_bus_exit(bus); 1424 1425 if (chip->region_requested) 1426 pci_release_regions(chip->pci); 1427 1428 pci_disable_device(chip->pci); 1429 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1430 release_firmware(chip->fw); 1431 #endif 1432 1433 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1434 if (hda->need_i915_power) 1435 snd_hdac_display_power(bus, false); 1436 } 1437 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1438 snd_hdac_i915_exit(bus); 1439 kfree(hda); 1440 1441 return 0; 1442 } 1443 1444 static int azx_dev_disconnect(struct snd_device *device) 1445 { 1446 struct azx *chip = device->device_data; 1447 1448 chip->bus.shutdown = 1; 1449 return 0; 1450 } 1451 1452 static int azx_dev_free(struct snd_device *device) 1453 { 1454 return azx_free(device->device_data); 1455 } 1456 1457 #ifdef SUPPORT_VGA_SWITCHEROO 1458 /* 1459 * Check of disabled HDMI controller by vga_switcheroo 1460 */ 1461 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1462 { 1463 struct pci_dev *p; 1464 1465 /* check only discrete GPU */ 1466 switch (pci->vendor) { 1467 case PCI_VENDOR_ID_ATI: 1468 case PCI_VENDOR_ID_AMD: 1469 case PCI_VENDOR_ID_NVIDIA: 1470 if (pci->devfn == 1) { 1471 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1472 pci->bus->number, 0); 1473 if (p) { 1474 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1475 return p; 1476 pci_dev_put(p); 1477 } 1478 } 1479 break; 1480 } 1481 return NULL; 1482 } 1483 1484 static bool check_hdmi_disabled(struct pci_dev *pci) 1485 { 1486 bool vga_inactive = false; 1487 struct pci_dev *p = get_bound_vga(pci); 1488 1489 if (p) { 1490 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1491 vga_inactive = true; 1492 pci_dev_put(p); 1493 } 1494 return vga_inactive; 1495 } 1496 #endif /* SUPPORT_VGA_SWITCHEROO */ 1497 1498 /* 1499 * white/black-listing for position_fix 1500 */ 1501 static struct snd_pci_quirk position_fix_list[] = { 1502 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1503 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1504 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1505 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1506 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1507 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1508 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1510 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1511 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1512 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1516 {} 1517 }; 1518 1519 static int check_position_fix(struct azx *chip, int fix) 1520 { 1521 const struct snd_pci_quirk *q; 1522 1523 switch (fix) { 1524 case POS_FIX_AUTO: 1525 case POS_FIX_LPIB: 1526 case POS_FIX_POSBUF: 1527 case POS_FIX_VIACOMBO: 1528 case POS_FIX_COMBO: 1529 case POS_FIX_SKL: 1530 return fix; 1531 } 1532 1533 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1534 if (q) { 1535 dev_info(chip->card->dev, 1536 "position_fix set to %d for device %04x:%04x\n", 1537 q->value, q->subvendor, q->subdevice); 1538 return q->value; 1539 } 1540 1541 /* Check VIA/ATI HD Audio Controller exist */ 1542 if (chip->driver_type == AZX_DRIVER_VIA) { 1543 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1544 return POS_FIX_VIACOMBO; 1545 } 1546 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1547 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1548 return POS_FIX_LPIB; 1549 } 1550 if (chip->driver_type == AZX_DRIVER_SKL) { 1551 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1552 return POS_FIX_SKL; 1553 } 1554 return POS_FIX_AUTO; 1555 } 1556 1557 static void assign_position_fix(struct azx *chip, int fix) 1558 { 1559 static azx_get_pos_callback_t callbacks[] = { 1560 [POS_FIX_AUTO] = NULL, 1561 [POS_FIX_LPIB] = azx_get_pos_lpib, 1562 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1563 [POS_FIX_VIACOMBO] = azx_via_get_position, 1564 [POS_FIX_COMBO] = azx_get_pos_lpib, 1565 [POS_FIX_SKL] = azx_get_pos_skl, 1566 }; 1567 1568 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1569 1570 /* combo mode uses LPIB only for playback */ 1571 if (fix == POS_FIX_COMBO) 1572 chip->get_position[1] = NULL; 1573 1574 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1575 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1576 chip->get_delay[0] = chip->get_delay[1] = 1577 azx_get_delay_from_lpib; 1578 } 1579 1580 } 1581 1582 /* 1583 * black-lists for probe_mask 1584 */ 1585 static struct snd_pci_quirk probe_mask_list[] = { 1586 /* Thinkpad often breaks the controller communication when accessing 1587 * to the non-working (or non-existing) modem codec slot. 1588 */ 1589 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1590 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1591 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1592 /* broken BIOS */ 1593 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1594 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1595 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1596 /* forced codec slots */ 1597 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1598 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1599 /* WinFast VP200 H (Teradici) user reported broken communication */ 1600 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1601 {} 1602 }; 1603 1604 #define AZX_FORCE_CODEC_MASK 0x100 1605 1606 static void check_probe_mask(struct azx *chip, int dev) 1607 { 1608 const struct snd_pci_quirk *q; 1609 1610 chip->codec_probe_mask = probe_mask[dev]; 1611 if (chip->codec_probe_mask == -1) { 1612 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1613 if (q) { 1614 dev_info(chip->card->dev, 1615 "probe_mask set to 0x%x for device %04x:%04x\n", 1616 q->value, q->subvendor, q->subdevice); 1617 chip->codec_probe_mask = q->value; 1618 } 1619 } 1620 1621 /* check forced option */ 1622 if (chip->codec_probe_mask != -1 && 1623 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1624 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1625 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1626 (int)azx_bus(chip)->codec_mask); 1627 } 1628 } 1629 1630 /* 1631 * white/black-list for enable_msi 1632 */ 1633 static struct snd_pci_quirk msi_black_list[] = { 1634 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1635 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1636 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1637 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1638 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1639 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1640 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1641 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1642 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1643 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1644 {} 1645 }; 1646 1647 static void check_msi(struct azx *chip) 1648 { 1649 const struct snd_pci_quirk *q; 1650 1651 if (enable_msi >= 0) { 1652 chip->msi = !!enable_msi; 1653 return; 1654 } 1655 chip->msi = 1; /* enable MSI as default */ 1656 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1657 if (q) { 1658 dev_info(chip->card->dev, 1659 "msi for device %04x:%04x set to %d\n", 1660 q->subvendor, q->subdevice, q->value); 1661 chip->msi = q->value; 1662 return; 1663 } 1664 1665 /* NVidia chipsets seem to cause troubles with MSI */ 1666 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1667 dev_info(chip->card->dev, "Disabling MSI\n"); 1668 chip->msi = 0; 1669 } 1670 } 1671 1672 /* check the snoop mode availability */ 1673 static void azx_check_snoop_available(struct azx *chip) 1674 { 1675 int snoop = hda_snoop; 1676 1677 if (snoop >= 0) { 1678 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1679 snoop ? "snoop" : "non-snoop"); 1680 chip->snoop = snoop; 1681 return; 1682 } 1683 1684 snoop = true; 1685 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1686 chip->driver_type == AZX_DRIVER_VIA) { 1687 /* force to non-snoop mode for a new VIA controller 1688 * when BIOS is set 1689 */ 1690 u8 val; 1691 pci_read_config_byte(chip->pci, 0x42, &val); 1692 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1693 chip->pci->revision == 0x20)) 1694 snoop = false; 1695 } 1696 1697 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1698 snoop = false; 1699 1700 chip->snoop = snoop; 1701 if (!snoop) 1702 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1703 } 1704 1705 static void azx_probe_work(struct work_struct *work) 1706 { 1707 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1708 azx_probe_continue(&hda->chip); 1709 } 1710 1711 static int default_bdl_pos_adj(struct azx *chip) 1712 { 1713 /* some exceptions: Atoms seem problematic with value 1 */ 1714 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1715 switch (chip->pci->device) { 1716 case 0x0f04: /* Baytrail */ 1717 case 0x2284: /* Braswell */ 1718 return 32; 1719 } 1720 } 1721 1722 switch (chip->driver_type) { 1723 case AZX_DRIVER_ICH: 1724 case AZX_DRIVER_PCH: 1725 return 1; 1726 default: 1727 return 32; 1728 } 1729 } 1730 1731 /* 1732 * constructor 1733 */ 1734 static const struct hdac_io_ops pci_hda_io_ops; 1735 static const struct hda_controller_ops pci_hda_ops; 1736 1737 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1738 int dev, unsigned int driver_caps, 1739 struct azx **rchip) 1740 { 1741 static struct snd_device_ops ops = { 1742 .dev_disconnect = azx_dev_disconnect, 1743 .dev_free = azx_dev_free, 1744 }; 1745 struct hda_intel *hda; 1746 struct azx *chip; 1747 int err; 1748 1749 *rchip = NULL; 1750 1751 err = pci_enable_device(pci); 1752 if (err < 0) 1753 return err; 1754 1755 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1756 if (!hda) { 1757 pci_disable_device(pci); 1758 return -ENOMEM; 1759 } 1760 1761 chip = &hda->chip; 1762 mutex_init(&chip->open_mutex); 1763 chip->card = card; 1764 chip->pci = pci; 1765 chip->ops = &pci_hda_ops; 1766 chip->driver_caps = driver_caps; 1767 chip->driver_type = driver_caps & 0xff; 1768 check_msi(chip); 1769 chip->dev_index = dev; 1770 chip->jackpoll_ms = jackpoll_ms; 1771 INIT_LIST_HEAD(&chip->pcm_list); 1772 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1773 INIT_LIST_HEAD(&hda->list); 1774 init_vga_switcheroo(chip); 1775 init_completion(&hda->probe_wait); 1776 1777 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1778 1779 check_probe_mask(chip, dev); 1780 1781 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1782 chip->fallback_to_single_cmd = 1; 1783 else /* explicitly set to single_cmd or not */ 1784 chip->single_cmd = single_cmd; 1785 1786 azx_check_snoop_available(chip); 1787 1788 if (bdl_pos_adj[dev] < 0) 1789 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1790 else 1791 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1792 1793 /* Workaround for a communication error on CFL (bko#199007) */ 1794 if (IS_CFL(pci)) 1795 chip->polling_mode = 1; 1796 1797 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1798 if (err < 0) { 1799 kfree(hda); 1800 pci_disable_device(pci); 1801 return err; 1802 } 1803 1804 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1805 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1806 chip->bus.needs_damn_long_delay = 1; 1807 } 1808 1809 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1810 if (err < 0) { 1811 dev_err(card->dev, "Error creating device [card]!\n"); 1812 azx_free(chip); 1813 return err; 1814 } 1815 1816 /* continue probing in work context as may trigger request module */ 1817 INIT_WORK(&hda->probe_work, azx_probe_work); 1818 1819 *rchip = chip; 1820 1821 return 0; 1822 } 1823 1824 static int azx_first_init(struct azx *chip) 1825 { 1826 int dev = chip->dev_index; 1827 struct pci_dev *pci = chip->pci; 1828 struct snd_card *card = chip->card; 1829 struct hdac_bus *bus = azx_bus(chip); 1830 int err; 1831 unsigned short gcap; 1832 unsigned int dma_bits = 64; 1833 1834 #if BITS_PER_LONG != 64 1835 /* Fix up base address on ULI M5461 */ 1836 if (chip->driver_type == AZX_DRIVER_ULI) { 1837 u16 tmp3; 1838 pci_read_config_word(pci, 0x40, &tmp3); 1839 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1840 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1841 } 1842 #endif 1843 1844 err = pci_request_regions(pci, "ICH HD audio"); 1845 if (err < 0) 1846 return err; 1847 chip->region_requested = 1; 1848 1849 bus->addr = pci_resource_start(pci, 0); 1850 bus->remap_addr = pci_ioremap_bar(pci, 0); 1851 if (bus->remap_addr == NULL) { 1852 dev_err(card->dev, "ioremap error\n"); 1853 return -ENXIO; 1854 } 1855 1856 if (chip->driver_type == AZX_DRIVER_SKL) 1857 snd_hdac_bus_parse_capabilities(bus); 1858 1859 /* 1860 * Some Intel CPUs has always running timer (ART) feature and 1861 * controller may have Global time sync reporting capability, so 1862 * check both of these before declaring synchronized time reporting 1863 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1864 */ 1865 chip->gts_present = false; 1866 1867 #ifdef CONFIG_X86 1868 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1869 chip->gts_present = true; 1870 #endif 1871 1872 if (chip->msi) { 1873 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1874 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1875 pci->no_64bit_msi = true; 1876 } 1877 if (pci_enable_msi(pci) < 0) 1878 chip->msi = 0; 1879 } 1880 1881 if (azx_acquire_irq(chip, 0) < 0) 1882 return -EBUSY; 1883 1884 pci_set_master(pci); 1885 synchronize_irq(bus->irq); 1886 1887 gcap = azx_readw(chip, GCAP); 1888 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1889 1890 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1891 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1892 dma_bits = 40; 1893 1894 /* disable SB600 64bit support for safety */ 1895 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1896 struct pci_dev *p_smbus; 1897 dma_bits = 40; 1898 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1899 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1900 NULL); 1901 if (p_smbus) { 1902 if (p_smbus->revision < 0x30) 1903 gcap &= ~AZX_GCAP_64OK; 1904 pci_dev_put(p_smbus); 1905 } 1906 } 1907 1908 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1909 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1910 dma_bits = 40; 1911 1912 /* disable 64bit DMA address on some devices */ 1913 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1914 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1915 gcap &= ~AZX_GCAP_64OK; 1916 } 1917 1918 /* disable buffer size rounding to 128-byte multiples if supported */ 1919 if (align_buffer_size >= 0) 1920 chip->align_buffer_size = !!align_buffer_size; 1921 else { 1922 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1923 chip->align_buffer_size = 0; 1924 else 1925 chip->align_buffer_size = 1; 1926 } 1927 1928 /* allow 64bit DMA address if supported by H/W */ 1929 if (!(gcap & AZX_GCAP_64OK)) 1930 dma_bits = 32; 1931 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1932 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1933 } else { 1934 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1935 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1936 } 1937 1938 /* read number of streams from GCAP register instead of using 1939 * hardcoded value 1940 */ 1941 chip->capture_streams = (gcap >> 8) & 0x0f; 1942 chip->playback_streams = (gcap >> 12) & 0x0f; 1943 if (!chip->playback_streams && !chip->capture_streams) { 1944 /* gcap didn't give any info, switching to old method */ 1945 1946 switch (chip->driver_type) { 1947 case AZX_DRIVER_ULI: 1948 chip->playback_streams = ULI_NUM_PLAYBACK; 1949 chip->capture_streams = ULI_NUM_CAPTURE; 1950 break; 1951 case AZX_DRIVER_ATIHDMI: 1952 case AZX_DRIVER_ATIHDMI_NS: 1953 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1954 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1955 break; 1956 case AZX_DRIVER_GENERIC: 1957 default: 1958 chip->playback_streams = ICH6_NUM_PLAYBACK; 1959 chip->capture_streams = ICH6_NUM_CAPTURE; 1960 break; 1961 } 1962 } 1963 chip->capture_index_offset = 0; 1964 chip->playback_index_offset = chip->capture_streams; 1965 chip->num_streams = chip->playback_streams + chip->capture_streams; 1966 1967 /* sanity check for the SDxCTL.STRM field overflow */ 1968 if (chip->num_streams > 15 && 1969 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1970 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1971 "forcing separate stream tags", chip->num_streams); 1972 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1973 } 1974 1975 /* initialize streams */ 1976 err = azx_init_streams(chip); 1977 if (err < 0) 1978 return err; 1979 1980 err = azx_alloc_stream_pages(chip); 1981 if (err < 0) 1982 return err; 1983 1984 /* initialize chip */ 1985 azx_init_pci(chip); 1986 1987 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1988 snd_hdac_i915_set_bclk(bus); 1989 1990 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1991 1992 /* codec detection */ 1993 if (!azx_bus(chip)->codec_mask) { 1994 dev_err(card->dev, "no codecs found!\n"); 1995 return -ENODEV; 1996 } 1997 1998 strcpy(card->driver, "HDA-Intel"); 1999 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2000 sizeof(card->shortname)); 2001 snprintf(card->longname, sizeof(card->longname), 2002 "%s at 0x%lx irq %i", 2003 card->shortname, bus->addr, bus->irq); 2004 2005 return 0; 2006 } 2007 2008 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2009 /* callback from request_firmware_nowait() */ 2010 static void azx_firmware_cb(const struct firmware *fw, void *context) 2011 { 2012 struct snd_card *card = context; 2013 struct azx *chip = card->private_data; 2014 struct pci_dev *pci = chip->pci; 2015 2016 if (!fw) { 2017 dev_err(card->dev, "Cannot load firmware, aborting\n"); 2018 goto error; 2019 } 2020 2021 chip->fw = fw; 2022 if (!chip->disabled) { 2023 /* continue probing */ 2024 if (azx_probe_continue(chip)) 2025 goto error; 2026 } 2027 return; /* OK */ 2028 2029 error: 2030 snd_card_free(card); 2031 pci_set_drvdata(pci, NULL); 2032 } 2033 #endif 2034 2035 /* 2036 * HDA controller ops. 2037 */ 2038 2039 /* PCI register access. */ 2040 static void pci_azx_writel(u32 value, u32 __iomem *addr) 2041 { 2042 writel(value, addr); 2043 } 2044 2045 static u32 pci_azx_readl(u32 __iomem *addr) 2046 { 2047 return readl(addr); 2048 } 2049 2050 static void pci_azx_writew(u16 value, u16 __iomem *addr) 2051 { 2052 writew(value, addr); 2053 } 2054 2055 static u16 pci_azx_readw(u16 __iomem *addr) 2056 { 2057 return readw(addr); 2058 } 2059 2060 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 2061 { 2062 writeb(value, addr); 2063 } 2064 2065 static u8 pci_azx_readb(u8 __iomem *addr) 2066 { 2067 return readb(addr); 2068 } 2069 2070 static int disable_msi_reset_irq(struct azx *chip) 2071 { 2072 struct hdac_bus *bus = azx_bus(chip); 2073 int err; 2074 2075 free_irq(bus->irq, chip); 2076 bus->irq = -1; 2077 pci_disable_msi(chip->pci); 2078 chip->msi = 0; 2079 err = azx_acquire_irq(chip, 1); 2080 if (err < 0) 2081 return err; 2082 2083 return 0; 2084 } 2085 2086 /* DMA page allocation helpers. */ 2087 static int dma_alloc_pages(struct hdac_bus *bus, 2088 int type, 2089 size_t size, 2090 struct snd_dma_buffer *buf) 2091 { 2092 struct azx *chip = bus_to_azx(bus); 2093 int err; 2094 2095 err = snd_dma_alloc_pages(type, 2096 bus->dev, 2097 size, buf); 2098 if (err < 0) 2099 return err; 2100 mark_pages_wc(chip, buf, true); 2101 return 0; 2102 } 2103 2104 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 2105 { 2106 struct azx *chip = bus_to_azx(bus); 2107 2108 mark_pages_wc(chip, buf, false); 2109 snd_dma_free_pages(buf); 2110 } 2111 2112 static int substream_alloc_pages(struct azx *chip, 2113 struct snd_pcm_substream *substream, 2114 size_t size) 2115 { 2116 struct azx_dev *azx_dev = get_azx_dev(substream); 2117 int ret; 2118 2119 mark_runtime_wc(chip, azx_dev, substream, false); 2120 ret = snd_pcm_lib_malloc_pages(substream, size); 2121 if (ret < 0) 2122 return ret; 2123 mark_runtime_wc(chip, azx_dev, substream, true); 2124 return 0; 2125 } 2126 2127 static int substream_free_pages(struct azx *chip, 2128 struct snd_pcm_substream *substream) 2129 { 2130 struct azx_dev *azx_dev = get_azx_dev(substream); 2131 mark_runtime_wc(chip, azx_dev, substream, false); 2132 return snd_pcm_lib_free_pages(substream); 2133 } 2134 2135 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2136 struct vm_area_struct *area) 2137 { 2138 #ifdef CONFIG_X86 2139 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2140 struct azx *chip = apcm->chip; 2141 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 2142 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2143 #endif 2144 } 2145 2146 static const struct hdac_io_ops pci_hda_io_ops = { 2147 .reg_writel = pci_azx_writel, 2148 .reg_readl = pci_azx_readl, 2149 .reg_writew = pci_azx_writew, 2150 .reg_readw = pci_azx_readw, 2151 .reg_writeb = pci_azx_writeb, 2152 .reg_readb = pci_azx_readb, 2153 .dma_alloc_pages = dma_alloc_pages, 2154 .dma_free_pages = dma_free_pages, 2155 }; 2156 2157 static const struct hda_controller_ops pci_hda_ops = { 2158 .disable_msi_reset_irq = disable_msi_reset_irq, 2159 .substream_alloc_pages = substream_alloc_pages, 2160 .substream_free_pages = substream_free_pages, 2161 .pcm_mmap_prepare = pcm_mmap_prepare, 2162 .position_check = azx_position_check, 2163 .link_power = azx_intel_link_power, 2164 }; 2165 2166 static int azx_probe(struct pci_dev *pci, 2167 const struct pci_device_id *pci_id) 2168 { 2169 static int dev; 2170 struct snd_card *card; 2171 struct hda_intel *hda; 2172 struct azx *chip; 2173 bool schedule_probe; 2174 int err; 2175 2176 if (dev >= SNDRV_CARDS) 2177 return -ENODEV; 2178 if (!enable[dev]) { 2179 dev++; 2180 return -ENOENT; 2181 } 2182 2183 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2184 0, &card); 2185 if (err < 0) { 2186 dev_err(&pci->dev, "Error creating card!\n"); 2187 return err; 2188 } 2189 2190 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2191 if (err < 0) 2192 goto out_free; 2193 card->private_data = chip; 2194 hda = container_of(chip, struct hda_intel, chip); 2195 2196 pci_set_drvdata(pci, card); 2197 2198 err = register_vga_switcheroo(chip); 2199 if (err < 0) { 2200 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2201 goto out_free; 2202 } 2203 2204 if (check_hdmi_disabled(pci)) { 2205 dev_info(card->dev, "VGA controller is disabled\n"); 2206 dev_info(card->dev, "Delaying initialization\n"); 2207 chip->disabled = true; 2208 } 2209 2210 schedule_probe = !chip->disabled; 2211 2212 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2213 if (patch[dev] && *patch[dev]) { 2214 dev_info(card->dev, "Applying patch firmware '%s'\n", 2215 patch[dev]); 2216 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2217 &pci->dev, GFP_KERNEL, card, 2218 azx_firmware_cb); 2219 if (err < 0) 2220 goto out_free; 2221 schedule_probe = false; /* continued in azx_firmware_cb() */ 2222 } 2223 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2224 2225 #ifndef CONFIG_SND_HDA_I915 2226 if (CONTROLLER_IN_GPU(pci)) 2227 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2228 #endif 2229 2230 if (schedule_probe) 2231 schedule_work(&hda->probe_work); 2232 2233 dev++; 2234 if (chip->disabled) 2235 complete_all(&hda->probe_wait); 2236 return 0; 2237 2238 out_free: 2239 snd_card_free(card); 2240 return err; 2241 } 2242 2243 #ifdef CONFIG_PM 2244 /* On some boards setting power_save to a non 0 value leads to clicking / 2245 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2246 * figure out how to avoid these sounds, but that is not always feasible. 2247 * So we keep a list of devices where we disable powersaving as its known 2248 * to causes problems on these devices. 2249 */ 2250 static struct snd_pci_quirk power_save_blacklist[] = { 2251 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2252 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2253 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2254 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2255 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2256 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2257 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2258 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2259 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2260 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2261 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2262 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2263 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2264 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2265 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2266 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2267 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2268 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2269 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2270 {} 2271 }; 2272 #endif /* CONFIG_PM */ 2273 2274 static void set_default_power_save(struct azx *chip) 2275 { 2276 int val = power_save; 2277 2278 #ifdef CONFIG_PM 2279 if (pm_blacklist) { 2280 const struct snd_pci_quirk *q; 2281 2282 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2283 if (q && val) { 2284 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2285 q->subvendor, q->subdevice); 2286 val = 0; 2287 } 2288 } 2289 #endif /* CONFIG_PM */ 2290 snd_hda_set_power_save(&chip->bus, val * 1000); 2291 } 2292 2293 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2294 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2295 [AZX_DRIVER_NVIDIA] = 8, 2296 [AZX_DRIVER_TERA] = 1, 2297 }; 2298 2299 static int azx_probe_continue(struct azx *chip) 2300 { 2301 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2302 struct hdac_bus *bus = azx_bus(chip); 2303 struct pci_dev *pci = chip->pci; 2304 int dev = chip->dev_index; 2305 int err; 2306 2307 hda->probe_continued = 1; 2308 2309 /* bind with i915 if needed */ 2310 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2311 err = snd_hdac_i915_init(bus); 2312 if (err < 0) { 2313 /* if the controller is bound only with HDMI/DP 2314 * (for HSW and BDW), we need to abort the probe; 2315 * for other chips, still continue probing as other 2316 * codecs can be on the same link. 2317 */ 2318 if (CONTROLLER_IN_GPU(pci)) { 2319 dev_err(chip->card->dev, 2320 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2321 goto out_free; 2322 } else { 2323 /* don't bother any longer */ 2324 chip->driver_caps &= 2325 ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL); 2326 } 2327 } 2328 } 2329 2330 /* Request display power well for the HDA controller or codec. For 2331 * Haswell/Broadwell, both the display HDA controller and codec need 2332 * this power. For other platforms, like Baytrail/Braswell, only the 2333 * display codec needs the power and it can be released after probe. 2334 */ 2335 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 2336 /* HSW/BDW controllers need this power */ 2337 if (CONTROLLER_IN_GPU(pci)) 2338 hda->need_i915_power = 1; 2339 2340 err = snd_hdac_display_power(bus, true); 2341 if (err < 0) { 2342 dev_err(chip->card->dev, 2343 "Cannot turn on display power on i915\n"); 2344 goto i915_power_fail; 2345 } 2346 } 2347 2348 err = azx_first_init(chip); 2349 if (err < 0) 2350 goto out_free; 2351 2352 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2353 chip->beep_mode = beep_mode[dev]; 2354 #endif 2355 2356 /* create codec instances */ 2357 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2358 if (err < 0) 2359 goto out_free; 2360 2361 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2362 if (chip->fw) { 2363 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2364 chip->fw->data); 2365 if (err < 0) 2366 goto out_free; 2367 #ifndef CONFIG_PM 2368 release_firmware(chip->fw); /* no longer needed */ 2369 chip->fw = NULL; 2370 #endif 2371 } 2372 #endif 2373 if ((probe_only[dev] & 1) == 0) { 2374 err = azx_codec_configure(chip); 2375 if (err < 0) 2376 goto out_free; 2377 } 2378 2379 err = snd_card_register(chip->card); 2380 if (err < 0) 2381 goto out_free; 2382 2383 setup_vga_switcheroo_runtime_pm(chip); 2384 2385 chip->running = 1; 2386 azx_add_card_list(chip); 2387 2388 set_default_power_save(chip); 2389 2390 if (azx_has_pm_runtime(chip)) 2391 pm_runtime_put_autosuspend(&pci->dev); 2392 2393 out_free: 2394 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 2395 && !hda->need_i915_power) 2396 snd_hdac_display_power(bus, false); 2397 2398 i915_power_fail: 2399 if (err < 0) 2400 hda->init_failed = 1; 2401 complete_all(&hda->probe_wait); 2402 return err; 2403 } 2404 2405 static void azx_remove(struct pci_dev *pci) 2406 { 2407 struct snd_card *card = pci_get_drvdata(pci); 2408 struct azx *chip; 2409 struct hda_intel *hda; 2410 2411 if (card) { 2412 /* cancel the pending probing work */ 2413 chip = card->private_data; 2414 hda = container_of(chip, struct hda_intel, chip); 2415 /* FIXME: below is an ugly workaround. 2416 * Both device_release_driver() and driver_probe_device() 2417 * take *both* the device's and its parent's lock before 2418 * calling the remove() and probe() callbacks. The codec 2419 * probe takes the locks of both the codec itself and its 2420 * parent, i.e. the PCI controller dev. Meanwhile, when 2421 * the PCI controller is unbound, it takes its lock, too 2422 * ==> ouch, a deadlock! 2423 * As a workaround, we unlock temporarily here the controller 2424 * device during cancel_work_sync() call. 2425 */ 2426 device_unlock(&pci->dev); 2427 cancel_work_sync(&hda->probe_work); 2428 device_lock(&pci->dev); 2429 2430 snd_card_free(card); 2431 } 2432 } 2433 2434 static void azx_shutdown(struct pci_dev *pci) 2435 { 2436 struct snd_card *card = pci_get_drvdata(pci); 2437 struct azx *chip; 2438 2439 if (!card) 2440 return; 2441 chip = card->private_data; 2442 if (chip && chip->running) 2443 azx_stop_chip(chip); 2444 } 2445 2446 /* PCI IDs */ 2447 static const struct pci_device_id azx_ids[] = { 2448 /* CPT */ 2449 { PCI_DEVICE(0x8086, 0x1c20), 2450 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2451 /* PBG */ 2452 { PCI_DEVICE(0x8086, 0x1d20), 2453 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2454 /* Panther Point */ 2455 { PCI_DEVICE(0x8086, 0x1e20), 2456 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2457 /* Lynx Point */ 2458 { PCI_DEVICE(0x8086, 0x8c20), 2459 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2460 /* 9 Series */ 2461 { PCI_DEVICE(0x8086, 0x8ca0), 2462 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2463 /* Wellsburg */ 2464 { PCI_DEVICE(0x8086, 0x8d20), 2465 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2466 { PCI_DEVICE(0x8086, 0x8d21), 2467 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2468 /* Lewisburg */ 2469 { PCI_DEVICE(0x8086, 0xa1f0), 2470 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2471 { PCI_DEVICE(0x8086, 0xa270), 2472 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2473 /* Lynx Point-LP */ 2474 { PCI_DEVICE(0x8086, 0x9c20), 2475 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2476 /* Lynx Point-LP */ 2477 { PCI_DEVICE(0x8086, 0x9c21), 2478 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2479 /* Wildcat Point-LP */ 2480 { PCI_DEVICE(0x8086, 0x9ca0), 2481 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2482 /* Sunrise Point */ 2483 { PCI_DEVICE(0x8086, 0xa170), 2484 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2485 /* Sunrise Point-LP */ 2486 { PCI_DEVICE(0x8086, 0x9d70), 2487 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2488 /* Kabylake */ 2489 { PCI_DEVICE(0x8086, 0xa171), 2490 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2491 /* Kabylake-LP */ 2492 { PCI_DEVICE(0x8086, 0x9d71), 2493 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2494 /* Kabylake-H */ 2495 { PCI_DEVICE(0x8086, 0xa2f0), 2496 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2497 /* Coffelake */ 2498 { PCI_DEVICE(0x8086, 0xa348), 2499 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2500 /* Cannonlake */ 2501 { PCI_DEVICE(0x8086, 0x9dc8), 2502 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2503 /* Icelake */ 2504 { PCI_DEVICE(0x8086, 0x34c8), 2505 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2506 /* Broxton-P(Apollolake) */ 2507 { PCI_DEVICE(0x8086, 0x5a98), 2508 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2509 /* Broxton-T */ 2510 { PCI_DEVICE(0x8086, 0x1a98), 2511 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2512 /* Gemini-Lake */ 2513 { PCI_DEVICE(0x8086, 0x3198), 2514 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2515 /* Haswell */ 2516 { PCI_DEVICE(0x8086, 0x0a0c), 2517 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2518 { PCI_DEVICE(0x8086, 0x0c0c), 2519 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2520 { PCI_DEVICE(0x8086, 0x0d0c), 2521 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2522 /* Broadwell */ 2523 { PCI_DEVICE(0x8086, 0x160c), 2524 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2525 /* 5 Series/3400 */ 2526 { PCI_DEVICE(0x8086, 0x3b56), 2527 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2528 /* Poulsbo */ 2529 { PCI_DEVICE(0x8086, 0x811b), 2530 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2531 /* Oaktrail */ 2532 { PCI_DEVICE(0x8086, 0x080a), 2533 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2534 /* BayTrail */ 2535 { PCI_DEVICE(0x8086, 0x0f04), 2536 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2537 /* Braswell */ 2538 { PCI_DEVICE(0x8086, 0x2284), 2539 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2540 /* ICH6 */ 2541 { PCI_DEVICE(0x8086, 0x2668), 2542 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2543 /* ICH7 */ 2544 { PCI_DEVICE(0x8086, 0x27d8), 2545 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2546 /* ESB2 */ 2547 { PCI_DEVICE(0x8086, 0x269a), 2548 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2549 /* ICH8 */ 2550 { PCI_DEVICE(0x8086, 0x284b), 2551 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2552 /* ICH9 */ 2553 { PCI_DEVICE(0x8086, 0x293e), 2554 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2555 /* ICH9 */ 2556 { PCI_DEVICE(0x8086, 0x293f), 2557 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2558 /* ICH10 */ 2559 { PCI_DEVICE(0x8086, 0x3a3e), 2560 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2561 /* ICH10 */ 2562 { PCI_DEVICE(0x8086, 0x3a6e), 2563 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2564 /* Generic Intel */ 2565 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2566 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2567 .class_mask = 0xffffff, 2568 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2569 /* ATI SB 450/600/700/800/900 */ 2570 { PCI_DEVICE(0x1002, 0x437b), 2571 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2572 { PCI_DEVICE(0x1002, 0x4383), 2573 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2574 /* AMD Hudson */ 2575 { PCI_DEVICE(0x1022, 0x780d), 2576 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2577 /* AMD Raven */ 2578 { PCI_DEVICE(0x1022, 0x15e3), 2579 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2580 AZX_DCAPS_PM_RUNTIME }, 2581 /* ATI HDMI */ 2582 { PCI_DEVICE(0x1002, 0x0002), 2583 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2584 { PCI_DEVICE(0x1002, 0x1308), 2585 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2586 { PCI_DEVICE(0x1002, 0x157a), 2587 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2588 { PCI_DEVICE(0x1002, 0x15b3), 2589 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2590 { PCI_DEVICE(0x1002, 0x793b), 2591 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2592 { PCI_DEVICE(0x1002, 0x7919), 2593 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2594 { PCI_DEVICE(0x1002, 0x960f), 2595 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2596 { PCI_DEVICE(0x1002, 0x970f), 2597 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2598 { PCI_DEVICE(0x1002, 0x9840), 2599 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2600 { PCI_DEVICE(0x1002, 0xaa00), 2601 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2602 { PCI_DEVICE(0x1002, 0xaa08), 2603 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2604 { PCI_DEVICE(0x1002, 0xaa10), 2605 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2606 { PCI_DEVICE(0x1002, 0xaa18), 2607 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2608 { PCI_DEVICE(0x1002, 0xaa20), 2609 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2610 { PCI_DEVICE(0x1002, 0xaa28), 2611 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2612 { PCI_DEVICE(0x1002, 0xaa30), 2613 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2614 { PCI_DEVICE(0x1002, 0xaa38), 2615 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2616 { PCI_DEVICE(0x1002, 0xaa40), 2617 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2618 { PCI_DEVICE(0x1002, 0xaa48), 2619 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2620 { PCI_DEVICE(0x1002, 0xaa50), 2621 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2622 { PCI_DEVICE(0x1002, 0xaa58), 2623 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2624 { PCI_DEVICE(0x1002, 0xaa60), 2625 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2626 { PCI_DEVICE(0x1002, 0xaa68), 2627 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2628 { PCI_DEVICE(0x1002, 0xaa80), 2629 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2630 { PCI_DEVICE(0x1002, 0xaa88), 2631 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2632 { PCI_DEVICE(0x1002, 0xaa90), 2633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2634 { PCI_DEVICE(0x1002, 0xaa98), 2635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2636 { PCI_DEVICE(0x1002, 0x9902), 2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2638 { PCI_DEVICE(0x1002, 0xaaa0), 2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2640 { PCI_DEVICE(0x1002, 0xaaa8), 2641 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2642 { PCI_DEVICE(0x1002, 0xaab0), 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2644 { PCI_DEVICE(0x1002, 0xaac0), 2645 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2646 { PCI_DEVICE(0x1002, 0xaac8), 2647 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2648 { PCI_DEVICE(0x1002, 0xaad8), 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2650 { PCI_DEVICE(0x1002, 0xaae8), 2651 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2652 { PCI_DEVICE(0x1002, 0xaae0), 2653 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2654 { PCI_DEVICE(0x1002, 0xaaf0), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2656 /* VIA VT8251/VT8237A */ 2657 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2658 /* VIA GFX VT7122/VX900 */ 2659 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2660 /* VIA GFX VT6122/VX11 */ 2661 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2662 /* SIS966 */ 2663 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2664 /* ULI M5461 */ 2665 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2666 /* NVIDIA MCP */ 2667 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2668 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2669 .class_mask = 0xffffff, 2670 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2671 /* Teradici */ 2672 { PCI_DEVICE(0x6549, 0x1200), 2673 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2674 { PCI_DEVICE(0x6549, 0x2200), 2675 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2676 /* Creative X-Fi (CA0110-IBG) */ 2677 /* CTHDA chips */ 2678 { PCI_DEVICE(0x1102, 0x0010), 2679 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2680 { PCI_DEVICE(0x1102, 0x0012), 2681 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2682 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2683 /* the following entry conflicts with snd-ctxfi driver, 2684 * as ctxfi driver mutates from HD-audio to native mode with 2685 * a special command sequence. 2686 */ 2687 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2688 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2689 .class_mask = 0xffffff, 2690 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2691 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2692 #else 2693 /* this entry seems still valid -- i.e. without emu20kx chip */ 2694 { PCI_DEVICE(0x1102, 0x0009), 2695 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2696 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2697 #endif 2698 /* CM8888 */ 2699 { PCI_DEVICE(0x13f6, 0x5011), 2700 .driver_data = AZX_DRIVER_CMEDIA | 2701 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2702 /* Vortex86MX */ 2703 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2704 /* VMware HDAudio */ 2705 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2706 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2707 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2708 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2709 .class_mask = 0xffffff, 2710 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2711 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2712 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2713 .class_mask = 0xffffff, 2714 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2715 { 0, } 2716 }; 2717 MODULE_DEVICE_TABLE(pci, azx_ids); 2718 2719 /* pci_driver definition */ 2720 static struct pci_driver azx_driver = { 2721 .name = KBUILD_MODNAME, 2722 .id_table = azx_ids, 2723 .probe = azx_probe, 2724 .remove = azx_remove, 2725 .shutdown = azx_shutdown, 2726 .driver = { 2727 .pm = AZX_PM_OPS, 2728 }, 2729 }; 2730 2731 module_pci_driver(azx_driver); 2732