1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* Define VIA HD Audio Device ID*/ 90 #define VIA_HDAC_DEVICE_ID 0x3288 91 92 /* max number of SDs */ 93 /* ICH, ATI and VIA have 4 playback and 4 capture */ 94 #define ICH6_NUM_CAPTURE 4 95 #define ICH6_NUM_PLAYBACK 4 96 97 /* ULI has 6 playback and 5 capture */ 98 #define ULI_NUM_CAPTURE 5 99 #define ULI_NUM_PLAYBACK 6 100 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 102 #define ATIHDMI_NUM_CAPTURE 0 103 #define ATIHDMI_NUM_PLAYBACK 8 104 105 /* TERA has 4 playback and 3 capture */ 106 #define TERA_NUM_CAPTURE 3 107 #define TERA_NUM_PLAYBACK 4 108 109 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113 static char *model[SNDRV_CARDS]; 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117 static int probe_only[SNDRV_CARDS]; 118 static int jackpoll_ms[SNDRV_CARDS]; 119 static int single_cmd = -1; 120 static int enable_msi = -1; 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER 122 static char *patch[SNDRV_CARDS]; 123 #endif 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127 #endif 128 static bool dmic_detect = 1; 129 130 module_param_array(index, int, NULL, 0444); 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132 module_param_array(id, charp, NULL, 0444); 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134 module_param_array(enable, bool, NULL, 0444); 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136 module_param_array(model, charp, NULL, 0444); 137 MODULE_PARM_DESC(model, "Use the given board model."); 138 module_param_array(position_fix, int, NULL, 0444); 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141 module_param_array(bdl_pos_adj, int, NULL, 0644); 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143 module_param_array(probe_mask, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145 module_param_array(probe_only, int, NULL, 0444); 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147 module_param_array(jackpoll_ms, int, NULL, 0444); 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149 module_param(single_cmd, bint, 0444); 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152 module_param(enable_msi, bint, 0444); 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER 155 module_param_array(patch, charp, NULL, 0444); 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157 #endif 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP 159 module_param_array(beep_mode, bool, NULL, 0444); 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162 #endif 163 module_param(dmic_detect, bool, 0444); 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1); " 166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 167 168 #ifdef CONFIG_PM 169 static int param_set_xint(const char *val, const struct kernel_param *kp); 170 static const struct kernel_param_ops param_ops_xint = { 171 .set = param_set_xint, 172 .get = param_get_int, 173 }; 174 #define param_check_xint param_check_int 175 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 177 module_param(power_save, xint, 0644); 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 179 "(in second, 0 = disable)."); 180 181 static bool pm_blacklist = true; 182 module_param(pm_blacklist, bool, 0644); 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 184 185 /* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189 static bool power_save_controller = 1; 190 module_param(power_save_controller, bool, 0644); 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192 #else 193 #define power_save 0 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_DESCRIPTION("Intel HDA driver"); 212 213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 215 #define SUPPORT_VGA_SWITCHEROO 216 #endif 217 #endif 218 219 220 /* 221 */ 222 223 /* driver types */ 224 enum { 225 AZX_DRIVER_ICH, 226 AZX_DRIVER_PCH, 227 AZX_DRIVER_SCH, 228 AZX_DRIVER_SKL, 229 AZX_DRIVER_HDMI, 230 AZX_DRIVER_ATI, 231 AZX_DRIVER_ATIHDMI, 232 AZX_DRIVER_ATIHDMI_NS, 233 AZX_DRIVER_VIA, 234 AZX_DRIVER_SIS, 235 AZX_DRIVER_ULI, 236 AZX_DRIVER_NVIDIA, 237 AZX_DRIVER_TERA, 238 AZX_DRIVER_CTX, 239 AZX_DRIVER_CTHDA, 240 AZX_DRIVER_CMEDIA, 241 AZX_DRIVER_ZHAOXIN, 242 AZX_DRIVER_GENERIC, 243 AZX_NUM_DRIVERS, /* keep this as last entry */ 244 }; 245 246 #define azx_get_snoop_type(chip) \ 247 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 248 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 249 250 /* quirks for old Intel chipsets */ 251 #define AZX_DCAPS_INTEL_ICH \ 252 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 253 254 /* quirks for Intel PCH */ 255 #define AZX_DCAPS_INTEL_PCH_BASE \ 256 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 257 AZX_DCAPS_SNOOP_TYPE(SCH)) 258 259 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 260 #define AZX_DCAPS_INTEL_PCH_NOPM \ 261 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 262 263 /* PCH for HSW/BDW; with runtime PM */ 264 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 265 #define AZX_DCAPS_INTEL_PCH \ 266 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 267 268 /* HSW HDMI */ 269 #define AZX_DCAPS_INTEL_HASWELL \ 270 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 271 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 272 AZX_DCAPS_SNOOP_TYPE(SCH)) 273 274 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 275 #define AZX_DCAPS_INTEL_BROADWELL \ 276 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 277 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 278 AZX_DCAPS_SNOOP_TYPE(SCH)) 279 280 #define AZX_DCAPS_INTEL_BAYTRAIL \ 281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 282 283 #define AZX_DCAPS_INTEL_BRASWELL \ 284 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 285 AZX_DCAPS_I915_COMPONENT) 286 287 #define AZX_DCAPS_INTEL_SKYLAKE \ 288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 289 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 290 291 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 292 293 /* quirks for ATI SB / AMD Hudson */ 294 #define AZX_DCAPS_PRESET_ATI_SB \ 295 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 296 AZX_DCAPS_SNOOP_TYPE(ATI)) 297 298 /* quirks for ATI/AMD HDMI */ 299 #define AZX_DCAPS_PRESET_ATI_HDMI \ 300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 301 AZX_DCAPS_NO_MSI64) 302 303 /* quirks for ATI HDMI with snoop off */ 304 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 305 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 306 307 /* quirks for AMD SB */ 308 #define AZX_DCAPS_PRESET_AMD_SB \ 309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 310 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 311 AZX_DCAPS_RETRY_PROBE) 312 313 /* quirks for Nvidia */ 314 #define AZX_DCAPS_PRESET_NVIDIA \ 315 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 316 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 317 318 #define AZX_DCAPS_PRESET_CTHDA \ 319 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 320 AZX_DCAPS_NO_64BIT |\ 321 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 322 323 /* 324 * vga_switcheroo support 325 */ 326 #ifdef SUPPORT_VGA_SWITCHEROO 327 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 328 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 329 #else 330 #define use_vga_switcheroo(chip) 0 331 #define needs_eld_notify_link(chip) false 332 #endif 333 334 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 335 ((pci)->device == 0x0c0c) || \ 336 ((pci)->device == 0x0d0c) || \ 337 ((pci)->device == 0x160c) || \ 338 ((pci)->device == 0x490d)) 339 340 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 341 342 static const char * const driver_short_names[] = { 343 [AZX_DRIVER_ICH] = "HDA Intel", 344 [AZX_DRIVER_PCH] = "HDA Intel PCH", 345 [AZX_DRIVER_SCH] = "HDA Intel MID", 346 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 348 [AZX_DRIVER_ATI] = "HDA ATI SB", 349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 351 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 352 [AZX_DRIVER_SIS] = "HDA SIS966", 353 [AZX_DRIVER_ULI] = "HDA ULI M5461", 354 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 355 [AZX_DRIVER_TERA] = "HDA Teradici", 356 [AZX_DRIVER_CTX] = "HDA Creative", 357 [AZX_DRIVER_CTHDA] = "HDA Creative", 358 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 359 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 360 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 361 }; 362 363 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 364 static void set_default_power_save(struct azx *chip); 365 366 /* 367 * initialize the PCI registers 368 */ 369 /* update bits in a PCI register byte */ 370 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 371 unsigned char mask, unsigned char val) 372 { 373 unsigned char data; 374 375 pci_read_config_byte(pci, reg, &data); 376 data &= ~mask; 377 data |= (val & mask); 378 pci_write_config_byte(pci, reg, data); 379 } 380 381 static void azx_init_pci(struct azx *chip) 382 { 383 int snoop_type = azx_get_snoop_type(chip); 384 385 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 386 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 387 * Ensuring these bits are 0 clears playback static on some HD Audio 388 * codecs. 389 * The PCI register TCSEL is defined in the Intel manuals. 390 */ 391 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 392 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 393 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 394 } 395 396 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 397 * we need to enable snoop. 398 */ 399 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 400 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 401 azx_snoop(chip)); 402 update_pci_byte(chip->pci, 403 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 404 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 405 } 406 407 /* For NVIDIA HDA, enable snoop */ 408 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 409 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 410 azx_snoop(chip)); 411 update_pci_byte(chip->pci, 412 NVIDIA_HDA_TRANSREG_ADDR, 413 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 414 update_pci_byte(chip->pci, 415 NVIDIA_HDA_ISTRM_COH, 416 0x01, NVIDIA_HDA_ENABLE_COHBIT); 417 update_pci_byte(chip->pci, 418 NVIDIA_HDA_OSTRM_COH, 419 0x01, NVIDIA_HDA_ENABLE_COHBIT); 420 } 421 422 /* Enable SCH/PCH snoop if needed */ 423 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 424 unsigned short snoop; 425 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 426 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 427 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 428 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 429 if (!azx_snoop(chip)) 430 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 431 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 432 pci_read_config_word(chip->pci, 433 INTEL_SCH_HDA_DEVC, &snoop); 434 } 435 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 436 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 437 "Disabled" : "Enabled"); 438 } 439 } 440 441 /* 442 * In BXT-P A0, HD-Audio DMA requests is later than expected, 443 * and makes an audio stream sensitive to system latencies when 444 * 24/32 bits are playing. 445 * Adjusting threshold of DMA fifo to force the DMA request 446 * sooner to improve latency tolerance at the expense of power. 447 */ 448 static void bxt_reduce_dma_latency(struct azx *chip) 449 { 450 u32 val; 451 452 val = azx_readl(chip, VS_EM4L); 453 val &= (0x3 << 20); 454 azx_writel(chip, VS_EM4L, val); 455 } 456 457 /* 458 * ML_LCAP bits: 459 * bit 0: 6 MHz Supported 460 * bit 1: 12 MHz Supported 461 * bit 2: 24 MHz Supported 462 * bit 3: 48 MHz Supported 463 * bit 4: 96 MHz Supported 464 * bit 5: 192 MHz Supported 465 */ 466 static int intel_get_lctl_scf(struct azx *chip) 467 { 468 struct hdac_bus *bus = azx_bus(chip); 469 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 470 u32 val, t; 471 int i; 472 473 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 474 475 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 476 t = preferred_bits[i]; 477 if (val & (1 << t)) 478 return t; 479 } 480 481 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 482 return 0; 483 } 484 485 static int intel_ml_lctl_set_power(struct azx *chip, int state) 486 { 487 struct hdac_bus *bus = azx_bus(chip); 488 u32 val; 489 int timeout; 490 491 /* 492 * the codecs are sharing the first link setting by default 493 * If other links are enabled for stream, they need similar fix 494 */ 495 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 496 val &= ~AZX_MLCTL_SPA; 497 val |= state << AZX_MLCTL_SPA_SHIFT; 498 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 499 /* wait for CPA */ 500 timeout = 50; 501 while (timeout) { 502 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 503 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 504 return 0; 505 timeout--; 506 udelay(10); 507 } 508 509 return -1; 510 } 511 512 static void intel_init_lctl(struct azx *chip) 513 { 514 struct hdac_bus *bus = azx_bus(chip); 515 u32 val; 516 int ret; 517 518 /* 0. check lctl register value is correct or not */ 519 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 520 /* if SCF is already set, let's use it */ 521 if ((val & ML_LCTL_SCF_MASK) != 0) 522 return; 523 524 /* 525 * Before operating on SPA, CPA must match SPA. 526 * Any deviation may result in undefined behavior. 527 */ 528 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 529 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 530 return; 531 532 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 533 ret = intel_ml_lctl_set_power(chip, 0); 534 udelay(100); 535 if (ret) 536 goto set_spa; 537 538 /* 2. update SCF to select a properly audio clock*/ 539 val &= ~ML_LCTL_SCF_MASK; 540 val |= intel_get_lctl_scf(chip); 541 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 542 543 set_spa: 544 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 545 intel_ml_lctl_set_power(chip, 1); 546 udelay(100); 547 } 548 549 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 550 { 551 struct hdac_bus *bus = azx_bus(chip); 552 struct pci_dev *pci = chip->pci; 553 u32 val; 554 555 snd_hdac_set_codec_wakeup(bus, true); 556 if (chip->driver_type == AZX_DRIVER_SKL) { 557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 558 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 560 } 561 azx_init_chip(chip, full_reset); 562 if (chip->driver_type == AZX_DRIVER_SKL) { 563 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 564 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 565 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 566 } 567 568 snd_hdac_set_codec_wakeup(bus, false); 569 570 /* reduce dma latency to avoid noise */ 571 if (IS_BXT(pci)) 572 bxt_reduce_dma_latency(chip); 573 574 if (bus->mlcap != NULL) 575 intel_init_lctl(chip); 576 } 577 578 /* calculate runtime delay from LPIB */ 579 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 580 unsigned int pos) 581 { 582 struct snd_pcm_substream *substream = azx_dev->core.substream; 583 int stream = substream->stream; 584 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 585 int delay; 586 587 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 588 delay = pos - lpib_pos; 589 else 590 delay = lpib_pos - pos; 591 if (delay < 0) { 592 if (delay >= azx_dev->core.delay_negative_threshold) 593 delay = 0; 594 else 595 delay += azx_dev->core.bufsize; 596 } 597 598 if (delay >= azx_dev->core.period_bytes) { 599 dev_info(chip->card->dev, 600 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 601 delay, azx_dev->core.period_bytes); 602 delay = 0; 603 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 604 chip->get_delay[stream] = NULL; 605 } 606 607 return bytes_to_frames(substream->runtime, delay); 608 } 609 610 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 611 612 /* called from IRQ */ 613 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 614 { 615 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 616 int ok; 617 618 ok = azx_position_ok(chip, azx_dev); 619 if (ok == 1) { 620 azx_dev->irq_pending = 0; 621 return ok; 622 } else if (ok == 0) { 623 /* bogus IRQ, process it later */ 624 azx_dev->irq_pending = 1; 625 schedule_work(&hda->irq_pending_work); 626 } 627 return 0; 628 } 629 630 #define display_power(chip, enable) \ 631 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 632 633 /* 634 * Check whether the current DMA position is acceptable for updating 635 * periods. Returns non-zero if it's OK. 636 * 637 * Many HD-audio controllers appear pretty inaccurate about 638 * the update-IRQ timing. The IRQ is issued before actually the 639 * data is processed. So, we need to process it afterwords in a 640 * workqueue. 641 */ 642 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 643 { 644 struct snd_pcm_substream *substream = azx_dev->core.substream; 645 int stream = substream->stream; 646 u32 wallclk; 647 unsigned int pos; 648 649 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 650 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 651 return -1; /* bogus (too early) interrupt */ 652 653 if (chip->get_position[stream]) 654 pos = chip->get_position[stream](chip, azx_dev); 655 else { /* use the position buffer as default */ 656 pos = azx_get_pos_posbuf(chip, azx_dev); 657 if (!pos || pos == (u32)-1) { 658 dev_info(chip->card->dev, 659 "Invalid position buffer, using LPIB read method instead.\n"); 660 chip->get_position[stream] = azx_get_pos_lpib; 661 if (chip->get_position[0] == azx_get_pos_lpib && 662 chip->get_position[1] == azx_get_pos_lpib) 663 azx_bus(chip)->use_posbuf = false; 664 pos = azx_get_pos_lpib(chip, azx_dev); 665 chip->get_delay[stream] = NULL; 666 } else { 667 chip->get_position[stream] = azx_get_pos_posbuf; 668 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 669 chip->get_delay[stream] = azx_get_delay_from_lpib; 670 } 671 } 672 673 if (pos >= azx_dev->core.bufsize) 674 pos = 0; 675 676 if (WARN_ONCE(!azx_dev->core.period_bytes, 677 "hda-intel: zero azx_dev->period_bytes")) 678 return -1; /* this shouldn't happen! */ 679 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 680 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 681 /* NG - it's below the first next period boundary */ 682 return chip->bdl_pos_adj ? 0 : -1; 683 azx_dev->core.start_wallclk += wallclk; 684 return 1; /* OK, it's fine */ 685 } 686 687 /* 688 * The work for pending PCM period updates. 689 */ 690 static void azx_irq_pending_work(struct work_struct *work) 691 { 692 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 693 struct azx *chip = &hda->chip; 694 struct hdac_bus *bus = azx_bus(chip); 695 struct hdac_stream *s; 696 int pending, ok; 697 698 if (!hda->irq_pending_warned) { 699 dev_info(chip->card->dev, 700 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 701 chip->card->number); 702 hda->irq_pending_warned = 1; 703 } 704 705 for (;;) { 706 pending = 0; 707 spin_lock_irq(&bus->reg_lock); 708 list_for_each_entry(s, &bus->stream_list, list) { 709 struct azx_dev *azx_dev = stream_to_azx_dev(s); 710 if (!azx_dev->irq_pending || 711 !s->substream || 712 !s->running) 713 continue; 714 ok = azx_position_ok(chip, azx_dev); 715 if (ok > 0) { 716 azx_dev->irq_pending = 0; 717 spin_unlock(&bus->reg_lock); 718 snd_pcm_period_elapsed(s->substream); 719 spin_lock(&bus->reg_lock); 720 } else if (ok < 0) { 721 pending = 0; /* too early */ 722 } else 723 pending++; 724 } 725 spin_unlock_irq(&bus->reg_lock); 726 if (!pending) 727 return; 728 msleep(1); 729 } 730 } 731 732 /* clear irq_pending flags and assure no on-going workq */ 733 static void azx_clear_irq_pending(struct azx *chip) 734 { 735 struct hdac_bus *bus = azx_bus(chip); 736 struct hdac_stream *s; 737 738 spin_lock_irq(&bus->reg_lock); 739 list_for_each_entry(s, &bus->stream_list, list) { 740 struct azx_dev *azx_dev = stream_to_azx_dev(s); 741 azx_dev->irq_pending = 0; 742 } 743 spin_unlock_irq(&bus->reg_lock); 744 } 745 746 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 747 { 748 struct hdac_bus *bus = azx_bus(chip); 749 750 if (request_irq(chip->pci->irq, azx_interrupt, 751 chip->msi ? 0 : IRQF_SHARED, 752 chip->card->irq_descr, chip)) { 753 dev_err(chip->card->dev, 754 "unable to grab IRQ %d, disabling device\n", 755 chip->pci->irq); 756 if (do_disconnect) 757 snd_card_disconnect(chip->card); 758 return -1; 759 } 760 bus->irq = chip->pci->irq; 761 chip->card->sync_irq = bus->irq; 762 pci_intx(chip->pci, !chip->msi); 763 return 0; 764 } 765 766 /* get the current DMA position with correction on VIA chips */ 767 static unsigned int azx_via_get_position(struct azx *chip, 768 struct azx_dev *azx_dev) 769 { 770 unsigned int link_pos, mini_pos, bound_pos; 771 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 772 unsigned int fifo_size; 773 774 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 775 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 776 /* Playback, no problem using link position */ 777 return link_pos; 778 } 779 780 /* Capture */ 781 /* For new chipset, 782 * use mod to get the DMA position just like old chipset 783 */ 784 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 785 mod_dma_pos %= azx_dev->core.period_bytes; 786 787 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 788 789 if (azx_dev->insufficient) { 790 /* Link position never gather than FIFO size */ 791 if (link_pos <= fifo_size) 792 return 0; 793 794 azx_dev->insufficient = 0; 795 } 796 797 if (link_pos <= fifo_size) 798 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 799 else 800 mini_pos = link_pos - fifo_size; 801 802 /* Find nearest previous boudary */ 803 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 804 mod_link_pos = link_pos % azx_dev->core.period_bytes; 805 if (mod_link_pos >= fifo_size) 806 bound_pos = link_pos - mod_link_pos; 807 else if (mod_dma_pos >= mod_mini_pos) 808 bound_pos = mini_pos - mod_mini_pos; 809 else { 810 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 811 if (bound_pos >= azx_dev->core.bufsize) 812 bound_pos = 0; 813 } 814 815 /* Calculate real DMA position we want */ 816 return bound_pos + mod_dma_pos; 817 } 818 819 #define AMD_FIFO_SIZE 32 820 821 /* get the current DMA position with FIFO size correction */ 822 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 823 { 824 struct snd_pcm_substream *substream = azx_dev->core.substream; 825 struct snd_pcm_runtime *runtime = substream->runtime; 826 unsigned int pos, delay; 827 828 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 829 if (!runtime) 830 return pos; 831 832 runtime->delay = AMD_FIFO_SIZE; 833 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 834 if (azx_dev->insufficient) { 835 if (pos < delay) { 836 delay = pos; 837 runtime->delay = bytes_to_frames(runtime, pos); 838 } else { 839 azx_dev->insufficient = 0; 840 } 841 } 842 843 /* correct the DMA position for capture stream */ 844 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 845 if (pos < delay) 846 pos += azx_dev->core.bufsize; 847 pos -= delay; 848 } 849 850 return pos; 851 } 852 853 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 854 unsigned int pos) 855 { 856 struct snd_pcm_substream *substream = azx_dev->core.substream; 857 858 /* just read back the calculated value in the above */ 859 return substream->runtime->delay; 860 } 861 862 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 863 struct azx_dev *azx_dev) 864 { 865 return _snd_hdac_chip_readl(azx_bus(chip), 866 AZX_REG_VS_SDXDPIB_XBASE + 867 (AZX_REG_VS_SDXDPIB_XINTERVAL * 868 azx_dev->core.index)); 869 } 870 871 /* get the current DMA position with correction on SKL+ chips */ 872 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 873 { 874 /* DPIB register gives a more accurate position for playback */ 875 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 876 return azx_skl_get_dpib_pos(chip, azx_dev); 877 878 /* For capture, we need to read posbuf, but it requires a delay 879 * for the possible boundary overlap; the read of DPIB fetches the 880 * actual posbuf 881 */ 882 udelay(20); 883 azx_skl_get_dpib_pos(chip, azx_dev); 884 return azx_get_pos_posbuf(chip, azx_dev); 885 } 886 887 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 888 { 889 azx_stop_chip(chip); 890 if (!skip_link_reset) 891 azx_enter_link_reset(chip); 892 azx_clear_irq_pending(chip); 893 display_power(chip, false); 894 } 895 896 #ifdef CONFIG_PM 897 static DEFINE_MUTEX(card_list_lock); 898 static LIST_HEAD(card_list); 899 900 static void azx_shutdown_chip(struct azx *chip) 901 { 902 __azx_shutdown_chip(chip, false); 903 } 904 905 static void azx_add_card_list(struct azx *chip) 906 { 907 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 908 mutex_lock(&card_list_lock); 909 list_add(&hda->list, &card_list); 910 mutex_unlock(&card_list_lock); 911 } 912 913 static void azx_del_card_list(struct azx *chip) 914 { 915 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 916 mutex_lock(&card_list_lock); 917 list_del_init(&hda->list); 918 mutex_unlock(&card_list_lock); 919 } 920 921 /* trigger power-save check at writing parameter */ 922 static int param_set_xint(const char *val, const struct kernel_param *kp) 923 { 924 struct hda_intel *hda; 925 struct azx *chip; 926 int prev = power_save; 927 int ret = param_set_int(val, kp); 928 929 if (ret || prev == power_save) 930 return ret; 931 932 mutex_lock(&card_list_lock); 933 list_for_each_entry(hda, &card_list, list) { 934 chip = &hda->chip; 935 if (!hda->probe_continued || chip->disabled) 936 continue; 937 snd_hda_set_power_save(&chip->bus, power_save * 1000); 938 } 939 mutex_unlock(&card_list_lock); 940 return 0; 941 } 942 943 /* 944 * power management 945 */ 946 static bool azx_is_pm_ready(struct snd_card *card) 947 { 948 struct azx *chip; 949 struct hda_intel *hda; 950 951 if (!card) 952 return false; 953 chip = card->private_data; 954 hda = container_of(chip, struct hda_intel, chip); 955 if (chip->disabled || hda->init_failed || !chip->running) 956 return false; 957 return true; 958 } 959 960 static void __azx_runtime_resume(struct azx *chip) 961 { 962 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 963 struct hdac_bus *bus = azx_bus(chip); 964 struct hda_codec *codec; 965 int status; 966 967 display_power(chip, true); 968 if (hda->need_i915_power) 969 snd_hdac_i915_set_bclk(bus); 970 971 /* Read STATESTS before controller reset */ 972 status = azx_readw(chip, STATESTS); 973 974 azx_init_pci(chip); 975 hda_intel_init_chip(chip, true); 976 977 /* Avoid codec resume if runtime resume is for system suspend */ 978 if (!chip->pm_prepared) { 979 list_for_each_codec(codec, &chip->bus) { 980 if (codec->relaxed_resume) 981 continue; 982 983 if (codec->forced_resume || (status & (1 << codec->addr))) 984 pm_request_resume(hda_codec_dev(codec)); 985 } 986 } 987 988 /* power down again for link-controlled chips */ 989 if (!hda->need_i915_power) 990 display_power(chip, false); 991 } 992 993 #ifdef CONFIG_PM_SLEEP 994 static int azx_prepare(struct device *dev) 995 { 996 struct snd_card *card = dev_get_drvdata(dev); 997 struct azx *chip; 998 999 if (!azx_is_pm_ready(card)) 1000 return 0; 1001 1002 chip = card->private_data; 1003 chip->pm_prepared = 1; 1004 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1005 1006 flush_work(&azx_bus(chip)->unsol_work); 1007 1008 /* HDA controller always requires different WAKEEN for runtime suspend 1009 * and system suspend, so don't use direct-complete here. 1010 */ 1011 return 0; 1012 } 1013 1014 static void azx_complete(struct device *dev) 1015 { 1016 struct snd_card *card = dev_get_drvdata(dev); 1017 struct azx *chip; 1018 1019 if (!azx_is_pm_ready(card)) 1020 return; 1021 1022 chip = card->private_data; 1023 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1024 chip->pm_prepared = 0; 1025 } 1026 1027 static int azx_suspend(struct device *dev) 1028 { 1029 struct snd_card *card = dev_get_drvdata(dev); 1030 struct azx *chip; 1031 struct hdac_bus *bus; 1032 1033 if (!azx_is_pm_ready(card)) 1034 return 0; 1035 1036 chip = card->private_data; 1037 bus = azx_bus(chip); 1038 azx_shutdown_chip(chip); 1039 if (bus->irq >= 0) { 1040 free_irq(bus->irq, chip); 1041 bus->irq = -1; 1042 chip->card->sync_irq = -1; 1043 } 1044 1045 if (chip->msi) 1046 pci_disable_msi(chip->pci); 1047 1048 trace_azx_suspend(chip); 1049 return 0; 1050 } 1051 1052 static int azx_resume(struct device *dev) 1053 { 1054 struct snd_card *card = dev_get_drvdata(dev); 1055 struct azx *chip; 1056 1057 if (!azx_is_pm_ready(card)) 1058 return 0; 1059 1060 chip = card->private_data; 1061 if (chip->msi) 1062 if (pci_enable_msi(chip->pci) < 0) 1063 chip->msi = 0; 1064 if (azx_acquire_irq(chip, 1) < 0) 1065 return -EIO; 1066 1067 __azx_runtime_resume(chip); 1068 1069 trace_azx_resume(chip); 1070 return 0; 1071 } 1072 1073 /* put codec down to D3 at hibernation for Intel SKL+; 1074 * otherwise BIOS may still access the codec and screw up the driver 1075 */ 1076 static int azx_freeze_noirq(struct device *dev) 1077 { 1078 struct snd_card *card = dev_get_drvdata(dev); 1079 struct azx *chip = card->private_data; 1080 struct pci_dev *pci = to_pci_dev(dev); 1081 1082 if (!azx_is_pm_ready(card)) 1083 return 0; 1084 if (chip->driver_type == AZX_DRIVER_SKL) 1085 pci_set_power_state(pci, PCI_D3hot); 1086 1087 return 0; 1088 } 1089 1090 static int azx_thaw_noirq(struct device *dev) 1091 { 1092 struct snd_card *card = dev_get_drvdata(dev); 1093 struct azx *chip = card->private_data; 1094 struct pci_dev *pci = to_pci_dev(dev); 1095 1096 if (!azx_is_pm_ready(card)) 1097 return 0; 1098 if (chip->driver_type == AZX_DRIVER_SKL) 1099 pci_set_power_state(pci, PCI_D0); 1100 1101 return 0; 1102 } 1103 #endif /* CONFIG_PM_SLEEP */ 1104 1105 static int azx_runtime_suspend(struct device *dev) 1106 { 1107 struct snd_card *card = dev_get_drvdata(dev); 1108 struct azx *chip; 1109 1110 if (!azx_is_pm_ready(card)) 1111 return 0; 1112 chip = card->private_data; 1113 1114 /* enable controller wake up event */ 1115 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1116 1117 azx_shutdown_chip(chip); 1118 trace_azx_runtime_suspend(chip); 1119 return 0; 1120 } 1121 1122 static int azx_runtime_resume(struct device *dev) 1123 { 1124 struct snd_card *card = dev_get_drvdata(dev); 1125 struct azx *chip; 1126 1127 if (!azx_is_pm_ready(card)) 1128 return 0; 1129 chip = card->private_data; 1130 __azx_runtime_resume(chip); 1131 1132 /* disable controller Wake Up event*/ 1133 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1134 1135 trace_azx_runtime_resume(chip); 1136 return 0; 1137 } 1138 1139 static int azx_runtime_idle(struct device *dev) 1140 { 1141 struct snd_card *card = dev_get_drvdata(dev); 1142 struct azx *chip; 1143 struct hda_intel *hda; 1144 1145 if (!card) 1146 return 0; 1147 1148 chip = card->private_data; 1149 hda = container_of(chip, struct hda_intel, chip); 1150 if (chip->disabled || hda->init_failed) 1151 return 0; 1152 1153 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1154 azx_bus(chip)->codec_powered || !chip->running) 1155 return -EBUSY; 1156 1157 /* ELD notification gets broken when HD-audio bus is off */ 1158 if (needs_eld_notify_link(chip)) 1159 return -EBUSY; 1160 1161 return 0; 1162 } 1163 1164 static const struct dev_pm_ops azx_pm = { 1165 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1166 #ifdef CONFIG_PM_SLEEP 1167 .prepare = azx_prepare, 1168 .complete = azx_complete, 1169 .freeze_noirq = azx_freeze_noirq, 1170 .thaw_noirq = azx_thaw_noirq, 1171 #endif 1172 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1173 }; 1174 1175 #define AZX_PM_OPS &azx_pm 1176 #else 1177 #define azx_add_card_list(chip) /* NOP */ 1178 #define azx_del_card_list(chip) /* NOP */ 1179 #define AZX_PM_OPS NULL 1180 #endif /* CONFIG_PM */ 1181 1182 1183 static int azx_probe_continue(struct azx *chip); 1184 1185 #ifdef SUPPORT_VGA_SWITCHEROO 1186 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1187 1188 static void azx_vs_set_state(struct pci_dev *pci, 1189 enum vga_switcheroo_state state) 1190 { 1191 struct snd_card *card = pci_get_drvdata(pci); 1192 struct azx *chip = card->private_data; 1193 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1194 struct hda_codec *codec; 1195 bool disabled; 1196 1197 wait_for_completion(&hda->probe_wait); 1198 if (hda->init_failed) 1199 return; 1200 1201 disabled = (state == VGA_SWITCHEROO_OFF); 1202 if (chip->disabled == disabled) 1203 return; 1204 1205 if (!hda->probe_continued) { 1206 chip->disabled = disabled; 1207 if (!disabled) { 1208 dev_info(chip->card->dev, 1209 "Start delayed initialization\n"); 1210 if (azx_probe_continue(chip) < 0) 1211 dev_err(chip->card->dev, "initialization error\n"); 1212 } 1213 } else { 1214 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1215 disabled ? "Disabling" : "Enabling"); 1216 if (disabled) { 1217 list_for_each_codec(codec, &chip->bus) { 1218 pm_runtime_suspend(hda_codec_dev(codec)); 1219 pm_runtime_disable(hda_codec_dev(codec)); 1220 } 1221 pm_runtime_suspend(card->dev); 1222 pm_runtime_disable(card->dev); 1223 /* when we get suspended by vga_switcheroo we end up in D3cold, 1224 * however we have no ACPI handle, so pci/acpi can't put us there, 1225 * put ourselves there */ 1226 pci->current_state = PCI_D3cold; 1227 chip->disabled = true; 1228 if (snd_hda_lock_devices(&chip->bus)) 1229 dev_warn(chip->card->dev, 1230 "Cannot lock devices!\n"); 1231 } else { 1232 snd_hda_unlock_devices(&chip->bus); 1233 chip->disabled = false; 1234 pm_runtime_enable(card->dev); 1235 list_for_each_codec(codec, &chip->bus) { 1236 pm_runtime_enable(hda_codec_dev(codec)); 1237 pm_runtime_resume(hda_codec_dev(codec)); 1238 } 1239 } 1240 } 1241 } 1242 1243 static bool azx_vs_can_switch(struct pci_dev *pci) 1244 { 1245 struct snd_card *card = pci_get_drvdata(pci); 1246 struct azx *chip = card->private_data; 1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1248 1249 wait_for_completion(&hda->probe_wait); 1250 if (hda->init_failed) 1251 return false; 1252 if (chip->disabled || !hda->probe_continued) 1253 return true; 1254 if (snd_hda_lock_devices(&chip->bus)) 1255 return false; 1256 snd_hda_unlock_devices(&chip->bus); 1257 return true; 1258 } 1259 1260 /* 1261 * The discrete GPU cannot power down unless the HDA controller runtime 1262 * suspends, so activate runtime PM on codecs even if power_save == 0. 1263 */ 1264 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1265 { 1266 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1267 struct hda_codec *codec; 1268 1269 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1270 list_for_each_codec(codec, &chip->bus) 1271 codec->auto_runtime_pm = 1; 1272 /* reset the power save setup */ 1273 if (chip->running) 1274 set_default_power_save(chip); 1275 } 1276 } 1277 1278 static void azx_vs_gpu_bound(struct pci_dev *pci, 1279 enum vga_switcheroo_client_id client_id) 1280 { 1281 struct snd_card *card = pci_get_drvdata(pci); 1282 struct azx *chip = card->private_data; 1283 1284 if (client_id == VGA_SWITCHEROO_DIS) 1285 chip->bus.keep_power = 0; 1286 setup_vga_switcheroo_runtime_pm(chip); 1287 } 1288 1289 static void init_vga_switcheroo(struct azx *chip) 1290 { 1291 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1292 struct pci_dev *p = get_bound_vga(chip->pci); 1293 struct pci_dev *parent; 1294 if (p) { 1295 dev_info(chip->card->dev, 1296 "Handle vga_switcheroo audio client\n"); 1297 hda->use_vga_switcheroo = 1; 1298 1299 /* cleared in either gpu_bound op or codec probe, or when its 1300 * upstream port has _PR3 (i.e. dGPU). 1301 */ 1302 parent = pci_upstream_bridge(p); 1303 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1304 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1305 pci_dev_put(p); 1306 } 1307 } 1308 1309 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1310 .set_gpu_state = azx_vs_set_state, 1311 .can_switch = azx_vs_can_switch, 1312 .gpu_bound = azx_vs_gpu_bound, 1313 }; 1314 1315 static int register_vga_switcheroo(struct azx *chip) 1316 { 1317 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1318 struct pci_dev *p; 1319 int err; 1320 1321 if (!hda->use_vga_switcheroo) 1322 return 0; 1323 1324 p = get_bound_vga(chip->pci); 1325 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1326 pci_dev_put(p); 1327 1328 if (err < 0) 1329 return err; 1330 hda->vga_switcheroo_registered = 1; 1331 1332 return 0; 1333 } 1334 #else 1335 #define init_vga_switcheroo(chip) /* NOP */ 1336 #define register_vga_switcheroo(chip) 0 1337 #define check_hdmi_disabled(pci) false 1338 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1339 #endif /* SUPPORT_VGA_SWITCHER */ 1340 1341 /* 1342 * destructor 1343 */ 1344 static void azx_free(struct azx *chip) 1345 { 1346 struct pci_dev *pci = chip->pci; 1347 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1348 struct hdac_bus *bus = azx_bus(chip); 1349 1350 if (hda->freed) 1351 return; 1352 1353 if (azx_has_pm_runtime(chip) && chip->running) 1354 pm_runtime_get_noresume(&pci->dev); 1355 chip->running = 0; 1356 1357 azx_del_card_list(chip); 1358 1359 hda->init_failed = 1; /* to be sure */ 1360 complete_all(&hda->probe_wait); 1361 1362 if (use_vga_switcheroo(hda)) { 1363 if (chip->disabled && hda->probe_continued) 1364 snd_hda_unlock_devices(&chip->bus); 1365 if (hda->vga_switcheroo_registered) 1366 vga_switcheroo_unregister_client(chip->pci); 1367 } 1368 1369 if (bus->chip_init) { 1370 azx_clear_irq_pending(chip); 1371 azx_stop_all_streams(chip); 1372 azx_stop_chip(chip); 1373 } 1374 1375 if (bus->irq >= 0) 1376 free_irq(bus->irq, (void*)chip); 1377 1378 azx_free_stream_pages(chip); 1379 azx_free_streams(chip); 1380 snd_hdac_bus_exit(bus); 1381 1382 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1383 release_firmware(chip->fw); 1384 #endif 1385 display_power(chip, false); 1386 1387 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1388 snd_hdac_i915_exit(bus); 1389 1390 hda->freed = 1; 1391 } 1392 1393 static int azx_dev_disconnect(struct snd_device *device) 1394 { 1395 struct azx *chip = device->device_data; 1396 struct hdac_bus *bus = azx_bus(chip); 1397 1398 chip->bus.shutdown = 1; 1399 cancel_work_sync(&bus->unsol_work); 1400 1401 return 0; 1402 } 1403 1404 static int azx_dev_free(struct snd_device *device) 1405 { 1406 azx_free(device->device_data); 1407 return 0; 1408 } 1409 1410 #ifdef SUPPORT_VGA_SWITCHEROO 1411 #ifdef CONFIG_ACPI 1412 /* ATPX is in the integrated GPU's namespace */ 1413 static bool atpx_present(void) 1414 { 1415 struct pci_dev *pdev = NULL; 1416 acpi_handle dhandle, atpx_handle; 1417 acpi_status status; 1418 1419 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1420 dhandle = ACPI_HANDLE(&pdev->dev); 1421 if (dhandle) { 1422 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1423 if (ACPI_SUCCESS(status)) { 1424 pci_dev_put(pdev); 1425 return true; 1426 } 1427 } 1428 } 1429 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1430 dhandle = ACPI_HANDLE(&pdev->dev); 1431 if (dhandle) { 1432 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1433 if (ACPI_SUCCESS(status)) { 1434 pci_dev_put(pdev); 1435 return true; 1436 } 1437 } 1438 } 1439 return false; 1440 } 1441 #else 1442 static bool atpx_present(void) 1443 { 1444 return false; 1445 } 1446 #endif 1447 1448 /* 1449 * Check of disabled HDMI controller by vga_switcheroo 1450 */ 1451 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1452 { 1453 struct pci_dev *p; 1454 1455 /* check only discrete GPU */ 1456 switch (pci->vendor) { 1457 case PCI_VENDOR_ID_ATI: 1458 case PCI_VENDOR_ID_AMD: 1459 if (pci->devfn == 1) { 1460 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1461 pci->bus->number, 0); 1462 if (p) { 1463 /* ATPX is in the integrated GPU's ACPI namespace 1464 * rather than the dGPU's namespace. However, 1465 * the dGPU is the one who is involved in 1466 * vgaswitcheroo. 1467 */ 1468 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1469 atpx_present()) 1470 return p; 1471 pci_dev_put(p); 1472 } 1473 } 1474 break; 1475 case PCI_VENDOR_ID_NVIDIA: 1476 if (pci->devfn == 1) { 1477 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1478 pci->bus->number, 0); 1479 if (p) { 1480 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1481 return p; 1482 pci_dev_put(p); 1483 } 1484 } 1485 break; 1486 } 1487 return NULL; 1488 } 1489 1490 static bool check_hdmi_disabled(struct pci_dev *pci) 1491 { 1492 bool vga_inactive = false; 1493 struct pci_dev *p = get_bound_vga(pci); 1494 1495 if (p) { 1496 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1497 vga_inactive = true; 1498 pci_dev_put(p); 1499 } 1500 return vga_inactive; 1501 } 1502 #endif /* SUPPORT_VGA_SWITCHEROO */ 1503 1504 /* 1505 * allow/deny-listing for position_fix 1506 */ 1507 static const struct snd_pci_quirk position_fix_list[] = { 1508 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1510 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1511 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1512 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1516 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1517 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1518 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1519 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1520 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1521 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1522 {} 1523 }; 1524 1525 static int check_position_fix(struct azx *chip, int fix) 1526 { 1527 const struct snd_pci_quirk *q; 1528 1529 switch (fix) { 1530 case POS_FIX_AUTO: 1531 case POS_FIX_LPIB: 1532 case POS_FIX_POSBUF: 1533 case POS_FIX_VIACOMBO: 1534 case POS_FIX_COMBO: 1535 case POS_FIX_SKL: 1536 case POS_FIX_FIFO: 1537 return fix; 1538 } 1539 1540 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1541 if (q) { 1542 dev_info(chip->card->dev, 1543 "position_fix set to %d for device %04x:%04x\n", 1544 q->value, q->subvendor, q->subdevice); 1545 return q->value; 1546 } 1547 1548 /* Check VIA/ATI HD Audio Controller exist */ 1549 if (chip->driver_type == AZX_DRIVER_VIA) { 1550 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1551 return POS_FIX_VIACOMBO; 1552 } 1553 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1554 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1555 return POS_FIX_FIFO; 1556 } 1557 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1558 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1559 return POS_FIX_LPIB; 1560 } 1561 if (chip->driver_type == AZX_DRIVER_SKL) { 1562 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1563 return POS_FIX_SKL; 1564 } 1565 return POS_FIX_AUTO; 1566 } 1567 1568 static void assign_position_fix(struct azx *chip, int fix) 1569 { 1570 static const azx_get_pos_callback_t callbacks[] = { 1571 [POS_FIX_AUTO] = NULL, 1572 [POS_FIX_LPIB] = azx_get_pos_lpib, 1573 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1574 [POS_FIX_VIACOMBO] = azx_via_get_position, 1575 [POS_FIX_COMBO] = azx_get_pos_lpib, 1576 [POS_FIX_SKL] = azx_get_pos_skl, 1577 [POS_FIX_FIFO] = azx_get_pos_fifo, 1578 }; 1579 1580 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1581 1582 /* combo mode uses LPIB only for playback */ 1583 if (fix == POS_FIX_COMBO) 1584 chip->get_position[1] = NULL; 1585 1586 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1587 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1588 chip->get_delay[0] = chip->get_delay[1] = 1589 azx_get_delay_from_lpib; 1590 } 1591 1592 if (fix == POS_FIX_FIFO) 1593 chip->get_delay[0] = chip->get_delay[1] = 1594 azx_get_delay_from_fifo; 1595 } 1596 1597 /* 1598 * deny-lists for probe_mask 1599 */ 1600 static const struct snd_pci_quirk probe_mask_list[] = { 1601 /* Thinkpad often breaks the controller communication when accessing 1602 * to the non-working (or non-existing) modem codec slot. 1603 */ 1604 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1605 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1606 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1607 /* broken BIOS */ 1608 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1609 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1610 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1611 /* forced codec slots */ 1612 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1613 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1614 /* WinFast VP200 H (Teradici) user reported broken communication */ 1615 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1616 {} 1617 }; 1618 1619 #define AZX_FORCE_CODEC_MASK 0x100 1620 1621 static void check_probe_mask(struct azx *chip, int dev) 1622 { 1623 const struct snd_pci_quirk *q; 1624 1625 chip->codec_probe_mask = probe_mask[dev]; 1626 if (chip->codec_probe_mask == -1) { 1627 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1628 if (q) { 1629 dev_info(chip->card->dev, 1630 "probe_mask set to 0x%x for device %04x:%04x\n", 1631 q->value, q->subvendor, q->subdevice); 1632 chip->codec_probe_mask = q->value; 1633 } 1634 } 1635 1636 /* check forced option */ 1637 if (chip->codec_probe_mask != -1 && 1638 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1639 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1640 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1641 (int)azx_bus(chip)->codec_mask); 1642 } 1643 } 1644 1645 /* 1646 * allow/deny-list for enable_msi 1647 */ 1648 static const struct snd_pci_quirk msi_deny_list[] = { 1649 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1650 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1651 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1652 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1653 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1654 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1655 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1656 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1657 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1658 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1659 {} 1660 }; 1661 1662 static void check_msi(struct azx *chip) 1663 { 1664 const struct snd_pci_quirk *q; 1665 1666 if (enable_msi >= 0) { 1667 chip->msi = !!enable_msi; 1668 return; 1669 } 1670 chip->msi = 1; /* enable MSI as default */ 1671 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1672 if (q) { 1673 dev_info(chip->card->dev, 1674 "msi for device %04x:%04x set to %d\n", 1675 q->subvendor, q->subdevice, q->value); 1676 chip->msi = q->value; 1677 return; 1678 } 1679 1680 /* NVidia chipsets seem to cause troubles with MSI */ 1681 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1682 dev_info(chip->card->dev, "Disabling MSI\n"); 1683 chip->msi = 0; 1684 } 1685 } 1686 1687 /* check the snoop mode availability */ 1688 static void azx_check_snoop_available(struct azx *chip) 1689 { 1690 int snoop = hda_snoop; 1691 1692 if (snoop >= 0) { 1693 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1694 snoop ? "snoop" : "non-snoop"); 1695 chip->snoop = snoop; 1696 chip->uc_buffer = !snoop; 1697 return; 1698 } 1699 1700 snoop = true; 1701 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1702 chip->driver_type == AZX_DRIVER_VIA) { 1703 /* force to non-snoop mode for a new VIA controller 1704 * when BIOS is set 1705 */ 1706 u8 val; 1707 pci_read_config_byte(chip->pci, 0x42, &val); 1708 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1709 chip->pci->revision == 0x20)) 1710 snoop = false; 1711 } 1712 1713 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1714 snoop = false; 1715 1716 chip->snoop = snoop; 1717 if (!snoop) { 1718 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1719 /* C-Media requires non-cached pages only for CORB/RIRB */ 1720 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1721 chip->uc_buffer = true; 1722 } 1723 } 1724 1725 static void azx_probe_work(struct work_struct *work) 1726 { 1727 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1728 azx_probe_continue(&hda->chip); 1729 } 1730 1731 static int default_bdl_pos_adj(struct azx *chip) 1732 { 1733 /* some exceptions: Atoms seem problematic with value 1 */ 1734 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1735 switch (chip->pci->device) { 1736 case 0x0f04: /* Baytrail */ 1737 case 0x2284: /* Braswell */ 1738 return 32; 1739 } 1740 } 1741 1742 switch (chip->driver_type) { 1743 case AZX_DRIVER_ICH: 1744 case AZX_DRIVER_PCH: 1745 return 1; 1746 default: 1747 return 32; 1748 } 1749 } 1750 1751 /* 1752 * constructor 1753 */ 1754 static const struct hda_controller_ops pci_hda_ops; 1755 1756 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1757 int dev, unsigned int driver_caps, 1758 struct azx **rchip) 1759 { 1760 static const struct snd_device_ops ops = { 1761 .dev_disconnect = azx_dev_disconnect, 1762 .dev_free = azx_dev_free, 1763 }; 1764 struct hda_intel *hda; 1765 struct azx *chip; 1766 int err; 1767 1768 *rchip = NULL; 1769 1770 err = pcim_enable_device(pci); 1771 if (err < 0) 1772 return err; 1773 1774 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1775 if (!hda) 1776 return -ENOMEM; 1777 1778 chip = &hda->chip; 1779 mutex_init(&chip->open_mutex); 1780 chip->card = card; 1781 chip->pci = pci; 1782 chip->ops = &pci_hda_ops; 1783 chip->driver_caps = driver_caps; 1784 chip->driver_type = driver_caps & 0xff; 1785 check_msi(chip); 1786 chip->dev_index = dev; 1787 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1788 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1789 INIT_LIST_HEAD(&chip->pcm_list); 1790 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1791 INIT_LIST_HEAD(&hda->list); 1792 init_vga_switcheroo(chip); 1793 init_completion(&hda->probe_wait); 1794 1795 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1796 1797 check_probe_mask(chip, dev); 1798 1799 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1800 chip->fallback_to_single_cmd = 1; 1801 else /* explicitly set to single_cmd or not */ 1802 chip->single_cmd = single_cmd; 1803 1804 azx_check_snoop_available(chip); 1805 1806 if (bdl_pos_adj[dev] < 0) 1807 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1808 else 1809 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1810 1811 err = azx_bus_init(chip, model[dev]); 1812 if (err < 0) 1813 return err; 1814 1815 /* use the non-cached pages in non-snoop mode */ 1816 if (!azx_snoop(chip)) 1817 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC; 1818 1819 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1820 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1821 chip->bus.core.needs_damn_long_delay = 1; 1822 } 1823 1824 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1825 if (err < 0) { 1826 dev_err(card->dev, "Error creating device [card]!\n"); 1827 azx_free(chip); 1828 return err; 1829 } 1830 1831 /* continue probing in work context as may trigger request module */ 1832 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1833 1834 *rchip = chip; 1835 1836 return 0; 1837 } 1838 1839 static int azx_first_init(struct azx *chip) 1840 { 1841 int dev = chip->dev_index; 1842 struct pci_dev *pci = chip->pci; 1843 struct snd_card *card = chip->card; 1844 struct hdac_bus *bus = azx_bus(chip); 1845 int err; 1846 unsigned short gcap; 1847 unsigned int dma_bits = 64; 1848 1849 #if BITS_PER_LONG != 64 1850 /* Fix up base address on ULI M5461 */ 1851 if (chip->driver_type == AZX_DRIVER_ULI) { 1852 u16 tmp3; 1853 pci_read_config_word(pci, 0x40, &tmp3); 1854 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1855 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1856 } 1857 #endif 1858 1859 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1860 if (err < 0) 1861 return err; 1862 1863 bus->addr = pci_resource_start(pci, 0); 1864 bus->remap_addr = pcim_iomap_table(pci)[0]; 1865 1866 if (chip->driver_type == AZX_DRIVER_SKL) 1867 snd_hdac_bus_parse_capabilities(bus); 1868 1869 /* 1870 * Some Intel CPUs has always running timer (ART) feature and 1871 * controller may have Global time sync reporting capability, so 1872 * check both of these before declaring synchronized time reporting 1873 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1874 */ 1875 chip->gts_present = false; 1876 1877 #ifdef CONFIG_X86 1878 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1879 chip->gts_present = true; 1880 #endif 1881 1882 if (chip->msi) { 1883 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1884 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1885 pci->no_64bit_msi = true; 1886 } 1887 if (pci_enable_msi(pci) < 0) 1888 chip->msi = 0; 1889 } 1890 1891 pci_set_master(pci); 1892 1893 gcap = azx_readw(chip, GCAP); 1894 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1895 1896 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1897 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1898 dma_bits = 40; 1899 1900 /* disable SB600 64bit support for safety */ 1901 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1902 struct pci_dev *p_smbus; 1903 dma_bits = 40; 1904 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1905 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1906 NULL); 1907 if (p_smbus) { 1908 if (p_smbus->revision < 0x30) 1909 gcap &= ~AZX_GCAP_64OK; 1910 pci_dev_put(p_smbus); 1911 } 1912 } 1913 1914 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1915 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1916 dma_bits = 40; 1917 1918 /* disable 64bit DMA address on some devices */ 1919 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1920 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1921 gcap &= ~AZX_GCAP_64OK; 1922 } 1923 1924 /* disable buffer size rounding to 128-byte multiples if supported */ 1925 if (align_buffer_size >= 0) 1926 chip->align_buffer_size = !!align_buffer_size; 1927 else { 1928 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1929 chip->align_buffer_size = 0; 1930 else 1931 chip->align_buffer_size = 1; 1932 } 1933 1934 /* allow 64bit DMA address if supported by H/W */ 1935 if (!(gcap & AZX_GCAP_64OK)) 1936 dma_bits = 32; 1937 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1938 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1939 1940 /* read number of streams from GCAP register instead of using 1941 * hardcoded value 1942 */ 1943 chip->capture_streams = (gcap >> 8) & 0x0f; 1944 chip->playback_streams = (gcap >> 12) & 0x0f; 1945 if (!chip->playback_streams && !chip->capture_streams) { 1946 /* gcap didn't give any info, switching to old method */ 1947 1948 switch (chip->driver_type) { 1949 case AZX_DRIVER_ULI: 1950 chip->playback_streams = ULI_NUM_PLAYBACK; 1951 chip->capture_streams = ULI_NUM_CAPTURE; 1952 break; 1953 case AZX_DRIVER_ATIHDMI: 1954 case AZX_DRIVER_ATIHDMI_NS: 1955 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1956 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1957 break; 1958 case AZX_DRIVER_GENERIC: 1959 default: 1960 chip->playback_streams = ICH6_NUM_PLAYBACK; 1961 chip->capture_streams = ICH6_NUM_CAPTURE; 1962 break; 1963 } 1964 } 1965 chip->capture_index_offset = 0; 1966 chip->playback_index_offset = chip->capture_streams; 1967 chip->num_streams = chip->playback_streams + chip->capture_streams; 1968 1969 /* sanity check for the SDxCTL.STRM field overflow */ 1970 if (chip->num_streams > 15 && 1971 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1972 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1973 "forcing separate stream tags", chip->num_streams); 1974 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1975 } 1976 1977 /* initialize streams */ 1978 err = azx_init_streams(chip); 1979 if (err < 0) 1980 return err; 1981 1982 err = azx_alloc_stream_pages(chip); 1983 if (err < 0) 1984 return err; 1985 1986 /* initialize chip */ 1987 azx_init_pci(chip); 1988 1989 snd_hdac_i915_set_bclk(bus); 1990 1991 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1992 1993 /* codec detection */ 1994 if (!azx_bus(chip)->codec_mask) { 1995 dev_err(card->dev, "no codecs found!\n"); 1996 /* keep running the rest for the runtime PM */ 1997 } 1998 1999 if (azx_acquire_irq(chip, 0) < 0) 2000 return -EBUSY; 2001 2002 strcpy(card->driver, "HDA-Intel"); 2003 strscpy(card->shortname, driver_short_names[chip->driver_type], 2004 sizeof(card->shortname)); 2005 snprintf(card->longname, sizeof(card->longname), 2006 "%s at 0x%lx irq %i", 2007 card->shortname, bus->addr, bus->irq); 2008 2009 return 0; 2010 } 2011 2012 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2013 /* callback from request_firmware_nowait() */ 2014 static void azx_firmware_cb(const struct firmware *fw, void *context) 2015 { 2016 struct snd_card *card = context; 2017 struct azx *chip = card->private_data; 2018 2019 if (fw) 2020 chip->fw = fw; 2021 else 2022 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2023 if (!chip->disabled) { 2024 /* continue probing */ 2025 azx_probe_continue(chip); 2026 } 2027 } 2028 #endif 2029 2030 static int disable_msi_reset_irq(struct azx *chip) 2031 { 2032 struct hdac_bus *bus = azx_bus(chip); 2033 int err; 2034 2035 free_irq(bus->irq, chip); 2036 bus->irq = -1; 2037 chip->card->sync_irq = -1; 2038 pci_disable_msi(chip->pci); 2039 chip->msi = 0; 2040 err = azx_acquire_irq(chip, 1); 2041 if (err < 0) 2042 return err; 2043 2044 return 0; 2045 } 2046 2047 /* Denylist for skipping the whole probe: 2048 * some HD-audio PCI entries are exposed without any codecs, and such devices 2049 * should be ignored from the beginning. 2050 */ 2051 static const struct pci_device_id driver_denylist[] = { 2052 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2053 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2054 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2055 {} 2056 }; 2057 2058 static const struct hda_controller_ops pci_hda_ops = { 2059 .disable_msi_reset_irq = disable_msi_reset_irq, 2060 .position_check = azx_position_check, 2061 }; 2062 2063 static int azx_probe(struct pci_dev *pci, 2064 const struct pci_device_id *pci_id) 2065 { 2066 static int dev; 2067 struct snd_card *card; 2068 struct hda_intel *hda; 2069 struct azx *chip; 2070 bool schedule_probe; 2071 int err; 2072 2073 if (pci_match_id(driver_denylist, pci)) { 2074 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2075 return -ENODEV; 2076 } 2077 2078 if (dev >= SNDRV_CARDS) 2079 return -ENODEV; 2080 if (!enable[dev]) { 2081 dev++; 2082 return -ENOENT; 2083 } 2084 2085 /* 2086 * stop probe if another Intel's DSP driver should be activated 2087 */ 2088 if (dmic_detect) { 2089 err = snd_intel_dsp_driver_probe(pci); 2090 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2091 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2092 return -ENODEV; 2093 } 2094 } else { 2095 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2096 } 2097 2098 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2099 0, &card); 2100 if (err < 0) { 2101 dev_err(&pci->dev, "Error creating card!\n"); 2102 return err; 2103 } 2104 2105 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2106 if (err < 0) 2107 goto out_free; 2108 card->private_data = chip; 2109 hda = container_of(chip, struct hda_intel, chip); 2110 2111 pci_set_drvdata(pci, card); 2112 2113 err = register_vga_switcheroo(chip); 2114 if (err < 0) { 2115 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2116 goto out_free; 2117 } 2118 2119 if (check_hdmi_disabled(pci)) { 2120 dev_info(card->dev, "VGA controller is disabled\n"); 2121 dev_info(card->dev, "Delaying initialization\n"); 2122 chip->disabled = true; 2123 } 2124 2125 schedule_probe = !chip->disabled; 2126 2127 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2128 if (patch[dev] && *patch[dev]) { 2129 dev_info(card->dev, "Applying patch firmware '%s'\n", 2130 patch[dev]); 2131 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2132 &pci->dev, GFP_KERNEL, card, 2133 azx_firmware_cb); 2134 if (err < 0) 2135 goto out_free; 2136 schedule_probe = false; /* continued in azx_firmware_cb() */ 2137 } 2138 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2139 2140 #ifndef CONFIG_SND_HDA_I915 2141 if (CONTROLLER_IN_GPU(pci)) 2142 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2143 #endif 2144 2145 if (schedule_probe) 2146 schedule_delayed_work(&hda->probe_work, 0); 2147 2148 dev++; 2149 if (chip->disabled) 2150 complete_all(&hda->probe_wait); 2151 return 0; 2152 2153 out_free: 2154 snd_card_free(card); 2155 return err; 2156 } 2157 2158 #ifdef CONFIG_PM 2159 /* On some boards setting power_save to a non 0 value leads to clicking / 2160 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2161 * figure out how to avoid these sounds, but that is not always feasible. 2162 * So we keep a list of devices where we disable powersaving as its known 2163 * to causes problems on these devices. 2164 */ 2165 static const struct snd_pci_quirk power_save_denylist[] = { 2166 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2167 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2168 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2169 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2170 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2171 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2172 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2173 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2174 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2175 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2176 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2177 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2178 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2179 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2180 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2181 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2182 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2183 /* https://bugs.launchpad.net/bugs/1821663 */ 2184 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2185 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2186 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2187 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2188 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2189 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2190 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2191 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2192 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2193 /* https://bugs.launchpad.net/bugs/1821663 */ 2194 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2195 {} 2196 }; 2197 #endif /* CONFIG_PM */ 2198 2199 static void set_default_power_save(struct azx *chip) 2200 { 2201 int val = power_save; 2202 2203 #ifdef CONFIG_PM 2204 if (pm_blacklist) { 2205 const struct snd_pci_quirk *q; 2206 2207 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2208 if (q && val) { 2209 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2210 q->subvendor, q->subdevice); 2211 val = 0; 2212 } 2213 } 2214 #endif /* CONFIG_PM */ 2215 snd_hda_set_power_save(&chip->bus, val * 1000); 2216 } 2217 2218 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2219 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2220 [AZX_DRIVER_NVIDIA] = 8, 2221 [AZX_DRIVER_TERA] = 1, 2222 }; 2223 2224 static int azx_probe_continue(struct azx *chip) 2225 { 2226 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2227 struct hdac_bus *bus = azx_bus(chip); 2228 struct pci_dev *pci = chip->pci; 2229 int dev = chip->dev_index; 2230 int err; 2231 2232 if (chip->disabled || hda->init_failed) 2233 return -EIO; 2234 if (hda->probe_retry) 2235 goto probe_retry; 2236 2237 to_hda_bus(bus)->bus_probing = 1; 2238 hda->probe_continued = 1; 2239 2240 /* bind with i915 if needed */ 2241 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2242 err = snd_hdac_i915_init(bus); 2243 if (err < 0) { 2244 /* if the controller is bound only with HDMI/DP 2245 * (for HSW and BDW), we need to abort the probe; 2246 * for other chips, still continue probing as other 2247 * codecs can be on the same link. 2248 */ 2249 if (CONTROLLER_IN_GPU(pci)) { 2250 dev_err(chip->card->dev, 2251 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2252 goto out_free; 2253 } else { 2254 /* don't bother any longer */ 2255 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2256 } 2257 } 2258 2259 /* HSW/BDW controllers need this power */ 2260 if (CONTROLLER_IN_GPU(pci)) 2261 hda->need_i915_power = true; 2262 } 2263 2264 /* Request display power well for the HDA controller or codec. For 2265 * Haswell/Broadwell, both the display HDA controller and codec need 2266 * this power. For other platforms, like Baytrail/Braswell, only the 2267 * display codec needs the power and it can be released after probe. 2268 */ 2269 display_power(chip, true); 2270 2271 err = azx_first_init(chip); 2272 if (err < 0) 2273 goto out_free; 2274 2275 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2276 chip->beep_mode = beep_mode[dev]; 2277 #endif 2278 2279 /* create codec instances */ 2280 if (bus->codec_mask) { 2281 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2282 if (err < 0) 2283 goto out_free; 2284 } 2285 2286 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2287 if (chip->fw) { 2288 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2289 chip->fw->data); 2290 if (err < 0) 2291 goto out_free; 2292 #ifndef CONFIG_PM 2293 release_firmware(chip->fw); /* no longer needed */ 2294 chip->fw = NULL; 2295 #endif 2296 } 2297 #endif 2298 2299 probe_retry: 2300 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2301 err = azx_codec_configure(chip); 2302 if (err) { 2303 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2304 ++hda->probe_retry < 60) { 2305 schedule_delayed_work(&hda->probe_work, 2306 msecs_to_jiffies(1000)); 2307 return 0; /* keep things up */ 2308 } 2309 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2310 goto out_free; 2311 } 2312 } 2313 2314 err = snd_card_register(chip->card); 2315 if (err < 0) 2316 goto out_free; 2317 2318 setup_vga_switcheroo_runtime_pm(chip); 2319 2320 chip->running = 1; 2321 azx_add_card_list(chip); 2322 2323 set_default_power_save(chip); 2324 2325 if (azx_has_pm_runtime(chip)) { 2326 pm_runtime_use_autosuspend(&pci->dev); 2327 pm_runtime_allow(&pci->dev); 2328 pm_runtime_put_autosuspend(&pci->dev); 2329 } 2330 2331 out_free: 2332 if (err < 0) { 2333 azx_free(chip); 2334 return err; 2335 } 2336 2337 if (!hda->need_i915_power) 2338 display_power(chip, false); 2339 complete_all(&hda->probe_wait); 2340 to_hda_bus(bus)->bus_probing = 0; 2341 hda->probe_retry = 0; 2342 return 0; 2343 } 2344 2345 static void azx_remove(struct pci_dev *pci) 2346 { 2347 struct snd_card *card = pci_get_drvdata(pci); 2348 struct azx *chip; 2349 struct hda_intel *hda; 2350 2351 if (card) { 2352 /* cancel the pending probing work */ 2353 chip = card->private_data; 2354 hda = container_of(chip, struct hda_intel, chip); 2355 /* FIXME: below is an ugly workaround. 2356 * Both device_release_driver() and driver_probe_device() 2357 * take *both* the device's and its parent's lock before 2358 * calling the remove() and probe() callbacks. The codec 2359 * probe takes the locks of both the codec itself and its 2360 * parent, i.e. the PCI controller dev. Meanwhile, when 2361 * the PCI controller is unbound, it takes its lock, too 2362 * ==> ouch, a deadlock! 2363 * As a workaround, we unlock temporarily here the controller 2364 * device during cancel_work_sync() call. 2365 */ 2366 device_unlock(&pci->dev); 2367 cancel_delayed_work_sync(&hda->probe_work); 2368 device_lock(&pci->dev); 2369 2370 snd_card_free(card); 2371 } 2372 } 2373 2374 static void azx_shutdown(struct pci_dev *pci) 2375 { 2376 struct snd_card *card = pci_get_drvdata(pci); 2377 struct azx *chip; 2378 2379 if (!card) 2380 return; 2381 chip = card->private_data; 2382 if (chip && chip->running) 2383 __azx_shutdown_chip(chip, true); 2384 } 2385 2386 /* PCI IDs */ 2387 static const struct pci_device_id azx_ids[] = { 2388 /* CPT */ 2389 { PCI_DEVICE(0x8086, 0x1c20), 2390 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2391 /* PBG */ 2392 { PCI_DEVICE(0x8086, 0x1d20), 2393 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2394 /* Panther Point */ 2395 { PCI_DEVICE(0x8086, 0x1e20), 2396 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2397 /* Lynx Point */ 2398 { PCI_DEVICE(0x8086, 0x8c20), 2399 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2400 /* 9 Series */ 2401 { PCI_DEVICE(0x8086, 0x8ca0), 2402 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2403 /* Wellsburg */ 2404 { PCI_DEVICE(0x8086, 0x8d20), 2405 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2406 { PCI_DEVICE(0x8086, 0x8d21), 2407 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2408 /* Lewisburg */ 2409 { PCI_DEVICE(0x8086, 0xa1f0), 2410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2411 { PCI_DEVICE(0x8086, 0xa270), 2412 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2413 /* Lynx Point-LP */ 2414 { PCI_DEVICE(0x8086, 0x9c20), 2415 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2416 /* Lynx Point-LP */ 2417 { PCI_DEVICE(0x8086, 0x9c21), 2418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2419 /* Wildcat Point-LP */ 2420 { PCI_DEVICE(0x8086, 0x9ca0), 2421 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2422 /* Sunrise Point */ 2423 { PCI_DEVICE(0x8086, 0xa170), 2424 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2425 /* Sunrise Point-LP */ 2426 { PCI_DEVICE(0x8086, 0x9d70), 2427 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2428 /* Kabylake */ 2429 { PCI_DEVICE(0x8086, 0xa171), 2430 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2431 /* Kabylake-LP */ 2432 { PCI_DEVICE(0x8086, 0x9d71), 2433 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2434 /* Kabylake-H */ 2435 { PCI_DEVICE(0x8086, 0xa2f0), 2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2437 /* Coffelake */ 2438 { PCI_DEVICE(0x8086, 0xa348), 2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2440 /* Cannonlake */ 2441 { PCI_DEVICE(0x8086, 0x9dc8), 2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2443 /* CometLake-LP */ 2444 { PCI_DEVICE(0x8086, 0x02C8), 2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2446 /* CometLake-H */ 2447 { PCI_DEVICE(0x8086, 0x06C8), 2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2449 { PCI_DEVICE(0x8086, 0xf1c8), 2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2451 /* CometLake-S */ 2452 { PCI_DEVICE(0x8086, 0xa3f0), 2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2454 /* CometLake-R */ 2455 { PCI_DEVICE(0x8086, 0xf0c8), 2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2457 /* Icelake */ 2458 { PCI_DEVICE(0x8086, 0x34c8), 2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2460 /* Icelake-H */ 2461 { PCI_DEVICE(0x8086, 0x3dc8), 2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2463 /* Jasperlake */ 2464 { PCI_DEVICE(0x8086, 0x38c8), 2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2466 { PCI_DEVICE(0x8086, 0x4dc8), 2467 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2468 /* Tigerlake */ 2469 { PCI_DEVICE(0x8086, 0xa0c8), 2470 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2471 /* Tigerlake-H */ 2472 { PCI_DEVICE(0x8086, 0x43c8), 2473 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2474 /* DG1 */ 2475 { PCI_DEVICE(0x8086, 0x490d), 2476 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2477 /* Alderlake-S */ 2478 { PCI_DEVICE(0x8086, 0x7ad0), 2479 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2480 /* Alderlake-P */ 2481 { PCI_DEVICE(0x8086, 0x51c8), 2482 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2483 /* Alderlake-M */ 2484 { PCI_DEVICE(0x8086, 0x51cc), 2485 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2486 /* Elkhart Lake */ 2487 { PCI_DEVICE(0x8086, 0x4b55), 2488 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2489 { PCI_DEVICE(0x8086, 0x4b58), 2490 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2491 /* Broxton-P(Apollolake) */ 2492 { PCI_DEVICE(0x8086, 0x5a98), 2493 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2494 /* Broxton-T */ 2495 { PCI_DEVICE(0x8086, 0x1a98), 2496 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2497 /* Gemini-Lake */ 2498 { PCI_DEVICE(0x8086, 0x3198), 2499 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2500 /* Haswell */ 2501 { PCI_DEVICE(0x8086, 0x0a0c), 2502 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2503 { PCI_DEVICE(0x8086, 0x0c0c), 2504 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2505 { PCI_DEVICE(0x8086, 0x0d0c), 2506 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2507 /* Broadwell */ 2508 { PCI_DEVICE(0x8086, 0x160c), 2509 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2510 /* 5 Series/3400 */ 2511 { PCI_DEVICE(0x8086, 0x3b56), 2512 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2513 /* Poulsbo */ 2514 { PCI_DEVICE(0x8086, 0x811b), 2515 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2516 /* Oaktrail */ 2517 { PCI_DEVICE(0x8086, 0x080a), 2518 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2519 /* BayTrail */ 2520 { PCI_DEVICE(0x8086, 0x0f04), 2521 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2522 /* Braswell */ 2523 { PCI_DEVICE(0x8086, 0x2284), 2524 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2525 /* ICH6 */ 2526 { PCI_DEVICE(0x8086, 0x2668), 2527 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2528 /* ICH7 */ 2529 { PCI_DEVICE(0x8086, 0x27d8), 2530 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2531 /* ESB2 */ 2532 { PCI_DEVICE(0x8086, 0x269a), 2533 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2534 /* ICH8 */ 2535 { PCI_DEVICE(0x8086, 0x284b), 2536 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2537 /* ICH9 */ 2538 { PCI_DEVICE(0x8086, 0x293e), 2539 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2540 /* ICH9 */ 2541 { PCI_DEVICE(0x8086, 0x293f), 2542 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2543 /* ICH10 */ 2544 { PCI_DEVICE(0x8086, 0x3a3e), 2545 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2546 /* ICH10 */ 2547 { PCI_DEVICE(0x8086, 0x3a6e), 2548 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2549 /* Generic Intel */ 2550 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2551 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2552 .class_mask = 0xffffff, 2553 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2554 /* ATI SB 450/600/700/800/900 */ 2555 { PCI_DEVICE(0x1002, 0x437b), 2556 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2557 { PCI_DEVICE(0x1002, 0x4383), 2558 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2559 /* AMD Hudson */ 2560 { PCI_DEVICE(0x1022, 0x780d), 2561 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2562 /* AMD, X370 & co */ 2563 { PCI_DEVICE(0x1022, 0x1457), 2564 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2565 /* AMD, X570 & co */ 2566 { PCI_DEVICE(0x1022, 0x1487), 2567 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2568 /* AMD Stoney */ 2569 { PCI_DEVICE(0x1022, 0x157a), 2570 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2571 AZX_DCAPS_PM_RUNTIME }, 2572 /* AMD Raven */ 2573 { PCI_DEVICE(0x1022, 0x15e3), 2574 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2575 /* ATI HDMI */ 2576 { PCI_DEVICE(0x1002, 0x0002), 2577 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2578 AZX_DCAPS_PM_RUNTIME }, 2579 { PCI_DEVICE(0x1002, 0x1308), 2580 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2581 { PCI_DEVICE(0x1002, 0x157a), 2582 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2583 { PCI_DEVICE(0x1002, 0x15b3), 2584 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2585 { PCI_DEVICE(0x1002, 0x793b), 2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2587 { PCI_DEVICE(0x1002, 0x7919), 2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2589 { PCI_DEVICE(0x1002, 0x960f), 2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2591 { PCI_DEVICE(0x1002, 0x970f), 2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2593 { PCI_DEVICE(0x1002, 0x9840), 2594 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2595 { PCI_DEVICE(0x1002, 0xaa00), 2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2597 { PCI_DEVICE(0x1002, 0xaa08), 2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2599 { PCI_DEVICE(0x1002, 0xaa10), 2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2601 { PCI_DEVICE(0x1002, 0xaa18), 2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2603 { PCI_DEVICE(0x1002, 0xaa20), 2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2605 { PCI_DEVICE(0x1002, 0xaa28), 2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2607 { PCI_DEVICE(0x1002, 0xaa30), 2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2609 { PCI_DEVICE(0x1002, 0xaa38), 2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2611 { PCI_DEVICE(0x1002, 0xaa40), 2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2613 { PCI_DEVICE(0x1002, 0xaa48), 2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2615 { PCI_DEVICE(0x1002, 0xaa50), 2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2617 { PCI_DEVICE(0x1002, 0xaa58), 2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2619 { PCI_DEVICE(0x1002, 0xaa60), 2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2621 { PCI_DEVICE(0x1002, 0xaa68), 2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2623 { PCI_DEVICE(0x1002, 0xaa80), 2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2625 { PCI_DEVICE(0x1002, 0xaa88), 2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2627 { PCI_DEVICE(0x1002, 0xaa90), 2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2629 { PCI_DEVICE(0x1002, 0xaa98), 2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2631 { PCI_DEVICE(0x1002, 0x9902), 2632 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2633 { PCI_DEVICE(0x1002, 0xaaa0), 2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2635 { PCI_DEVICE(0x1002, 0xaaa8), 2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2637 { PCI_DEVICE(0x1002, 0xaab0), 2638 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2639 { PCI_DEVICE(0x1002, 0xaac0), 2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2641 AZX_DCAPS_PM_RUNTIME }, 2642 { PCI_DEVICE(0x1002, 0xaac8), 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2644 AZX_DCAPS_PM_RUNTIME }, 2645 { PCI_DEVICE(0x1002, 0xaad8), 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2647 AZX_DCAPS_PM_RUNTIME }, 2648 { PCI_DEVICE(0x1002, 0xaae0), 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2650 AZX_DCAPS_PM_RUNTIME }, 2651 { PCI_DEVICE(0x1002, 0xaae8), 2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2653 AZX_DCAPS_PM_RUNTIME }, 2654 { PCI_DEVICE(0x1002, 0xaaf0), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2656 AZX_DCAPS_PM_RUNTIME }, 2657 { PCI_DEVICE(0x1002, 0xaaf8), 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2659 AZX_DCAPS_PM_RUNTIME }, 2660 { PCI_DEVICE(0x1002, 0xab00), 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2662 AZX_DCAPS_PM_RUNTIME }, 2663 { PCI_DEVICE(0x1002, 0xab08), 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2665 AZX_DCAPS_PM_RUNTIME }, 2666 { PCI_DEVICE(0x1002, 0xab10), 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2668 AZX_DCAPS_PM_RUNTIME }, 2669 { PCI_DEVICE(0x1002, 0xab18), 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2671 AZX_DCAPS_PM_RUNTIME }, 2672 { PCI_DEVICE(0x1002, 0xab20), 2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2674 AZX_DCAPS_PM_RUNTIME }, 2675 { PCI_DEVICE(0x1002, 0xab28), 2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2677 AZX_DCAPS_PM_RUNTIME }, 2678 { PCI_DEVICE(0x1002, 0xab38), 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2680 AZX_DCAPS_PM_RUNTIME }, 2681 /* VIA VT8251/VT8237A */ 2682 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2683 /* VIA GFX VT7122/VX900 */ 2684 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2685 /* VIA GFX VT6122/VX11 */ 2686 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2687 /* SIS966 */ 2688 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2689 /* ULI M5461 */ 2690 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2691 /* NVIDIA MCP */ 2692 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2693 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2694 .class_mask = 0xffffff, 2695 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2696 /* Teradici */ 2697 { PCI_DEVICE(0x6549, 0x1200), 2698 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2699 { PCI_DEVICE(0x6549, 0x2200), 2700 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2701 /* Creative X-Fi (CA0110-IBG) */ 2702 /* CTHDA chips */ 2703 { PCI_DEVICE(0x1102, 0x0010), 2704 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2705 { PCI_DEVICE(0x1102, 0x0012), 2706 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2707 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2708 /* the following entry conflicts with snd-ctxfi driver, 2709 * as ctxfi driver mutates from HD-audio to native mode with 2710 * a special command sequence. 2711 */ 2712 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2713 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2714 .class_mask = 0xffffff, 2715 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2716 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2717 #else 2718 /* this entry seems still valid -- i.e. without emu20kx chip */ 2719 { PCI_DEVICE(0x1102, 0x0009), 2720 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2721 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2722 #endif 2723 /* CM8888 */ 2724 { PCI_DEVICE(0x13f6, 0x5011), 2725 .driver_data = AZX_DRIVER_CMEDIA | 2726 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2727 /* Vortex86MX */ 2728 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2729 /* VMware HDAudio */ 2730 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2731 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2732 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2734 .class_mask = 0xffffff, 2735 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2736 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2737 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2738 .class_mask = 0xffffff, 2739 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2740 /* Zhaoxin */ 2741 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2742 { 0, } 2743 }; 2744 MODULE_DEVICE_TABLE(pci, azx_ids); 2745 2746 /* pci_driver definition */ 2747 static struct pci_driver azx_driver = { 2748 .name = KBUILD_MODNAME, 2749 .id_table = azx_ids, 2750 .probe = azx_probe, 2751 .remove = azx_remove, 2752 .shutdown = azx_shutdown, 2753 .driver = { 2754 .pm = AZX_PM_OPS, 2755 }, 2756 }; 2757 2758 module_pci_driver(azx_driver); 2759