1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 40 #ifdef CONFIG_X86 41 /* for snoop control */ 42 #include <asm/pgtable.h> 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* Define VIA HD Audio Device ID*/ 90 #define VIA_HDAC_DEVICE_ID 0x3288 91 92 /* max number of SDs */ 93 /* ICH, ATI and VIA have 4 playback and 4 capture */ 94 #define ICH6_NUM_CAPTURE 4 95 #define ICH6_NUM_PLAYBACK 4 96 97 /* ULI has 6 playback and 5 capture */ 98 #define ULI_NUM_CAPTURE 5 99 #define ULI_NUM_PLAYBACK 6 100 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 102 #define ATIHDMI_NUM_CAPTURE 0 103 #define ATIHDMI_NUM_PLAYBACK 8 104 105 /* TERA has 4 playback and 3 capture */ 106 #define TERA_NUM_CAPTURE 3 107 #define TERA_NUM_PLAYBACK 4 108 109 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113 static char *model[SNDRV_CARDS]; 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117 static int probe_only[SNDRV_CARDS]; 118 static int jackpoll_ms[SNDRV_CARDS]; 119 static int single_cmd = -1; 120 static int enable_msi = -1; 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER 122 static char *patch[SNDRV_CARDS]; 123 #endif 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127 #endif 128 static bool dsp_driver = 1; 129 130 module_param_array(index, int, NULL, 0444); 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132 module_param_array(id, charp, NULL, 0444); 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134 module_param_array(enable, bool, NULL, 0444); 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136 module_param_array(model, charp, NULL, 0444); 137 MODULE_PARM_DESC(model, "Use the given board model."); 138 module_param_array(position_fix, int, NULL, 0444); 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141 module_param_array(bdl_pos_adj, int, NULL, 0644); 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143 module_param_array(probe_mask, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145 module_param_array(probe_only, int, NULL, 0444); 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147 module_param_array(jackpoll_ms, int, NULL, 0444); 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149 module_param(single_cmd, bint, 0444); 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152 module_param(enable_msi, bint, 0444); 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER 155 module_param_array(patch, charp, NULL, 0444); 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157 #endif 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP 159 module_param_array(beep_mode, bool, NULL, 0444); 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162 #endif 163 module_param(dsp_driver, bool, 0444); 164 MODULE_PARM_DESC(dsp_driver, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1)"); 166 167 #ifdef CONFIG_PM 168 static int param_set_xint(const char *val, const struct kernel_param *kp); 169 static const struct kernel_param_ops param_ops_xint = { 170 .set = param_set_xint, 171 .get = param_get_int, 172 }; 173 #define param_check_xint param_check_int 174 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 176 module_param(power_save, xint, 0644); 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 178 "(in second, 0 = disable)."); 179 180 static bool pm_blacklist = true; 181 module_param(pm_blacklist, bool, 0644); 182 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 183 184 /* reset the HD-audio controller in power save mode. 185 * this may give more power-saving, but will take longer time to 186 * wake up. 187 */ 188 static bool power_save_controller = 1; 189 module_param(power_save_controller, bool, 0644); 190 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 191 #else 192 #define power_save 0 193 #endif /* CONFIG_PM */ 194 195 static int align_buffer_size = -1; 196 module_param(align_buffer_size, bint, 0644); 197 MODULE_PARM_DESC(align_buffer_size, 198 "Force buffer and period sizes to be multiple of 128 bytes."); 199 200 #ifdef CONFIG_X86 201 static int hda_snoop = -1; 202 module_param_named(snoop, hda_snoop, bint, 0444); 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 204 #else 205 #define hda_snoop true 206 #endif 207 208 209 MODULE_LICENSE("GPL"); 210 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 211 "{Intel, ICH6M}," 212 "{Intel, ICH7}," 213 "{Intel, ESB2}," 214 "{Intel, ICH8}," 215 "{Intel, ICH9}," 216 "{Intel, ICH10}," 217 "{Intel, PCH}," 218 "{Intel, CPT}," 219 "{Intel, PPT}," 220 "{Intel, LPT}," 221 "{Intel, LPT_LP}," 222 "{Intel, WPT_LP}," 223 "{Intel, SPT}," 224 "{Intel, SPT_LP}," 225 "{Intel, HPT}," 226 "{Intel, PBG}," 227 "{Intel, SCH}," 228 "{ATI, SB450}," 229 "{ATI, SB600}," 230 "{ATI, RS600}," 231 "{ATI, RS690}," 232 "{ATI, RS780}," 233 "{ATI, R600}," 234 "{ATI, RV630}," 235 "{ATI, RV610}," 236 "{ATI, RV670}," 237 "{ATI, RV635}," 238 "{ATI, RV620}," 239 "{ATI, RV770}," 240 "{VIA, VT8251}," 241 "{VIA, VT8237A}," 242 "{SiS, SIS966}," 243 "{ULI, M5461}}"); 244 MODULE_DESCRIPTION("Intel HDA driver"); 245 246 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 247 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 248 #define SUPPORT_VGA_SWITCHEROO 249 #endif 250 #endif 251 252 253 /* 254 */ 255 256 /* driver types */ 257 enum { 258 AZX_DRIVER_ICH, 259 AZX_DRIVER_PCH, 260 AZX_DRIVER_SCH, 261 AZX_DRIVER_SKL, 262 AZX_DRIVER_HDMI, 263 AZX_DRIVER_ATI, 264 AZX_DRIVER_ATIHDMI, 265 AZX_DRIVER_ATIHDMI_NS, 266 AZX_DRIVER_VIA, 267 AZX_DRIVER_SIS, 268 AZX_DRIVER_ULI, 269 AZX_DRIVER_NVIDIA, 270 AZX_DRIVER_TERA, 271 AZX_DRIVER_CTX, 272 AZX_DRIVER_CTHDA, 273 AZX_DRIVER_CMEDIA, 274 AZX_DRIVER_ZHAOXIN, 275 AZX_DRIVER_GENERIC, 276 AZX_NUM_DRIVERS, /* keep this as last entry */ 277 }; 278 279 #define azx_get_snoop_type(chip) \ 280 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 281 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 282 283 /* quirks for old Intel chipsets */ 284 #define AZX_DCAPS_INTEL_ICH \ 285 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 286 287 /* quirks for Intel PCH */ 288 #define AZX_DCAPS_INTEL_PCH_BASE \ 289 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 290 AZX_DCAPS_SNOOP_TYPE(SCH)) 291 292 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 293 #define AZX_DCAPS_INTEL_PCH_NOPM \ 294 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 295 296 /* PCH for HSW/BDW; with runtime PM */ 297 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 298 #define AZX_DCAPS_INTEL_PCH \ 299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 300 301 /* HSW HDMI */ 302 #define AZX_DCAPS_INTEL_HASWELL \ 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 305 AZX_DCAPS_SNOOP_TYPE(SCH)) 306 307 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 308 #define AZX_DCAPS_INTEL_BROADWELL \ 309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 311 AZX_DCAPS_SNOOP_TYPE(SCH)) 312 313 #define AZX_DCAPS_INTEL_BAYTRAIL \ 314 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 315 316 #define AZX_DCAPS_INTEL_BRASWELL \ 317 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 318 AZX_DCAPS_I915_COMPONENT) 319 320 #define AZX_DCAPS_INTEL_SKYLAKE \ 321 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 322 AZX_DCAPS_SYNC_WRITE |\ 323 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 324 325 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 326 327 /* quirks for ATI SB / AMD Hudson */ 328 #define AZX_DCAPS_PRESET_ATI_SB \ 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 330 AZX_DCAPS_SNOOP_TYPE(ATI)) 331 332 /* quirks for ATI/AMD HDMI */ 333 #define AZX_DCAPS_PRESET_ATI_HDMI \ 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 335 AZX_DCAPS_NO_MSI64) 336 337 /* quirks for ATI HDMI with snoop off */ 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 340 341 /* quirks for AMD SB */ 342 #define AZX_DCAPS_PRESET_AMD_SB \ 343 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\ 344 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) 345 346 /* quirks for Nvidia */ 347 #define AZX_DCAPS_PRESET_NVIDIA \ 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 349 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 350 351 #define AZX_DCAPS_PRESET_CTHDA \ 352 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 353 AZX_DCAPS_NO_64BIT |\ 354 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 355 356 /* 357 * vga_switcheroo support 358 */ 359 #ifdef SUPPORT_VGA_SWITCHEROO 360 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 361 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 362 #else 363 #define use_vga_switcheroo(chip) 0 364 #define needs_eld_notify_link(chip) false 365 #endif 366 367 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 368 ((pci)->device == 0x0c0c) || \ 369 ((pci)->device == 0x0d0c) || \ 370 ((pci)->device == 0x160c)) 371 372 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 373 374 static char *driver_short_names[] = { 375 [AZX_DRIVER_ICH] = "HDA Intel", 376 [AZX_DRIVER_PCH] = "HDA Intel PCH", 377 [AZX_DRIVER_SCH] = "HDA Intel MID", 378 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 379 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 380 [AZX_DRIVER_ATI] = "HDA ATI SB", 381 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 382 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 383 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 384 [AZX_DRIVER_SIS] = "HDA SIS966", 385 [AZX_DRIVER_ULI] = "HDA ULI M5461", 386 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 387 [AZX_DRIVER_TERA] = "HDA Teradici", 388 [AZX_DRIVER_CTX] = "HDA Creative", 389 [AZX_DRIVER_CTHDA] = "HDA Creative", 390 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 391 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 392 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 393 }; 394 395 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 396 static void set_default_power_save(struct azx *chip); 397 398 /* 399 * initialize the PCI registers 400 */ 401 /* update bits in a PCI register byte */ 402 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 403 unsigned char mask, unsigned char val) 404 { 405 unsigned char data; 406 407 pci_read_config_byte(pci, reg, &data); 408 data &= ~mask; 409 data |= (val & mask); 410 pci_write_config_byte(pci, reg, data); 411 } 412 413 static void azx_init_pci(struct azx *chip) 414 { 415 int snoop_type = azx_get_snoop_type(chip); 416 417 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 418 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 419 * Ensuring these bits are 0 clears playback static on some HD Audio 420 * codecs. 421 * The PCI register TCSEL is defined in the Intel manuals. 422 */ 423 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 424 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 425 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 426 } 427 428 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 429 * we need to enable snoop. 430 */ 431 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 432 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 433 azx_snoop(chip)); 434 update_pci_byte(chip->pci, 435 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 436 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 437 } 438 439 /* For NVIDIA HDA, enable snoop */ 440 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 441 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 442 azx_snoop(chip)); 443 update_pci_byte(chip->pci, 444 NVIDIA_HDA_TRANSREG_ADDR, 445 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 446 update_pci_byte(chip->pci, 447 NVIDIA_HDA_ISTRM_COH, 448 0x01, NVIDIA_HDA_ENABLE_COHBIT); 449 update_pci_byte(chip->pci, 450 NVIDIA_HDA_OSTRM_COH, 451 0x01, NVIDIA_HDA_ENABLE_COHBIT); 452 } 453 454 /* Enable SCH/PCH snoop if needed */ 455 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 456 unsigned short snoop; 457 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 458 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 459 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 460 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 461 if (!azx_snoop(chip)) 462 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 463 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 464 pci_read_config_word(chip->pci, 465 INTEL_SCH_HDA_DEVC, &snoop); 466 } 467 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 468 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 469 "Disabled" : "Enabled"); 470 } 471 } 472 473 /* 474 * In BXT-P A0, HD-Audio DMA requests is later than expected, 475 * and makes an audio stream sensitive to system latencies when 476 * 24/32 bits are playing. 477 * Adjusting threshold of DMA fifo to force the DMA request 478 * sooner to improve latency tolerance at the expense of power. 479 */ 480 static void bxt_reduce_dma_latency(struct azx *chip) 481 { 482 u32 val; 483 484 val = azx_readl(chip, VS_EM4L); 485 val &= (0x3 << 20); 486 azx_writel(chip, VS_EM4L, val); 487 } 488 489 /* 490 * ML_LCAP bits: 491 * bit 0: 6 MHz Supported 492 * bit 1: 12 MHz Supported 493 * bit 2: 24 MHz Supported 494 * bit 3: 48 MHz Supported 495 * bit 4: 96 MHz Supported 496 * bit 5: 192 MHz Supported 497 */ 498 static int intel_get_lctl_scf(struct azx *chip) 499 { 500 struct hdac_bus *bus = azx_bus(chip); 501 static int preferred_bits[] = { 2, 3, 1, 4, 5 }; 502 u32 val, t; 503 int i; 504 505 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 506 507 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 508 t = preferred_bits[i]; 509 if (val & (1 << t)) 510 return t; 511 } 512 513 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 514 return 0; 515 } 516 517 static int intel_ml_lctl_set_power(struct azx *chip, int state) 518 { 519 struct hdac_bus *bus = azx_bus(chip); 520 u32 val; 521 int timeout; 522 523 /* 524 * the codecs are sharing the first link setting by default 525 * If other links are enabled for stream, they need similar fix 526 */ 527 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 528 val &= ~AZX_MLCTL_SPA; 529 val |= state << AZX_MLCTL_SPA_SHIFT; 530 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 531 /* wait for CPA */ 532 timeout = 50; 533 while (timeout) { 534 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 535 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 536 return 0; 537 timeout--; 538 udelay(10); 539 } 540 541 return -1; 542 } 543 544 static void intel_init_lctl(struct azx *chip) 545 { 546 struct hdac_bus *bus = azx_bus(chip); 547 u32 val; 548 int ret; 549 550 /* 0. check lctl register value is correct or not */ 551 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 552 /* if SCF is already set, let's use it */ 553 if ((val & ML_LCTL_SCF_MASK) != 0) 554 return; 555 556 /* 557 * Before operating on SPA, CPA must match SPA. 558 * Any deviation may result in undefined behavior. 559 */ 560 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 561 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 562 return; 563 564 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 565 ret = intel_ml_lctl_set_power(chip, 0); 566 udelay(100); 567 if (ret) 568 goto set_spa; 569 570 /* 2. update SCF to select a properly audio clock*/ 571 val &= ~ML_LCTL_SCF_MASK; 572 val |= intel_get_lctl_scf(chip); 573 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 574 575 set_spa: 576 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 577 intel_ml_lctl_set_power(chip, 1); 578 udelay(100); 579 } 580 581 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 582 { 583 struct hdac_bus *bus = azx_bus(chip); 584 struct pci_dev *pci = chip->pci; 585 u32 val; 586 587 snd_hdac_set_codec_wakeup(bus, true); 588 if (chip->driver_type == AZX_DRIVER_SKL) { 589 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 590 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 591 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 592 } 593 azx_init_chip(chip, full_reset); 594 if (chip->driver_type == AZX_DRIVER_SKL) { 595 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 596 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 597 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 598 } 599 600 snd_hdac_set_codec_wakeup(bus, false); 601 602 /* reduce dma latency to avoid noise */ 603 if (IS_BXT(pci)) 604 bxt_reduce_dma_latency(chip); 605 606 if (bus->mlcap != NULL) 607 intel_init_lctl(chip); 608 } 609 610 /* calculate runtime delay from LPIB */ 611 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 612 unsigned int pos) 613 { 614 struct snd_pcm_substream *substream = azx_dev->core.substream; 615 int stream = substream->stream; 616 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 617 int delay; 618 619 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 620 delay = pos - lpib_pos; 621 else 622 delay = lpib_pos - pos; 623 if (delay < 0) { 624 if (delay >= azx_dev->core.delay_negative_threshold) 625 delay = 0; 626 else 627 delay += azx_dev->core.bufsize; 628 } 629 630 if (delay >= azx_dev->core.period_bytes) { 631 dev_info(chip->card->dev, 632 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 633 delay, azx_dev->core.period_bytes); 634 delay = 0; 635 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 636 chip->get_delay[stream] = NULL; 637 } 638 639 return bytes_to_frames(substream->runtime, delay); 640 } 641 642 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 643 644 /* called from IRQ */ 645 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 646 { 647 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 648 int ok; 649 650 ok = azx_position_ok(chip, azx_dev); 651 if (ok == 1) { 652 azx_dev->irq_pending = 0; 653 return ok; 654 } else if (ok == 0) { 655 /* bogus IRQ, process it later */ 656 azx_dev->irq_pending = 1; 657 schedule_work(&hda->irq_pending_work); 658 } 659 return 0; 660 } 661 662 #define display_power(chip, enable) \ 663 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 664 665 /* 666 * Check whether the current DMA position is acceptable for updating 667 * periods. Returns non-zero if it's OK. 668 * 669 * Many HD-audio controllers appear pretty inaccurate about 670 * the update-IRQ timing. The IRQ is issued before actually the 671 * data is processed. So, we need to process it afterwords in a 672 * workqueue. 673 */ 674 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 675 { 676 struct snd_pcm_substream *substream = azx_dev->core.substream; 677 int stream = substream->stream; 678 u32 wallclk; 679 unsigned int pos; 680 681 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 682 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 683 return -1; /* bogus (too early) interrupt */ 684 685 if (chip->get_position[stream]) 686 pos = chip->get_position[stream](chip, azx_dev); 687 else { /* use the position buffer as default */ 688 pos = azx_get_pos_posbuf(chip, azx_dev); 689 if (!pos || pos == (u32)-1) { 690 dev_info(chip->card->dev, 691 "Invalid position buffer, using LPIB read method instead.\n"); 692 chip->get_position[stream] = azx_get_pos_lpib; 693 if (chip->get_position[0] == azx_get_pos_lpib && 694 chip->get_position[1] == azx_get_pos_lpib) 695 azx_bus(chip)->use_posbuf = false; 696 pos = azx_get_pos_lpib(chip, azx_dev); 697 chip->get_delay[stream] = NULL; 698 } else { 699 chip->get_position[stream] = azx_get_pos_posbuf; 700 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 701 chip->get_delay[stream] = azx_get_delay_from_lpib; 702 } 703 } 704 705 if (pos >= azx_dev->core.bufsize) 706 pos = 0; 707 708 if (WARN_ONCE(!azx_dev->core.period_bytes, 709 "hda-intel: zero azx_dev->period_bytes")) 710 return -1; /* this shouldn't happen! */ 711 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 712 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 713 /* NG - it's below the first next period boundary */ 714 return chip->bdl_pos_adj ? 0 : -1; 715 azx_dev->core.start_wallclk += wallclk; 716 return 1; /* OK, it's fine */ 717 } 718 719 /* 720 * The work for pending PCM period updates. 721 */ 722 static void azx_irq_pending_work(struct work_struct *work) 723 { 724 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 725 struct azx *chip = &hda->chip; 726 struct hdac_bus *bus = azx_bus(chip); 727 struct hdac_stream *s; 728 int pending, ok; 729 730 if (!hda->irq_pending_warned) { 731 dev_info(chip->card->dev, 732 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 733 chip->card->number); 734 hda->irq_pending_warned = 1; 735 } 736 737 for (;;) { 738 pending = 0; 739 spin_lock_irq(&bus->reg_lock); 740 list_for_each_entry(s, &bus->stream_list, list) { 741 struct azx_dev *azx_dev = stream_to_azx_dev(s); 742 if (!azx_dev->irq_pending || 743 !s->substream || 744 !s->running) 745 continue; 746 ok = azx_position_ok(chip, azx_dev); 747 if (ok > 0) { 748 azx_dev->irq_pending = 0; 749 spin_unlock(&bus->reg_lock); 750 snd_pcm_period_elapsed(s->substream); 751 spin_lock(&bus->reg_lock); 752 } else if (ok < 0) { 753 pending = 0; /* too early */ 754 } else 755 pending++; 756 } 757 spin_unlock_irq(&bus->reg_lock); 758 if (!pending) 759 return; 760 msleep(1); 761 } 762 } 763 764 /* clear irq_pending flags and assure no on-going workq */ 765 static void azx_clear_irq_pending(struct azx *chip) 766 { 767 struct hdac_bus *bus = azx_bus(chip); 768 struct hdac_stream *s; 769 770 spin_lock_irq(&bus->reg_lock); 771 list_for_each_entry(s, &bus->stream_list, list) { 772 struct azx_dev *azx_dev = stream_to_azx_dev(s); 773 azx_dev->irq_pending = 0; 774 } 775 spin_unlock_irq(&bus->reg_lock); 776 } 777 778 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 779 { 780 struct hdac_bus *bus = azx_bus(chip); 781 782 if (request_irq(chip->pci->irq, azx_interrupt, 783 chip->msi ? 0 : IRQF_SHARED, 784 chip->card->irq_descr, chip)) { 785 dev_err(chip->card->dev, 786 "unable to grab IRQ %d, disabling device\n", 787 chip->pci->irq); 788 if (do_disconnect) 789 snd_card_disconnect(chip->card); 790 return -1; 791 } 792 bus->irq = chip->pci->irq; 793 pci_intx(chip->pci, !chip->msi); 794 return 0; 795 } 796 797 /* get the current DMA position with correction on VIA chips */ 798 static unsigned int azx_via_get_position(struct azx *chip, 799 struct azx_dev *azx_dev) 800 { 801 unsigned int link_pos, mini_pos, bound_pos; 802 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 803 unsigned int fifo_size; 804 805 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 806 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 807 /* Playback, no problem using link position */ 808 return link_pos; 809 } 810 811 /* Capture */ 812 /* For new chipset, 813 * use mod to get the DMA position just like old chipset 814 */ 815 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 816 mod_dma_pos %= azx_dev->core.period_bytes; 817 818 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 819 820 if (azx_dev->insufficient) { 821 /* Link position never gather than FIFO size */ 822 if (link_pos <= fifo_size) 823 return 0; 824 825 azx_dev->insufficient = 0; 826 } 827 828 if (link_pos <= fifo_size) 829 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 830 else 831 mini_pos = link_pos - fifo_size; 832 833 /* Find nearest previous boudary */ 834 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 835 mod_link_pos = link_pos % azx_dev->core.period_bytes; 836 if (mod_link_pos >= fifo_size) 837 bound_pos = link_pos - mod_link_pos; 838 else if (mod_dma_pos >= mod_mini_pos) 839 bound_pos = mini_pos - mod_mini_pos; 840 else { 841 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 842 if (bound_pos >= azx_dev->core.bufsize) 843 bound_pos = 0; 844 } 845 846 /* Calculate real DMA position we want */ 847 return bound_pos + mod_dma_pos; 848 } 849 850 #define AMD_FIFO_SIZE 32 851 852 /* get the current DMA position with FIFO size correction */ 853 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 854 { 855 struct snd_pcm_substream *substream = azx_dev->core.substream; 856 struct snd_pcm_runtime *runtime = substream->runtime; 857 unsigned int pos, delay; 858 859 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 860 if (!runtime) 861 return pos; 862 863 runtime->delay = AMD_FIFO_SIZE; 864 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 865 if (azx_dev->insufficient) { 866 if (pos < delay) { 867 delay = pos; 868 runtime->delay = bytes_to_frames(runtime, pos); 869 } else { 870 azx_dev->insufficient = 0; 871 } 872 } 873 874 /* correct the DMA position for capture stream */ 875 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 876 if (pos < delay) 877 pos += azx_dev->core.bufsize; 878 pos -= delay; 879 } 880 881 return pos; 882 } 883 884 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 885 unsigned int pos) 886 { 887 struct snd_pcm_substream *substream = azx_dev->core.substream; 888 889 /* just read back the calculated value in the above */ 890 return substream->runtime->delay; 891 } 892 893 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 894 struct azx_dev *azx_dev) 895 { 896 return _snd_hdac_chip_readl(azx_bus(chip), 897 AZX_REG_VS_SDXDPIB_XBASE + 898 (AZX_REG_VS_SDXDPIB_XINTERVAL * 899 azx_dev->core.index)); 900 } 901 902 /* get the current DMA position with correction on SKL+ chips */ 903 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 904 { 905 /* DPIB register gives a more accurate position for playback */ 906 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 907 return azx_skl_get_dpib_pos(chip, azx_dev); 908 909 /* For capture, we need to read posbuf, but it requires a delay 910 * for the possible boundary overlap; the read of DPIB fetches the 911 * actual posbuf 912 */ 913 udelay(20); 914 azx_skl_get_dpib_pos(chip, azx_dev); 915 return azx_get_pos_posbuf(chip, azx_dev); 916 } 917 918 #ifdef CONFIG_PM 919 static DEFINE_MUTEX(card_list_lock); 920 static LIST_HEAD(card_list); 921 922 static void azx_add_card_list(struct azx *chip) 923 { 924 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 925 mutex_lock(&card_list_lock); 926 list_add(&hda->list, &card_list); 927 mutex_unlock(&card_list_lock); 928 } 929 930 static void azx_del_card_list(struct azx *chip) 931 { 932 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 933 mutex_lock(&card_list_lock); 934 list_del_init(&hda->list); 935 mutex_unlock(&card_list_lock); 936 } 937 938 /* trigger power-save check at writing parameter */ 939 static int param_set_xint(const char *val, const struct kernel_param *kp) 940 { 941 struct hda_intel *hda; 942 struct azx *chip; 943 int prev = power_save; 944 int ret = param_set_int(val, kp); 945 946 if (ret || prev == power_save) 947 return ret; 948 949 mutex_lock(&card_list_lock); 950 list_for_each_entry(hda, &card_list, list) { 951 chip = &hda->chip; 952 if (!hda->probe_continued || chip->disabled) 953 continue; 954 snd_hda_set_power_save(&chip->bus, power_save * 1000); 955 } 956 mutex_unlock(&card_list_lock); 957 return 0; 958 } 959 960 /* 961 * power management 962 */ 963 static bool azx_is_pm_ready(struct snd_card *card) 964 { 965 struct azx *chip; 966 struct hda_intel *hda; 967 968 if (!card) 969 return false; 970 chip = card->private_data; 971 hda = container_of(chip, struct hda_intel, chip); 972 if (chip->disabled || hda->init_failed || !chip->running) 973 return false; 974 return true; 975 } 976 977 static void __azx_runtime_suspend(struct azx *chip) 978 { 979 azx_stop_chip(chip); 980 azx_enter_link_reset(chip); 981 azx_clear_irq_pending(chip); 982 display_power(chip, false); 983 } 984 985 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 986 { 987 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 988 struct hdac_bus *bus = azx_bus(chip); 989 struct hda_codec *codec; 990 int status; 991 992 display_power(chip, true); 993 if (hda->need_i915_power) 994 snd_hdac_i915_set_bclk(bus); 995 996 /* Read STATESTS before controller reset */ 997 status = azx_readw(chip, STATESTS); 998 999 azx_init_pci(chip); 1000 hda_intel_init_chip(chip, true); 1001 1002 if (status && from_rt) { 1003 list_for_each_codec(codec, &chip->bus) 1004 if (status & (1 << codec->addr)) 1005 schedule_delayed_work(&codec->jackpoll_work, 1006 codec->jackpoll_interval); 1007 } 1008 1009 /* power down again for link-controlled chips */ 1010 if (!hda->need_i915_power) 1011 display_power(chip, false); 1012 } 1013 1014 #ifdef CONFIG_PM_SLEEP 1015 static int azx_suspend(struct device *dev) 1016 { 1017 struct snd_card *card = dev_get_drvdata(dev); 1018 struct azx *chip; 1019 struct hdac_bus *bus; 1020 1021 if (!azx_is_pm_ready(card)) 1022 return 0; 1023 1024 chip = card->private_data; 1025 bus = azx_bus(chip); 1026 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1027 __azx_runtime_suspend(chip); 1028 if (bus->irq >= 0) { 1029 free_irq(bus->irq, chip); 1030 bus->irq = -1; 1031 } 1032 1033 if (chip->msi) 1034 pci_disable_msi(chip->pci); 1035 1036 trace_azx_suspend(chip); 1037 return 0; 1038 } 1039 1040 static int azx_resume(struct device *dev) 1041 { 1042 struct snd_card *card = dev_get_drvdata(dev); 1043 struct azx *chip; 1044 1045 if (!azx_is_pm_ready(card)) 1046 return 0; 1047 1048 chip = card->private_data; 1049 if (chip->msi) 1050 if (pci_enable_msi(chip->pci) < 0) 1051 chip->msi = 0; 1052 if (azx_acquire_irq(chip, 1) < 0) 1053 return -EIO; 1054 __azx_runtime_resume(chip, false); 1055 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1056 1057 trace_azx_resume(chip); 1058 return 0; 1059 } 1060 1061 /* put codec down to D3 at hibernation for Intel SKL+; 1062 * otherwise BIOS may still access the codec and screw up the driver 1063 */ 1064 static int azx_freeze_noirq(struct device *dev) 1065 { 1066 struct snd_card *card = dev_get_drvdata(dev); 1067 struct azx *chip = card->private_data; 1068 struct pci_dev *pci = to_pci_dev(dev); 1069 1070 if (chip->driver_type == AZX_DRIVER_SKL) 1071 pci_set_power_state(pci, PCI_D3hot); 1072 1073 return 0; 1074 } 1075 1076 static int azx_thaw_noirq(struct device *dev) 1077 { 1078 struct snd_card *card = dev_get_drvdata(dev); 1079 struct azx *chip = card->private_data; 1080 struct pci_dev *pci = to_pci_dev(dev); 1081 1082 if (chip->driver_type == AZX_DRIVER_SKL) 1083 pci_set_power_state(pci, PCI_D0); 1084 1085 return 0; 1086 } 1087 #endif /* CONFIG_PM_SLEEP */ 1088 1089 static int azx_runtime_suspend(struct device *dev) 1090 { 1091 struct snd_card *card = dev_get_drvdata(dev); 1092 struct azx *chip; 1093 1094 if (!azx_is_pm_ready(card)) 1095 return 0; 1096 chip = card->private_data; 1097 if (!azx_has_pm_runtime(chip)) 1098 return 0; 1099 1100 /* enable controller wake up event */ 1101 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1102 STATESTS_INT_MASK); 1103 1104 __azx_runtime_suspend(chip); 1105 trace_azx_runtime_suspend(chip); 1106 return 0; 1107 } 1108 1109 static int azx_runtime_resume(struct device *dev) 1110 { 1111 struct snd_card *card = dev_get_drvdata(dev); 1112 struct azx *chip; 1113 1114 if (!azx_is_pm_ready(card)) 1115 return 0; 1116 chip = card->private_data; 1117 if (!azx_has_pm_runtime(chip)) 1118 return 0; 1119 __azx_runtime_resume(chip, true); 1120 1121 /* disable controller Wake Up event*/ 1122 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1123 ~STATESTS_INT_MASK); 1124 1125 trace_azx_runtime_resume(chip); 1126 return 0; 1127 } 1128 1129 static int azx_runtime_idle(struct device *dev) 1130 { 1131 struct snd_card *card = dev_get_drvdata(dev); 1132 struct azx *chip; 1133 struct hda_intel *hda; 1134 1135 if (!card) 1136 return 0; 1137 1138 chip = card->private_data; 1139 hda = container_of(chip, struct hda_intel, chip); 1140 if (chip->disabled || hda->init_failed) 1141 return 0; 1142 1143 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1144 azx_bus(chip)->codec_powered || !chip->running) 1145 return -EBUSY; 1146 1147 /* ELD notification gets broken when HD-audio bus is off */ 1148 if (needs_eld_notify_link(chip)) 1149 return -EBUSY; 1150 1151 return 0; 1152 } 1153 1154 static const struct dev_pm_ops azx_pm = { 1155 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1156 #ifdef CONFIG_PM_SLEEP 1157 .freeze_noirq = azx_freeze_noirq, 1158 .thaw_noirq = azx_thaw_noirq, 1159 #endif 1160 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1161 }; 1162 1163 #define AZX_PM_OPS &azx_pm 1164 #else 1165 #define azx_add_card_list(chip) /* NOP */ 1166 #define azx_del_card_list(chip) /* NOP */ 1167 #define AZX_PM_OPS NULL 1168 #endif /* CONFIG_PM */ 1169 1170 1171 static int azx_probe_continue(struct azx *chip); 1172 1173 #ifdef SUPPORT_VGA_SWITCHEROO 1174 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1175 1176 static void azx_vs_set_state(struct pci_dev *pci, 1177 enum vga_switcheroo_state state) 1178 { 1179 struct snd_card *card = pci_get_drvdata(pci); 1180 struct azx *chip = card->private_data; 1181 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1182 struct hda_codec *codec; 1183 bool disabled; 1184 1185 wait_for_completion(&hda->probe_wait); 1186 if (hda->init_failed) 1187 return; 1188 1189 disabled = (state == VGA_SWITCHEROO_OFF); 1190 if (chip->disabled == disabled) 1191 return; 1192 1193 if (!hda->probe_continued) { 1194 chip->disabled = disabled; 1195 if (!disabled) { 1196 dev_info(chip->card->dev, 1197 "Start delayed initialization\n"); 1198 if (azx_probe_continue(chip) < 0) { 1199 dev_err(chip->card->dev, "initialization error\n"); 1200 hda->init_failed = true; 1201 } 1202 } 1203 } else { 1204 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1205 disabled ? "Disabling" : "Enabling"); 1206 if (disabled) { 1207 list_for_each_codec(codec, &chip->bus) { 1208 pm_runtime_suspend(hda_codec_dev(codec)); 1209 pm_runtime_disable(hda_codec_dev(codec)); 1210 } 1211 pm_runtime_suspend(card->dev); 1212 pm_runtime_disable(card->dev); 1213 /* when we get suspended by vga_switcheroo we end up in D3cold, 1214 * however we have no ACPI handle, so pci/acpi can't put us there, 1215 * put ourselves there */ 1216 pci->current_state = PCI_D3cold; 1217 chip->disabled = true; 1218 if (snd_hda_lock_devices(&chip->bus)) 1219 dev_warn(chip->card->dev, 1220 "Cannot lock devices!\n"); 1221 } else { 1222 snd_hda_unlock_devices(&chip->bus); 1223 chip->disabled = false; 1224 pm_runtime_enable(card->dev); 1225 list_for_each_codec(codec, &chip->bus) { 1226 pm_runtime_enable(hda_codec_dev(codec)); 1227 pm_runtime_resume(hda_codec_dev(codec)); 1228 } 1229 } 1230 } 1231 } 1232 1233 static bool azx_vs_can_switch(struct pci_dev *pci) 1234 { 1235 struct snd_card *card = pci_get_drvdata(pci); 1236 struct azx *chip = card->private_data; 1237 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1238 1239 wait_for_completion(&hda->probe_wait); 1240 if (hda->init_failed) 1241 return false; 1242 if (chip->disabled || !hda->probe_continued) 1243 return true; 1244 if (snd_hda_lock_devices(&chip->bus)) 1245 return false; 1246 snd_hda_unlock_devices(&chip->bus); 1247 return true; 1248 } 1249 1250 /* 1251 * The discrete GPU cannot power down unless the HDA controller runtime 1252 * suspends, so activate runtime PM on codecs even if power_save == 0. 1253 */ 1254 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1255 { 1256 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1257 struct hda_codec *codec; 1258 1259 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1260 list_for_each_codec(codec, &chip->bus) 1261 codec->auto_runtime_pm = 1; 1262 /* reset the power save setup */ 1263 if (chip->running) 1264 set_default_power_save(chip); 1265 } 1266 } 1267 1268 static void azx_vs_gpu_bound(struct pci_dev *pci, 1269 enum vga_switcheroo_client_id client_id) 1270 { 1271 struct snd_card *card = pci_get_drvdata(pci); 1272 struct azx *chip = card->private_data; 1273 1274 if (client_id == VGA_SWITCHEROO_DIS) 1275 chip->bus.keep_power = 0; 1276 setup_vga_switcheroo_runtime_pm(chip); 1277 } 1278 1279 static void init_vga_switcheroo(struct azx *chip) 1280 { 1281 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1282 struct pci_dev *p = get_bound_vga(chip->pci); 1283 struct pci_dev *parent; 1284 if (p) { 1285 dev_info(chip->card->dev, 1286 "Handle vga_switcheroo audio client\n"); 1287 hda->use_vga_switcheroo = 1; 1288 1289 /* cleared in either gpu_bound op or codec probe, or when its 1290 * upstream port has _PR3 (i.e. dGPU). 1291 */ 1292 parent = pci_upstream_bridge(p); 1293 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1294 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1295 pci_dev_put(p); 1296 } 1297 } 1298 1299 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1300 .set_gpu_state = azx_vs_set_state, 1301 .can_switch = azx_vs_can_switch, 1302 .gpu_bound = azx_vs_gpu_bound, 1303 }; 1304 1305 static int register_vga_switcheroo(struct azx *chip) 1306 { 1307 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1308 struct pci_dev *p; 1309 int err; 1310 1311 if (!hda->use_vga_switcheroo) 1312 return 0; 1313 1314 p = get_bound_vga(chip->pci); 1315 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1316 pci_dev_put(p); 1317 1318 if (err < 0) 1319 return err; 1320 hda->vga_switcheroo_registered = 1; 1321 1322 return 0; 1323 } 1324 #else 1325 #define init_vga_switcheroo(chip) /* NOP */ 1326 #define register_vga_switcheroo(chip) 0 1327 #define check_hdmi_disabled(pci) false 1328 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1329 #endif /* SUPPORT_VGA_SWITCHER */ 1330 1331 /* 1332 * destructor 1333 */ 1334 static int azx_free(struct azx *chip) 1335 { 1336 struct pci_dev *pci = chip->pci; 1337 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1338 struct hdac_bus *bus = azx_bus(chip); 1339 1340 if (azx_has_pm_runtime(chip) && chip->running) 1341 pm_runtime_get_noresume(&pci->dev); 1342 chip->running = 0; 1343 1344 azx_del_card_list(chip); 1345 1346 hda->init_failed = 1; /* to be sure */ 1347 complete_all(&hda->probe_wait); 1348 1349 if (use_vga_switcheroo(hda)) { 1350 if (chip->disabled && hda->probe_continued) 1351 snd_hda_unlock_devices(&chip->bus); 1352 if (hda->vga_switcheroo_registered) 1353 vga_switcheroo_unregister_client(chip->pci); 1354 } 1355 1356 if (bus->chip_init) { 1357 azx_clear_irq_pending(chip); 1358 azx_stop_all_streams(chip); 1359 azx_stop_chip(chip); 1360 } 1361 1362 if (bus->irq >= 0) 1363 free_irq(bus->irq, (void*)chip); 1364 if (chip->msi) 1365 pci_disable_msi(chip->pci); 1366 iounmap(bus->remap_addr); 1367 1368 azx_free_stream_pages(chip); 1369 azx_free_streams(chip); 1370 snd_hdac_bus_exit(bus); 1371 1372 if (chip->region_requested) 1373 pci_release_regions(chip->pci); 1374 1375 pci_disable_device(chip->pci); 1376 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1377 release_firmware(chip->fw); 1378 #endif 1379 display_power(chip, false); 1380 1381 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1382 snd_hdac_i915_exit(bus); 1383 kfree(hda); 1384 1385 return 0; 1386 } 1387 1388 static int azx_dev_disconnect(struct snd_device *device) 1389 { 1390 struct azx *chip = device->device_data; 1391 struct hdac_bus *bus = azx_bus(chip); 1392 1393 chip->bus.shutdown = 1; 1394 cancel_work_sync(&bus->unsol_work); 1395 1396 return 0; 1397 } 1398 1399 static int azx_dev_free(struct snd_device *device) 1400 { 1401 return azx_free(device->device_data); 1402 } 1403 1404 #ifdef SUPPORT_VGA_SWITCHEROO 1405 #ifdef CONFIG_ACPI 1406 /* ATPX is in the integrated GPU's namespace */ 1407 static bool atpx_present(void) 1408 { 1409 struct pci_dev *pdev = NULL; 1410 acpi_handle dhandle, atpx_handle; 1411 acpi_status status; 1412 1413 while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) { 1414 dhandle = ACPI_HANDLE(&pdev->dev); 1415 if (dhandle) { 1416 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1417 if (!ACPI_FAILURE(status)) { 1418 pci_dev_put(pdev); 1419 return true; 1420 } 1421 } 1422 } 1423 return false; 1424 } 1425 #else 1426 static bool atpx_present(void) 1427 { 1428 return false; 1429 } 1430 #endif 1431 1432 /* 1433 * Check of disabled HDMI controller by vga_switcheroo 1434 */ 1435 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1436 { 1437 struct pci_dev *p; 1438 1439 /* check only discrete GPU */ 1440 switch (pci->vendor) { 1441 case PCI_VENDOR_ID_ATI: 1442 case PCI_VENDOR_ID_AMD: 1443 if (pci->devfn == 1) { 1444 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1445 pci->bus->number, 0); 1446 if (p) { 1447 /* ATPX is in the integrated GPU's ACPI namespace 1448 * rather than the dGPU's namespace. However, 1449 * the dGPU is the one who is involved in 1450 * vgaswitcheroo. 1451 */ 1452 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1453 atpx_present()) 1454 return p; 1455 pci_dev_put(p); 1456 } 1457 } 1458 break; 1459 case PCI_VENDOR_ID_NVIDIA: 1460 if (pci->devfn == 1) { 1461 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1462 pci->bus->number, 0); 1463 if (p) { 1464 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1465 return p; 1466 pci_dev_put(p); 1467 } 1468 } 1469 break; 1470 } 1471 return NULL; 1472 } 1473 1474 static bool check_hdmi_disabled(struct pci_dev *pci) 1475 { 1476 bool vga_inactive = false; 1477 struct pci_dev *p = get_bound_vga(pci); 1478 1479 if (p) { 1480 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1481 vga_inactive = true; 1482 pci_dev_put(p); 1483 } 1484 return vga_inactive; 1485 } 1486 #endif /* SUPPORT_VGA_SWITCHEROO */ 1487 1488 /* 1489 * white/black-listing for position_fix 1490 */ 1491 static struct snd_pci_quirk position_fix_list[] = { 1492 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1493 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1494 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1495 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1496 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1497 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1498 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1499 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1500 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1501 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1502 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1503 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1504 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1505 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1506 {} 1507 }; 1508 1509 static int check_position_fix(struct azx *chip, int fix) 1510 { 1511 const struct snd_pci_quirk *q; 1512 1513 switch (fix) { 1514 case POS_FIX_AUTO: 1515 case POS_FIX_LPIB: 1516 case POS_FIX_POSBUF: 1517 case POS_FIX_VIACOMBO: 1518 case POS_FIX_COMBO: 1519 case POS_FIX_SKL: 1520 case POS_FIX_FIFO: 1521 return fix; 1522 } 1523 1524 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1525 if (q) { 1526 dev_info(chip->card->dev, 1527 "position_fix set to %d for device %04x:%04x\n", 1528 q->value, q->subvendor, q->subdevice); 1529 return q->value; 1530 } 1531 1532 /* Check VIA/ATI HD Audio Controller exist */ 1533 if (chip->driver_type == AZX_DRIVER_VIA) { 1534 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1535 return POS_FIX_VIACOMBO; 1536 } 1537 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1538 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1539 return POS_FIX_FIFO; 1540 } 1541 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1542 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1543 return POS_FIX_LPIB; 1544 } 1545 if (chip->driver_type == AZX_DRIVER_SKL) { 1546 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1547 return POS_FIX_SKL; 1548 } 1549 return POS_FIX_AUTO; 1550 } 1551 1552 static void assign_position_fix(struct azx *chip, int fix) 1553 { 1554 static azx_get_pos_callback_t callbacks[] = { 1555 [POS_FIX_AUTO] = NULL, 1556 [POS_FIX_LPIB] = azx_get_pos_lpib, 1557 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1558 [POS_FIX_VIACOMBO] = azx_via_get_position, 1559 [POS_FIX_COMBO] = azx_get_pos_lpib, 1560 [POS_FIX_SKL] = azx_get_pos_skl, 1561 [POS_FIX_FIFO] = azx_get_pos_fifo, 1562 }; 1563 1564 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1565 1566 /* combo mode uses LPIB only for playback */ 1567 if (fix == POS_FIX_COMBO) 1568 chip->get_position[1] = NULL; 1569 1570 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1571 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1572 chip->get_delay[0] = chip->get_delay[1] = 1573 azx_get_delay_from_lpib; 1574 } 1575 1576 if (fix == POS_FIX_FIFO) 1577 chip->get_delay[0] = chip->get_delay[1] = 1578 azx_get_delay_from_fifo; 1579 } 1580 1581 /* 1582 * black-lists for probe_mask 1583 */ 1584 static struct snd_pci_quirk probe_mask_list[] = { 1585 /* Thinkpad often breaks the controller communication when accessing 1586 * to the non-working (or non-existing) modem codec slot. 1587 */ 1588 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1589 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1590 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1591 /* broken BIOS */ 1592 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1593 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1594 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1595 /* forced codec slots */ 1596 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1597 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1598 /* WinFast VP200 H (Teradici) user reported broken communication */ 1599 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1600 {} 1601 }; 1602 1603 #define AZX_FORCE_CODEC_MASK 0x100 1604 1605 static void check_probe_mask(struct azx *chip, int dev) 1606 { 1607 const struct snd_pci_quirk *q; 1608 1609 chip->codec_probe_mask = probe_mask[dev]; 1610 if (chip->codec_probe_mask == -1) { 1611 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1612 if (q) { 1613 dev_info(chip->card->dev, 1614 "probe_mask set to 0x%x for device %04x:%04x\n", 1615 q->value, q->subvendor, q->subdevice); 1616 chip->codec_probe_mask = q->value; 1617 } 1618 } 1619 1620 /* check forced option */ 1621 if (chip->codec_probe_mask != -1 && 1622 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1623 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1624 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1625 (int)azx_bus(chip)->codec_mask); 1626 } 1627 } 1628 1629 /* 1630 * white/black-list for enable_msi 1631 */ 1632 static struct snd_pci_quirk msi_black_list[] = { 1633 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1634 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1635 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1636 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1637 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1638 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1639 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1640 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1641 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1642 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1643 {} 1644 }; 1645 1646 static void check_msi(struct azx *chip) 1647 { 1648 const struct snd_pci_quirk *q; 1649 1650 if (enable_msi >= 0) { 1651 chip->msi = !!enable_msi; 1652 return; 1653 } 1654 chip->msi = 1; /* enable MSI as default */ 1655 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1656 if (q) { 1657 dev_info(chip->card->dev, 1658 "msi for device %04x:%04x set to %d\n", 1659 q->subvendor, q->subdevice, q->value); 1660 chip->msi = q->value; 1661 return; 1662 } 1663 1664 /* NVidia chipsets seem to cause troubles with MSI */ 1665 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1666 dev_info(chip->card->dev, "Disabling MSI\n"); 1667 chip->msi = 0; 1668 } 1669 } 1670 1671 /* check the snoop mode availability */ 1672 static void azx_check_snoop_available(struct azx *chip) 1673 { 1674 int snoop = hda_snoop; 1675 1676 if (snoop >= 0) { 1677 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1678 snoop ? "snoop" : "non-snoop"); 1679 chip->snoop = snoop; 1680 chip->uc_buffer = !snoop; 1681 return; 1682 } 1683 1684 snoop = true; 1685 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1686 chip->driver_type == AZX_DRIVER_VIA) { 1687 /* force to non-snoop mode for a new VIA controller 1688 * when BIOS is set 1689 */ 1690 u8 val; 1691 pci_read_config_byte(chip->pci, 0x42, &val); 1692 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1693 chip->pci->revision == 0x20)) 1694 snoop = false; 1695 } 1696 1697 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1698 snoop = false; 1699 1700 chip->snoop = snoop; 1701 if (!snoop) { 1702 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1703 /* C-Media requires non-cached pages only for CORB/RIRB */ 1704 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1705 chip->uc_buffer = true; 1706 } 1707 } 1708 1709 static void azx_probe_work(struct work_struct *work) 1710 { 1711 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1712 azx_probe_continue(&hda->chip); 1713 } 1714 1715 static int default_bdl_pos_adj(struct azx *chip) 1716 { 1717 /* some exceptions: Atoms seem problematic with value 1 */ 1718 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1719 switch (chip->pci->device) { 1720 case 0x0f04: /* Baytrail */ 1721 case 0x2284: /* Braswell */ 1722 return 32; 1723 } 1724 } 1725 1726 switch (chip->driver_type) { 1727 case AZX_DRIVER_ICH: 1728 case AZX_DRIVER_PCH: 1729 return 1; 1730 default: 1731 return 32; 1732 } 1733 } 1734 1735 /* 1736 * constructor 1737 */ 1738 static const struct hda_controller_ops pci_hda_ops; 1739 1740 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1741 int dev, unsigned int driver_caps, 1742 struct azx **rchip) 1743 { 1744 static struct snd_device_ops ops = { 1745 .dev_disconnect = azx_dev_disconnect, 1746 .dev_free = azx_dev_free, 1747 }; 1748 struct hda_intel *hda; 1749 struct azx *chip; 1750 int err; 1751 1752 *rchip = NULL; 1753 1754 err = pci_enable_device(pci); 1755 if (err < 0) 1756 return err; 1757 1758 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1759 if (!hda) { 1760 pci_disable_device(pci); 1761 return -ENOMEM; 1762 } 1763 1764 chip = &hda->chip; 1765 mutex_init(&chip->open_mutex); 1766 chip->card = card; 1767 chip->pci = pci; 1768 chip->ops = &pci_hda_ops; 1769 chip->driver_caps = driver_caps; 1770 chip->driver_type = driver_caps & 0xff; 1771 check_msi(chip); 1772 chip->dev_index = dev; 1773 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1774 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1775 INIT_LIST_HEAD(&chip->pcm_list); 1776 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1777 INIT_LIST_HEAD(&hda->list); 1778 init_vga_switcheroo(chip); 1779 init_completion(&hda->probe_wait); 1780 1781 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1782 1783 check_probe_mask(chip, dev); 1784 1785 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1786 chip->fallback_to_single_cmd = 1; 1787 else /* explicitly set to single_cmd or not */ 1788 chip->single_cmd = single_cmd; 1789 1790 azx_check_snoop_available(chip); 1791 1792 if (bdl_pos_adj[dev] < 0) 1793 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1794 else 1795 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1796 1797 err = azx_bus_init(chip, model[dev]); 1798 if (err < 0) { 1799 kfree(hda); 1800 pci_disable_device(pci); 1801 return err; 1802 } 1803 1804 /* use the non-cached pages in non-snoop mode */ 1805 if (!azx_snoop(chip)) 1806 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1807 1808 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1809 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1810 chip->bus.needs_damn_long_delay = 1; 1811 } 1812 1813 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1814 if (err < 0) { 1815 dev_err(card->dev, "Error creating device [card]!\n"); 1816 azx_free(chip); 1817 return err; 1818 } 1819 1820 /* continue probing in work context as may trigger request module */ 1821 INIT_WORK(&hda->probe_work, azx_probe_work); 1822 1823 *rchip = chip; 1824 1825 return 0; 1826 } 1827 1828 static int azx_first_init(struct azx *chip) 1829 { 1830 int dev = chip->dev_index; 1831 struct pci_dev *pci = chip->pci; 1832 struct snd_card *card = chip->card; 1833 struct hdac_bus *bus = azx_bus(chip); 1834 int err; 1835 unsigned short gcap; 1836 unsigned int dma_bits = 64; 1837 1838 #if BITS_PER_LONG != 64 1839 /* Fix up base address on ULI M5461 */ 1840 if (chip->driver_type == AZX_DRIVER_ULI) { 1841 u16 tmp3; 1842 pci_read_config_word(pci, 0x40, &tmp3); 1843 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1844 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1845 } 1846 #endif 1847 1848 err = pci_request_regions(pci, "ICH HD audio"); 1849 if (err < 0) 1850 return err; 1851 chip->region_requested = 1; 1852 1853 bus->addr = pci_resource_start(pci, 0); 1854 bus->remap_addr = pci_ioremap_bar(pci, 0); 1855 if (bus->remap_addr == NULL) { 1856 dev_err(card->dev, "ioremap error\n"); 1857 return -ENXIO; 1858 } 1859 1860 if (chip->driver_type == AZX_DRIVER_SKL) 1861 snd_hdac_bus_parse_capabilities(bus); 1862 1863 /* 1864 * Some Intel CPUs has always running timer (ART) feature and 1865 * controller may have Global time sync reporting capability, so 1866 * check both of these before declaring synchronized time reporting 1867 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1868 */ 1869 chip->gts_present = false; 1870 1871 #ifdef CONFIG_X86 1872 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1873 chip->gts_present = true; 1874 #endif 1875 1876 if (chip->msi) { 1877 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1878 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1879 pci->no_64bit_msi = true; 1880 } 1881 if (pci_enable_msi(pci) < 0) 1882 chip->msi = 0; 1883 } 1884 1885 pci_set_master(pci); 1886 synchronize_irq(bus->irq); 1887 1888 gcap = azx_readw(chip, GCAP); 1889 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1890 1891 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1892 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1893 dma_bits = 40; 1894 1895 /* disable SB600 64bit support for safety */ 1896 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1897 struct pci_dev *p_smbus; 1898 dma_bits = 40; 1899 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1900 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1901 NULL); 1902 if (p_smbus) { 1903 if (p_smbus->revision < 0x30) 1904 gcap &= ~AZX_GCAP_64OK; 1905 pci_dev_put(p_smbus); 1906 } 1907 } 1908 1909 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1910 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1911 dma_bits = 40; 1912 1913 /* disable 64bit DMA address on some devices */ 1914 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1915 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1916 gcap &= ~AZX_GCAP_64OK; 1917 } 1918 1919 /* disable buffer size rounding to 128-byte multiples if supported */ 1920 if (align_buffer_size >= 0) 1921 chip->align_buffer_size = !!align_buffer_size; 1922 else { 1923 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1924 chip->align_buffer_size = 0; 1925 else 1926 chip->align_buffer_size = 1; 1927 } 1928 1929 /* allow 64bit DMA address if supported by H/W */ 1930 if (!(gcap & AZX_GCAP_64OK)) 1931 dma_bits = 32; 1932 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1933 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1934 } else { 1935 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1936 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1937 } 1938 1939 /* read number of streams from GCAP register instead of using 1940 * hardcoded value 1941 */ 1942 chip->capture_streams = (gcap >> 8) & 0x0f; 1943 chip->playback_streams = (gcap >> 12) & 0x0f; 1944 if (!chip->playback_streams && !chip->capture_streams) { 1945 /* gcap didn't give any info, switching to old method */ 1946 1947 switch (chip->driver_type) { 1948 case AZX_DRIVER_ULI: 1949 chip->playback_streams = ULI_NUM_PLAYBACK; 1950 chip->capture_streams = ULI_NUM_CAPTURE; 1951 break; 1952 case AZX_DRIVER_ATIHDMI: 1953 case AZX_DRIVER_ATIHDMI_NS: 1954 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1955 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1956 break; 1957 case AZX_DRIVER_GENERIC: 1958 default: 1959 chip->playback_streams = ICH6_NUM_PLAYBACK; 1960 chip->capture_streams = ICH6_NUM_CAPTURE; 1961 break; 1962 } 1963 } 1964 chip->capture_index_offset = 0; 1965 chip->playback_index_offset = chip->capture_streams; 1966 chip->num_streams = chip->playback_streams + chip->capture_streams; 1967 1968 /* sanity check for the SDxCTL.STRM field overflow */ 1969 if (chip->num_streams > 15 && 1970 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1971 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1972 "forcing separate stream tags", chip->num_streams); 1973 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1974 } 1975 1976 /* initialize streams */ 1977 err = azx_init_streams(chip); 1978 if (err < 0) 1979 return err; 1980 1981 err = azx_alloc_stream_pages(chip); 1982 if (err < 0) 1983 return err; 1984 1985 /* initialize chip */ 1986 azx_init_pci(chip); 1987 1988 snd_hdac_i915_set_bclk(bus); 1989 1990 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1991 1992 /* codec detection */ 1993 if (!azx_bus(chip)->codec_mask) { 1994 dev_err(card->dev, "no codecs found!\n"); 1995 return -ENODEV; 1996 } 1997 1998 if (azx_acquire_irq(chip, 0) < 0) 1999 return -EBUSY; 2000 2001 strcpy(card->driver, "HDA-Intel"); 2002 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2003 sizeof(card->shortname)); 2004 snprintf(card->longname, sizeof(card->longname), 2005 "%s at 0x%lx irq %i", 2006 card->shortname, bus->addr, bus->irq); 2007 2008 return 0; 2009 } 2010 2011 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2012 /* callback from request_firmware_nowait() */ 2013 static void azx_firmware_cb(const struct firmware *fw, void *context) 2014 { 2015 struct snd_card *card = context; 2016 struct azx *chip = card->private_data; 2017 struct pci_dev *pci = chip->pci; 2018 2019 if (!fw) { 2020 dev_err(card->dev, "Cannot load firmware, aborting\n"); 2021 goto error; 2022 } 2023 2024 chip->fw = fw; 2025 if (!chip->disabled) { 2026 /* continue probing */ 2027 if (azx_probe_continue(chip)) 2028 goto error; 2029 } 2030 return; /* OK */ 2031 2032 error: 2033 snd_card_free(card); 2034 pci_set_drvdata(pci, NULL); 2035 } 2036 #endif 2037 2038 static int disable_msi_reset_irq(struct azx *chip) 2039 { 2040 struct hdac_bus *bus = azx_bus(chip); 2041 int err; 2042 2043 free_irq(bus->irq, chip); 2044 bus->irq = -1; 2045 pci_disable_msi(chip->pci); 2046 chip->msi = 0; 2047 err = azx_acquire_irq(chip, 1); 2048 if (err < 0) 2049 return err; 2050 2051 return 0; 2052 } 2053 2054 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2055 struct vm_area_struct *area) 2056 { 2057 #ifdef CONFIG_X86 2058 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2059 struct azx *chip = apcm->chip; 2060 if (chip->uc_buffer) 2061 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2062 #endif 2063 } 2064 2065 static const struct hda_controller_ops pci_hda_ops = { 2066 .disable_msi_reset_irq = disable_msi_reset_irq, 2067 .pcm_mmap_prepare = pcm_mmap_prepare, 2068 .position_check = azx_position_check, 2069 }; 2070 2071 static int azx_probe(struct pci_dev *pci, 2072 const struct pci_device_id *pci_id) 2073 { 2074 static int dev; 2075 struct snd_card *card; 2076 struct hda_intel *hda; 2077 struct azx *chip; 2078 bool schedule_probe; 2079 int err; 2080 2081 if (dev >= SNDRV_CARDS) 2082 return -ENODEV; 2083 if (!enable[dev]) { 2084 dev++; 2085 return -ENOENT; 2086 } 2087 2088 /* 2089 * stop probe if another Intel's DSP driver should be activated 2090 */ 2091 if (dsp_driver) { 2092 err = snd_intel_dsp_driver_probe(pci); 2093 if (err != SND_INTEL_DSP_DRIVER_ANY && 2094 err != SND_INTEL_DSP_DRIVER_LEGACY) 2095 return -ENODEV; 2096 } 2097 2098 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2099 0, &card); 2100 if (err < 0) { 2101 dev_err(&pci->dev, "Error creating card!\n"); 2102 return err; 2103 } 2104 2105 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2106 if (err < 0) 2107 goto out_free; 2108 card->private_data = chip; 2109 hda = container_of(chip, struct hda_intel, chip); 2110 2111 pci_set_drvdata(pci, card); 2112 2113 err = register_vga_switcheroo(chip); 2114 if (err < 0) { 2115 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2116 goto out_free; 2117 } 2118 2119 if (check_hdmi_disabled(pci)) { 2120 dev_info(card->dev, "VGA controller is disabled\n"); 2121 dev_info(card->dev, "Delaying initialization\n"); 2122 chip->disabled = true; 2123 } 2124 2125 schedule_probe = !chip->disabled; 2126 2127 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2128 if (patch[dev] && *patch[dev]) { 2129 dev_info(card->dev, "Applying patch firmware '%s'\n", 2130 patch[dev]); 2131 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2132 &pci->dev, GFP_KERNEL, card, 2133 azx_firmware_cb); 2134 if (err < 0) 2135 goto out_free; 2136 schedule_probe = false; /* continued in azx_firmware_cb() */ 2137 } 2138 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2139 2140 #ifndef CONFIG_SND_HDA_I915 2141 if (CONTROLLER_IN_GPU(pci)) 2142 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2143 #endif 2144 2145 if (schedule_probe) 2146 schedule_work(&hda->probe_work); 2147 2148 dev++; 2149 if (chip->disabled) 2150 complete_all(&hda->probe_wait); 2151 return 0; 2152 2153 out_free: 2154 snd_card_free(card); 2155 return err; 2156 } 2157 2158 #ifdef CONFIG_PM 2159 /* On some boards setting power_save to a non 0 value leads to clicking / 2160 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2161 * figure out how to avoid these sounds, but that is not always feasible. 2162 * So we keep a list of devices where we disable powersaving as its known 2163 * to causes problems on these devices. 2164 */ 2165 static struct snd_pci_quirk power_save_blacklist[] = { 2166 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2167 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2168 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2169 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2170 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2171 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2172 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2173 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2174 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2175 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2176 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2177 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2178 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2179 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2180 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2181 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2182 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2183 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2184 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2185 /* https://bugs.launchpad.net/bugs/1821663 */ 2186 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2187 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2188 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2189 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2190 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2191 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2192 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2193 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2194 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2195 /* https://bugs.launchpad.net/bugs/1821663 */ 2196 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2197 {} 2198 }; 2199 #endif /* CONFIG_PM */ 2200 2201 static void set_default_power_save(struct azx *chip) 2202 { 2203 int val = power_save; 2204 2205 #ifdef CONFIG_PM 2206 if (pm_blacklist) { 2207 const struct snd_pci_quirk *q; 2208 2209 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2210 if (q && val) { 2211 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2212 q->subvendor, q->subdevice); 2213 val = 0; 2214 } 2215 } 2216 #endif /* CONFIG_PM */ 2217 snd_hda_set_power_save(&chip->bus, val * 1000); 2218 } 2219 2220 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2221 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2222 [AZX_DRIVER_NVIDIA] = 8, 2223 [AZX_DRIVER_TERA] = 1, 2224 }; 2225 2226 static int azx_probe_continue(struct azx *chip) 2227 { 2228 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2229 struct hdac_bus *bus = azx_bus(chip); 2230 struct pci_dev *pci = chip->pci; 2231 int dev = chip->dev_index; 2232 int err; 2233 2234 to_hda_bus(bus)->bus_probing = 1; 2235 hda->probe_continued = 1; 2236 2237 /* bind with i915 if needed */ 2238 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2239 err = snd_hdac_i915_init(bus); 2240 if (err < 0) { 2241 /* if the controller is bound only with HDMI/DP 2242 * (for HSW and BDW), we need to abort the probe; 2243 * for other chips, still continue probing as other 2244 * codecs can be on the same link. 2245 */ 2246 if (CONTROLLER_IN_GPU(pci)) { 2247 dev_err(chip->card->dev, 2248 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2249 goto out_free; 2250 } else { 2251 /* don't bother any longer */ 2252 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2253 } 2254 } 2255 2256 /* HSW/BDW controllers need this power */ 2257 if (CONTROLLER_IN_GPU(pci)) 2258 hda->need_i915_power = 1; 2259 } 2260 2261 /* Request display power well for the HDA controller or codec. For 2262 * Haswell/Broadwell, both the display HDA controller and codec need 2263 * this power. For other platforms, like Baytrail/Braswell, only the 2264 * display codec needs the power and it can be released after probe. 2265 */ 2266 display_power(chip, true); 2267 2268 err = azx_first_init(chip); 2269 if (err < 0) 2270 goto out_free; 2271 2272 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2273 chip->beep_mode = beep_mode[dev]; 2274 #endif 2275 2276 /* create codec instances */ 2277 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2278 if (err < 0) 2279 goto out_free; 2280 2281 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2282 if (chip->fw) { 2283 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2284 chip->fw->data); 2285 if (err < 0) 2286 goto out_free; 2287 #ifndef CONFIG_PM 2288 release_firmware(chip->fw); /* no longer needed */ 2289 chip->fw = NULL; 2290 #endif 2291 } 2292 #endif 2293 if ((probe_only[dev] & 1) == 0) { 2294 err = azx_codec_configure(chip); 2295 if (err < 0) 2296 goto out_free; 2297 } 2298 2299 err = snd_card_register(chip->card); 2300 if (err < 0) 2301 goto out_free; 2302 2303 setup_vga_switcheroo_runtime_pm(chip); 2304 2305 chip->running = 1; 2306 azx_add_card_list(chip); 2307 2308 set_default_power_save(chip); 2309 2310 if (azx_has_pm_runtime(chip)) 2311 pm_runtime_put_autosuspend(&pci->dev); 2312 2313 out_free: 2314 if (err < 0 || !hda->need_i915_power) 2315 display_power(chip, false); 2316 if (err < 0) 2317 hda->init_failed = 1; 2318 complete_all(&hda->probe_wait); 2319 to_hda_bus(bus)->bus_probing = 0; 2320 return err; 2321 } 2322 2323 static void azx_remove(struct pci_dev *pci) 2324 { 2325 struct snd_card *card = pci_get_drvdata(pci); 2326 struct azx *chip; 2327 struct hda_intel *hda; 2328 2329 if (card) { 2330 /* cancel the pending probing work */ 2331 chip = card->private_data; 2332 hda = container_of(chip, struct hda_intel, chip); 2333 /* FIXME: below is an ugly workaround. 2334 * Both device_release_driver() and driver_probe_device() 2335 * take *both* the device's and its parent's lock before 2336 * calling the remove() and probe() callbacks. The codec 2337 * probe takes the locks of both the codec itself and its 2338 * parent, i.e. the PCI controller dev. Meanwhile, when 2339 * the PCI controller is unbound, it takes its lock, too 2340 * ==> ouch, a deadlock! 2341 * As a workaround, we unlock temporarily here the controller 2342 * device during cancel_work_sync() call. 2343 */ 2344 device_unlock(&pci->dev); 2345 cancel_work_sync(&hda->probe_work); 2346 device_lock(&pci->dev); 2347 2348 snd_card_free(card); 2349 } 2350 } 2351 2352 static void azx_shutdown(struct pci_dev *pci) 2353 { 2354 struct snd_card *card = pci_get_drvdata(pci); 2355 struct azx *chip; 2356 2357 if (!card) 2358 return; 2359 chip = card->private_data; 2360 if (chip && chip->running) 2361 azx_stop_chip(chip); 2362 } 2363 2364 /* PCI IDs */ 2365 static const struct pci_device_id azx_ids[] = { 2366 /* CPT */ 2367 { PCI_DEVICE(0x8086, 0x1c20), 2368 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2369 /* PBG */ 2370 { PCI_DEVICE(0x8086, 0x1d20), 2371 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2372 /* Panther Point */ 2373 { PCI_DEVICE(0x8086, 0x1e20), 2374 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2375 /* Lynx Point */ 2376 { PCI_DEVICE(0x8086, 0x8c20), 2377 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2378 /* 9 Series */ 2379 { PCI_DEVICE(0x8086, 0x8ca0), 2380 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2381 /* Wellsburg */ 2382 { PCI_DEVICE(0x8086, 0x8d20), 2383 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2384 { PCI_DEVICE(0x8086, 0x8d21), 2385 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2386 /* Lewisburg */ 2387 { PCI_DEVICE(0x8086, 0xa1f0), 2388 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2389 { PCI_DEVICE(0x8086, 0xa270), 2390 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2391 /* Lynx Point-LP */ 2392 { PCI_DEVICE(0x8086, 0x9c20), 2393 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2394 /* Lynx Point-LP */ 2395 { PCI_DEVICE(0x8086, 0x9c21), 2396 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2397 /* Wildcat Point-LP */ 2398 { PCI_DEVICE(0x8086, 0x9ca0), 2399 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2400 /* Sunrise Point */ 2401 { PCI_DEVICE(0x8086, 0xa170), 2402 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2403 /* Sunrise Point-LP */ 2404 { PCI_DEVICE(0x8086, 0x9d70), 2405 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2406 /* Kabylake */ 2407 { PCI_DEVICE(0x8086, 0xa171), 2408 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2409 /* Kabylake-LP */ 2410 { PCI_DEVICE(0x8086, 0x9d71), 2411 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2412 /* Kabylake-H */ 2413 { PCI_DEVICE(0x8086, 0xa2f0), 2414 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2415 /* Coffelake */ 2416 { PCI_DEVICE(0x8086, 0xa348), 2417 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2418 /* Cannonlake */ 2419 { PCI_DEVICE(0x8086, 0x9dc8), 2420 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2421 /* CometLake-LP */ 2422 { PCI_DEVICE(0x8086, 0x02C8), 2423 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2424 /* CometLake-H */ 2425 { PCI_DEVICE(0x8086, 0x06C8), 2426 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2427 /* CometLake-S */ 2428 { PCI_DEVICE(0x8086, 0xa3f0), 2429 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2430 /* Icelake */ 2431 { PCI_DEVICE(0x8086, 0x34c8), 2432 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2433 /* Jasperlake */ 2434 { PCI_DEVICE(0x8086, 0x38c8), 2435 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2436 /* Tigerlake */ 2437 { PCI_DEVICE(0x8086, 0xa0c8), 2438 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2439 /* Elkhart Lake */ 2440 { PCI_DEVICE(0x8086, 0x4b55), 2441 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2442 /* Broxton-P(Apollolake) */ 2443 { PCI_DEVICE(0x8086, 0x5a98), 2444 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2445 /* Broxton-T */ 2446 { PCI_DEVICE(0x8086, 0x1a98), 2447 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2448 /* Gemini-Lake */ 2449 { PCI_DEVICE(0x8086, 0x3198), 2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2451 /* Haswell */ 2452 { PCI_DEVICE(0x8086, 0x0a0c), 2453 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2454 { PCI_DEVICE(0x8086, 0x0c0c), 2455 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2456 { PCI_DEVICE(0x8086, 0x0d0c), 2457 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2458 /* Broadwell */ 2459 { PCI_DEVICE(0x8086, 0x160c), 2460 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2461 /* 5 Series/3400 */ 2462 { PCI_DEVICE(0x8086, 0x3b56), 2463 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2464 /* Poulsbo */ 2465 { PCI_DEVICE(0x8086, 0x811b), 2466 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2467 /* Oaktrail */ 2468 { PCI_DEVICE(0x8086, 0x080a), 2469 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2470 /* BayTrail */ 2471 { PCI_DEVICE(0x8086, 0x0f04), 2472 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2473 /* Braswell */ 2474 { PCI_DEVICE(0x8086, 0x2284), 2475 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2476 /* ICH6 */ 2477 { PCI_DEVICE(0x8086, 0x2668), 2478 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2479 /* ICH7 */ 2480 { PCI_DEVICE(0x8086, 0x27d8), 2481 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2482 /* ESB2 */ 2483 { PCI_DEVICE(0x8086, 0x269a), 2484 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2485 /* ICH8 */ 2486 { PCI_DEVICE(0x8086, 0x284b), 2487 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2488 /* ICH9 */ 2489 { PCI_DEVICE(0x8086, 0x293e), 2490 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2491 /* ICH9 */ 2492 { PCI_DEVICE(0x8086, 0x293f), 2493 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2494 /* ICH10 */ 2495 { PCI_DEVICE(0x8086, 0x3a3e), 2496 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2497 /* ICH10 */ 2498 { PCI_DEVICE(0x8086, 0x3a6e), 2499 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2500 /* Generic Intel */ 2501 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2502 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2503 .class_mask = 0xffffff, 2504 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2505 /* ATI SB 450/600/700/800/900 */ 2506 { PCI_DEVICE(0x1002, 0x437b), 2507 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2508 { PCI_DEVICE(0x1002, 0x4383), 2509 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2510 /* AMD Hudson */ 2511 { PCI_DEVICE(0x1022, 0x780d), 2512 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2513 /* AMD, X370 & co */ 2514 { PCI_DEVICE(0x1022, 0x1457), 2515 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2516 /* AMD, X570 & co */ 2517 { PCI_DEVICE(0x1022, 0x1487), 2518 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2519 /* AMD Stoney */ 2520 { PCI_DEVICE(0x1022, 0x157a), 2521 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2522 AZX_DCAPS_PM_RUNTIME }, 2523 /* AMD Raven */ 2524 { PCI_DEVICE(0x1022, 0x15e3), 2525 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2526 /* ATI HDMI */ 2527 { PCI_DEVICE(0x1002, 0x0002), 2528 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2529 { PCI_DEVICE(0x1002, 0x1308), 2530 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2531 { PCI_DEVICE(0x1002, 0x157a), 2532 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2533 { PCI_DEVICE(0x1002, 0x15b3), 2534 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2535 { PCI_DEVICE(0x1002, 0x793b), 2536 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2537 { PCI_DEVICE(0x1002, 0x7919), 2538 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2539 { PCI_DEVICE(0x1002, 0x960f), 2540 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2541 { PCI_DEVICE(0x1002, 0x970f), 2542 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2543 { PCI_DEVICE(0x1002, 0x9840), 2544 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2545 { PCI_DEVICE(0x1002, 0xaa00), 2546 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2547 { PCI_DEVICE(0x1002, 0xaa08), 2548 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2549 { PCI_DEVICE(0x1002, 0xaa10), 2550 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2551 { PCI_DEVICE(0x1002, 0xaa18), 2552 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2553 { PCI_DEVICE(0x1002, 0xaa20), 2554 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2555 { PCI_DEVICE(0x1002, 0xaa28), 2556 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2557 { PCI_DEVICE(0x1002, 0xaa30), 2558 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2559 { PCI_DEVICE(0x1002, 0xaa38), 2560 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2561 { PCI_DEVICE(0x1002, 0xaa40), 2562 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2563 { PCI_DEVICE(0x1002, 0xaa48), 2564 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2565 { PCI_DEVICE(0x1002, 0xaa50), 2566 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2567 { PCI_DEVICE(0x1002, 0xaa58), 2568 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2569 { PCI_DEVICE(0x1002, 0xaa60), 2570 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2571 { PCI_DEVICE(0x1002, 0xaa68), 2572 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2573 { PCI_DEVICE(0x1002, 0xaa80), 2574 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2575 { PCI_DEVICE(0x1002, 0xaa88), 2576 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2577 { PCI_DEVICE(0x1002, 0xaa90), 2578 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2579 { PCI_DEVICE(0x1002, 0xaa98), 2580 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2581 { PCI_DEVICE(0x1002, 0x9902), 2582 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2583 { PCI_DEVICE(0x1002, 0xaaa0), 2584 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2585 { PCI_DEVICE(0x1002, 0xaaa8), 2586 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2587 { PCI_DEVICE(0x1002, 0xaab0), 2588 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2589 { PCI_DEVICE(0x1002, 0xaac0), 2590 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2591 { PCI_DEVICE(0x1002, 0xaac8), 2592 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2593 { PCI_DEVICE(0x1002, 0xaad8), 2594 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2595 AZX_DCAPS_PM_RUNTIME }, 2596 { PCI_DEVICE(0x1002, 0xaae0), 2597 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2598 AZX_DCAPS_PM_RUNTIME }, 2599 { PCI_DEVICE(0x1002, 0xaae8), 2600 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2601 AZX_DCAPS_PM_RUNTIME }, 2602 { PCI_DEVICE(0x1002, 0xaaf0), 2603 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2604 AZX_DCAPS_PM_RUNTIME }, 2605 { PCI_DEVICE(0x1002, 0xaaf8), 2606 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2607 AZX_DCAPS_PM_RUNTIME }, 2608 { PCI_DEVICE(0x1002, 0xab00), 2609 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2610 AZX_DCAPS_PM_RUNTIME }, 2611 { PCI_DEVICE(0x1002, 0xab08), 2612 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2613 AZX_DCAPS_PM_RUNTIME }, 2614 { PCI_DEVICE(0x1002, 0xab10), 2615 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2616 AZX_DCAPS_PM_RUNTIME }, 2617 { PCI_DEVICE(0x1002, 0xab18), 2618 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2619 AZX_DCAPS_PM_RUNTIME }, 2620 { PCI_DEVICE(0x1002, 0xab20), 2621 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2622 AZX_DCAPS_PM_RUNTIME }, 2623 { PCI_DEVICE(0x1002, 0xab38), 2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2625 AZX_DCAPS_PM_RUNTIME }, 2626 /* VIA VT8251/VT8237A */ 2627 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2628 /* VIA GFX VT7122/VX900 */ 2629 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2630 /* VIA GFX VT6122/VX11 */ 2631 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2632 /* SIS966 */ 2633 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2634 /* ULI M5461 */ 2635 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2636 /* NVIDIA MCP */ 2637 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2638 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2639 .class_mask = 0xffffff, 2640 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2641 /* Teradici */ 2642 { PCI_DEVICE(0x6549, 0x1200), 2643 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2644 { PCI_DEVICE(0x6549, 0x2200), 2645 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2646 /* Creative X-Fi (CA0110-IBG) */ 2647 /* CTHDA chips */ 2648 { PCI_DEVICE(0x1102, 0x0010), 2649 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2650 { PCI_DEVICE(0x1102, 0x0012), 2651 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2652 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2653 /* the following entry conflicts with snd-ctxfi driver, 2654 * as ctxfi driver mutates from HD-audio to native mode with 2655 * a special command sequence. 2656 */ 2657 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2658 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2659 .class_mask = 0xffffff, 2660 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2661 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2662 #else 2663 /* this entry seems still valid -- i.e. without emu20kx chip */ 2664 { PCI_DEVICE(0x1102, 0x0009), 2665 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2666 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2667 #endif 2668 /* CM8888 */ 2669 { PCI_DEVICE(0x13f6, 0x5011), 2670 .driver_data = AZX_DRIVER_CMEDIA | 2671 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2672 /* Vortex86MX */ 2673 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2674 /* VMware HDAudio */ 2675 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2676 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2677 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2678 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2679 .class_mask = 0xffffff, 2680 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2681 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2682 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2683 .class_mask = 0xffffff, 2684 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2685 /* Zhaoxin */ 2686 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2687 { 0, } 2688 }; 2689 MODULE_DEVICE_TABLE(pci, azx_ids); 2690 2691 /* pci_driver definition */ 2692 static struct pci_driver azx_driver = { 2693 .name = KBUILD_MODNAME, 2694 .id_table = azx_ids, 2695 .probe = azx_probe, 2696 .remove = azx_remove, 2697 .shutdown = azx_shutdown, 2698 .driver = { 2699 .pm = AZX_PM_OPS, 2700 }, 2701 }; 2702 2703 module_pci_driver(azx_driver); 2704