1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <linux/vgaarb.h> 61 #include <linux/vga_switcheroo.h> 62 #include <linux/firmware.h> 63 #include "hda_codec.h" 64 #include "hda_controller.h" 65 #include "hda_intel.h" 66 67 /* position fix mode */ 68 enum { 69 POS_FIX_AUTO, 70 POS_FIX_LPIB, 71 POS_FIX_POSBUF, 72 POS_FIX_VIACOMBO, 73 POS_FIX_COMBO, 74 }; 75 76 /* Defines for ATI HD Audio support in SB450 south bridge */ 77 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 78 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 79 80 /* Defines for Nvidia HDA support */ 81 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 82 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 83 #define NVIDIA_HDA_ISTRM_COH 0x4d 84 #define NVIDIA_HDA_OSTRM_COH 0x4c 85 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 86 87 /* Defines for Intel SCH HDA snoop control */ 88 #define INTEL_SCH_HDA_DEVC 0x78 89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 90 91 /* Define IN stream 0 FIFO size offset in VIA controller */ 92 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 93 /* Define VIA HD Audio Device ID*/ 94 #define VIA_HDAC_DEVICE_ID 0x3288 95 96 /* max number of SDs */ 97 /* ICH, ATI and VIA have 4 playback and 4 capture */ 98 #define ICH6_NUM_CAPTURE 4 99 #define ICH6_NUM_PLAYBACK 4 100 101 /* ULI has 6 playback and 5 capture */ 102 #define ULI_NUM_CAPTURE 5 103 #define ULI_NUM_PLAYBACK 6 104 105 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 106 #define ATIHDMI_NUM_CAPTURE 0 107 #define ATIHDMI_NUM_PLAYBACK 8 108 109 /* TERA has 4 playback and 3 capture */ 110 #define TERA_NUM_CAPTURE 3 111 #define TERA_NUM_PLAYBACK 4 112 113 114 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 115 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 116 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 117 static char *model[SNDRV_CARDS]; 118 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 119 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 120 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 121 static int probe_only[SNDRV_CARDS]; 122 static int jackpoll_ms[SNDRV_CARDS]; 123 static bool single_cmd; 124 static int enable_msi = -1; 125 #ifdef CONFIG_SND_HDA_PATCH_LOADER 126 static char *patch[SNDRV_CARDS]; 127 #endif 128 #ifdef CONFIG_SND_HDA_INPUT_BEEP 129 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 130 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 131 #endif 132 133 module_param_array(index, int, NULL, 0444); 134 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 135 module_param_array(id, charp, NULL, 0444); 136 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 137 module_param_array(enable, bool, NULL, 0444); 138 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 139 module_param_array(model, charp, NULL, 0444); 140 MODULE_PARM_DESC(model, "Use the given board model."); 141 module_param_array(position_fix, int, NULL, 0444); 142 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 144 module_param_array(bdl_pos_adj, int, NULL, 0644); 145 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 146 module_param_array(probe_mask, int, NULL, 0444); 147 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 148 module_param_array(probe_only, int, NULL, 0444); 149 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 150 module_param_array(jackpoll_ms, int, NULL, 0444); 151 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 152 module_param(single_cmd, bool, 0444); 153 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 154 "(for debugging only)."); 155 module_param(enable_msi, bint, 0444); 156 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 157 #ifdef CONFIG_SND_HDA_PATCH_LOADER 158 module_param_array(patch, charp, NULL, 0444); 159 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 160 #endif 161 #ifdef CONFIG_SND_HDA_INPUT_BEEP 162 module_param_array(beep_mode, bool, NULL, 0444); 163 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 164 "(0=off, 1=on) (default=1)."); 165 #endif 166 167 #ifdef CONFIG_PM 168 static int param_set_xint(const char *val, const struct kernel_param *kp); 169 static struct kernel_param_ops param_ops_xint = { 170 .set = param_set_xint, 171 .get = param_get_int, 172 }; 173 #define param_check_xint param_check_int 174 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 176 module_param(power_save, xint, 0644); 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 178 "(in second, 0 = disable)."); 179 180 /* reset the HD-audio controller in power save mode. 181 * this may give more power-saving, but will take longer time to 182 * wake up. 183 */ 184 static bool power_save_controller = 1; 185 module_param(power_save_controller, bool, 0644); 186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 187 #else 188 #define power_save 0 189 #endif /* CONFIG_PM */ 190 191 static int align_buffer_size = -1; 192 module_param(align_buffer_size, bint, 0644); 193 MODULE_PARM_DESC(align_buffer_size, 194 "Force buffer and period sizes to be multiple of 128 bytes."); 195 196 #ifdef CONFIG_X86 197 static int hda_snoop = -1; 198 module_param_named(snoop, hda_snoop, bint, 0444); 199 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 200 #else 201 #define hda_snoop true 202 #endif 203 204 205 MODULE_LICENSE("GPL"); 206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 207 "{Intel, ICH6M}," 208 "{Intel, ICH7}," 209 "{Intel, ESB2}," 210 "{Intel, ICH8}," 211 "{Intel, ICH9}," 212 "{Intel, ICH10}," 213 "{Intel, PCH}," 214 "{Intel, CPT}," 215 "{Intel, PPT}," 216 "{Intel, LPT}," 217 "{Intel, LPT_LP}," 218 "{Intel, WPT_LP}," 219 "{Intel, SPT}," 220 "{Intel, SPT_LP}," 221 "{Intel, HPT}," 222 "{Intel, PBG}," 223 "{Intel, SCH}," 224 "{ATI, SB450}," 225 "{ATI, SB600}," 226 "{ATI, RS600}," 227 "{ATI, RS690}," 228 "{ATI, RS780}," 229 "{ATI, R600}," 230 "{ATI, RV630}," 231 "{ATI, RV610}," 232 "{ATI, RV670}," 233 "{ATI, RV635}," 234 "{ATI, RV620}," 235 "{ATI, RV770}," 236 "{VIA, VT8251}," 237 "{VIA, VT8237A}," 238 "{SiS, SIS966}," 239 "{ULI, M5461}}"); 240 MODULE_DESCRIPTION("Intel HDA driver"); 241 242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 244 #define SUPPORT_VGA_SWITCHEROO 245 #endif 246 #endif 247 248 249 /* 250 */ 251 252 /* driver types */ 253 enum { 254 AZX_DRIVER_ICH, 255 AZX_DRIVER_PCH, 256 AZX_DRIVER_SCH, 257 AZX_DRIVER_HDMI, 258 AZX_DRIVER_ATI, 259 AZX_DRIVER_ATIHDMI, 260 AZX_DRIVER_ATIHDMI_NS, 261 AZX_DRIVER_VIA, 262 AZX_DRIVER_SIS, 263 AZX_DRIVER_ULI, 264 AZX_DRIVER_NVIDIA, 265 AZX_DRIVER_TERA, 266 AZX_DRIVER_CTX, 267 AZX_DRIVER_CTHDA, 268 AZX_DRIVER_CMEDIA, 269 AZX_DRIVER_GENERIC, 270 AZX_NUM_DRIVERS, /* keep this as last entry */ 271 }; 272 273 #define azx_get_snoop_type(chip) \ 274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 276 277 /* quirks for old Intel chipsets */ 278 #define AZX_DCAPS_INTEL_ICH \ 279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 280 281 /* quirks for Intel PCH */ 282 #define AZX_DCAPS_INTEL_PCH_NOPM \ 283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH)) 285 286 #define AZX_DCAPS_INTEL_PCH \ 287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 288 289 #define AZX_DCAPS_INTEL_HASWELL \ 290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 292 AZX_DCAPS_SNOOP_TYPE(SCH)) 293 294 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 295 #define AZX_DCAPS_INTEL_BROADWELL \ 296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 298 AZX_DCAPS_SNOOP_TYPE(SCH)) 299 300 #define AZX_DCAPS_INTEL_BRASWELL \ 301 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL) 302 303 #define AZX_DCAPS_INTEL_SKYLAKE \ 304 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 305 AZX_DCAPS_I915_POWERWELL) 306 307 /* quirks for ATI SB / AMD Hudson */ 308 #define AZX_DCAPS_PRESET_ATI_SB \ 309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 310 AZX_DCAPS_SNOOP_TYPE(ATI)) 311 312 /* quirks for ATI/AMD HDMI */ 313 #define AZX_DCAPS_PRESET_ATI_HDMI \ 314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 315 AZX_DCAPS_NO_MSI64) 316 317 /* quirks for ATI HDMI with snoop off */ 318 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 319 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 320 321 /* quirks for Nvidia */ 322 #define AZX_DCAPS_PRESET_NVIDIA \ 323 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 324 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 325 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 326 327 #define AZX_DCAPS_PRESET_CTHDA \ 328 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 329 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 330 331 /* 332 * VGA-switcher support 333 */ 334 #ifdef SUPPORT_VGA_SWITCHEROO 335 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 336 #else 337 #define use_vga_switcheroo(chip) 0 338 #endif 339 340 static char *driver_short_names[] = { 341 [AZX_DRIVER_ICH] = "HDA Intel", 342 [AZX_DRIVER_PCH] = "HDA Intel PCH", 343 [AZX_DRIVER_SCH] = "HDA Intel MID", 344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 345 [AZX_DRIVER_ATI] = "HDA ATI SB", 346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 348 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 349 [AZX_DRIVER_SIS] = "HDA SIS966", 350 [AZX_DRIVER_ULI] = "HDA ULI M5461", 351 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 352 [AZX_DRIVER_TERA] = "HDA Teradici", 353 [AZX_DRIVER_CTX] = "HDA Creative", 354 [AZX_DRIVER_CTHDA] = "HDA Creative", 355 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 356 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 357 }; 358 359 #ifdef CONFIG_X86 360 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 361 { 362 int pages; 363 364 if (azx_snoop(chip)) 365 return; 366 if (!dmab || !dmab->area || !dmab->bytes) 367 return; 368 369 #ifdef CONFIG_SND_DMA_SGBUF 370 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 371 struct snd_sg_buf *sgbuf = dmab->private_data; 372 if (chip->driver_type == AZX_DRIVER_CMEDIA) 373 return; /* deal with only CORB/RIRB buffers */ 374 if (on) 375 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 376 else 377 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 378 return; 379 } 380 #endif 381 382 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 383 if (on) 384 set_memory_wc((unsigned long)dmab->area, pages); 385 else 386 set_memory_wb((unsigned long)dmab->area, pages); 387 } 388 389 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 390 bool on) 391 { 392 __mark_pages_wc(chip, buf, on); 393 } 394 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 395 struct snd_pcm_substream *substream, bool on) 396 { 397 if (azx_dev->wc_marked != on) { 398 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 399 azx_dev->wc_marked = on; 400 } 401 } 402 #else 403 /* NOP for other archs */ 404 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 405 bool on) 406 { 407 } 408 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 409 struct snd_pcm_substream *substream, bool on) 410 { 411 } 412 #endif 413 414 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 415 416 /* 417 * initialize the PCI registers 418 */ 419 /* update bits in a PCI register byte */ 420 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 421 unsigned char mask, unsigned char val) 422 { 423 unsigned char data; 424 425 pci_read_config_byte(pci, reg, &data); 426 data &= ~mask; 427 data |= (val & mask); 428 pci_write_config_byte(pci, reg, data); 429 } 430 431 static void azx_init_pci(struct azx *chip) 432 { 433 int snoop_type = azx_get_snoop_type(chip); 434 435 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 436 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 437 * Ensuring these bits are 0 clears playback static on some HD Audio 438 * codecs. 439 * The PCI register TCSEL is defined in the Intel manuals. 440 */ 441 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 442 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 443 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 444 } 445 446 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 447 * we need to enable snoop. 448 */ 449 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 450 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 451 azx_snoop(chip)); 452 update_pci_byte(chip->pci, 453 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 454 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 455 } 456 457 /* For NVIDIA HDA, enable snoop */ 458 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 459 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 460 azx_snoop(chip)); 461 update_pci_byte(chip->pci, 462 NVIDIA_HDA_TRANSREG_ADDR, 463 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 464 update_pci_byte(chip->pci, 465 NVIDIA_HDA_ISTRM_COH, 466 0x01, NVIDIA_HDA_ENABLE_COHBIT); 467 update_pci_byte(chip->pci, 468 NVIDIA_HDA_OSTRM_COH, 469 0x01, NVIDIA_HDA_ENABLE_COHBIT); 470 } 471 472 /* Enable SCH/PCH snoop if needed */ 473 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 474 unsigned short snoop; 475 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 476 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 477 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 478 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 479 if (!azx_snoop(chip)) 480 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 481 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 482 pci_read_config_word(chip->pci, 483 INTEL_SCH_HDA_DEVC, &snoop); 484 } 485 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 486 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 487 "Disabled" : "Enabled"); 488 } 489 } 490 491 /* calculate runtime delay from LPIB */ 492 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 493 unsigned int pos) 494 { 495 struct snd_pcm_substream *substream = azx_dev->substream; 496 int stream = substream->stream; 497 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 498 int delay; 499 500 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 501 delay = pos - lpib_pos; 502 else 503 delay = lpib_pos - pos; 504 if (delay < 0) { 505 if (delay >= azx_dev->delay_negative_threshold) 506 delay = 0; 507 else 508 delay += azx_dev->bufsize; 509 } 510 511 if (delay >= azx_dev->period_bytes) { 512 dev_info(chip->card->dev, 513 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 514 delay, azx_dev->period_bytes); 515 delay = 0; 516 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 517 chip->get_delay[stream] = NULL; 518 } 519 520 return bytes_to_frames(substream->runtime, delay); 521 } 522 523 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 524 525 /* called from IRQ */ 526 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 527 { 528 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 529 int ok; 530 531 ok = azx_position_ok(chip, azx_dev); 532 if (ok == 1) { 533 azx_dev->irq_pending = 0; 534 return ok; 535 } else if (ok == 0) { 536 /* bogus IRQ, process it later */ 537 azx_dev->irq_pending = 1; 538 schedule_work(&hda->irq_pending_work); 539 } 540 return 0; 541 } 542 543 /* 544 * Check whether the current DMA position is acceptable for updating 545 * periods. Returns non-zero if it's OK. 546 * 547 * Many HD-audio controllers appear pretty inaccurate about 548 * the update-IRQ timing. The IRQ is issued before actually the 549 * data is processed. So, we need to process it afterwords in a 550 * workqueue. 551 */ 552 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 553 { 554 struct snd_pcm_substream *substream = azx_dev->substream; 555 int stream = substream->stream; 556 u32 wallclk; 557 unsigned int pos; 558 559 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 560 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 561 return -1; /* bogus (too early) interrupt */ 562 563 if (chip->get_position[stream]) 564 pos = chip->get_position[stream](chip, azx_dev); 565 else { /* use the position buffer as default */ 566 pos = azx_get_pos_posbuf(chip, azx_dev); 567 if (!pos || pos == (u32)-1) { 568 dev_info(chip->card->dev, 569 "Invalid position buffer, using LPIB read method instead.\n"); 570 chip->get_position[stream] = azx_get_pos_lpib; 571 pos = azx_get_pos_lpib(chip, azx_dev); 572 chip->get_delay[stream] = NULL; 573 } else { 574 chip->get_position[stream] = azx_get_pos_posbuf; 575 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 576 chip->get_delay[stream] = azx_get_delay_from_lpib; 577 } 578 } 579 580 if (pos >= azx_dev->bufsize) 581 pos = 0; 582 583 if (WARN_ONCE(!azx_dev->period_bytes, 584 "hda-intel: zero azx_dev->period_bytes")) 585 return -1; /* this shouldn't happen! */ 586 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 587 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 588 /* NG - it's below the first next period boundary */ 589 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; 590 azx_dev->start_wallclk += wallclk; 591 return 1; /* OK, it's fine */ 592 } 593 594 /* 595 * The work for pending PCM period updates. 596 */ 597 static void azx_irq_pending_work(struct work_struct *work) 598 { 599 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 600 struct azx *chip = &hda->chip; 601 int i, pending, ok; 602 603 if (!hda->irq_pending_warned) { 604 dev_info(chip->card->dev, 605 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 606 chip->card->number); 607 hda->irq_pending_warned = 1; 608 } 609 610 for (;;) { 611 pending = 0; 612 spin_lock_irq(&chip->reg_lock); 613 for (i = 0; i < chip->num_streams; i++) { 614 struct azx_dev *azx_dev = &chip->azx_dev[i]; 615 if (!azx_dev->irq_pending || 616 !azx_dev->substream || 617 !azx_dev->running) 618 continue; 619 ok = azx_position_ok(chip, azx_dev); 620 if (ok > 0) { 621 azx_dev->irq_pending = 0; 622 spin_unlock(&chip->reg_lock); 623 snd_pcm_period_elapsed(azx_dev->substream); 624 spin_lock(&chip->reg_lock); 625 } else if (ok < 0) { 626 pending = 0; /* too early */ 627 } else 628 pending++; 629 } 630 spin_unlock_irq(&chip->reg_lock); 631 if (!pending) 632 return; 633 msleep(1); 634 } 635 } 636 637 /* clear irq_pending flags and assure no on-going workq */ 638 static void azx_clear_irq_pending(struct azx *chip) 639 { 640 int i; 641 642 spin_lock_irq(&chip->reg_lock); 643 for (i = 0; i < chip->num_streams; i++) 644 chip->azx_dev[i].irq_pending = 0; 645 spin_unlock_irq(&chip->reg_lock); 646 } 647 648 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 649 { 650 if (request_irq(chip->pci->irq, azx_interrupt, 651 chip->msi ? 0 : IRQF_SHARED, 652 KBUILD_MODNAME, chip)) { 653 dev_err(chip->card->dev, 654 "unable to grab IRQ %d, disabling device\n", 655 chip->pci->irq); 656 if (do_disconnect) 657 snd_card_disconnect(chip->card); 658 return -1; 659 } 660 chip->irq = chip->pci->irq; 661 pci_intx(chip->pci, !chip->msi); 662 return 0; 663 } 664 665 /* get the current DMA position with correction on VIA chips */ 666 static unsigned int azx_via_get_position(struct azx *chip, 667 struct azx_dev *azx_dev) 668 { 669 unsigned int link_pos, mini_pos, bound_pos; 670 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 671 unsigned int fifo_size; 672 673 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); 674 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 675 /* Playback, no problem using link position */ 676 return link_pos; 677 } 678 679 /* Capture */ 680 /* For new chipset, 681 * use mod to get the DMA position just like old chipset 682 */ 683 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 684 mod_dma_pos %= azx_dev->period_bytes; 685 686 /* azx_dev->fifo_size can't get FIFO size of in stream. 687 * Get from base address + offset. 688 */ 689 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 690 691 if (azx_dev->insufficient) { 692 /* Link position never gather than FIFO size */ 693 if (link_pos <= fifo_size) 694 return 0; 695 696 azx_dev->insufficient = 0; 697 } 698 699 if (link_pos <= fifo_size) 700 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 701 else 702 mini_pos = link_pos - fifo_size; 703 704 /* Find nearest previous boudary */ 705 mod_mini_pos = mini_pos % azx_dev->period_bytes; 706 mod_link_pos = link_pos % azx_dev->period_bytes; 707 if (mod_link_pos >= fifo_size) 708 bound_pos = link_pos - mod_link_pos; 709 else if (mod_dma_pos >= mod_mini_pos) 710 bound_pos = mini_pos - mod_mini_pos; 711 else { 712 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 713 if (bound_pos >= azx_dev->bufsize) 714 bound_pos = 0; 715 } 716 717 /* Calculate real DMA position we want */ 718 return bound_pos + mod_dma_pos; 719 } 720 721 #ifdef CONFIG_PM 722 static DEFINE_MUTEX(card_list_lock); 723 static LIST_HEAD(card_list); 724 725 static void azx_add_card_list(struct azx *chip) 726 { 727 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 728 mutex_lock(&card_list_lock); 729 list_add(&hda->list, &card_list); 730 mutex_unlock(&card_list_lock); 731 } 732 733 static void azx_del_card_list(struct azx *chip) 734 { 735 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 736 mutex_lock(&card_list_lock); 737 list_del_init(&hda->list); 738 mutex_unlock(&card_list_lock); 739 } 740 741 /* trigger power-save check at writing parameter */ 742 static int param_set_xint(const char *val, const struct kernel_param *kp) 743 { 744 struct hda_intel *hda; 745 struct azx *chip; 746 int prev = power_save; 747 int ret = param_set_int(val, kp); 748 749 if (ret || prev == power_save) 750 return ret; 751 752 mutex_lock(&card_list_lock); 753 list_for_each_entry(hda, &card_list, list) { 754 chip = &hda->chip; 755 if (!chip->bus || chip->disabled) 756 continue; 757 snd_hda_set_power_save(chip->bus, power_save * 1000); 758 } 759 mutex_unlock(&card_list_lock); 760 return 0; 761 } 762 #else 763 #define azx_add_card_list(chip) /* NOP */ 764 #define azx_del_card_list(chip) /* NOP */ 765 #endif /* CONFIG_PM */ 766 767 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 768 /* 769 * power management 770 */ 771 static int azx_suspend(struct device *dev) 772 { 773 struct snd_card *card = dev_get_drvdata(dev); 774 struct azx *chip; 775 struct hda_intel *hda; 776 777 if (!card) 778 return 0; 779 780 chip = card->private_data; 781 hda = container_of(chip, struct hda_intel, chip); 782 if (chip->disabled || hda->init_failed) 783 return 0; 784 785 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 786 azx_clear_irq_pending(chip); 787 azx_stop_chip(chip); 788 azx_enter_link_reset(chip); 789 if (chip->irq >= 0) { 790 free_irq(chip->irq, chip); 791 chip->irq = -1; 792 } 793 794 if (chip->msi) 795 pci_disable_msi(chip->pci); 796 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 797 hda_display_power(hda, false); 798 return 0; 799 } 800 801 static int azx_resume(struct device *dev) 802 { 803 struct pci_dev *pci = to_pci_dev(dev); 804 struct snd_card *card = dev_get_drvdata(dev); 805 struct azx *chip; 806 struct hda_intel *hda; 807 808 if (!card) 809 return 0; 810 811 chip = card->private_data; 812 hda = container_of(chip, struct hda_intel, chip); 813 if (chip->disabled || hda->init_failed) 814 return 0; 815 816 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 817 hda_display_power(hda, true); 818 haswell_set_bclk(hda); 819 } 820 if (chip->msi) 821 if (pci_enable_msi(pci) < 0) 822 chip->msi = 0; 823 if (azx_acquire_irq(chip, 1) < 0) 824 return -EIO; 825 azx_init_pci(chip); 826 827 azx_init_chip(chip, true); 828 829 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 830 return 0; 831 } 832 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 833 834 #ifdef CONFIG_PM 835 static int azx_runtime_suspend(struct device *dev) 836 { 837 struct snd_card *card = dev_get_drvdata(dev); 838 struct azx *chip; 839 struct hda_intel *hda; 840 841 if (!card) 842 return 0; 843 844 chip = card->private_data; 845 hda = container_of(chip, struct hda_intel, chip); 846 if (chip->disabled || hda->init_failed) 847 return 0; 848 849 if (!azx_has_pm_runtime(chip)) 850 return 0; 851 852 /* enable controller wake up event */ 853 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 854 STATESTS_INT_MASK); 855 856 azx_stop_chip(chip); 857 azx_enter_link_reset(chip); 858 azx_clear_irq_pending(chip); 859 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 860 hda_display_power(hda, false); 861 862 return 0; 863 } 864 865 static int azx_runtime_resume(struct device *dev) 866 { 867 struct snd_card *card = dev_get_drvdata(dev); 868 struct azx *chip; 869 struct hda_intel *hda; 870 struct hda_bus *bus; 871 struct hda_codec *codec; 872 int status; 873 874 if (!card) 875 return 0; 876 877 chip = card->private_data; 878 hda = container_of(chip, struct hda_intel, chip); 879 if (chip->disabled || hda->init_failed) 880 return 0; 881 882 if (!azx_has_pm_runtime(chip)) 883 return 0; 884 885 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 886 hda_display_power(hda, true); 887 haswell_set_bclk(hda); 888 } 889 890 /* Read STATESTS before controller reset */ 891 status = azx_readw(chip, STATESTS); 892 893 azx_init_pci(chip); 894 azx_init_chip(chip, true); 895 896 bus = chip->bus; 897 if (status && bus) { 898 list_for_each_codec(codec, bus) 899 if (status & (1 << codec->addr)) 900 schedule_delayed_work(&codec->jackpoll_work, 901 codec->jackpoll_interval); 902 } 903 904 /* disable controller Wake Up event*/ 905 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 906 ~STATESTS_INT_MASK); 907 908 return 0; 909 } 910 911 static int azx_runtime_idle(struct device *dev) 912 { 913 struct snd_card *card = dev_get_drvdata(dev); 914 struct azx *chip; 915 struct hda_intel *hda; 916 917 if (!card) 918 return 0; 919 920 chip = card->private_data; 921 hda = container_of(chip, struct hda_intel, chip); 922 if (chip->disabled || hda->init_failed) 923 return 0; 924 925 if (!power_save_controller || !azx_has_pm_runtime(chip) || 926 chip->bus->core.codec_powered) 927 return -EBUSY; 928 929 return 0; 930 } 931 932 static const struct dev_pm_ops azx_pm = { 933 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 934 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 935 }; 936 937 #define AZX_PM_OPS &azx_pm 938 #else 939 #define AZX_PM_OPS NULL 940 #endif /* CONFIG_PM */ 941 942 943 static int azx_probe_continue(struct azx *chip); 944 945 #ifdef SUPPORT_VGA_SWITCHEROO 946 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 947 948 static void azx_vs_set_state(struct pci_dev *pci, 949 enum vga_switcheroo_state state) 950 { 951 struct snd_card *card = pci_get_drvdata(pci); 952 struct azx *chip = card->private_data; 953 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 954 bool disabled; 955 956 wait_for_completion(&hda->probe_wait); 957 if (hda->init_failed) 958 return; 959 960 disabled = (state == VGA_SWITCHEROO_OFF); 961 if (chip->disabled == disabled) 962 return; 963 964 if (!chip->bus) { 965 chip->disabled = disabled; 966 if (!disabled) { 967 dev_info(chip->card->dev, 968 "Start delayed initialization\n"); 969 if (azx_probe_continue(chip) < 0) { 970 dev_err(chip->card->dev, "initialization error\n"); 971 hda->init_failed = true; 972 } 973 } 974 } else { 975 dev_info(chip->card->dev, "%s via VGA-switcheroo\n", 976 disabled ? "Disabling" : "Enabling"); 977 if (disabled) { 978 pm_runtime_put_sync_suspend(card->dev); 979 azx_suspend(card->dev); 980 /* when we get suspended by vga switcheroo we end up in D3cold, 981 * however we have no ACPI handle, so pci/acpi can't put us there, 982 * put ourselves there */ 983 pci->current_state = PCI_D3cold; 984 chip->disabled = true; 985 if (snd_hda_lock_devices(chip->bus)) 986 dev_warn(chip->card->dev, 987 "Cannot lock devices!\n"); 988 } else { 989 snd_hda_unlock_devices(chip->bus); 990 pm_runtime_get_noresume(card->dev); 991 chip->disabled = false; 992 azx_resume(card->dev); 993 } 994 } 995 } 996 997 static bool azx_vs_can_switch(struct pci_dev *pci) 998 { 999 struct snd_card *card = pci_get_drvdata(pci); 1000 struct azx *chip = card->private_data; 1001 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1002 1003 wait_for_completion(&hda->probe_wait); 1004 if (hda->init_failed) 1005 return false; 1006 if (chip->disabled || !chip->bus) 1007 return true; 1008 if (snd_hda_lock_devices(chip->bus)) 1009 return false; 1010 snd_hda_unlock_devices(chip->bus); 1011 return true; 1012 } 1013 1014 static void init_vga_switcheroo(struct azx *chip) 1015 { 1016 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1017 struct pci_dev *p = get_bound_vga(chip->pci); 1018 if (p) { 1019 dev_info(chip->card->dev, 1020 "Handle VGA-switcheroo audio client\n"); 1021 hda->use_vga_switcheroo = 1; 1022 pci_dev_put(p); 1023 } 1024 } 1025 1026 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1027 .set_gpu_state = azx_vs_set_state, 1028 .can_switch = azx_vs_can_switch, 1029 }; 1030 1031 static int register_vga_switcheroo(struct azx *chip) 1032 { 1033 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1034 int err; 1035 1036 if (!hda->use_vga_switcheroo) 1037 return 0; 1038 /* FIXME: currently only handling DIS controller 1039 * is there any machine with two switchable HDMI audio controllers? 1040 */ 1041 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1042 VGA_SWITCHEROO_DIS, 1043 chip->bus != NULL); 1044 if (err < 0) 1045 return err; 1046 hda->vga_switcheroo_registered = 1; 1047 1048 /* register as an optimus hdmi audio power domain */ 1049 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1050 &hda->hdmi_pm_domain); 1051 return 0; 1052 } 1053 #else 1054 #define init_vga_switcheroo(chip) /* NOP */ 1055 #define register_vga_switcheroo(chip) 0 1056 #define check_hdmi_disabled(pci) false 1057 #endif /* SUPPORT_VGA_SWITCHER */ 1058 1059 /* 1060 * destructor 1061 */ 1062 static int azx_free(struct azx *chip) 1063 { 1064 struct pci_dev *pci = chip->pci; 1065 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1066 int i; 1067 1068 if (azx_has_pm_runtime(chip) && chip->running) 1069 pm_runtime_get_noresume(&pci->dev); 1070 1071 azx_del_card_list(chip); 1072 1073 hda->init_failed = 1; /* to be sure */ 1074 complete_all(&hda->probe_wait); 1075 1076 if (use_vga_switcheroo(hda)) { 1077 if (chip->disabled && chip->bus) 1078 snd_hda_unlock_devices(chip->bus); 1079 if (hda->vga_switcheroo_registered) 1080 vga_switcheroo_unregister_client(chip->pci); 1081 } 1082 1083 if (chip->initialized) { 1084 azx_clear_irq_pending(chip); 1085 for (i = 0; i < chip->num_streams; i++) 1086 azx_stream_stop(chip, &chip->azx_dev[i]); 1087 azx_stop_chip(chip); 1088 } 1089 1090 if (chip->irq >= 0) 1091 free_irq(chip->irq, (void*)chip); 1092 if (chip->msi) 1093 pci_disable_msi(chip->pci); 1094 iounmap(chip->remap_addr); 1095 1096 azx_free_stream_pages(chip); 1097 if (chip->region_requested) 1098 pci_release_regions(chip->pci); 1099 pci_disable_device(chip->pci); 1100 kfree(chip->azx_dev); 1101 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1102 release_firmware(chip->fw); 1103 #endif 1104 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1105 hda_display_power(hda, false); 1106 hda_i915_exit(hda); 1107 } 1108 kfree(hda); 1109 1110 return 0; 1111 } 1112 1113 static int azx_dev_free(struct snd_device *device) 1114 { 1115 return azx_free(device->device_data); 1116 } 1117 1118 #ifdef SUPPORT_VGA_SWITCHEROO 1119 /* 1120 * Check of disabled HDMI controller by vga-switcheroo 1121 */ 1122 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1123 { 1124 struct pci_dev *p; 1125 1126 /* check only discrete GPU */ 1127 switch (pci->vendor) { 1128 case PCI_VENDOR_ID_ATI: 1129 case PCI_VENDOR_ID_AMD: 1130 case PCI_VENDOR_ID_NVIDIA: 1131 if (pci->devfn == 1) { 1132 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1133 pci->bus->number, 0); 1134 if (p) { 1135 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1136 return p; 1137 pci_dev_put(p); 1138 } 1139 } 1140 break; 1141 } 1142 return NULL; 1143 } 1144 1145 static bool check_hdmi_disabled(struct pci_dev *pci) 1146 { 1147 bool vga_inactive = false; 1148 struct pci_dev *p = get_bound_vga(pci); 1149 1150 if (p) { 1151 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1152 vga_inactive = true; 1153 pci_dev_put(p); 1154 } 1155 return vga_inactive; 1156 } 1157 #endif /* SUPPORT_VGA_SWITCHEROO */ 1158 1159 /* 1160 * white/black-listing for position_fix 1161 */ 1162 static struct snd_pci_quirk position_fix_list[] = { 1163 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1164 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1165 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1166 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1167 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1168 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1169 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1170 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1171 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1172 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1173 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1174 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1175 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1176 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1177 {} 1178 }; 1179 1180 static int check_position_fix(struct azx *chip, int fix) 1181 { 1182 const struct snd_pci_quirk *q; 1183 1184 switch (fix) { 1185 case POS_FIX_AUTO: 1186 case POS_FIX_LPIB: 1187 case POS_FIX_POSBUF: 1188 case POS_FIX_VIACOMBO: 1189 case POS_FIX_COMBO: 1190 return fix; 1191 } 1192 1193 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1194 if (q) { 1195 dev_info(chip->card->dev, 1196 "position_fix set to %d for device %04x:%04x\n", 1197 q->value, q->subvendor, q->subdevice); 1198 return q->value; 1199 } 1200 1201 /* Check VIA/ATI HD Audio Controller exist */ 1202 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 1203 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1204 return POS_FIX_VIACOMBO; 1205 } 1206 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1207 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1208 return POS_FIX_LPIB; 1209 } 1210 return POS_FIX_AUTO; 1211 } 1212 1213 static void assign_position_fix(struct azx *chip, int fix) 1214 { 1215 static azx_get_pos_callback_t callbacks[] = { 1216 [POS_FIX_AUTO] = NULL, 1217 [POS_FIX_LPIB] = azx_get_pos_lpib, 1218 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1219 [POS_FIX_VIACOMBO] = azx_via_get_position, 1220 [POS_FIX_COMBO] = azx_get_pos_lpib, 1221 }; 1222 1223 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1224 1225 /* combo mode uses LPIB only for playback */ 1226 if (fix == POS_FIX_COMBO) 1227 chip->get_position[1] = NULL; 1228 1229 if (fix == POS_FIX_POSBUF && 1230 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1231 chip->get_delay[0] = chip->get_delay[1] = 1232 azx_get_delay_from_lpib; 1233 } 1234 1235 } 1236 1237 /* 1238 * black-lists for probe_mask 1239 */ 1240 static struct snd_pci_quirk probe_mask_list[] = { 1241 /* Thinkpad often breaks the controller communication when accessing 1242 * to the non-working (or non-existing) modem codec slot. 1243 */ 1244 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1245 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1246 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1247 /* broken BIOS */ 1248 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1249 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1250 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1251 /* forced codec slots */ 1252 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1253 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1254 /* WinFast VP200 H (Teradici) user reported broken communication */ 1255 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1256 {} 1257 }; 1258 1259 #define AZX_FORCE_CODEC_MASK 0x100 1260 1261 static void check_probe_mask(struct azx *chip, int dev) 1262 { 1263 const struct snd_pci_quirk *q; 1264 1265 chip->codec_probe_mask = probe_mask[dev]; 1266 if (chip->codec_probe_mask == -1) { 1267 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1268 if (q) { 1269 dev_info(chip->card->dev, 1270 "probe_mask set to 0x%x for device %04x:%04x\n", 1271 q->value, q->subvendor, q->subdevice); 1272 chip->codec_probe_mask = q->value; 1273 } 1274 } 1275 1276 /* check forced option */ 1277 if (chip->codec_probe_mask != -1 && 1278 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1279 chip->codec_mask = chip->codec_probe_mask & 0xff; 1280 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1281 chip->codec_mask); 1282 } 1283 } 1284 1285 /* 1286 * white/black-list for enable_msi 1287 */ 1288 static struct snd_pci_quirk msi_black_list[] = { 1289 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1290 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1291 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1292 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1293 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1294 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1295 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1296 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1297 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1298 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1299 {} 1300 }; 1301 1302 static void check_msi(struct azx *chip) 1303 { 1304 const struct snd_pci_quirk *q; 1305 1306 if (enable_msi >= 0) { 1307 chip->msi = !!enable_msi; 1308 return; 1309 } 1310 chip->msi = 1; /* enable MSI as default */ 1311 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1312 if (q) { 1313 dev_info(chip->card->dev, 1314 "msi for device %04x:%04x set to %d\n", 1315 q->subvendor, q->subdevice, q->value); 1316 chip->msi = q->value; 1317 return; 1318 } 1319 1320 /* NVidia chipsets seem to cause troubles with MSI */ 1321 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1322 dev_info(chip->card->dev, "Disabling MSI\n"); 1323 chip->msi = 0; 1324 } 1325 } 1326 1327 /* check the snoop mode availability */ 1328 static void azx_check_snoop_available(struct azx *chip) 1329 { 1330 int snoop = hda_snoop; 1331 1332 if (snoop >= 0) { 1333 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1334 snoop ? "snoop" : "non-snoop"); 1335 chip->snoop = snoop; 1336 return; 1337 } 1338 1339 snoop = true; 1340 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1341 chip->driver_type == AZX_DRIVER_VIA) { 1342 /* force to non-snoop mode for a new VIA controller 1343 * when BIOS is set 1344 */ 1345 u8 val; 1346 pci_read_config_byte(chip->pci, 0x42, &val); 1347 if (!(val & 0x80) && chip->pci->revision == 0x30) 1348 snoop = false; 1349 } 1350 1351 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1352 snoop = false; 1353 1354 chip->snoop = snoop; 1355 if (!snoop) 1356 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1357 } 1358 1359 static void azx_probe_work(struct work_struct *work) 1360 { 1361 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1362 azx_probe_continue(&hda->chip); 1363 } 1364 1365 /* 1366 * constructor 1367 */ 1368 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1369 int dev, unsigned int driver_caps, 1370 const struct hda_controller_ops *hda_ops, 1371 struct azx **rchip) 1372 { 1373 static struct snd_device_ops ops = { 1374 .dev_free = azx_dev_free, 1375 }; 1376 struct hda_intel *hda; 1377 struct azx *chip; 1378 int err; 1379 1380 *rchip = NULL; 1381 1382 err = pci_enable_device(pci); 1383 if (err < 0) 1384 return err; 1385 1386 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1387 if (!hda) { 1388 pci_disable_device(pci); 1389 return -ENOMEM; 1390 } 1391 1392 chip = &hda->chip; 1393 spin_lock_init(&chip->reg_lock); 1394 mutex_init(&chip->open_mutex); 1395 chip->card = card; 1396 chip->pci = pci; 1397 chip->ops = hda_ops; 1398 chip->irq = -1; 1399 chip->driver_caps = driver_caps; 1400 chip->driver_type = driver_caps & 0xff; 1401 check_msi(chip); 1402 chip->dev_index = dev; 1403 chip->jackpoll_ms = jackpoll_ms; 1404 INIT_LIST_HEAD(&chip->pcm_list); 1405 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1406 INIT_LIST_HEAD(&hda->list); 1407 init_vga_switcheroo(chip); 1408 init_completion(&hda->probe_wait); 1409 1410 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1411 1412 check_probe_mask(chip, dev); 1413 1414 chip->single_cmd = single_cmd; 1415 azx_check_snoop_available(chip); 1416 1417 if (bdl_pos_adj[dev] < 0) { 1418 switch (chip->driver_type) { 1419 case AZX_DRIVER_ICH: 1420 case AZX_DRIVER_PCH: 1421 bdl_pos_adj[dev] = 1; 1422 break; 1423 default: 1424 bdl_pos_adj[dev] = 32; 1425 break; 1426 } 1427 } 1428 chip->bdl_pos_adj = bdl_pos_adj; 1429 1430 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1431 if (err < 0) { 1432 dev_err(card->dev, "Error creating device [card]!\n"); 1433 azx_free(chip); 1434 return err; 1435 } 1436 1437 /* continue probing in work context as may trigger request module */ 1438 INIT_WORK(&hda->probe_work, azx_probe_work); 1439 1440 *rchip = chip; 1441 1442 return 0; 1443 } 1444 1445 static int azx_first_init(struct azx *chip) 1446 { 1447 int dev = chip->dev_index; 1448 struct pci_dev *pci = chip->pci; 1449 struct snd_card *card = chip->card; 1450 int err; 1451 unsigned short gcap; 1452 unsigned int dma_bits = 64; 1453 1454 #if BITS_PER_LONG != 64 1455 /* Fix up base address on ULI M5461 */ 1456 if (chip->driver_type == AZX_DRIVER_ULI) { 1457 u16 tmp3; 1458 pci_read_config_word(pci, 0x40, &tmp3); 1459 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1460 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1461 } 1462 #endif 1463 1464 err = pci_request_regions(pci, "ICH HD audio"); 1465 if (err < 0) 1466 return err; 1467 chip->region_requested = 1; 1468 1469 chip->addr = pci_resource_start(pci, 0); 1470 chip->remap_addr = pci_ioremap_bar(pci, 0); 1471 if (chip->remap_addr == NULL) { 1472 dev_err(card->dev, "ioremap error\n"); 1473 return -ENXIO; 1474 } 1475 1476 if (chip->msi) { 1477 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1478 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1479 pci->no_64bit_msi = true; 1480 } 1481 if (pci_enable_msi(pci) < 0) 1482 chip->msi = 0; 1483 } 1484 1485 if (azx_acquire_irq(chip, 0) < 0) 1486 return -EBUSY; 1487 1488 pci_set_master(pci); 1489 synchronize_irq(chip->irq); 1490 1491 gcap = azx_readw(chip, GCAP); 1492 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1493 1494 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1495 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1496 dma_bits = 40; 1497 1498 /* disable SB600 64bit support for safety */ 1499 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1500 struct pci_dev *p_smbus; 1501 dma_bits = 40; 1502 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1503 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1504 NULL); 1505 if (p_smbus) { 1506 if (p_smbus->revision < 0x30) 1507 gcap &= ~AZX_GCAP_64OK; 1508 pci_dev_put(p_smbus); 1509 } 1510 } 1511 1512 /* disable 64bit DMA address on some devices */ 1513 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1514 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1515 gcap &= ~AZX_GCAP_64OK; 1516 } 1517 1518 /* disable buffer size rounding to 128-byte multiples if supported */ 1519 if (align_buffer_size >= 0) 1520 chip->align_buffer_size = !!align_buffer_size; 1521 else { 1522 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1523 chip->align_buffer_size = 0; 1524 else 1525 chip->align_buffer_size = 1; 1526 } 1527 1528 /* allow 64bit DMA address if supported by H/W */ 1529 if (!(gcap & AZX_GCAP_64OK)) 1530 dma_bits = 32; 1531 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) { 1532 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits)); 1533 } else { 1534 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 1535 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 1536 } 1537 1538 /* read number of streams from GCAP register instead of using 1539 * hardcoded value 1540 */ 1541 chip->capture_streams = (gcap >> 8) & 0x0f; 1542 chip->playback_streams = (gcap >> 12) & 0x0f; 1543 if (!chip->playback_streams && !chip->capture_streams) { 1544 /* gcap didn't give any info, switching to old method */ 1545 1546 switch (chip->driver_type) { 1547 case AZX_DRIVER_ULI: 1548 chip->playback_streams = ULI_NUM_PLAYBACK; 1549 chip->capture_streams = ULI_NUM_CAPTURE; 1550 break; 1551 case AZX_DRIVER_ATIHDMI: 1552 case AZX_DRIVER_ATIHDMI_NS: 1553 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1554 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1555 break; 1556 case AZX_DRIVER_GENERIC: 1557 default: 1558 chip->playback_streams = ICH6_NUM_PLAYBACK; 1559 chip->capture_streams = ICH6_NUM_CAPTURE; 1560 break; 1561 } 1562 } 1563 chip->capture_index_offset = 0; 1564 chip->playback_index_offset = chip->capture_streams; 1565 chip->num_streams = chip->playback_streams + chip->capture_streams; 1566 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 1567 GFP_KERNEL); 1568 if (!chip->azx_dev) 1569 return -ENOMEM; 1570 1571 err = azx_alloc_stream_pages(chip); 1572 if (err < 0) 1573 return err; 1574 1575 /* initialize streams */ 1576 azx_init_stream(chip); 1577 1578 /* initialize chip */ 1579 azx_init_pci(chip); 1580 1581 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1582 struct hda_intel *hda; 1583 1584 hda = container_of(chip, struct hda_intel, chip); 1585 haswell_set_bclk(hda); 1586 } 1587 1588 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 1589 1590 /* codec detection */ 1591 if (!chip->codec_mask) { 1592 dev_err(card->dev, "no codecs found!\n"); 1593 return -ENODEV; 1594 } 1595 1596 strcpy(card->driver, "HDA-Intel"); 1597 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1598 sizeof(card->shortname)); 1599 snprintf(card->longname, sizeof(card->longname), 1600 "%s at 0x%lx irq %i", 1601 card->shortname, chip->addr, chip->irq); 1602 1603 return 0; 1604 } 1605 1606 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1607 /* callback from request_firmware_nowait() */ 1608 static void azx_firmware_cb(const struct firmware *fw, void *context) 1609 { 1610 struct snd_card *card = context; 1611 struct azx *chip = card->private_data; 1612 struct pci_dev *pci = chip->pci; 1613 1614 if (!fw) { 1615 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1616 goto error; 1617 } 1618 1619 chip->fw = fw; 1620 if (!chip->disabled) { 1621 /* continue probing */ 1622 if (azx_probe_continue(chip)) 1623 goto error; 1624 } 1625 return; /* OK */ 1626 1627 error: 1628 snd_card_free(card); 1629 pci_set_drvdata(pci, NULL); 1630 } 1631 #endif 1632 1633 /* 1634 * HDA controller ops. 1635 */ 1636 1637 /* PCI register access. */ 1638 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1639 { 1640 writel(value, addr); 1641 } 1642 1643 static u32 pci_azx_readl(u32 __iomem *addr) 1644 { 1645 return readl(addr); 1646 } 1647 1648 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1649 { 1650 writew(value, addr); 1651 } 1652 1653 static u16 pci_azx_readw(u16 __iomem *addr) 1654 { 1655 return readw(addr); 1656 } 1657 1658 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1659 { 1660 writeb(value, addr); 1661 } 1662 1663 static u8 pci_azx_readb(u8 __iomem *addr) 1664 { 1665 return readb(addr); 1666 } 1667 1668 static int disable_msi_reset_irq(struct azx *chip) 1669 { 1670 int err; 1671 1672 free_irq(chip->irq, chip); 1673 chip->irq = -1; 1674 pci_disable_msi(chip->pci); 1675 chip->msi = 0; 1676 err = azx_acquire_irq(chip, 1); 1677 if (err < 0) 1678 return err; 1679 1680 return 0; 1681 } 1682 1683 /* DMA page allocation helpers. */ 1684 static int dma_alloc_pages(struct azx *chip, 1685 int type, 1686 size_t size, 1687 struct snd_dma_buffer *buf) 1688 { 1689 int err; 1690 1691 err = snd_dma_alloc_pages(type, 1692 chip->card->dev, 1693 size, buf); 1694 if (err < 0) 1695 return err; 1696 mark_pages_wc(chip, buf, true); 1697 return 0; 1698 } 1699 1700 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) 1701 { 1702 mark_pages_wc(chip, buf, false); 1703 snd_dma_free_pages(buf); 1704 } 1705 1706 static int substream_alloc_pages(struct azx *chip, 1707 struct snd_pcm_substream *substream, 1708 size_t size) 1709 { 1710 struct azx_dev *azx_dev = get_azx_dev(substream); 1711 int ret; 1712 1713 mark_runtime_wc(chip, azx_dev, substream, false); 1714 azx_dev->bufsize = 0; 1715 azx_dev->period_bytes = 0; 1716 azx_dev->format_val = 0; 1717 ret = snd_pcm_lib_malloc_pages(substream, size); 1718 if (ret < 0) 1719 return ret; 1720 mark_runtime_wc(chip, azx_dev, substream, true); 1721 return 0; 1722 } 1723 1724 static int substream_free_pages(struct azx *chip, 1725 struct snd_pcm_substream *substream) 1726 { 1727 struct azx_dev *azx_dev = get_azx_dev(substream); 1728 mark_runtime_wc(chip, azx_dev, substream, false); 1729 return snd_pcm_lib_free_pages(substream); 1730 } 1731 1732 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1733 struct vm_area_struct *area) 1734 { 1735 #ifdef CONFIG_X86 1736 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1737 struct azx *chip = apcm->chip; 1738 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1739 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1740 #endif 1741 } 1742 1743 static const struct hda_controller_ops pci_hda_ops = { 1744 .reg_writel = pci_azx_writel, 1745 .reg_readl = pci_azx_readl, 1746 .reg_writew = pci_azx_writew, 1747 .reg_readw = pci_azx_readw, 1748 .reg_writeb = pci_azx_writeb, 1749 .reg_readb = pci_azx_readb, 1750 .disable_msi_reset_irq = disable_msi_reset_irq, 1751 .dma_alloc_pages = dma_alloc_pages, 1752 .dma_free_pages = dma_free_pages, 1753 .substream_alloc_pages = substream_alloc_pages, 1754 .substream_free_pages = substream_free_pages, 1755 .pcm_mmap_prepare = pcm_mmap_prepare, 1756 .position_check = azx_position_check, 1757 }; 1758 1759 static int azx_probe(struct pci_dev *pci, 1760 const struct pci_device_id *pci_id) 1761 { 1762 static int dev; 1763 struct snd_card *card; 1764 struct hda_intel *hda; 1765 struct azx *chip; 1766 bool schedule_probe; 1767 int err; 1768 1769 if (dev >= SNDRV_CARDS) 1770 return -ENODEV; 1771 if (!enable[dev]) { 1772 dev++; 1773 return -ENOENT; 1774 } 1775 1776 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1777 0, &card); 1778 if (err < 0) { 1779 dev_err(&pci->dev, "Error creating card!\n"); 1780 return err; 1781 } 1782 1783 err = azx_create(card, pci, dev, pci_id->driver_data, 1784 &pci_hda_ops, &chip); 1785 if (err < 0) 1786 goto out_free; 1787 card->private_data = chip; 1788 hda = container_of(chip, struct hda_intel, chip); 1789 1790 pci_set_drvdata(pci, card); 1791 1792 err = register_vga_switcheroo(chip); 1793 if (err < 0) { 1794 dev_err(card->dev, "Error registering VGA-switcheroo client\n"); 1795 goto out_free; 1796 } 1797 1798 if (check_hdmi_disabled(pci)) { 1799 dev_info(card->dev, "VGA controller is disabled\n"); 1800 dev_info(card->dev, "Delaying initialization\n"); 1801 chip->disabled = true; 1802 } 1803 1804 schedule_probe = !chip->disabled; 1805 1806 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1807 if (patch[dev] && *patch[dev]) { 1808 dev_info(card->dev, "Applying patch firmware '%s'\n", 1809 patch[dev]); 1810 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1811 &pci->dev, GFP_KERNEL, card, 1812 azx_firmware_cb); 1813 if (err < 0) 1814 goto out_free; 1815 schedule_probe = false; /* continued in azx_firmware_cb() */ 1816 } 1817 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1818 1819 #ifndef CONFIG_SND_HDA_I915 1820 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1821 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); 1822 #endif 1823 1824 if (schedule_probe) 1825 schedule_work(&hda->probe_work); 1826 1827 dev++; 1828 if (chip->disabled) 1829 complete_all(&hda->probe_wait); 1830 return 0; 1831 1832 out_free: 1833 snd_card_free(card); 1834 return err; 1835 } 1836 1837 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1838 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1839 [AZX_DRIVER_NVIDIA] = 8, 1840 [AZX_DRIVER_TERA] = 1, 1841 }; 1842 1843 static int azx_probe_continue(struct azx *chip) 1844 { 1845 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1846 struct pci_dev *pci = chip->pci; 1847 int dev = chip->dev_index; 1848 int err; 1849 1850 /* Request power well for Haswell HDA controller and codec */ 1851 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1852 #ifdef CONFIG_SND_HDA_I915 1853 err = hda_i915_init(hda); 1854 if (err < 0) 1855 goto out_free; 1856 err = hda_display_power(hda, true); 1857 if (err < 0) { 1858 dev_err(chip->card->dev, 1859 "Cannot turn on display power on i915\n"); 1860 goto out_free; 1861 } 1862 #endif 1863 } 1864 1865 err = azx_first_init(chip); 1866 if (err < 0) 1867 goto out_free; 1868 1869 #ifdef CONFIG_SND_HDA_INPUT_BEEP 1870 chip->beep_mode = beep_mode[dev]; 1871 #endif 1872 1873 /* create codec instances */ 1874 err = azx_bus_create(chip, model[dev]); 1875 if (err < 0) 1876 goto out_free; 1877 1878 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 1879 if (err < 0) 1880 goto out_free; 1881 1882 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1883 if (chip->fw) { 1884 err = snd_hda_load_patch(chip->bus, chip->fw->size, 1885 chip->fw->data); 1886 if (err < 0) 1887 goto out_free; 1888 #ifndef CONFIG_PM 1889 release_firmware(chip->fw); /* no longer needed */ 1890 chip->fw = NULL; 1891 #endif 1892 } 1893 #endif 1894 if ((probe_only[dev] & 1) == 0) { 1895 err = azx_codec_configure(chip); 1896 if (err < 0) 1897 goto out_free; 1898 } 1899 1900 err = snd_card_register(chip->card); 1901 if (err < 0) 1902 goto out_free; 1903 1904 chip->running = 1; 1905 azx_add_card_list(chip); 1906 snd_hda_set_power_save(chip->bus, power_save * 1000); 1907 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 1908 pm_runtime_put_noidle(&pci->dev); 1909 1910 out_free: 1911 if (err < 0) 1912 hda->init_failed = 1; 1913 complete_all(&hda->probe_wait); 1914 return err; 1915 } 1916 1917 static void azx_remove(struct pci_dev *pci) 1918 { 1919 struct snd_card *card = pci_get_drvdata(pci); 1920 1921 if (card) 1922 snd_card_free(card); 1923 } 1924 1925 static void azx_shutdown(struct pci_dev *pci) 1926 { 1927 struct snd_card *card = pci_get_drvdata(pci); 1928 struct azx *chip; 1929 1930 if (!card) 1931 return; 1932 chip = card->private_data; 1933 if (chip && chip->running) 1934 azx_stop_chip(chip); 1935 } 1936 1937 /* PCI IDs */ 1938 static const struct pci_device_id azx_ids[] = { 1939 /* CPT */ 1940 { PCI_DEVICE(0x8086, 0x1c20), 1941 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1942 /* PBG */ 1943 { PCI_DEVICE(0x8086, 0x1d20), 1944 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1945 /* Panther Point */ 1946 { PCI_DEVICE(0x8086, 0x1e20), 1947 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1948 /* Lynx Point */ 1949 { PCI_DEVICE(0x8086, 0x8c20), 1950 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1951 /* 9 Series */ 1952 { PCI_DEVICE(0x8086, 0x8ca0), 1953 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1954 /* Wellsburg */ 1955 { PCI_DEVICE(0x8086, 0x8d20), 1956 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1957 { PCI_DEVICE(0x8086, 0x8d21), 1958 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1959 /* Lynx Point-LP */ 1960 { PCI_DEVICE(0x8086, 0x9c20), 1961 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1962 /* Lynx Point-LP */ 1963 { PCI_DEVICE(0x8086, 0x9c21), 1964 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1965 /* Wildcat Point-LP */ 1966 { PCI_DEVICE(0x8086, 0x9ca0), 1967 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1968 /* Sunrise Point */ 1969 { PCI_DEVICE(0x8086, 0xa170), 1970 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 1971 /* Sunrise Point-LP */ 1972 { PCI_DEVICE(0x8086, 0x9d70), 1973 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 1974 /* Haswell */ 1975 { PCI_DEVICE(0x8086, 0x0a0c), 1976 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 1977 { PCI_DEVICE(0x8086, 0x0c0c), 1978 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 1979 { PCI_DEVICE(0x8086, 0x0d0c), 1980 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 1981 /* Broadwell */ 1982 { PCI_DEVICE(0x8086, 0x160c), 1983 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 1984 /* 5 Series/3400 */ 1985 { PCI_DEVICE(0x8086, 0x3b56), 1986 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1987 /* Poulsbo */ 1988 { PCI_DEVICE(0x8086, 0x811b), 1989 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1990 /* Oaktrail */ 1991 { PCI_DEVICE(0x8086, 0x080a), 1992 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1993 /* BayTrail */ 1994 { PCI_DEVICE(0x8086, 0x0f04), 1995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1996 /* Braswell */ 1997 { PCI_DEVICE(0x8086, 0x2284), 1998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 1999 /* ICH6 */ 2000 { PCI_DEVICE(0x8086, 0x2668), 2001 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2002 /* ICH7 */ 2003 { PCI_DEVICE(0x8086, 0x27d8), 2004 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2005 /* ESB2 */ 2006 { PCI_DEVICE(0x8086, 0x269a), 2007 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2008 /* ICH8 */ 2009 { PCI_DEVICE(0x8086, 0x284b), 2010 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2011 /* ICH9 */ 2012 { PCI_DEVICE(0x8086, 0x293e), 2013 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2014 /* ICH9 */ 2015 { PCI_DEVICE(0x8086, 0x293f), 2016 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2017 /* ICH10 */ 2018 { PCI_DEVICE(0x8086, 0x3a3e), 2019 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2020 /* ICH10 */ 2021 { PCI_DEVICE(0x8086, 0x3a6e), 2022 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2023 /* Generic Intel */ 2024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2025 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2026 .class_mask = 0xffffff, 2027 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2028 /* ATI SB 450/600/700/800/900 */ 2029 { PCI_DEVICE(0x1002, 0x437b), 2030 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2031 { PCI_DEVICE(0x1002, 0x4383), 2032 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2033 /* AMD Hudson */ 2034 { PCI_DEVICE(0x1022, 0x780d), 2035 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2036 /* ATI HDMI */ 2037 { PCI_DEVICE(0x1002, 0x793b), 2038 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2039 { PCI_DEVICE(0x1002, 0x7919), 2040 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2041 { PCI_DEVICE(0x1002, 0x960f), 2042 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2043 { PCI_DEVICE(0x1002, 0x970f), 2044 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2045 { PCI_DEVICE(0x1002, 0xaa00), 2046 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2047 { PCI_DEVICE(0x1002, 0xaa08), 2048 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2049 { PCI_DEVICE(0x1002, 0xaa10), 2050 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2051 { PCI_DEVICE(0x1002, 0xaa18), 2052 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2053 { PCI_DEVICE(0x1002, 0xaa20), 2054 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2055 { PCI_DEVICE(0x1002, 0xaa28), 2056 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2057 { PCI_DEVICE(0x1002, 0xaa30), 2058 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2059 { PCI_DEVICE(0x1002, 0xaa38), 2060 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2061 { PCI_DEVICE(0x1002, 0xaa40), 2062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2063 { PCI_DEVICE(0x1002, 0xaa48), 2064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2065 { PCI_DEVICE(0x1002, 0xaa50), 2066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2067 { PCI_DEVICE(0x1002, 0xaa58), 2068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2069 { PCI_DEVICE(0x1002, 0xaa60), 2070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2071 { PCI_DEVICE(0x1002, 0xaa68), 2072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2073 { PCI_DEVICE(0x1002, 0xaa80), 2074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2075 { PCI_DEVICE(0x1002, 0xaa88), 2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2077 { PCI_DEVICE(0x1002, 0xaa90), 2078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2079 { PCI_DEVICE(0x1002, 0xaa98), 2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2081 { PCI_DEVICE(0x1002, 0x9902), 2082 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2083 { PCI_DEVICE(0x1002, 0xaaa0), 2084 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2085 { PCI_DEVICE(0x1002, 0xaaa8), 2086 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2087 { PCI_DEVICE(0x1002, 0xaab0), 2088 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2089 /* VIA VT8251/VT8237A */ 2090 { PCI_DEVICE(0x1106, 0x3288), 2091 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 2092 /* VIA GFX VT7122/VX900 */ 2093 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2094 /* VIA GFX VT6122/VX11 */ 2095 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2096 /* SIS966 */ 2097 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2098 /* ULI M5461 */ 2099 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2100 /* NVIDIA MCP */ 2101 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2102 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2103 .class_mask = 0xffffff, 2104 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2105 /* Teradici */ 2106 { PCI_DEVICE(0x6549, 0x1200), 2107 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2108 { PCI_DEVICE(0x6549, 0x2200), 2109 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2110 /* Creative X-Fi (CA0110-IBG) */ 2111 /* CTHDA chips */ 2112 { PCI_DEVICE(0x1102, 0x0010), 2113 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2114 { PCI_DEVICE(0x1102, 0x0012), 2115 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2116 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2117 /* the following entry conflicts with snd-ctxfi driver, 2118 * as ctxfi driver mutates from HD-audio to native mode with 2119 * a special command sequence. 2120 */ 2121 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2122 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2123 .class_mask = 0xffffff, 2124 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2125 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2126 #else 2127 /* this entry seems still valid -- i.e. without emu20kx chip */ 2128 { PCI_DEVICE(0x1102, 0x0009), 2129 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2130 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2131 #endif 2132 /* CM8888 */ 2133 { PCI_DEVICE(0x13f6, 0x5011), 2134 .driver_data = AZX_DRIVER_CMEDIA | 2135 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2136 /* Vortex86MX */ 2137 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2138 /* VMware HDAudio */ 2139 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2140 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2141 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2142 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2143 .class_mask = 0xffffff, 2144 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2145 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2146 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2147 .class_mask = 0xffffff, 2148 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2149 { 0, } 2150 }; 2151 MODULE_DEVICE_TABLE(pci, azx_ids); 2152 2153 /* pci_driver definition */ 2154 static struct pci_driver azx_driver = { 2155 .name = KBUILD_MODNAME, 2156 .id_table = azx_ids, 2157 .probe = azx_probe, 2158 .remove = azx_remove, 2159 .shutdown = azx_shutdown, 2160 .driver = { 2161 .pm = AZX_PM_OPS, 2162 }, 2163 }; 2164 2165 module_pci_driver(azx_driver); 2166