1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/apple-gmux.h> 54 #include <linux/firmware.h> 55 #include <sound/hda_codec.h> 56 #include "hda_controller.h" 57 #include "hda_intel.h" 58 59 #define CREATE_TRACE_POINTS 60 #include "hda_intel_trace.h" 61 62 /* position fix mode */ 63 enum { 64 POS_FIX_AUTO, 65 POS_FIX_LPIB, 66 POS_FIX_POSBUF, 67 POS_FIX_VIACOMBO, 68 POS_FIX_COMBO, 69 POS_FIX_SKL, 70 POS_FIX_FIFO, 71 }; 72 73 /* Defines for ATI HD Audio support in SB450 south bridge */ 74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 76 77 /* Defines for Nvidia HDA support */ 78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 80 #define NVIDIA_HDA_ISTRM_COH 0x4d 81 #define NVIDIA_HDA_OSTRM_COH 0x4c 82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 83 84 /* Defines for Intel SCH HDA snoop control */ 85 #define INTEL_HDA_CGCTL 0x48 86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 87 #define INTEL_SCH_HDA_DEVC 0x78 88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 89 90 /* max number of SDs */ 91 /* ICH, ATI and VIA have 4 playback and 4 capture */ 92 #define ICH6_NUM_CAPTURE 4 93 #define ICH6_NUM_PLAYBACK 4 94 95 /* ULI has 6 playback and 5 capture */ 96 #define ULI_NUM_CAPTURE 5 97 #define ULI_NUM_PLAYBACK 6 98 99 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 100 #define ATIHDMI_NUM_CAPTURE 0 101 #define ATIHDMI_NUM_PLAYBACK 8 102 103 104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 107 static char *model[SNDRV_CARDS]; 108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int probe_only[SNDRV_CARDS]; 112 static int jackpoll_ms[SNDRV_CARDS]; 113 static int single_cmd = -1; 114 static int enable_msi = -1; 115 #ifdef CONFIG_SND_HDA_PATCH_LOADER 116 static char *patch[SNDRV_CARDS]; 117 #endif 118 #ifdef CONFIG_SND_HDA_INPUT_BEEP 119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 120 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 121 #endif 122 static bool dmic_detect = 1; 123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 124 125 module_param_array(index, int, NULL, 0444); 126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 127 module_param_array(id, charp, NULL, 0444); 128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 129 module_param_array(enable, bool, NULL, 0444); 130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 131 module_param_array(model, charp, NULL, 0444); 132 MODULE_PARM_DESC(model, "Use the given board model."); 133 module_param_array(position_fix, int, NULL, 0444); 134 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 136 module_param_array(bdl_pos_adj, int, NULL, 0644); 137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 138 module_param_array(probe_mask, int, NULL, 0444); 139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 140 module_param_array(probe_only, int, NULL, 0444); 141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 142 module_param_array(jackpoll_ms, int, NULL, 0444); 143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 144 module_param(single_cmd, bint, 0444); 145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 146 "(for debugging only)."); 147 module_param(enable_msi, bint, 0444); 148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 149 #ifdef CONFIG_SND_HDA_PATCH_LOADER 150 module_param_array(patch, charp, NULL, 0444); 151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 152 #endif 153 #ifdef CONFIG_SND_HDA_INPUT_BEEP 154 module_param_array(beep_mode, bool, NULL, 0444); 155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 156 "(0=off, 1=on) (default=1)."); 157 #endif 158 module_param(dmic_detect, bool, 0444); 159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 160 "(0=off, 1=on) (default=1); " 161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 162 module_param(ctl_dev_id, bool, 0444); 163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 164 165 #ifdef CONFIG_PM 166 static int param_set_xint(const char *val, const struct kernel_param *kp); 167 static const struct kernel_param_ops param_ops_xint = { 168 .set = param_set_xint, 169 .get = param_get_int, 170 }; 171 #define param_check_xint param_check_int 172 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 174 module_param(power_save, xint, 0644); 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 176 "(in second, 0 = disable)."); 177 178 static bool pm_blacklist = true; 179 module_param(pm_blacklist, bool, 0644); 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 181 182 /* reset the HD-audio controller in power save mode. 183 * this may give more power-saving, but will take longer time to 184 * wake up. 185 */ 186 static bool power_save_controller = 1; 187 module_param(power_save_controller, bool, 0644); 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 189 #else 190 #define power_save 0 191 #endif /* CONFIG_PM */ 192 193 static int align_buffer_size = -1; 194 module_param(align_buffer_size, bint, 0644); 195 MODULE_PARM_DESC(align_buffer_size, 196 "Force buffer and period sizes to be multiple of 128 bytes."); 197 198 #ifdef CONFIG_X86 199 static int hda_snoop = -1; 200 module_param_named(snoop, hda_snoop, bint, 0444); 201 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 202 #else 203 #define hda_snoop true 204 #endif 205 206 207 MODULE_LICENSE("GPL"); 208 MODULE_DESCRIPTION("Intel HDA driver"); 209 210 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 211 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 212 #define SUPPORT_VGA_SWITCHEROO 213 #endif 214 #endif 215 216 217 /* 218 */ 219 220 /* driver types */ 221 enum { 222 AZX_DRIVER_ICH, 223 AZX_DRIVER_PCH, 224 AZX_DRIVER_SCH, 225 AZX_DRIVER_SKL, 226 AZX_DRIVER_HDMI, 227 AZX_DRIVER_ATI, 228 AZX_DRIVER_ATIHDMI, 229 AZX_DRIVER_ATIHDMI_NS, 230 AZX_DRIVER_GFHDMI, 231 AZX_DRIVER_VIA, 232 AZX_DRIVER_SIS, 233 AZX_DRIVER_ULI, 234 AZX_DRIVER_NVIDIA, 235 AZX_DRIVER_TERA, 236 AZX_DRIVER_CTX, 237 AZX_DRIVER_CTHDA, 238 AZX_DRIVER_CMEDIA, 239 AZX_DRIVER_ZHAOXIN, 240 AZX_DRIVER_GENERIC, 241 AZX_NUM_DRIVERS, /* keep this as last entry */ 242 }; 243 244 #define azx_get_snoop_type(chip) \ 245 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 246 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 247 248 /* quirks for old Intel chipsets */ 249 #define AZX_DCAPS_INTEL_ICH \ 250 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 251 252 /* quirks for Intel PCH */ 253 #define AZX_DCAPS_INTEL_PCH_BASE \ 254 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 255 AZX_DCAPS_SNOOP_TYPE(SCH)) 256 257 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 258 #define AZX_DCAPS_INTEL_PCH_NOPM \ 259 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 260 261 /* PCH for HSW/BDW; with runtime PM */ 262 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 263 #define AZX_DCAPS_INTEL_PCH \ 264 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 265 266 /* HSW HDMI */ 267 #define AZX_DCAPS_INTEL_HASWELL \ 268 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 269 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 270 AZX_DCAPS_SNOOP_TYPE(SCH)) 271 272 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 273 #define AZX_DCAPS_INTEL_BROADWELL \ 274 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 275 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 276 AZX_DCAPS_SNOOP_TYPE(SCH)) 277 278 #define AZX_DCAPS_INTEL_BAYTRAIL \ 279 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 280 281 #define AZX_DCAPS_INTEL_BRASWELL \ 282 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 283 AZX_DCAPS_I915_COMPONENT) 284 285 #define AZX_DCAPS_INTEL_SKYLAKE \ 286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 287 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 288 289 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 290 291 /* quirks for ATI SB / AMD Hudson */ 292 #define AZX_DCAPS_PRESET_ATI_SB \ 293 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 294 AZX_DCAPS_SNOOP_TYPE(ATI)) 295 296 /* quirks for ATI/AMD HDMI */ 297 #define AZX_DCAPS_PRESET_ATI_HDMI \ 298 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 299 AZX_DCAPS_NO_MSI64) 300 301 /* quirks for ATI HDMI with snoop off */ 302 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 303 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 304 305 /* quirks for AMD SB */ 306 #define AZX_DCAPS_PRESET_AMD_SB \ 307 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 308 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 309 AZX_DCAPS_RETRY_PROBE) 310 311 /* quirks for Nvidia */ 312 #define AZX_DCAPS_PRESET_NVIDIA \ 313 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 314 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 315 316 #define AZX_DCAPS_PRESET_CTHDA \ 317 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 318 AZX_DCAPS_NO_64BIT |\ 319 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 320 321 /* 322 * vga_switcheroo support 323 */ 324 #ifdef SUPPORT_VGA_SWITCHEROO 325 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 326 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 327 #else 328 #define use_vga_switcheroo(chip) 0 329 #define needs_eld_notify_link(chip) false 330 #endif 331 332 #define CONTROLLER_IN_GPU(pci) (((pci)->vendor == 0x8086) && \ 333 (((pci)->device == 0x0a0c) || \ 334 ((pci)->device == 0x0c0c) || \ 335 ((pci)->device == 0x0d0c) || \ 336 ((pci)->device == 0x160c) || \ 337 ((pci)->device == 0x490d) || \ 338 ((pci)->device == 0x4f90) || \ 339 ((pci)->device == 0x4f91) || \ 340 ((pci)->device == 0x4f92))) 341 342 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 343 344 static const char * const driver_short_names[] = { 345 [AZX_DRIVER_ICH] = "HDA Intel", 346 [AZX_DRIVER_PCH] = "HDA Intel PCH", 347 [AZX_DRIVER_SCH] = "HDA Intel MID", 348 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 349 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 350 [AZX_DRIVER_ATI] = "HDA ATI SB", 351 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 352 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 353 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 354 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 355 [AZX_DRIVER_SIS] = "HDA SIS966", 356 [AZX_DRIVER_ULI] = "HDA ULI M5461", 357 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 358 [AZX_DRIVER_TERA] = "HDA Teradici", 359 [AZX_DRIVER_CTX] = "HDA Creative", 360 [AZX_DRIVER_CTHDA] = "HDA Creative", 361 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 362 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 363 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 364 }; 365 366 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 367 static void set_default_power_save(struct azx *chip); 368 369 /* 370 * initialize the PCI registers 371 */ 372 /* update bits in a PCI register byte */ 373 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 374 unsigned char mask, unsigned char val) 375 { 376 unsigned char data; 377 378 pci_read_config_byte(pci, reg, &data); 379 data &= ~mask; 380 data |= (val & mask); 381 pci_write_config_byte(pci, reg, data); 382 } 383 384 static void azx_init_pci(struct azx *chip) 385 { 386 int snoop_type = azx_get_snoop_type(chip); 387 388 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 389 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 390 * Ensuring these bits are 0 clears playback static on some HD Audio 391 * codecs. 392 * The PCI register TCSEL is defined in the Intel manuals. 393 */ 394 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 395 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 396 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 397 } 398 399 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 400 * we need to enable snoop. 401 */ 402 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 403 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 404 azx_snoop(chip)); 405 update_pci_byte(chip->pci, 406 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 407 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 408 } 409 410 /* For NVIDIA HDA, enable snoop */ 411 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 412 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 413 azx_snoop(chip)); 414 update_pci_byte(chip->pci, 415 NVIDIA_HDA_TRANSREG_ADDR, 416 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 417 update_pci_byte(chip->pci, 418 NVIDIA_HDA_ISTRM_COH, 419 0x01, NVIDIA_HDA_ENABLE_COHBIT); 420 update_pci_byte(chip->pci, 421 NVIDIA_HDA_OSTRM_COH, 422 0x01, NVIDIA_HDA_ENABLE_COHBIT); 423 } 424 425 /* Enable SCH/PCH snoop if needed */ 426 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 427 unsigned short snoop; 428 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 429 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 430 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 431 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 432 if (!azx_snoop(chip)) 433 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 434 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 435 pci_read_config_word(chip->pci, 436 INTEL_SCH_HDA_DEVC, &snoop); 437 } 438 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 439 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 440 "Disabled" : "Enabled"); 441 } 442 } 443 444 /* 445 * In BXT-P A0, HD-Audio DMA requests is later than expected, 446 * and makes an audio stream sensitive to system latencies when 447 * 24/32 bits are playing. 448 * Adjusting threshold of DMA fifo to force the DMA request 449 * sooner to improve latency tolerance at the expense of power. 450 */ 451 static void bxt_reduce_dma_latency(struct azx *chip) 452 { 453 u32 val; 454 455 val = azx_readl(chip, VS_EM4L); 456 val &= (0x3 << 20); 457 azx_writel(chip, VS_EM4L, val); 458 } 459 460 /* 461 * ML_LCAP bits: 462 * bit 0: 6 MHz Supported 463 * bit 1: 12 MHz Supported 464 * bit 2: 24 MHz Supported 465 * bit 3: 48 MHz Supported 466 * bit 4: 96 MHz Supported 467 * bit 5: 192 MHz Supported 468 */ 469 static int intel_get_lctl_scf(struct azx *chip) 470 { 471 struct hdac_bus *bus = azx_bus(chip); 472 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 473 u32 val, t; 474 int i; 475 476 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 477 478 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 479 t = preferred_bits[i]; 480 if (val & (1 << t)) 481 return t; 482 } 483 484 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 485 return 0; 486 } 487 488 static int intel_ml_lctl_set_power(struct azx *chip, int state) 489 { 490 struct hdac_bus *bus = azx_bus(chip); 491 u32 val; 492 int timeout; 493 494 /* 495 * Changes to LCTL.SCF are only needed for the first multi-link dealing 496 * with external codecs 497 */ 498 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 499 val &= ~AZX_ML_LCTL_SPA; 500 val |= state << AZX_ML_LCTL_SPA_SHIFT; 501 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 502 /* wait for CPA */ 503 timeout = 50; 504 while (timeout) { 505 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 506 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 507 return 0; 508 timeout--; 509 udelay(10); 510 } 511 512 return -1; 513 } 514 515 static void intel_init_lctl(struct azx *chip) 516 { 517 struct hdac_bus *bus = azx_bus(chip); 518 u32 val; 519 int ret; 520 521 /* 0. check lctl register value is correct or not */ 522 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 523 /* only perform additional configurations if the SCF is initially based on 6MHz */ 524 if ((val & AZX_ML_LCTL_SCF) != 0) 525 return; 526 527 /* 528 * Before operating on SPA, CPA must match SPA. 529 * Any deviation may result in undefined behavior. 530 */ 531 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 532 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 533 return; 534 535 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 536 ret = intel_ml_lctl_set_power(chip, 0); 537 udelay(100); 538 if (ret) 539 goto set_spa; 540 541 /* 2. update SCF to select an audio clock different from 6MHz */ 542 val &= ~AZX_ML_LCTL_SCF; 543 val |= intel_get_lctl_scf(chip); 544 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 545 546 set_spa: 547 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 548 intel_ml_lctl_set_power(chip, 1); 549 udelay(100); 550 } 551 552 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 553 { 554 struct hdac_bus *bus = azx_bus(chip); 555 struct pci_dev *pci = chip->pci; 556 u32 val; 557 558 snd_hdac_set_codec_wakeup(bus, true); 559 if (chip->driver_type == AZX_DRIVER_SKL) { 560 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 561 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 562 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 563 } 564 azx_init_chip(chip, full_reset); 565 if (chip->driver_type == AZX_DRIVER_SKL) { 566 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 567 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 568 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 569 } 570 571 snd_hdac_set_codec_wakeup(bus, false); 572 573 /* reduce dma latency to avoid noise */ 574 if (IS_BXT(pci)) 575 bxt_reduce_dma_latency(chip); 576 577 if (bus->mlcap != NULL) 578 intel_init_lctl(chip); 579 } 580 581 /* calculate runtime delay from LPIB */ 582 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 583 unsigned int pos) 584 { 585 struct snd_pcm_substream *substream = azx_dev->core.substream; 586 int stream = substream->stream; 587 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 588 int delay; 589 590 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 591 delay = pos - lpib_pos; 592 else 593 delay = lpib_pos - pos; 594 if (delay < 0) { 595 if (delay >= azx_dev->core.delay_negative_threshold) 596 delay = 0; 597 else 598 delay += azx_dev->core.bufsize; 599 } 600 601 if (delay >= azx_dev->core.period_bytes) { 602 dev_info(chip->card->dev, 603 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 604 delay, azx_dev->core.period_bytes); 605 delay = 0; 606 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 607 chip->get_delay[stream] = NULL; 608 } 609 610 return bytes_to_frames(substream->runtime, delay); 611 } 612 613 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 614 615 /* called from IRQ */ 616 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 617 { 618 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 619 int ok; 620 621 ok = azx_position_ok(chip, azx_dev); 622 if (ok == 1) { 623 azx_dev->irq_pending = 0; 624 return ok; 625 } else if (ok == 0) { 626 /* bogus IRQ, process it later */ 627 azx_dev->irq_pending = 1; 628 schedule_work(&hda->irq_pending_work); 629 } 630 return 0; 631 } 632 633 #define display_power(chip, enable) \ 634 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 635 636 /* 637 * Check whether the current DMA position is acceptable for updating 638 * periods. Returns non-zero if it's OK. 639 * 640 * Many HD-audio controllers appear pretty inaccurate about 641 * the update-IRQ timing. The IRQ is issued before actually the 642 * data is processed. So, we need to process it afterwords in a 643 * workqueue. 644 * 645 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 646 */ 647 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 648 { 649 struct snd_pcm_substream *substream = azx_dev->core.substream; 650 struct snd_pcm_runtime *runtime = substream->runtime; 651 int stream = substream->stream; 652 u32 wallclk; 653 unsigned int pos; 654 snd_pcm_uframes_t hwptr, target; 655 656 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 657 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 658 return -1; /* bogus (too early) interrupt */ 659 660 if (chip->get_position[stream]) 661 pos = chip->get_position[stream](chip, azx_dev); 662 else { /* use the position buffer as default */ 663 pos = azx_get_pos_posbuf(chip, azx_dev); 664 if (!pos || pos == (u32)-1) { 665 dev_info(chip->card->dev, 666 "Invalid position buffer, using LPIB read method instead.\n"); 667 chip->get_position[stream] = azx_get_pos_lpib; 668 if (chip->get_position[0] == azx_get_pos_lpib && 669 chip->get_position[1] == azx_get_pos_lpib) 670 azx_bus(chip)->use_posbuf = false; 671 pos = azx_get_pos_lpib(chip, azx_dev); 672 chip->get_delay[stream] = NULL; 673 } else { 674 chip->get_position[stream] = azx_get_pos_posbuf; 675 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 676 chip->get_delay[stream] = azx_get_delay_from_lpib; 677 } 678 } 679 680 if (pos >= azx_dev->core.bufsize) 681 pos = 0; 682 683 if (WARN_ONCE(!azx_dev->core.period_bytes, 684 "hda-intel: zero azx_dev->period_bytes")) 685 return -1; /* this shouldn't happen! */ 686 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 687 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 688 /* NG - it's below the first next period boundary */ 689 return chip->bdl_pos_adj ? 0 : -1; 690 azx_dev->core.start_wallclk += wallclk; 691 692 if (azx_dev->core.no_period_wakeup) 693 return 1; /* OK, no need to check period boundary */ 694 695 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 696 return 1; /* OK, already in hwptr updating process */ 697 698 /* check whether the period gets really elapsed */ 699 pos = bytes_to_frames(runtime, pos); 700 hwptr = runtime->hw_ptr_base + pos; 701 if (hwptr < runtime->status->hw_ptr) 702 hwptr += runtime->buffer_size; 703 target = runtime->hw_ptr_interrupt + runtime->period_size; 704 if (hwptr < target) { 705 /* too early wakeup, process it later */ 706 return chip->bdl_pos_adj ? 0 : -1; 707 } 708 709 return 1; /* OK, it's fine */ 710 } 711 712 /* 713 * The work for pending PCM period updates. 714 */ 715 static void azx_irq_pending_work(struct work_struct *work) 716 { 717 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 718 struct azx *chip = &hda->chip; 719 struct hdac_bus *bus = azx_bus(chip); 720 struct hdac_stream *s; 721 int pending, ok; 722 723 if (!hda->irq_pending_warned) { 724 dev_info(chip->card->dev, 725 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 726 chip->card->number); 727 hda->irq_pending_warned = 1; 728 } 729 730 for (;;) { 731 pending = 0; 732 spin_lock_irq(&bus->reg_lock); 733 list_for_each_entry(s, &bus->stream_list, list) { 734 struct azx_dev *azx_dev = stream_to_azx_dev(s); 735 if (!azx_dev->irq_pending || 736 !s->substream || 737 !s->running) 738 continue; 739 ok = azx_position_ok(chip, azx_dev); 740 if (ok > 0) { 741 azx_dev->irq_pending = 0; 742 spin_unlock(&bus->reg_lock); 743 snd_pcm_period_elapsed(s->substream); 744 spin_lock(&bus->reg_lock); 745 } else if (ok < 0) { 746 pending = 0; /* too early */ 747 } else 748 pending++; 749 } 750 spin_unlock_irq(&bus->reg_lock); 751 if (!pending) 752 return; 753 msleep(1); 754 } 755 } 756 757 /* clear irq_pending flags and assure no on-going workq */ 758 static void azx_clear_irq_pending(struct azx *chip) 759 { 760 struct hdac_bus *bus = azx_bus(chip); 761 struct hdac_stream *s; 762 763 spin_lock_irq(&bus->reg_lock); 764 list_for_each_entry(s, &bus->stream_list, list) { 765 struct azx_dev *azx_dev = stream_to_azx_dev(s); 766 azx_dev->irq_pending = 0; 767 } 768 spin_unlock_irq(&bus->reg_lock); 769 } 770 771 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 772 { 773 struct hdac_bus *bus = azx_bus(chip); 774 775 if (request_irq(chip->pci->irq, azx_interrupt, 776 chip->msi ? 0 : IRQF_SHARED, 777 chip->card->irq_descr, chip)) { 778 dev_err(chip->card->dev, 779 "unable to grab IRQ %d, disabling device\n", 780 chip->pci->irq); 781 if (do_disconnect) 782 snd_card_disconnect(chip->card); 783 return -1; 784 } 785 bus->irq = chip->pci->irq; 786 chip->card->sync_irq = bus->irq; 787 pci_intx(chip->pci, !chip->msi); 788 return 0; 789 } 790 791 /* get the current DMA position with correction on VIA chips */ 792 static unsigned int azx_via_get_position(struct azx *chip, 793 struct azx_dev *azx_dev) 794 { 795 unsigned int link_pos, mini_pos, bound_pos; 796 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 797 unsigned int fifo_size; 798 799 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 800 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 801 /* Playback, no problem using link position */ 802 return link_pos; 803 } 804 805 /* Capture */ 806 /* For new chipset, 807 * use mod to get the DMA position just like old chipset 808 */ 809 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 810 mod_dma_pos %= azx_dev->core.period_bytes; 811 812 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 813 814 if (azx_dev->insufficient) { 815 /* Link position never gather than FIFO size */ 816 if (link_pos <= fifo_size) 817 return 0; 818 819 azx_dev->insufficient = 0; 820 } 821 822 if (link_pos <= fifo_size) 823 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 824 else 825 mini_pos = link_pos - fifo_size; 826 827 /* Find nearest previous boudary */ 828 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 829 mod_link_pos = link_pos % azx_dev->core.period_bytes; 830 if (mod_link_pos >= fifo_size) 831 bound_pos = link_pos - mod_link_pos; 832 else if (mod_dma_pos >= mod_mini_pos) 833 bound_pos = mini_pos - mod_mini_pos; 834 else { 835 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 836 if (bound_pos >= azx_dev->core.bufsize) 837 bound_pos = 0; 838 } 839 840 /* Calculate real DMA position we want */ 841 return bound_pos + mod_dma_pos; 842 } 843 844 #define AMD_FIFO_SIZE 32 845 846 /* get the current DMA position with FIFO size correction */ 847 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 848 { 849 struct snd_pcm_substream *substream = azx_dev->core.substream; 850 struct snd_pcm_runtime *runtime = substream->runtime; 851 unsigned int pos, delay; 852 853 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 854 if (!runtime) 855 return pos; 856 857 runtime->delay = AMD_FIFO_SIZE; 858 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 859 if (azx_dev->insufficient) { 860 if (pos < delay) { 861 delay = pos; 862 runtime->delay = bytes_to_frames(runtime, pos); 863 } else { 864 azx_dev->insufficient = 0; 865 } 866 } 867 868 /* correct the DMA position for capture stream */ 869 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 870 if (pos < delay) 871 pos += azx_dev->core.bufsize; 872 pos -= delay; 873 } 874 875 return pos; 876 } 877 878 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 879 unsigned int pos) 880 { 881 struct snd_pcm_substream *substream = azx_dev->core.substream; 882 883 /* just read back the calculated value in the above */ 884 return substream->runtime->delay; 885 } 886 887 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 888 { 889 azx_stop_chip(chip); 890 if (!skip_link_reset) 891 azx_enter_link_reset(chip); 892 azx_clear_irq_pending(chip); 893 display_power(chip, false); 894 } 895 896 #ifdef CONFIG_PM 897 static DEFINE_MUTEX(card_list_lock); 898 static LIST_HEAD(card_list); 899 900 static void azx_shutdown_chip(struct azx *chip) 901 { 902 __azx_shutdown_chip(chip, false); 903 } 904 905 static void azx_add_card_list(struct azx *chip) 906 { 907 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 908 mutex_lock(&card_list_lock); 909 list_add(&hda->list, &card_list); 910 mutex_unlock(&card_list_lock); 911 } 912 913 static void azx_del_card_list(struct azx *chip) 914 { 915 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 916 mutex_lock(&card_list_lock); 917 list_del_init(&hda->list); 918 mutex_unlock(&card_list_lock); 919 } 920 921 /* trigger power-save check at writing parameter */ 922 static int param_set_xint(const char *val, const struct kernel_param *kp) 923 { 924 struct hda_intel *hda; 925 struct azx *chip; 926 int prev = power_save; 927 int ret = param_set_int(val, kp); 928 929 if (ret || prev == power_save) 930 return ret; 931 932 mutex_lock(&card_list_lock); 933 list_for_each_entry(hda, &card_list, list) { 934 chip = &hda->chip; 935 if (!hda->probe_continued || chip->disabled) 936 continue; 937 snd_hda_set_power_save(&chip->bus, power_save * 1000); 938 } 939 mutex_unlock(&card_list_lock); 940 return 0; 941 } 942 943 /* 944 * power management 945 */ 946 static bool azx_is_pm_ready(struct snd_card *card) 947 { 948 struct azx *chip; 949 struct hda_intel *hda; 950 951 if (!card) 952 return false; 953 chip = card->private_data; 954 hda = container_of(chip, struct hda_intel, chip); 955 if (chip->disabled || hda->init_failed || !chip->running) 956 return false; 957 return true; 958 } 959 960 static void __azx_runtime_resume(struct azx *chip) 961 { 962 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 963 struct hdac_bus *bus = azx_bus(chip); 964 struct hda_codec *codec; 965 int status; 966 967 display_power(chip, true); 968 if (hda->need_i915_power) 969 snd_hdac_i915_set_bclk(bus); 970 971 /* Read STATESTS before controller reset */ 972 status = azx_readw(chip, STATESTS); 973 974 azx_init_pci(chip); 975 hda_intel_init_chip(chip, true); 976 977 /* Avoid codec resume if runtime resume is for system suspend */ 978 if (!chip->pm_prepared) { 979 list_for_each_codec(codec, &chip->bus) { 980 if (codec->relaxed_resume) 981 continue; 982 983 if (codec->forced_resume || (status & (1 << codec->addr))) 984 pm_request_resume(hda_codec_dev(codec)); 985 } 986 } 987 988 /* power down again for link-controlled chips */ 989 if (!hda->need_i915_power) 990 display_power(chip, false); 991 } 992 993 #ifdef CONFIG_PM_SLEEP 994 static int azx_prepare(struct device *dev) 995 { 996 struct snd_card *card = dev_get_drvdata(dev); 997 struct azx *chip; 998 999 if (!azx_is_pm_ready(card)) 1000 return 0; 1001 1002 chip = card->private_data; 1003 chip->pm_prepared = 1; 1004 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1005 1006 flush_work(&azx_bus(chip)->unsol_work); 1007 1008 /* HDA controller always requires different WAKEEN for runtime suspend 1009 * and system suspend, so don't use direct-complete here. 1010 */ 1011 return 0; 1012 } 1013 1014 static void azx_complete(struct device *dev) 1015 { 1016 struct snd_card *card = dev_get_drvdata(dev); 1017 struct azx *chip; 1018 1019 if (!azx_is_pm_ready(card)) 1020 return; 1021 1022 chip = card->private_data; 1023 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1024 chip->pm_prepared = 0; 1025 } 1026 1027 static int azx_suspend(struct device *dev) 1028 { 1029 struct snd_card *card = dev_get_drvdata(dev); 1030 struct azx *chip; 1031 struct hdac_bus *bus; 1032 1033 if (!azx_is_pm_ready(card)) 1034 return 0; 1035 1036 chip = card->private_data; 1037 bus = azx_bus(chip); 1038 azx_shutdown_chip(chip); 1039 if (bus->irq >= 0) { 1040 free_irq(bus->irq, chip); 1041 bus->irq = -1; 1042 chip->card->sync_irq = -1; 1043 } 1044 1045 if (chip->msi) 1046 pci_disable_msi(chip->pci); 1047 1048 trace_azx_suspend(chip); 1049 return 0; 1050 } 1051 1052 static int azx_resume(struct device *dev) 1053 { 1054 struct snd_card *card = dev_get_drvdata(dev); 1055 struct azx *chip; 1056 1057 if (!azx_is_pm_ready(card)) 1058 return 0; 1059 1060 chip = card->private_data; 1061 if (chip->msi) 1062 if (pci_enable_msi(chip->pci) < 0) 1063 chip->msi = 0; 1064 if (azx_acquire_irq(chip, 1) < 0) 1065 return -EIO; 1066 1067 __azx_runtime_resume(chip); 1068 1069 trace_azx_resume(chip); 1070 return 0; 1071 } 1072 1073 /* put codec down to D3 at hibernation for Intel SKL+; 1074 * otherwise BIOS may still access the codec and screw up the driver 1075 */ 1076 static int azx_freeze_noirq(struct device *dev) 1077 { 1078 struct snd_card *card = dev_get_drvdata(dev); 1079 struct azx *chip = card->private_data; 1080 struct pci_dev *pci = to_pci_dev(dev); 1081 1082 if (!azx_is_pm_ready(card)) 1083 return 0; 1084 if (chip->driver_type == AZX_DRIVER_SKL) 1085 pci_set_power_state(pci, PCI_D3hot); 1086 1087 return 0; 1088 } 1089 1090 static int azx_thaw_noirq(struct device *dev) 1091 { 1092 struct snd_card *card = dev_get_drvdata(dev); 1093 struct azx *chip = card->private_data; 1094 struct pci_dev *pci = to_pci_dev(dev); 1095 1096 if (!azx_is_pm_ready(card)) 1097 return 0; 1098 if (chip->driver_type == AZX_DRIVER_SKL) 1099 pci_set_power_state(pci, PCI_D0); 1100 1101 return 0; 1102 } 1103 #endif /* CONFIG_PM_SLEEP */ 1104 1105 static int azx_runtime_suspend(struct device *dev) 1106 { 1107 struct snd_card *card = dev_get_drvdata(dev); 1108 struct azx *chip; 1109 1110 if (!azx_is_pm_ready(card)) 1111 return 0; 1112 chip = card->private_data; 1113 1114 /* enable controller wake up event */ 1115 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1116 1117 azx_shutdown_chip(chip); 1118 trace_azx_runtime_suspend(chip); 1119 return 0; 1120 } 1121 1122 static int azx_runtime_resume(struct device *dev) 1123 { 1124 struct snd_card *card = dev_get_drvdata(dev); 1125 struct azx *chip; 1126 1127 if (!azx_is_pm_ready(card)) 1128 return 0; 1129 chip = card->private_data; 1130 __azx_runtime_resume(chip); 1131 1132 /* disable controller Wake Up event*/ 1133 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1134 1135 trace_azx_runtime_resume(chip); 1136 return 0; 1137 } 1138 1139 static int azx_runtime_idle(struct device *dev) 1140 { 1141 struct snd_card *card = dev_get_drvdata(dev); 1142 struct azx *chip; 1143 struct hda_intel *hda; 1144 1145 if (!card) 1146 return 0; 1147 1148 chip = card->private_data; 1149 hda = container_of(chip, struct hda_intel, chip); 1150 if (chip->disabled || hda->init_failed) 1151 return 0; 1152 1153 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1154 azx_bus(chip)->codec_powered || !chip->running) 1155 return -EBUSY; 1156 1157 /* ELD notification gets broken when HD-audio bus is off */ 1158 if (needs_eld_notify_link(chip)) 1159 return -EBUSY; 1160 1161 return 0; 1162 } 1163 1164 static const struct dev_pm_ops azx_pm = { 1165 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1166 #ifdef CONFIG_PM_SLEEP 1167 .prepare = azx_prepare, 1168 .complete = azx_complete, 1169 .freeze_noirq = azx_freeze_noirq, 1170 .thaw_noirq = azx_thaw_noirq, 1171 #endif 1172 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1173 }; 1174 1175 #define AZX_PM_OPS &azx_pm 1176 #else 1177 #define azx_add_card_list(chip) /* NOP */ 1178 #define azx_del_card_list(chip) /* NOP */ 1179 #define AZX_PM_OPS NULL 1180 #endif /* CONFIG_PM */ 1181 1182 1183 static int azx_probe_continue(struct azx *chip); 1184 1185 #ifdef SUPPORT_VGA_SWITCHEROO 1186 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1187 1188 static void azx_vs_set_state(struct pci_dev *pci, 1189 enum vga_switcheroo_state state) 1190 { 1191 struct snd_card *card = pci_get_drvdata(pci); 1192 struct azx *chip = card->private_data; 1193 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1194 struct hda_codec *codec; 1195 bool disabled; 1196 1197 wait_for_completion(&hda->probe_wait); 1198 if (hda->init_failed) 1199 return; 1200 1201 disabled = (state == VGA_SWITCHEROO_OFF); 1202 if (chip->disabled == disabled) 1203 return; 1204 1205 if (!hda->probe_continued) { 1206 chip->disabled = disabled; 1207 if (!disabled) { 1208 dev_info(chip->card->dev, 1209 "Start delayed initialization\n"); 1210 if (azx_probe_continue(chip) < 0) 1211 dev_err(chip->card->dev, "initialization error\n"); 1212 } 1213 } else { 1214 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1215 disabled ? "Disabling" : "Enabling"); 1216 if (disabled) { 1217 list_for_each_codec(codec, &chip->bus) { 1218 pm_runtime_suspend(hda_codec_dev(codec)); 1219 pm_runtime_disable(hda_codec_dev(codec)); 1220 } 1221 pm_runtime_suspend(card->dev); 1222 pm_runtime_disable(card->dev); 1223 /* when we get suspended by vga_switcheroo we end up in D3cold, 1224 * however we have no ACPI handle, so pci/acpi can't put us there, 1225 * put ourselves there */ 1226 pci->current_state = PCI_D3cold; 1227 chip->disabled = true; 1228 if (snd_hda_lock_devices(&chip->bus)) 1229 dev_warn(chip->card->dev, 1230 "Cannot lock devices!\n"); 1231 } else { 1232 snd_hda_unlock_devices(&chip->bus); 1233 chip->disabled = false; 1234 pm_runtime_enable(card->dev); 1235 list_for_each_codec(codec, &chip->bus) { 1236 pm_runtime_enable(hda_codec_dev(codec)); 1237 pm_runtime_resume(hda_codec_dev(codec)); 1238 } 1239 } 1240 } 1241 } 1242 1243 static bool azx_vs_can_switch(struct pci_dev *pci) 1244 { 1245 struct snd_card *card = pci_get_drvdata(pci); 1246 struct azx *chip = card->private_data; 1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1248 1249 wait_for_completion(&hda->probe_wait); 1250 if (hda->init_failed) 1251 return false; 1252 if (chip->disabled || !hda->probe_continued) 1253 return true; 1254 if (snd_hda_lock_devices(&chip->bus)) 1255 return false; 1256 snd_hda_unlock_devices(&chip->bus); 1257 return true; 1258 } 1259 1260 /* 1261 * The discrete GPU cannot power down unless the HDA controller runtime 1262 * suspends, so activate runtime PM on codecs even if power_save == 0. 1263 */ 1264 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1265 { 1266 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1267 struct hda_codec *codec; 1268 1269 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1270 list_for_each_codec(codec, &chip->bus) 1271 codec->auto_runtime_pm = 1; 1272 /* reset the power save setup */ 1273 if (chip->running) 1274 set_default_power_save(chip); 1275 } 1276 } 1277 1278 static void azx_vs_gpu_bound(struct pci_dev *pci, 1279 enum vga_switcheroo_client_id client_id) 1280 { 1281 struct snd_card *card = pci_get_drvdata(pci); 1282 struct azx *chip = card->private_data; 1283 1284 if (client_id == VGA_SWITCHEROO_DIS) 1285 chip->bus.keep_power = 0; 1286 setup_vga_switcheroo_runtime_pm(chip); 1287 } 1288 1289 static void init_vga_switcheroo(struct azx *chip) 1290 { 1291 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1292 struct pci_dev *p = get_bound_vga(chip->pci); 1293 struct pci_dev *parent; 1294 if (p) { 1295 dev_info(chip->card->dev, 1296 "Handle vga_switcheroo audio client\n"); 1297 hda->use_vga_switcheroo = 1; 1298 1299 /* cleared in either gpu_bound op or codec probe, or when its 1300 * upstream port has _PR3 (i.e. dGPU). 1301 */ 1302 parent = pci_upstream_bridge(p); 1303 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1304 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1305 pci_dev_put(p); 1306 } 1307 } 1308 1309 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1310 .set_gpu_state = azx_vs_set_state, 1311 .can_switch = azx_vs_can_switch, 1312 .gpu_bound = azx_vs_gpu_bound, 1313 }; 1314 1315 static int register_vga_switcheroo(struct azx *chip) 1316 { 1317 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1318 struct pci_dev *p; 1319 int err; 1320 1321 if (!hda->use_vga_switcheroo) 1322 return 0; 1323 1324 p = get_bound_vga(chip->pci); 1325 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1326 pci_dev_put(p); 1327 1328 if (err < 0) 1329 return err; 1330 hda->vga_switcheroo_registered = 1; 1331 1332 return 0; 1333 } 1334 #else 1335 #define init_vga_switcheroo(chip) /* NOP */ 1336 #define register_vga_switcheroo(chip) 0 1337 #define check_hdmi_disabled(pci) false 1338 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1339 #endif /* SUPPORT_VGA_SWITCHER */ 1340 1341 /* 1342 * destructor 1343 */ 1344 static void azx_free(struct azx *chip) 1345 { 1346 struct pci_dev *pci = chip->pci; 1347 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1348 struct hdac_bus *bus = azx_bus(chip); 1349 1350 if (hda->freed) 1351 return; 1352 1353 if (azx_has_pm_runtime(chip) && chip->running) { 1354 pm_runtime_get_noresume(&pci->dev); 1355 pm_runtime_forbid(&pci->dev); 1356 pm_runtime_dont_use_autosuspend(&pci->dev); 1357 } 1358 1359 chip->running = 0; 1360 1361 azx_del_card_list(chip); 1362 1363 hda->init_failed = 1; /* to be sure */ 1364 complete_all(&hda->probe_wait); 1365 1366 if (use_vga_switcheroo(hda)) { 1367 if (chip->disabled && hda->probe_continued) 1368 snd_hda_unlock_devices(&chip->bus); 1369 if (hda->vga_switcheroo_registered) 1370 vga_switcheroo_unregister_client(chip->pci); 1371 } 1372 1373 if (bus->chip_init) { 1374 azx_clear_irq_pending(chip); 1375 azx_stop_all_streams(chip); 1376 azx_stop_chip(chip); 1377 } 1378 1379 if (bus->irq >= 0) 1380 free_irq(bus->irq, (void*)chip); 1381 1382 azx_free_stream_pages(chip); 1383 azx_free_streams(chip); 1384 snd_hdac_bus_exit(bus); 1385 1386 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1387 release_firmware(chip->fw); 1388 #endif 1389 display_power(chip, false); 1390 1391 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1392 snd_hdac_i915_exit(bus); 1393 1394 hda->freed = 1; 1395 } 1396 1397 static int azx_dev_disconnect(struct snd_device *device) 1398 { 1399 struct azx *chip = device->device_data; 1400 struct hdac_bus *bus = azx_bus(chip); 1401 1402 chip->bus.shutdown = 1; 1403 cancel_work_sync(&bus->unsol_work); 1404 1405 return 0; 1406 } 1407 1408 static int azx_dev_free(struct snd_device *device) 1409 { 1410 azx_free(device->device_data); 1411 return 0; 1412 } 1413 1414 #ifdef SUPPORT_VGA_SWITCHEROO 1415 #ifdef CONFIG_ACPI 1416 /* ATPX is in the integrated GPU's namespace */ 1417 static bool atpx_present(void) 1418 { 1419 struct pci_dev *pdev = NULL; 1420 acpi_handle dhandle, atpx_handle; 1421 acpi_status status; 1422 1423 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1424 dhandle = ACPI_HANDLE(&pdev->dev); 1425 if (dhandle) { 1426 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1427 if (ACPI_SUCCESS(status)) { 1428 pci_dev_put(pdev); 1429 return true; 1430 } 1431 } 1432 } 1433 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1434 dhandle = ACPI_HANDLE(&pdev->dev); 1435 if (dhandle) { 1436 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1437 if (ACPI_SUCCESS(status)) { 1438 pci_dev_put(pdev); 1439 return true; 1440 } 1441 } 1442 } 1443 return false; 1444 } 1445 #else 1446 static bool atpx_present(void) 1447 { 1448 return false; 1449 } 1450 #endif 1451 1452 /* 1453 * Check of disabled HDMI controller by vga_switcheroo 1454 */ 1455 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1456 { 1457 struct pci_dev *p; 1458 1459 /* check only discrete GPU */ 1460 switch (pci->vendor) { 1461 case PCI_VENDOR_ID_ATI: 1462 case PCI_VENDOR_ID_AMD: 1463 if (pci->devfn == 1) { 1464 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1465 pci->bus->number, 0); 1466 if (p) { 1467 /* ATPX is in the integrated GPU's ACPI namespace 1468 * rather than the dGPU's namespace. However, 1469 * the dGPU is the one who is involved in 1470 * vgaswitcheroo. 1471 */ 1472 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1473 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1474 return p; 1475 pci_dev_put(p); 1476 } 1477 } 1478 break; 1479 case PCI_VENDOR_ID_NVIDIA: 1480 if (pci->devfn == 1) { 1481 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1482 pci->bus->number, 0); 1483 if (p) { 1484 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1485 return p; 1486 pci_dev_put(p); 1487 } 1488 } 1489 break; 1490 } 1491 return NULL; 1492 } 1493 1494 static bool check_hdmi_disabled(struct pci_dev *pci) 1495 { 1496 bool vga_inactive = false; 1497 struct pci_dev *p = get_bound_vga(pci); 1498 1499 if (p) { 1500 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1501 vga_inactive = true; 1502 pci_dev_put(p); 1503 } 1504 return vga_inactive; 1505 } 1506 #endif /* SUPPORT_VGA_SWITCHEROO */ 1507 1508 /* 1509 * allow/deny-listing for position_fix 1510 */ 1511 static const struct snd_pci_quirk position_fix_list[] = { 1512 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1516 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1517 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1518 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1519 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1520 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1521 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1522 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1523 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1524 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1525 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1526 {} 1527 }; 1528 1529 static int check_position_fix(struct azx *chip, int fix) 1530 { 1531 const struct snd_pci_quirk *q; 1532 1533 switch (fix) { 1534 case POS_FIX_AUTO: 1535 case POS_FIX_LPIB: 1536 case POS_FIX_POSBUF: 1537 case POS_FIX_VIACOMBO: 1538 case POS_FIX_COMBO: 1539 case POS_FIX_SKL: 1540 case POS_FIX_FIFO: 1541 return fix; 1542 } 1543 1544 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1545 if (q) { 1546 dev_info(chip->card->dev, 1547 "position_fix set to %d for device %04x:%04x\n", 1548 q->value, q->subvendor, q->subdevice); 1549 return q->value; 1550 } 1551 1552 /* Check VIA/ATI HD Audio Controller exist */ 1553 if (chip->driver_type == AZX_DRIVER_VIA) { 1554 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1555 return POS_FIX_VIACOMBO; 1556 } 1557 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1558 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1559 return POS_FIX_FIFO; 1560 } 1561 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1562 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1563 return POS_FIX_LPIB; 1564 } 1565 if (chip->driver_type == AZX_DRIVER_SKL) { 1566 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1567 return POS_FIX_SKL; 1568 } 1569 return POS_FIX_AUTO; 1570 } 1571 1572 static void assign_position_fix(struct azx *chip, int fix) 1573 { 1574 static const azx_get_pos_callback_t callbacks[] = { 1575 [POS_FIX_AUTO] = NULL, 1576 [POS_FIX_LPIB] = azx_get_pos_lpib, 1577 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1578 [POS_FIX_VIACOMBO] = azx_via_get_position, 1579 [POS_FIX_COMBO] = azx_get_pos_lpib, 1580 [POS_FIX_SKL] = azx_get_pos_posbuf, 1581 [POS_FIX_FIFO] = azx_get_pos_fifo, 1582 }; 1583 1584 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1585 1586 /* combo mode uses LPIB only for playback */ 1587 if (fix == POS_FIX_COMBO) 1588 chip->get_position[1] = NULL; 1589 1590 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1591 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1592 chip->get_delay[0] = chip->get_delay[1] = 1593 azx_get_delay_from_lpib; 1594 } 1595 1596 if (fix == POS_FIX_FIFO) 1597 chip->get_delay[0] = chip->get_delay[1] = 1598 azx_get_delay_from_fifo; 1599 } 1600 1601 /* 1602 * deny-lists for probe_mask 1603 */ 1604 static const struct snd_pci_quirk probe_mask_list[] = { 1605 /* Thinkpad often breaks the controller communication when accessing 1606 * to the non-working (or non-existing) modem codec slot. 1607 */ 1608 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1609 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1610 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1611 /* broken BIOS */ 1612 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1613 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1614 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1615 /* forced codec slots */ 1616 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1617 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1618 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1619 /* WinFast VP200 H (Teradici) user reported broken communication */ 1620 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1621 {} 1622 }; 1623 1624 #define AZX_FORCE_CODEC_MASK 0x100 1625 1626 static void check_probe_mask(struct azx *chip, int dev) 1627 { 1628 const struct snd_pci_quirk *q; 1629 1630 chip->codec_probe_mask = probe_mask[dev]; 1631 if (chip->codec_probe_mask == -1) { 1632 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1633 if (q) { 1634 dev_info(chip->card->dev, 1635 "probe_mask set to 0x%x for device %04x:%04x\n", 1636 q->value, q->subvendor, q->subdevice); 1637 chip->codec_probe_mask = q->value; 1638 } 1639 } 1640 1641 /* check forced option */ 1642 if (chip->codec_probe_mask != -1 && 1643 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1644 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1645 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1646 (int)azx_bus(chip)->codec_mask); 1647 } 1648 } 1649 1650 /* 1651 * allow/deny-list for enable_msi 1652 */ 1653 static const struct snd_pci_quirk msi_deny_list[] = { 1654 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1655 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1656 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1657 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1658 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1659 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1660 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1661 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1662 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1663 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1664 {} 1665 }; 1666 1667 static void check_msi(struct azx *chip) 1668 { 1669 const struct snd_pci_quirk *q; 1670 1671 if (enable_msi >= 0) { 1672 chip->msi = !!enable_msi; 1673 return; 1674 } 1675 chip->msi = 1; /* enable MSI as default */ 1676 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1677 if (q) { 1678 dev_info(chip->card->dev, 1679 "msi for device %04x:%04x set to %d\n", 1680 q->subvendor, q->subdevice, q->value); 1681 chip->msi = q->value; 1682 return; 1683 } 1684 1685 /* NVidia chipsets seem to cause troubles with MSI */ 1686 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1687 dev_info(chip->card->dev, "Disabling MSI\n"); 1688 chip->msi = 0; 1689 } 1690 } 1691 1692 /* check the snoop mode availability */ 1693 static void azx_check_snoop_available(struct azx *chip) 1694 { 1695 int snoop = hda_snoop; 1696 1697 if (snoop >= 0) { 1698 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1699 snoop ? "snoop" : "non-snoop"); 1700 chip->snoop = snoop; 1701 chip->uc_buffer = !snoop; 1702 return; 1703 } 1704 1705 snoop = true; 1706 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1707 chip->driver_type == AZX_DRIVER_VIA) { 1708 /* force to non-snoop mode for a new VIA controller 1709 * when BIOS is set 1710 */ 1711 u8 val; 1712 pci_read_config_byte(chip->pci, 0x42, &val); 1713 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1714 chip->pci->revision == 0x20)) 1715 snoop = false; 1716 } 1717 1718 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1719 snoop = false; 1720 1721 chip->snoop = snoop; 1722 if (!snoop) { 1723 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1724 /* C-Media requires non-cached pages only for CORB/RIRB */ 1725 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1726 chip->uc_buffer = true; 1727 } 1728 } 1729 1730 static void azx_probe_work(struct work_struct *work) 1731 { 1732 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1733 azx_probe_continue(&hda->chip); 1734 } 1735 1736 static int default_bdl_pos_adj(struct azx *chip) 1737 { 1738 /* some exceptions: Atoms seem problematic with value 1 */ 1739 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1740 switch (chip->pci->device) { 1741 case 0x0f04: /* Baytrail */ 1742 case 0x2284: /* Braswell */ 1743 return 32; 1744 } 1745 } 1746 1747 switch (chip->driver_type) { 1748 /* 1749 * increase the bdl size for Glenfly Gpus for hardware 1750 * limitation on hdac interrupt interval 1751 */ 1752 case AZX_DRIVER_GFHDMI: 1753 return 128; 1754 case AZX_DRIVER_ICH: 1755 case AZX_DRIVER_PCH: 1756 return 1; 1757 default: 1758 return 32; 1759 } 1760 } 1761 1762 /* 1763 * constructor 1764 */ 1765 static const struct hda_controller_ops pci_hda_ops; 1766 1767 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1768 int dev, unsigned int driver_caps, 1769 struct azx **rchip) 1770 { 1771 static const struct snd_device_ops ops = { 1772 .dev_disconnect = azx_dev_disconnect, 1773 .dev_free = azx_dev_free, 1774 }; 1775 struct hda_intel *hda; 1776 struct azx *chip; 1777 int err; 1778 1779 *rchip = NULL; 1780 1781 err = pcim_enable_device(pci); 1782 if (err < 0) 1783 return err; 1784 1785 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1786 if (!hda) 1787 return -ENOMEM; 1788 1789 chip = &hda->chip; 1790 mutex_init(&chip->open_mutex); 1791 chip->card = card; 1792 chip->pci = pci; 1793 chip->ops = &pci_hda_ops; 1794 chip->driver_caps = driver_caps; 1795 chip->driver_type = driver_caps & 0xff; 1796 check_msi(chip); 1797 chip->dev_index = dev; 1798 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1799 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1800 INIT_LIST_HEAD(&chip->pcm_list); 1801 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1802 INIT_LIST_HEAD(&hda->list); 1803 init_vga_switcheroo(chip); 1804 init_completion(&hda->probe_wait); 1805 1806 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1807 1808 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1809 chip->fallback_to_single_cmd = 1; 1810 else /* explicitly set to single_cmd or not */ 1811 chip->single_cmd = single_cmd; 1812 1813 azx_check_snoop_available(chip); 1814 1815 if (bdl_pos_adj[dev] < 0) 1816 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1817 else 1818 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1819 1820 err = azx_bus_init(chip, model[dev]); 1821 if (err < 0) 1822 return err; 1823 1824 /* use the non-cached pages in non-snoop mode */ 1825 if (!azx_snoop(chip)) 1826 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG; 1827 1828 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1829 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1830 chip->bus.core.needs_damn_long_delay = 1; 1831 } 1832 1833 check_probe_mask(chip, dev); 1834 1835 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1836 if (err < 0) { 1837 dev_err(card->dev, "Error creating device [card]!\n"); 1838 azx_free(chip); 1839 return err; 1840 } 1841 1842 /* continue probing in work context as may trigger request module */ 1843 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1844 1845 *rchip = chip; 1846 1847 return 0; 1848 } 1849 1850 static int azx_first_init(struct azx *chip) 1851 { 1852 int dev = chip->dev_index; 1853 struct pci_dev *pci = chip->pci; 1854 struct snd_card *card = chip->card; 1855 struct hdac_bus *bus = azx_bus(chip); 1856 int err; 1857 unsigned short gcap; 1858 unsigned int dma_bits = 64; 1859 1860 #if BITS_PER_LONG != 64 1861 /* Fix up base address on ULI M5461 */ 1862 if (chip->driver_type == AZX_DRIVER_ULI) { 1863 u16 tmp3; 1864 pci_read_config_word(pci, 0x40, &tmp3); 1865 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1866 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1867 } 1868 #endif 1869 /* 1870 * Fix response write request not synced to memory when handle 1871 * hdac interrupt on Glenfly Gpus 1872 */ 1873 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1874 bus->polling_mode = 1; 1875 1876 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1877 if (err < 0) 1878 return err; 1879 1880 bus->addr = pci_resource_start(pci, 0); 1881 bus->remap_addr = pcim_iomap_table(pci)[0]; 1882 1883 if (chip->driver_type == AZX_DRIVER_SKL) 1884 snd_hdac_bus_parse_capabilities(bus); 1885 1886 /* 1887 * Some Intel CPUs has always running timer (ART) feature and 1888 * controller may have Global time sync reporting capability, so 1889 * check both of these before declaring synchronized time reporting 1890 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1891 */ 1892 chip->gts_present = false; 1893 1894 #ifdef CONFIG_X86 1895 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1896 chip->gts_present = true; 1897 #endif 1898 1899 if (chip->msi) { 1900 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1901 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1902 pci->no_64bit_msi = true; 1903 } 1904 if (pci_enable_msi(pci) < 0) 1905 chip->msi = 0; 1906 } 1907 1908 pci_set_master(pci); 1909 1910 gcap = azx_readw(chip, GCAP); 1911 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1912 1913 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1914 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1915 dma_bits = 40; 1916 1917 /* disable SB600 64bit support for safety */ 1918 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1919 struct pci_dev *p_smbus; 1920 dma_bits = 40; 1921 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1922 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1923 NULL); 1924 if (p_smbus) { 1925 if (p_smbus->revision < 0x30) 1926 gcap &= ~AZX_GCAP_64OK; 1927 pci_dev_put(p_smbus); 1928 } 1929 } 1930 1931 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1932 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1933 dma_bits = 40; 1934 1935 /* disable 64bit DMA address on some devices */ 1936 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1937 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1938 gcap &= ~AZX_GCAP_64OK; 1939 } 1940 1941 /* disable buffer size rounding to 128-byte multiples if supported */ 1942 if (align_buffer_size >= 0) 1943 chip->align_buffer_size = !!align_buffer_size; 1944 else { 1945 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1946 chip->align_buffer_size = 0; 1947 else 1948 chip->align_buffer_size = 1; 1949 } 1950 1951 /* allow 64bit DMA address if supported by H/W */ 1952 if (!(gcap & AZX_GCAP_64OK)) 1953 dma_bits = 32; 1954 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1955 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1956 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1957 1958 /* read number of streams from GCAP register instead of using 1959 * hardcoded value 1960 */ 1961 chip->capture_streams = (gcap >> 8) & 0x0f; 1962 chip->playback_streams = (gcap >> 12) & 0x0f; 1963 if (!chip->playback_streams && !chip->capture_streams) { 1964 /* gcap didn't give any info, switching to old method */ 1965 1966 switch (chip->driver_type) { 1967 case AZX_DRIVER_ULI: 1968 chip->playback_streams = ULI_NUM_PLAYBACK; 1969 chip->capture_streams = ULI_NUM_CAPTURE; 1970 break; 1971 case AZX_DRIVER_ATIHDMI: 1972 case AZX_DRIVER_ATIHDMI_NS: 1973 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1974 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1975 break; 1976 case AZX_DRIVER_GFHDMI: 1977 case AZX_DRIVER_GENERIC: 1978 default: 1979 chip->playback_streams = ICH6_NUM_PLAYBACK; 1980 chip->capture_streams = ICH6_NUM_CAPTURE; 1981 break; 1982 } 1983 } 1984 chip->capture_index_offset = 0; 1985 chip->playback_index_offset = chip->capture_streams; 1986 chip->num_streams = chip->playback_streams + chip->capture_streams; 1987 1988 /* sanity check for the SDxCTL.STRM field overflow */ 1989 if (chip->num_streams > 15 && 1990 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1991 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1992 "forcing separate stream tags", chip->num_streams); 1993 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1994 } 1995 1996 /* initialize streams */ 1997 err = azx_init_streams(chip); 1998 if (err < 0) 1999 return err; 2000 2001 err = azx_alloc_stream_pages(chip); 2002 if (err < 0) 2003 return err; 2004 2005 /* initialize chip */ 2006 azx_init_pci(chip); 2007 2008 snd_hdac_i915_set_bclk(bus); 2009 2010 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2011 2012 /* codec detection */ 2013 if (!azx_bus(chip)->codec_mask) { 2014 dev_err(card->dev, "no codecs found!\n"); 2015 /* keep running the rest for the runtime PM */ 2016 } 2017 2018 if (azx_acquire_irq(chip, 0) < 0) 2019 return -EBUSY; 2020 2021 strcpy(card->driver, "HDA-Intel"); 2022 strscpy(card->shortname, driver_short_names[chip->driver_type], 2023 sizeof(card->shortname)); 2024 snprintf(card->longname, sizeof(card->longname), 2025 "%s at 0x%lx irq %i", 2026 card->shortname, bus->addr, bus->irq); 2027 2028 return 0; 2029 } 2030 2031 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2032 /* callback from request_firmware_nowait() */ 2033 static void azx_firmware_cb(const struct firmware *fw, void *context) 2034 { 2035 struct snd_card *card = context; 2036 struct azx *chip = card->private_data; 2037 2038 if (fw) 2039 chip->fw = fw; 2040 else 2041 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2042 if (!chip->disabled) { 2043 /* continue probing */ 2044 azx_probe_continue(chip); 2045 } 2046 } 2047 #endif 2048 2049 static int disable_msi_reset_irq(struct azx *chip) 2050 { 2051 struct hdac_bus *bus = azx_bus(chip); 2052 int err; 2053 2054 free_irq(bus->irq, chip); 2055 bus->irq = -1; 2056 chip->card->sync_irq = -1; 2057 pci_disable_msi(chip->pci); 2058 chip->msi = 0; 2059 err = azx_acquire_irq(chip, 1); 2060 if (err < 0) 2061 return err; 2062 2063 return 0; 2064 } 2065 2066 /* Denylist for skipping the whole probe: 2067 * some HD-audio PCI entries are exposed without any codecs, and such devices 2068 * should be ignored from the beginning. 2069 */ 2070 static const struct pci_device_id driver_denylist[] = { 2071 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2072 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2073 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2074 {} 2075 }; 2076 2077 static const struct hda_controller_ops pci_hda_ops = { 2078 .disable_msi_reset_irq = disable_msi_reset_irq, 2079 .position_check = azx_position_check, 2080 }; 2081 2082 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2083 2084 static int azx_probe(struct pci_dev *pci, 2085 const struct pci_device_id *pci_id) 2086 { 2087 struct snd_card *card; 2088 struct hda_intel *hda; 2089 struct azx *chip; 2090 bool schedule_probe; 2091 int dev; 2092 int err; 2093 2094 if (pci_match_id(driver_denylist, pci)) { 2095 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2096 return -ENODEV; 2097 } 2098 2099 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2100 if (dev >= SNDRV_CARDS) 2101 return -ENODEV; 2102 if (!enable[dev]) { 2103 set_bit(dev, probed_devs); 2104 return -ENOENT; 2105 } 2106 2107 /* 2108 * stop probe if another Intel's DSP driver should be activated 2109 */ 2110 if (dmic_detect) { 2111 err = snd_intel_dsp_driver_probe(pci); 2112 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2113 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2114 return -ENODEV; 2115 } 2116 } else { 2117 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2118 } 2119 2120 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2121 0, &card); 2122 if (err < 0) { 2123 dev_err(&pci->dev, "Error creating card!\n"); 2124 return err; 2125 } 2126 2127 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2128 if (err < 0) 2129 goto out_free; 2130 card->private_data = chip; 2131 hda = container_of(chip, struct hda_intel, chip); 2132 2133 pci_set_drvdata(pci, card); 2134 2135 err = register_vga_switcheroo(chip); 2136 if (err < 0) { 2137 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2138 goto out_free; 2139 } 2140 2141 if (check_hdmi_disabled(pci)) { 2142 dev_info(card->dev, "VGA controller is disabled\n"); 2143 dev_info(card->dev, "Delaying initialization\n"); 2144 chip->disabled = true; 2145 } 2146 2147 schedule_probe = !chip->disabled; 2148 2149 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2150 if (patch[dev] && *patch[dev]) { 2151 dev_info(card->dev, "Applying patch firmware '%s'\n", 2152 patch[dev]); 2153 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2154 &pci->dev, GFP_KERNEL, card, 2155 azx_firmware_cb); 2156 if (err < 0) 2157 goto out_free; 2158 schedule_probe = false; /* continued in azx_firmware_cb() */ 2159 } 2160 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2161 2162 #ifndef CONFIG_SND_HDA_I915 2163 if (CONTROLLER_IN_GPU(pci)) 2164 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2165 #endif 2166 2167 if (schedule_probe) 2168 schedule_delayed_work(&hda->probe_work, 0); 2169 2170 set_bit(dev, probed_devs); 2171 if (chip->disabled) 2172 complete_all(&hda->probe_wait); 2173 return 0; 2174 2175 out_free: 2176 snd_card_free(card); 2177 return err; 2178 } 2179 2180 #ifdef CONFIG_PM 2181 /* On some boards setting power_save to a non 0 value leads to clicking / 2182 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2183 * figure out how to avoid these sounds, but that is not always feasible. 2184 * So we keep a list of devices where we disable powersaving as its known 2185 * to causes problems on these devices. 2186 */ 2187 static const struct snd_pci_quirk power_save_denylist[] = { 2188 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2189 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2190 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2191 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2192 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2193 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2194 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2195 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2196 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2197 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2198 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2199 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2200 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2201 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2202 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2203 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2204 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2205 /* https://bugs.launchpad.net/bugs/1821663 */ 2206 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2207 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2208 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2209 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2210 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2211 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2212 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2213 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2214 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2215 /* https://bugs.launchpad.net/bugs/1821663 */ 2216 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2217 {} 2218 }; 2219 #endif /* CONFIG_PM */ 2220 2221 static void set_default_power_save(struct azx *chip) 2222 { 2223 int val = power_save; 2224 2225 #ifdef CONFIG_PM 2226 if (pm_blacklist) { 2227 const struct snd_pci_quirk *q; 2228 2229 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2230 if (q && val) { 2231 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2232 q->subvendor, q->subdevice); 2233 val = 0; 2234 } 2235 } 2236 #endif /* CONFIG_PM */ 2237 snd_hda_set_power_save(&chip->bus, val * 1000); 2238 } 2239 2240 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2241 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2242 [AZX_DRIVER_NVIDIA] = 8, 2243 [AZX_DRIVER_TERA] = 1, 2244 }; 2245 2246 static int azx_probe_continue(struct azx *chip) 2247 { 2248 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2249 struct hdac_bus *bus = azx_bus(chip); 2250 struct pci_dev *pci = chip->pci; 2251 int dev = chip->dev_index; 2252 int err; 2253 2254 if (chip->disabled || hda->init_failed) 2255 return -EIO; 2256 if (hda->probe_retry) 2257 goto probe_retry; 2258 2259 to_hda_bus(bus)->bus_probing = 1; 2260 hda->probe_continued = 1; 2261 2262 /* bind with i915 if needed */ 2263 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2264 err = snd_hdac_i915_init(bus); 2265 if (err < 0) { 2266 /* if the controller is bound only with HDMI/DP 2267 * (for HSW and BDW), we need to abort the probe; 2268 * for other chips, still continue probing as other 2269 * codecs can be on the same link. 2270 */ 2271 if (CONTROLLER_IN_GPU(pci)) { 2272 dev_err(chip->card->dev, 2273 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2274 goto out_free; 2275 } else { 2276 /* don't bother any longer */ 2277 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2278 } 2279 } 2280 2281 /* HSW/BDW controllers need this power */ 2282 if (CONTROLLER_IN_GPU(pci)) 2283 hda->need_i915_power = true; 2284 } 2285 2286 /* Request display power well for the HDA controller or codec. For 2287 * Haswell/Broadwell, both the display HDA controller and codec need 2288 * this power. For other platforms, like Baytrail/Braswell, only the 2289 * display codec needs the power and it can be released after probe. 2290 */ 2291 display_power(chip, true); 2292 2293 err = azx_first_init(chip); 2294 if (err < 0) 2295 goto out_free; 2296 2297 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2298 chip->beep_mode = beep_mode[dev]; 2299 #endif 2300 2301 chip->ctl_dev_id = ctl_dev_id; 2302 2303 /* create codec instances */ 2304 if (bus->codec_mask) { 2305 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2306 if (err < 0) 2307 goto out_free; 2308 } 2309 2310 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2311 if (chip->fw) { 2312 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2313 chip->fw->data); 2314 if (err < 0) 2315 goto out_free; 2316 #ifndef CONFIG_PM 2317 release_firmware(chip->fw); /* no longer needed */ 2318 chip->fw = NULL; 2319 #endif 2320 } 2321 #endif 2322 2323 probe_retry: 2324 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2325 err = azx_codec_configure(chip); 2326 if (err) { 2327 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2328 ++hda->probe_retry < 60) { 2329 schedule_delayed_work(&hda->probe_work, 2330 msecs_to_jiffies(1000)); 2331 return 0; /* keep things up */ 2332 } 2333 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2334 goto out_free; 2335 } 2336 } 2337 2338 err = snd_card_register(chip->card); 2339 if (err < 0) 2340 goto out_free; 2341 2342 setup_vga_switcheroo_runtime_pm(chip); 2343 2344 chip->running = 1; 2345 azx_add_card_list(chip); 2346 2347 set_default_power_save(chip); 2348 2349 if (azx_has_pm_runtime(chip)) { 2350 pm_runtime_use_autosuspend(&pci->dev); 2351 pm_runtime_allow(&pci->dev); 2352 pm_runtime_put_autosuspend(&pci->dev); 2353 } 2354 2355 out_free: 2356 if (err < 0) { 2357 pci_set_drvdata(pci, NULL); 2358 snd_card_free(chip->card); 2359 return err; 2360 } 2361 2362 if (!hda->need_i915_power) 2363 display_power(chip, false); 2364 complete_all(&hda->probe_wait); 2365 to_hda_bus(bus)->bus_probing = 0; 2366 hda->probe_retry = 0; 2367 return 0; 2368 } 2369 2370 static void azx_remove(struct pci_dev *pci) 2371 { 2372 struct snd_card *card = pci_get_drvdata(pci); 2373 struct azx *chip; 2374 struct hda_intel *hda; 2375 2376 if (card) { 2377 /* cancel the pending probing work */ 2378 chip = card->private_data; 2379 hda = container_of(chip, struct hda_intel, chip); 2380 /* FIXME: below is an ugly workaround. 2381 * Both device_release_driver() and driver_probe_device() 2382 * take *both* the device's and its parent's lock before 2383 * calling the remove() and probe() callbacks. The codec 2384 * probe takes the locks of both the codec itself and its 2385 * parent, i.e. the PCI controller dev. Meanwhile, when 2386 * the PCI controller is unbound, it takes its lock, too 2387 * ==> ouch, a deadlock! 2388 * As a workaround, we unlock temporarily here the controller 2389 * device during cancel_work_sync() call. 2390 */ 2391 device_unlock(&pci->dev); 2392 cancel_delayed_work_sync(&hda->probe_work); 2393 device_lock(&pci->dev); 2394 2395 clear_bit(chip->dev_index, probed_devs); 2396 pci_set_drvdata(pci, NULL); 2397 snd_card_free(card); 2398 } 2399 } 2400 2401 static void azx_shutdown(struct pci_dev *pci) 2402 { 2403 struct snd_card *card = pci_get_drvdata(pci); 2404 struct azx *chip; 2405 2406 if (!card) 2407 return; 2408 chip = card->private_data; 2409 if (chip && chip->running) 2410 __azx_shutdown_chip(chip, true); 2411 } 2412 2413 /* PCI IDs */ 2414 static const struct pci_device_id azx_ids[] = { 2415 /* CPT */ 2416 { PCI_DEVICE(0x8086, 0x1c20), 2417 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2418 /* PBG */ 2419 { PCI_DEVICE(0x8086, 0x1d20), 2420 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2421 /* Panther Point */ 2422 { PCI_DEVICE(0x8086, 0x1e20), 2423 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2424 /* Lynx Point */ 2425 { PCI_DEVICE(0x8086, 0x8c20), 2426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2427 /* 9 Series */ 2428 { PCI_DEVICE(0x8086, 0x8ca0), 2429 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2430 /* Wellsburg */ 2431 { PCI_DEVICE(0x8086, 0x8d20), 2432 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2433 { PCI_DEVICE(0x8086, 0x8d21), 2434 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2435 /* Lewisburg */ 2436 { PCI_DEVICE(0x8086, 0xa1f0), 2437 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2438 { PCI_DEVICE(0x8086, 0xa270), 2439 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2440 /* Lynx Point-LP */ 2441 { PCI_DEVICE(0x8086, 0x9c20), 2442 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2443 /* Lynx Point-LP */ 2444 { PCI_DEVICE(0x8086, 0x9c21), 2445 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2446 /* Wildcat Point-LP */ 2447 { PCI_DEVICE(0x8086, 0x9ca0), 2448 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2449 /* Sunrise Point */ 2450 { PCI_DEVICE(0x8086, 0xa170), 2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2452 /* Sunrise Point-LP */ 2453 { PCI_DEVICE(0x8086, 0x9d70), 2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2455 /* Kabylake */ 2456 { PCI_DEVICE(0x8086, 0xa171), 2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2458 /* Kabylake-LP */ 2459 { PCI_DEVICE(0x8086, 0x9d71), 2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2461 /* Kabylake-H */ 2462 { PCI_DEVICE(0x8086, 0xa2f0), 2463 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2464 /* Coffelake */ 2465 { PCI_DEVICE(0x8086, 0xa348), 2466 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2467 /* Cannonlake */ 2468 { PCI_DEVICE(0x8086, 0x9dc8), 2469 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2470 /* CometLake-LP */ 2471 { PCI_DEVICE(0x8086, 0x02C8), 2472 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2473 /* CometLake-H */ 2474 { PCI_DEVICE(0x8086, 0x06C8), 2475 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2476 { PCI_DEVICE(0x8086, 0xf1c8), 2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2478 /* CometLake-S */ 2479 { PCI_DEVICE(0x8086, 0xa3f0), 2480 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2481 /* CometLake-R */ 2482 { PCI_DEVICE(0x8086, 0xf0c8), 2483 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2484 /* Icelake */ 2485 { PCI_DEVICE(0x8086, 0x34c8), 2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2487 /* Icelake-H */ 2488 { PCI_DEVICE(0x8086, 0x3dc8), 2489 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2490 /* Jasperlake */ 2491 { PCI_DEVICE(0x8086, 0x38c8), 2492 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2493 { PCI_DEVICE(0x8086, 0x4dc8), 2494 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2495 /* Tigerlake */ 2496 { PCI_DEVICE(0x8086, 0xa0c8), 2497 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2498 /* Tigerlake-H */ 2499 { PCI_DEVICE(0x8086, 0x43c8), 2500 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2501 /* DG1 */ 2502 { PCI_DEVICE(0x8086, 0x490d), 2503 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2504 /* DG2 */ 2505 { PCI_DEVICE(0x8086, 0x4f90), 2506 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2507 { PCI_DEVICE(0x8086, 0x4f91), 2508 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2509 { PCI_DEVICE(0x8086, 0x4f92), 2510 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2511 /* Alderlake-S */ 2512 { PCI_DEVICE(0x8086, 0x7ad0), 2513 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2514 /* Alderlake-P */ 2515 { PCI_DEVICE(0x8086, 0x51c8), 2516 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2517 { PCI_DEVICE(0x8086, 0x51c9), 2518 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2519 { PCI_DEVICE(0x8086, 0x51cd), 2520 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2521 /* Alderlake-M */ 2522 { PCI_DEVICE(0x8086, 0x51cc), 2523 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2524 /* Alderlake-N */ 2525 { PCI_DEVICE(0x8086, 0x54c8), 2526 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2527 /* Elkhart Lake */ 2528 { PCI_DEVICE(0x8086, 0x4b55), 2529 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2530 { PCI_DEVICE(0x8086, 0x4b58), 2531 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2532 /* Raptor Lake */ 2533 { PCI_DEVICE(0x8086, 0x7a50), 2534 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2535 { PCI_DEVICE(0x8086, 0x51ca), 2536 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2537 { PCI_DEVICE(0x8086, 0x51cb), 2538 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2539 { PCI_DEVICE(0x8086, 0x51ce), 2540 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2541 { PCI_DEVICE(0x8086, 0x51cf), 2542 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2543 /* Meteorlake-P */ 2544 { PCI_DEVICE(0x8086, 0x7e28), 2545 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2546 /* Lunarlake-P */ 2547 { PCI_DEVICE(0x8086, 0xa828), 2548 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2549 /* Broxton-P(Apollolake) */ 2550 { PCI_DEVICE(0x8086, 0x5a98), 2551 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2552 /* Broxton-T */ 2553 { PCI_DEVICE(0x8086, 0x1a98), 2554 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2555 /* Gemini-Lake */ 2556 { PCI_DEVICE(0x8086, 0x3198), 2557 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2558 /* Haswell */ 2559 { PCI_DEVICE(0x8086, 0x0a0c), 2560 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2561 { PCI_DEVICE(0x8086, 0x0c0c), 2562 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2563 { PCI_DEVICE(0x8086, 0x0d0c), 2564 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2565 /* Broadwell */ 2566 { PCI_DEVICE(0x8086, 0x160c), 2567 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2568 /* 5 Series/3400 */ 2569 { PCI_DEVICE(0x8086, 0x3b56), 2570 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2571 { PCI_DEVICE(0x8086, 0x3b57), 2572 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2573 /* Poulsbo */ 2574 { PCI_DEVICE(0x8086, 0x811b), 2575 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2576 AZX_DCAPS_POSFIX_LPIB }, 2577 /* Oaktrail */ 2578 { PCI_DEVICE(0x8086, 0x080a), 2579 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2580 /* BayTrail */ 2581 { PCI_DEVICE(0x8086, 0x0f04), 2582 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2583 /* Braswell */ 2584 { PCI_DEVICE(0x8086, 0x2284), 2585 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2586 /* ICH6 */ 2587 { PCI_DEVICE(0x8086, 0x2668), 2588 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2589 /* ICH7 */ 2590 { PCI_DEVICE(0x8086, 0x27d8), 2591 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2592 /* ESB2 */ 2593 { PCI_DEVICE(0x8086, 0x269a), 2594 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2595 /* ICH8 */ 2596 { PCI_DEVICE(0x8086, 0x284b), 2597 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2598 /* ICH9 */ 2599 { PCI_DEVICE(0x8086, 0x293e), 2600 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2601 /* ICH9 */ 2602 { PCI_DEVICE(0x8086, 0x293f), 2603 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2604 /* ICH10 */ 2605 { PCI_DEVICE(0x8086, 0x3a3e), 2606 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2607 /* ICH10 */ 2608 { PCI_DEVICE(0x8086, 0x3a6e), 2609 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2610 /* Generic Intel */ 2611 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2612 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2613 .class_mask = 0xffffff, 2614 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2615 /* ATI SB 450/600/700/800/900 */ 2616 { PCI_DEVICE(0x1002, 0x437b), 2617 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2618 { PCI_DEVICE(0x1002, 0x4383), 2619 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2620 /* AMD Hudson */ 2621 { PCI_DEVICE(0x1022, 0x780d), 2622 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2623 /* AMD, X370 & co */ 2624 { PCI_DEVICE(0x1022, 0x1457), 2625 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2626 /* AMD, X570 & co */ 2627 { PCI_DEVICE(0x1022, 0x1487), 2628 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2629 /* AMD Stoney */ 2630 { PCI_DEVICE(0x1022, 0x157a), 2631 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2632 AZX_DCAPS_PM_RUNTIME }, 2633 /* AMD Raven */ 2634 { PCI_DEVICE(0x1022, 0x15e3), 2635 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2636 /* ATI HDMI */ 2637 { PCI_DEVICE(0x1002, 0x0002), 2638 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2639 AZX_DCAPS_PM_RUNTIME }, 2640 { PCI_DEVICE(0x1002, 0x1308), 2641 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2642 { PCI_DEVICE(0x1002, 0x157a), 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2644 { PCI_DEVICE(0x1002, 0x15b3), 2645 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2646 { PCI_DEVICE(0x1002, 0x793b), 2647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2648 { PCI_DEVICE(0x1002, 0x7919), 2649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2650 { PCI_DEVICE(0x1002, 0x960f), 2651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2652 { PCI_DEVICE(0x1002, 0x970f), 2653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2654 { PCI_DEVICE(0x1002, 0x9840), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2656 { PCI_DEVICE(0x1002, 0xaa00), 2657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2658 { PCI_DEVICE(0x1002, 0xaa08), 2659 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2660 { PCI_DEVICE(0x1002, 0xaa10), 2661 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2662 { PCI_DEVICE(0x1002, 0xaa18), 2663 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2664 { PCI_DEVICE(0x1002, 0xaa20), 2665 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2666 { PCI_DEVICE(0x1002, 0xaa28), 2667 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2668 { PCI_DEVICE(0x1002, 0xaa30), 2669 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2670 { PCI_DEVICE(0x1002, 0xaa38), 2671 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2672 { PCI_DEVICE(0x1002, 0xaa40), 2673 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2674 { PCI_DEVICE(0x1002, 0xaa48), 2675 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2676 { PCI_DEVICE(0x1002, 0xaa50), 2677 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2678 { PCI_DEVICE(0x1002, 0xaa58), 2679 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2680 { PCI_DEVICE(0x1002, 0xaa60), 2681 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2682 { PCI_DEVICE(0x1002, 0xaa68), 2683 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2684 { PCI_DEVICE(0x1002, 0xaa80), 2685 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2686 { PCI_DEVICE(0x1002, 0xaa88), 2687 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2688 { PCI_DEVICE(0x1002, 0xaa90), 2689 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2690 { PCI_DEVICE(0x1002, 0xaa98), 2691 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2692 { PCI_DEVICE(0x1002, 0x9902), 2693 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2694 { PCI_DEVICE(0x1002, 0xaaa0), 2695 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2696 { PCI_DEVICE(0x1002, 0xaaa8), 2697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2698 { PCI_DEVICE(0x1002, 0xaab0), 2699 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2700 { PCI_DEVICE(0x1002, 0xaac0), 2701 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2702 AZX_DCAPS_PM_RUNTIME }, 2703 { PCI_DEVICE(0x1002, 0xaac8), 2704 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2705 AZX_DCAPS_PM_RUNTIME }, 2706 { PCI_DEVICE(0x1002, 0xaad8), 2707 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2708 AZX_DCAPS_PM_RUNTIME }, 2709 { PCI_DEVICE(0x1002, 0xaae0), 2710 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2711 AZX_DCAPS_PM_RUNTIME }, 2712 { PCI_DEVICE(0x1002, 0xaae8), 2713 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2714 AZX_DCAPS_PM_RUNTIME }, 2715 { PCI_DEVICE(0x1002, 0xaaf0), 2716 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2717 AZX_DCAPS_PM_RUNTIME }, 2718 { PCI_DEVICE(0x1002, 0xaaf8), 2719 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2720 AZX_DCAPS_PM_RUNTIME }, 2721 { PCI_DEVICE(0x1002, 0xab00), 2722 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2723 AZX_DCAPS_PM_RUNTIME }, 2724 { PCI_DEVICE(0x1002, 0xab08), 2725 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2726 AZX_DCAPS_PM_RUNTIME }, 2727 { PCI_DEVICE(0x1002, 0xab10), 2728 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2729 AZX_DCAPS_PM_RUNTIME }, 2730 { PCI_DEVICE(0x1002, 0xab18), 2731 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2732 AZX_DCAPS_PM_RUNTIME }, 2733 { PCI_DEVICE(0x1002, 0xab20), 2734 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2735 AZX_DCAPS_PM_RUNTIME }, 2736 { PCI_DEVICE(0x1002, 0xab28), 2737 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2738 AZX_DCAPS_PM_RUNTIME }, 2739 { PCI_DEVICE(0x1002, 0xab30), 2740 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2741 AZX_DCAPS_PM_RUNTIME }, 2742 { PCI_DEVICE(0x1002, 0xab38), 2743 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2744 AZX_DCAPS_PM_RUNTIME }, 2745 /* GLENFLY */ 2746 { PCI_DEVICE(0x6766, PCI_ANY_ID), 2747 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2748 .class_mask = 0xffffff, 2749 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2750 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2751 /* VIA VT8251/VT8237A */ 2752 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2753 /* VIA GFX VT7122/VX900 */ 2754 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2755 /* VIA GFX VT6122/VX11 */ 2756 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2757 /* SIS966 */ 2758 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2759 /* ULI M5461 */ 2760 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2761 /* NVIDIA MCP */ 2762 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2763 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2764 .class_mask = 0xffffff, 2765 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2766 /* Teradici */ 2767 { PCI_DEVICE(0x6549, 0x1200), 2768 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2769 { PCI_DEVICE(0x6549, 0x2200), 2770 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2771 /* Creative X-Fi (CA0110-IBG) */ 2772 /* CTHDA chips */ 2773 { PCI_DEVICE(0x1102, 0x0010), 2774 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2775 { PCI_DEVICE(0x1102, 0x0012), 2776 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2777 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2778 /* the following entry conflicts with snd-ctxfi driver, 2779 * as ctxfi driver mutates from HD-audio to native mode with 2780 * a special command sequence. 2781 */ 2782 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2783 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2784 .class_mask = 0xffffff, 2785 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2786 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2787 #else 2788 /* this entry seems still valid -- i.e. without emu20kx chip */ 2789 { PCI_DEVICE(0x1102, 0x0009), 2790 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2791 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2792 #endif 2793 /* CM8888 */ 2794 { PCI_DEVICE(0x13f6, 0x5011), 2795 .driver_data = AZX_DRIVER_CMEDIA | 2796 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2797 /* Vortex86MX */ 2798 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2799 /* VMware HDAudio */ 2800 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2801 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2802 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2803 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2804 .class_mask = 0xffffff, 2805 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2806 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2807 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2808 .class_mask = 0xffffff, 2809 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2810 /* Zhaoxin */ 2811 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2812 { 0, } 2813 }; 2814 MODULE_DEVICE_TABLE(pci, azx_ids); 2815 2816 /* pci_driver definition */ 2817 static struct pci_driver azx_driver = { 2818 .name = KBUILD_MODNAME, 2819 .id_table = azx_ids, 2820 .probe = azx_probe, 2821 .remove = azx_remove, 2822 .shutdown = azx_shutdown, 2823 .driver = { 2824 .pm = AZX_PM_OPS, 2825 }, 2826 }; 2827 2828 module_pci_driver(azx_driver); 2829