1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <asm/io.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/kernel.h> 41 #include <linux/module.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/moduleparam.h> 44 #include <linux/init.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/mutex.h> 48 #include <linux/reboot.h> 49 #include <sound/core.h> 50 #include <sound/initval.h> 51 #include "hda_codec.h" 52 53 54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 57 static char *model[SNDRV_CARDS]; 58 static int position_fix[SNDRV_CARDS]; 59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 61 static int probe_only[SNDRV_CARDS]; 62 static int single_cmd; 63 static int enable_msi = -1; 64 #ifdef CONFIG_SND_HDA_PATCH_LOADER 65 static char *patch[SNDRV_CARDS]; 66 #endif 67 #ifdef CONFIG_SND_HDA_INPUT_BEEP 68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 69 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 70 #endif 71 72 module_param_array(index, int, NULL, 0444); 73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 74 module_param_array(id, charp, NULL, 0444); 75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 76 module_param_array(enable, bool, NULL, 0444); 77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 78 module_param_array(model, charp, NULL, 0444); 79 MODULE_PARM_DESC(model, "Use the given board model."); 80 module_param_array(position_fix, int, NULL, 0444); 81 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 82 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO)."); 83 module_param_array(bdl_pos_adj, int, NULL, 0644); 84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 85 module_param_array(probe_mask, int, NULL, 0444); 86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 87 module_param_array(probe_only, int, NULL, 0444); 88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 89 module_param(single_cmd, bool, 0444); 90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 91 "(for debugging only)."); 92 module_param(enable_msi, int, 0444); 93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 94 #ifdef CONFIG_SND_HDA_PATCH_LOADER 95 module_param_array(patch, charp, NULL, 0444); 96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 97 #endif 98 #ifdef CONFIG_SND_HDA_INPUT_BEEP 99 module_param_array(beep_mode, int, NULL, 0444); 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 101 "(0=off, 1=on, 2=mute switch on/off) (default=1)."); 102 #endif 103 104 #ifdef CONFIG_SND_HDA_POWER_SAVE 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 106 module_param(power_save, int, 0644); 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 108 "(in second, 0 = disable)."); 109 110 /* reset the HD-audio controller in power save mode. 111 * this may give more power-saving, but will take longer time to 112 * wake up. 113 */ 114 static int power_save_controller = 1; 115 module_param(power_save_controller, bool, 0644); 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 117 #endif 118 119 MODULE_LICENSE("GPL"); 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 121 "{Intel, ICH6M}," 122 "{Intel, ICH7}," 123 "{Intel, ESB2}," 124 "{Intel, ICH8}," 125 "{Intel, ICH9}," 126 "{Intel, ICH10}," 127 "{Intel, PCH}," 128 "{Intel, CPT}," 129 "{Intel, PPT}," 130 "{Intel, PBG}," 131 "{Intel, SCH}," 132 "{ATI, SB450}," 133 "{ATI, SB600}," 134 "{ATI, RS600}," 135 "{ATI, RS690}," 136 "{ATI, RS780}," 137 "{ATI, R600}," 138 "{ATI, RV630}," 139 "{ATI, RV610}," 140 "{ATI, RV670}," 141 "{ATI, RV635}," 142 "{ATI, RV620}," 143 "{ATI, RV770}," 144 "{VIA, VT8251}," 145 "{VIA, VT8237A}," 146 "{SiS, SIS966}," 147 "{ULI, M5461}}"); 148 MODULE_DESCRIPTION("Intel HDA driver"); 149 150 #ifdef CONFIG_SND_VERBOSE_PRINTK 151 #define SFX /* nop */ 152 #else 153 #define SFX "hda-intel: " 154 #endif 155 156 /* 157 * registers 158 */ 159 #define ICH6_REG_GCAP 0x00 160 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ 161 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 162 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 163 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ 164 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ 165 #define ICH6_REG_VMIN 0x02 166 #define ICH6_REG_VMAJ 0x03 167 #define ICH6_REG_OUTPAY 0x04 168 #define ICH6_REG_INPAY 0x06 169 #define ICH6_REG_GCTL 0x08 170 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ 171 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ 172 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 173 #define ICH6_REG_WAKEEN 0x0c 174 #define ICH6_REG_STATESTS 0x0e 175 #define ICH6_REG_GSTS 0x10 176 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ 177 #define ICH6_REG_INTCTL 0x20 178 #define ICH6_REG_INTSTS 0x24 179 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ 180 #define ICH6_REG_SYNC 0x34 181 #define ICH6_REG_CORBLBASE 0x40 182 #define ICH6_REG_CORBUBASE 0x44 183 #define ICH6_REG_CORBWP 0x48 184 #define ICH6_REG_CORBRP 0x4a 185 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ 186 #define ICH6_REG_CORBCTL 0x4c 187 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ 188 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 189 #define ICH6_REG_CORBSTS 0x4d 190 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ 191 #define ICH6_REG_CORBSIZE 0x4e 192 193 #define ICH6_REG_RIRBLBASE 0x50 194 #define ICH6_REG_RIRBUBASE 0x54 195 #define ICH6_REG_RIRBWP 0x58 196 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ 197 #define ICH6_REG_RINTCNT 0x5a 198 #define ICH6_REG_RIRBCTL 0x5c 199 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 200 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 201 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 202 #define ICH6_REG_RIRBSTS 0x5d 203 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ 204 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 205 #define ICH6_REG_RIRBSIZE 0x5e 206 207 #define ICH6_REG_IC 0x60 208 #define ICH6_REG_IR 0x64 209 #define ICH6_REG_IRS 0x68 210 #define ICH6_IRS_VALID (1<<1) 211 #define ICH6_IRS_BUSY (1<<0) 212 213 #define ICH6_REG_DPLBASE 0x70 214 #define ICH6_REG_DPUBASE 0x74 215 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 216 217 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 218 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 219 220 /* stream register offsets from stream base */ 221 #define ICH6_REG_SD_CTL 0x00 222 #define ICH6_REG_SD_STS 0x03 223 #define ICH6_REG_SD_LPIB 0x04 224 #define ICH6_REG_SD_CBL 0x08 225 #define ICH6_REG_SD_LVI 0x0c 226 #define ICH6_REG_SD_FIFOW 0x0e 227 #define ICH6_REG_SD_FIFOSIZE 0x10 228 #define ICH6_REG_SD_FORMAT 0x12 229 #define ICH6_REG_SD_BDLPL 0x18 230 #define ICH6_REG_SD_BDLPU 0x1c 231 232 /* PCI space */ 233 #define ICH6_PCIREG_TCSEL 0x44 234 235 /* 236 * other constants 237 */ 238 239 /* max number of SDs */ 240 /* ICH, ATI and VIA have 4 playback and 4 capture */ 241 #define ICH6_NUM_CAPTURE 4 242 #define ICH6_NUM_PLAYBACK 4 243 244 /* ULI has 6 playback and 5 capture */ 245 #define ULI_NUM_CAPTURE 5 246 #define ULI_NUM_PLAYBACK 6 247 248 /* ATI HDMI has 1 playback and 0 capture */ 249 #define ATIHDMI_NUM_CAPTURE 0 250 #define ATIHDMI_NUM_PLAYBACK 1 251 252 /* TERA has 4 playback and 3 capture */ 253 #define TERA_NUM_CAPTURE 3 254 #define TERA_NUM_PLAYBACK 4 255 256 /* this number is statically defined for simplicity */ 257 #define MAX_AZX_DEV 16 258 259 /* max number of fragments - we may use more if allocating more pages for BDL */ 260 #define BDL_SIZE 4096 261 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 262 #define AZX_MAX_FRAG 32 263 /* max buffer size - no h/w limit, you can increase as you like */ 264 #define AZX_MAX_BUF_SIZE (1024*1024*1024) 265 266 /* RIRB int mask: overrun[2], response[0] */ 267 #define RIRB_INT_RESPONSE 0x01 268 #define RIRB_INT_OVERRUN 0x04 269 #define RIRB_INT_MASK 0x05 270 271 /* STATESTS int mask: S3,SD2,SD1,SD0 */ 272 #define AZX_MAX_CODECS 8 273 #define AZX_DEFAULT_CODECS 4 274 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) 275 276 /* SD_CTL bits */ 277 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 278 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 279 #define SD_CTL_STRIPE (3 << 16) /* stripe control */ 280 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 281 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 282 #define SD_CTL_STREAM_TAG_MASK (0xf << 20) 283 #define SD_CTL_STREAM_TAG_SHIFT 20 284 285 /* SD_CTL and SD_STS */ 286 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 287 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 288 #define SD_INT_COMPLETE 0x04 /* completion interrupt */ 289 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 290 SD_INT_COMPLETE) 291 292 /* SD_STS */ 293 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 294 295 /* INTCTL and INTSTS */ 296 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 297 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 298 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 299 300 /* below are so far hardcoded - should read registers in future */ 301 #define ICH6_MAX_CORB_ENTRIES 256 302 #define ICH6_MAX_RIRB_ENTRIES 256 303 304 /* position fix mode */ 305 enum { 306 POS_FIX_AUTO, 307 POS_FIX_LPIB, 308 POS_FIX_POSBUF, 309 POS_FIX_VIACOMBO, 310 }; 311 312 /* Defines for ATI HD Audio support in SB450 south bridge */ 313 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 314 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 315 316 /* Defines for Nvidia HDA support */ 317 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 318 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 319 #define NVIDIA_HDA_ISTRM_COH 0x4d 320 #define NVIDIA_HDA_OSTRM_COH 0x4c 321 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 322 323 /* Defines for Intel SCH HDA snoop control */ 324 #define INTEL_SCH_HDA_DEVC 0x78 325 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 326 327 /* Define IN stream 0 FIFO size offset in VIA controller */ 328 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 329 /* Define VIA HD Audio Device ID*/ 330 #define VIA_HDAC_DEVICE_ID 0x3288 331 332 /* HD Audio class code */ 333 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 334 335 /* 336 */ 337 338 struct azx_dev { 339 struct snd_dma_buffer bdl; /* BDL buffer */ 340 u32 *posbuf; /* position buffer pointer */ 341 342 unsigned int bufsize; /* size of the play buffer in bytes */ 343 unsigned int period_bytes; /* size of the period in bytes */ 344 unsigned int frags; /* number for period in the play buffer */ 345 unsigned int fifo_size; /* FIFO size */ 346 unsigned long start_wallclk; /* start + minimum wallclk */ 347 unsigned long period_wallclk; /* wallclk for period */ 348 349 void __iomem *sd_addr; /* stream descriptor pointer */ 350 351 u32 sd_int_sta_mask; /* stream int status mask */ 352 353 /* pcm support */ 354 struct snd_pcm_substream *substream; /* assigned substream, 355 * set in PCM open 356 */ 357 unsigned int format_val; /* format value to be set in the 358 * controller and the codec 359 */ 360 unsigned char stream_tag; /* assigned stream */ 361 unsigned char index; /* stream index */ 362 int device; /* last device number assigned to */ 363 364 unsigned int opened :1; 365 unsigned int running :1; 366 unsigned int irq_pending :1; 367 /* 368 * For VIA: 369 * A flag to ensure DMA position is 0 370 * when link position is not greater than FIFO size 371 */ 372 unsigned int insufficient :1; 373 }; 374 375 /* CORB/RIRB */ 376 struct azx_rb { 377 u32 *buf; /* CORB/RIRB buffer 378 * Each CORB entry is 4byte, RIRB is 8byte 379 */ 380 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 381 /* for RIRB */ 382 unsigned short rp, wp; /* read/write pointers */ 383 int cmds[AZX_MAX_CODECS]; /* number of pending requests */ 384 u32 res[AZX_MAX_CODECS]; /* last read value */ 385 }; 386 387 struct azx { 388 struct snd_card *card; 389 struct pci_dev *pci; 390 int dev_index; 391 392 /* chip type specific */ 393 int driver_type; 394 int playback_streams; 395 int playback_index_offset; 396 int capture_streams; 397 int capture_index_offset; 398 int num_streams; 399 400 /* pci resources */ 401 unsigned long addr; 402 void __iomem *remap_addr; 403 int irq; 404 405 /* locks */ 406 spinlock_t reg_lock; 407 struct mutex open_mutex; 408 409 /* streams (x num_streams) */ 410 struct azx_dev *azx_dev; 411 412 /* PCM */ 413 struct snd_pcm *pcm[HDA_MAX_PCMS]; 414 415 /* HD codec */ 416 unsigned short codec_mask; 417 int codec_probe_mask; /* copied from probe_mask option */ 418 struct hda_bus *bus; 419 unsigned int beep_mode; 420 421 /* CORB/RIRB */ 422 struct azx_rb corb; 423 struct azx_rb rirb; 424 425 /* CORB/RIRB and position buffers */ 426 struct snd_dma_buffer rb; 427 struct snd_dma_buffer posbuf; 428 429 /* flags */ 430 int position_fix[2]; /* for both playback/capture streams */ 431 int poll_count; 432 unsigned int running :1; 433 unsigned int initialized :1; 434 unsigned int single_cmd :1; 435 unsigned int polling_mode :1; 436 unsigned int msi :1; 437 unsigned int irq_pending_warned :1; 438 unsigned int probing :1; /* codec probing phase */ 439 440 /* for debugging */ 441 unsigned int last_cmd[AZX_MAX_CODECS]; 442 443 /* for pending irqs */ 444 struct work_struct irq_pending_work; 445 446 /* reboot notifier (for mysterious hangup problem at power-down) */ 447 struct notifier_block reboot_notifier; 448 }; 449 450 /* driver types */ 451 enum { 452 AZX_DRIVER_ICH, 453 AZX_DRIVER_PCH, 454 AZX_DRIVER_SCH, 455 AZX_DRIVER_ATI, 456 AZX_DRIVER_ATIHDMI, 457 AZX_DRIVER_VIA, 458 AZX_DRIVER_SIS, 459 AZX_DRIVER_ULI, 460 AZX_DRIVER_NVIDIA, 461 AZX_DRIVER_TERA, 462 AZX_DRIVER_CTX, 463 AZX_DRIVER_GENERIC, 464 AZX_NUM_DRIVERS, /* keep this as last entry */ 465 }; 466 467 static char *driver_short_names[] __devinitdata = { 468 [AZX_DRIVER_ICH] = "HDA Intel", 469 [AZX_DRIVER_PCH] = "HDA Intel PCH", 470 [AZX_DRIVER_SCH] = "HDA Intel MID", 471 [AZX_DRIVER_ATI] = "HDA ATI SB", 472 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 473 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 474 [AZX_DRIVER_SIS] = "HDA SIS966", 475 [AZX_DRIVER_ULI] = "HDA ULI M5461", 476 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 477 [AZX_DRIVER_TERA] = "HDA Teradici", 478 [AZX_DRIVER_CTX] = "HDA Creative", 479 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 480 }; 481 482 /* 483 * macros for easy use 484 */ 485 #define azx_writel(chip,reg,value) \ 486 writel(value, (chip)->remap_addr + ICH6_REG_##reg) 487 #define azx_readl(chip,reg) \ 488 readl((chip)->remap_addr + ICH6_REG_##reg) 489 #define azx_writew(chip,reg,value) \ 490 writew(value, (chip)->remap_addr + ICH6_REG_##reg) 491 #define azx_readw(chip,reg) \ 492 readw((chip)->remap_addr + ICH6_REG_##reg) 493 #define azx_writeb(chip,reg,value) \ 494 writeb(value, (chip)->remap_addr + ICH6_REG_##reg) 495 #define azx_readb(chip,reg) \ 496 readb((chip)->remap_addr + ICH6_REG_##reg) 497 498 #define azx_sd_writel(dev,reg,value) \ 499 writel(value, (dev)->sd_addr + ICH6_REG_##reg) 500 #define azx_sd_readl(dev,reg) \ 501 readl((dev)->sd_addr + ICH6_REG_##reg) 502 #define azx_sd_writew(dev,reg,value) \ 503 writew(value, (dev)->sd_addr + ICH6_REG_##reg) 504 #define azx_sd_readw(dev,reg) \ 505 readw((dev)->sd_addr + ICH6_REG_##reg) 506 #define azx_sd_writeb(dev,reg,value) \ 507 writeb(value, (dev)->sd_addr + ICH6_REG_##reg) 508 #define azx_sd_readb(dev,reg) \ 509 readb((dev)->sd_addr + ICH6_REG_##reg) 510 511 /* for pcm support */ 512 #define get_azx_dev(substream) (substream->runtime->private_data) 513 514 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 515 static int azx_send_cmd(struct hda_bus *bus, unsigned int val); 516 /* 517 * Interface for HD codec 518 */ 519 520 /* 521 * CORB / RIRB interface 522 */ 523 static int azx_alloc_cmd_io(struct azx *chip) 524 { 525 int err; 526 527 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 528 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 529 snd_dma_pci_data(chip->pci), 530 PAGE_SIZE, &chip->rb); 531 if (err < 0) { 532 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); 533 return err; 534 } 535 return 0; 536 } 537 538 static void azx_init_cmd_io(struct azx *chip) 539 { 540 spin_lock_irq(&chip->reg_lock); 541 /* CORB set up */ 542 chip->corb.addr = chip->rb.addr; 543 chip->corb.buf = (u32 *)chip->rb.area; 544 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); 545 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); 546 547 /* set the corb size to 256 entries (ULI requires explicitly) */ 548 azx_writeb(chip, CORBSIZE, 0x02); 549 /* set the corb write pointer to 0 */ 550 azx_writew(chip, CORBWP, 0); 551 /* reset the corb hw read pointer */ 552 azx_writew(chip, CORBRP, ICH6_CORBRP_RST); 553 /* enable corb dma */ 554 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); 555 556 /* RIRB set up */ 557 chip->rirb.addr = chip->rb.addr + 2048; 558 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); 559 chip->rirb.wp = chip->rirb.rp = 0; 560 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); 561 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); 562 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); 563 564 /* set the rirb size to 256 entries (ULI requires explicitly) */ 565 azx_writeb(chip, RIRBSIZE, 0x02); 566 /* reset the rirb hw write pointer */ 567 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); 568 /* set N=1, get RIRB response interrupt for new entry */ 569 if (chip->driver_type == AZX_DRIVER_CTX) 570 azx_writew(chip, RINTCNT, 0xc0); 571 else 572 azx_writew(chip, RINTCNT, 1); 573 /* enable rirb dma and response irq */ 574 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 575 spin_unlock_irq(&chip->reg_lock); 576 } 577 578 static void azx_free_cmd_io(struct azx *chip) 579 { 580 spin_lock_irq(&chip->reg_lock); 581 /* disable ringbuffer DMAs */ 582 azx_writeb(chip, RIRBCTL, 0); 583 azx_writeb(chip, CORBCTL, 0); 584 spin_unlock_irq(&chip->reg_lock); 585 } 586 587 static unsigned int azx_command_addr(u32 cmd) 588 { 589 unsigned int addr = cmd >> 28; 590 591 if (addr >= AZX_MAX_CODECS) { 592 snd_BUG(); 593 addr = 0; 594 } 595 596 return addr; 597 } 598 599 static unsigned int azx_response_addr(u32 res) 600 { 601 unsigned int addr = res & 0xf; 602 603 if (addr >= AZX_MAX_CODECS) { 604 snd_BUG(); 605 addr = 0; 606 } 607 608 return addr; 609 } 610 611 /* send a command */ 612 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) 613 { 614 struct azx *chip = bus->private_data; 615 unsigned int addr = azx_command_addr(val); 616 unsigned int wp; 617 618 spin_lock_irq(&chip->reg_lock); 619 620 /* add command to corb */ 621 wp = azx_readb(chip, CORBWP); 622 wp++; 623 wp %= ICH6_MAX_CORB_ENTRIES; 624 625 chip->rirb.cmds[addr]++; 626 chip->corb.buf[wp] = cpu_to_le32(val); 627 azx_writel(chip, CORBWP, wp); 628 629 spin_unlock_irq(&chip->reg_lock); 630 631 return 0; 632 } 633 634 #define ICH6_RIRB_EX_UNSOL_EV (1<<4) 635 636 /* retrieve RIRB entry - called from interrupt handler */ 637 static void azx_update_rirb(struct azx *chip) 638 { 639 unsigned int rp, wp; 640 unsigned int addr; 641 u32 res, res_ex; 642 643 wp = azx_readb(chip, RIRBWP); 644 if (wp == chip->rirb.wp) 645 return; 646 chip->rirb.wp = wp; 647 648 while (chip->rirb.rp != wp) { 649 chip->rirb.rp++; 650 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 651 652 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 653 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 654 res = le32_to_cpu(chip->rirb.buf[rp]); 655 addr = azx_response_addr(res_ex); 656 if (res_ex & ICH6_RIRB_EX_UNSOL_EV) 657 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 658 else if (chip->rirb.cmds[addr]) { 659 chip->rirb.res[addr] = res; 660 smp_wmb(); 661 chip->rirb.cmds[addr]--; 662 } else 663 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, " 664 "last cmd=%#08x\n", 665 res, res_ex, 666 chip->last_cmd[addr]); 667 } 668 } 669 670 /* receive a response */ 671 static unsigned int azx_rirb_get_response(struct hda_bus *bus, 672 unsigned int addr) 673 { 674 struct azx *chip = bus->private_data; 675 unsigned long timeout; 676 int do_poll = 0; 677 678 again: 679 timeout = jiffies + msecs_to_jiffies(1000); 680 for (;;) { 681 if (chip->polling_mode || do_poll) { 682 spin_lock_irq(&chip->reg_lock); 683 azx_update_rirb(chip); 684 spin_unlock_irq(&chip->reg_lock); 685 } 686 if (!chip->rirb.cmds[addr]) { 687 smp_rmb(); 688 bus->rirb_error = 0; 689 690 if (!do_poll) 691 chip->poll_count = 0; 692 return chip->rirb.res[addr]; /* the last value */ 693 } 694 if (time_after(jiffies, timeout)) 695 break; 696 if (bus->needs_damn_long_delay) 697 msleep(2); /* temporary workaround */ 698 else { 699 udelay(10); 700 cond_resched(); 701 } 702 } 703 704 if (!chip->polling_mode && chip->poll_count < 2) { 705 snd_printdd(SFX "azx_get_response timeout, " 706 "polling the codec once: last cmd=0x%08x\n", 707 chip->last_cmd[addr]); 708 do_poll = 1; 709 chip->poll_count++; 710 goto again; 711 } 712 713 714 if (!chip->polling_mode) { 715 snd_printk(KERN_WARNING SFX "azx_get_response timeout, " 716 "switching to polling mode: last cmd=0x%08x\n", 717 chip->last_cmd[addr]); 718 chip->polling_mode = 1; 719 goto again; 720 } 721 722 if (chip->msi) { 723 snd_printk(KERN_WARNING SFX "No response from codec, " 724 "disabling MSI: last cmd=0x%08x\n", 725 chip->last_cmd[addr]); 726 free_irq(chip->irq, chip); 727 chip->irq = -1; 728 pci_disable_msi(chip->pci); 729 chip->msi = 0; 730 if (azx_acquire_irq(chip, 1) < 0) { 731 bus->rirb_error = 1; 732 return -1; 733 } 734 goto again; 735 } 736 737 if (chip->probing) { 738 /* If this critical timeout happens during the codec probing 739 * phase, this is likely an access to a non-existing codec 740 * slot. Better to return an error and reset the system. 741 */ 742 return -1; 743 } 744 745 /* a fatal communication error; need either to reset or to fallback 746 * to the single_cmd mode 747 */ 748 bus->rirb_error = 1; 749 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { 750 bus->response_reset = 1; 751 return -1; /* give a chance to retry */ 752 } 753 754 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " 755 "switching to single_cmd mode: last cmd=0x%08x\n", 756 chip->last_cmd[addr]); 757 chip->single_cmd = 1; 758 bus->response_reset = 0; 759 /* release CORB/RIRB */ 760 azx_free_cmd_io(chip); 761 /* disable unsolicited responses */ 762 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); 763 return -1; 764 } 765 766 /* 767 * Use the single immediate command instead of CORB/RIRB for simplicity 768 * 769 * Note: according to Intel, this is not preferred use. The command was 770 * intended for the BIOS only, and may get confused with unsolicited 771 * responses. So, we shouldn't use it for normal operation from the 772 * driver. 773 * I left the codes, however, for debugging/testing purposes. 774 */ 775 776 /* receive a response */ 777 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) 778 { 779 int timeout = 50; 780 781 while (timeout--) { 782 /* check IRV busy bit */ 783 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { 784 /* reuse rirb.res as the response return value */ 785 chip->rirb.res[addr] = azx_readl(chip, IR); 786 return 0; 787 } 788 udelay(1); 789 } 790 if (printk_ratelimit()) 791 snd_printd(SFX "get_response timeout: IRS=0x%x\n", 792 azx_readw(chip, IRS)); 793 chip->rirb.res[addr] = -1; 794 return -EIO; 795 } 796 797 /* send a command */ 798 static int azx_single_send_cmd(struct hda_bus *bus, u32 val) 799 { 800 struct azx *chip = bus->private_data; 801 unsigned int addr = azx_command_addr(val); 802 int timeout = 50; 803 804 bus->rirb_error = 0; 805 while (timeout--) { 806 /* check ICB busy bit */ 807 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { 808 /* Clear IRV valid bit */ 809 azx_writew(chip, IRS, azx_readw(chip, IRS) | 810 ICH6_IRS_VALID); 811 azx_writel(chip, IC, val); 812 azx_writew(chip, IRS, azx_readw(chip, IRS) | 813 ICH6_IRS_BUSY); 814 return azx_single_wait_for_response(chip, addr); 815 } 816 udelay(1); 817 } 818 if (printk_ratelimit()) 819 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", 820 azx_readw(chip, IRS), val); 821 return -EIO; 822 } 823 824 /* receive a response */ 825 static unsigned int azx_single_get_response(struct hda_bus *bus, 826 unsigned int addr) 827 { 828 struct azx *chip = bus->private_data; 829 return chip->rirb.res[addr]; 830 } 831 832 /* 833 * The below are the main callbacks from hda_codec. 834 * 835 * They are just the skeleton to call sub-callbacks according to the 836 * current setting of chip->single_cmd. 837 */ 838 839 /* send a command */ 840 static int azx_send_cmd(struct hda_bus *bus, unsigned int val) 841 { 842 struct azx *chip = bus->private_data; 843 844 chip->last_cmd[azx_command_addr(val)] = val; 845 if (chip->single_cmd) 846 return azx_single_send_cmd(bus, val); 847 else 848 return azx_corb_send_cmd(bus, val); 849 } 850 851 /* get a response */ 852 static unsigned int azx_get_response(struct hda_bus *bus, 853 unsigned int addr) 854 { 855 struct azx *chip = bus->private_data; 856 if (chip->single_cmd) 857 return azx_single_get_response(bus, addr); 858 else 859 return azx_rirb_get_response(bus, addr); 860 } 861 862 #ifdef CONFIG_SND_HDA_POWER_SAVE 863 static void azx_power_notify(struct hda_bus *bus); 864 #endif 865 866 /* reset codec link */ 867 static int azx_reset(struct azx *chip, int full_reset) 868 { 869 int count; 870 871 if (!full_reset) 872 goto __skip; 873 874 /* clear STATESTS */ 875 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 876 877 /* reset controller */ 878 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 879 880 count = 50; 881 while (azx_readb(chip, GCTL) && --count) 882 msleep(1); 883 884 /* delay for >= 100us for codec PLL to settle per spec 885 * Rev 0.9 section 5.5.1 886 */ 887 msleep(1); 888 889 /* Bring controller out of reset */ 890 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 891 892 count = 50; 893 while (!azx_readb(chip, GCTL) && --count) 894 msleep(1); 895 896 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 897 msleep(1); 898 899 __skip: 900 /* check to see if controller is ready */ 901 if (!azx_readb(chip, GCTL)) { 902 snd_printd(SFX "azx_reset: controller not ready!\n"); 903 return -EBUSY; 904 } 905 906 /* Accept unsolicited responses */ 907 if (!chip->single_cmd) 908 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | 909 ICH6_GCTL_UNSOL); 910 911 /* detect codecs */ 912 if (!chip->codec_mask) { 913 chip->codec_mask = azx_readw(chip, STATESTS); 914 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask); 915 } 916 917 return 0; 918 } 919 920 921 /* 922 * Lowlevel interface 923 */ 924 925 /* enable interrupts */ 926 static void azx_int_enable(struct azx *chip) 927 { 928 /* enable controller CIE and GIE */ 929 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 930 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 931 } 932 933 /* disable interrupts */ 934 static void azx_int_disable(struct azx *chip) 935 { 936 int i; 937 938 /* disable interrupts in stream descriptor */ 939 for (i = 0; i < chip->num_streams; i++) { 940 struct azx_dev *azx_dev = &chip->azx_dev[i]; 941 azx_sd_writeb(azx_dev, SD_CTL, 942 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); 943 } 944 945 /* disable SIE for all streams */ 946 azx_writeb(chip, INTCTL, 0); 947 948 /* disable controller CIE and GIE */ 949 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 950 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 951 } 952 953 /* clear interrupts */ 954 static void azx_int_clear(struct azx *chip) 955 { 956 int i; 957 958 /* clear stream status */ 959 for (i = 0; i < chip->num_streams; i++) { 960 struct azx_dev *azx_dev = &chip->azx_dev[i]; 961 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 962 } 963 964 /* clear STATESTS */ 965 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 966 967 /* clear rirb status */ 968 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 969 970 /* clear int status */ 971 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 972 } 973 974 /* start a stream */ 975 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) 976 { 977 /* 978 * Before stream start, initialize parameter 979 */ 980 azx_dev->insufficient = 1; 981 982 /* enable SIE */ 983 azx_writel(chip, INTCTL, 984 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); 985 /* set DMA start and interrupt mask */ 986 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 987 SD_CTL_DMA_START | SD_INT_MASK); 988 } 989 990 /* stop DMA */ 991 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) 992 { 993 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 994 ~(SD_CTL_DMA_START | SD_INT_MASK)); 995 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 996 } 997 998 /* stop a stream */ 999 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) 1000 { 1001 azx_stream_clear(chip, azx_dev); 1002 /* disable SIE */ 1003 azx_writel(chip, INTCTL, 1004 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); 1005 } 1006 1007 1008 /* 1009 * reset and start the controller registers 1010 */ 1011 static void azx_init_chip(struct azx *chip, int full_reset) 1012 { 1013 if (chip->initialized) 1014 return; 1015 1016 /* reset controller */ 1017 azx_reset(chip, full_reset); 1018 1019 /* initialize interrupts */ 1020 azx_int_clear(chip); 1021 azx_int_enable(chip); 1022 1023 /* initialize the codec command I/O */ 1024 if (!chip->single_cmd) 1025 azx_init_cmd_io(chip); 1026 1027 /* program the position buffer */ 1028 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); 1029 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); 1030 1031 chip->initialized = 1; 1032 } 1033 1034 /* 1035 * initialize the PCI registers 1036 */ 1037 /* update bits in a PCI register byte */ 1038 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 1039 unsigned char mask, unsigned char val) 1040 { 1041 unsigned char data; 1042 1043 pci_read_config_byte(pci, reg, &data); 1044 data &= ~mask; 1045 data |= (val & mask); 1046 pci_write_config_byte(pci, reg, data); 1047 } 1048 1049 static void azx_init_pci(struct azx *chip) 1050 { 1051 unsigned short snoop; 1052 1053 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 1054 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 1055 * Ensuring these bits are 0 clears playback static on some HD Audio 1056 * codecs. 1057 * The PCI register TCSEL is defined in the Intel manuals. 1058 */ 1059 if (chip->driver_type != AZX_DRIVER_ATI && 1060 chip->driver_type != AZX_DRIVER_ATIHDMI) 1061 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); 1062 1063 switch (chip->driver_type) { 1064 case AZX_DRIVER_ATI: 1065 /* For ATI SB450 azalia HD audio, we need to enable snoop */ 1066 update_pci_byte(chip->pci, 1067 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 1068 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP); 1069 break; 1070 case AZX_DRIVER_NVIDIA: 1071 /* For NVIDIA HDA, enable snoop */ 1072 update_pci_byte(chip->pci, 1073 NVIDIA_HDA_TRANSREG_ADDR, 1074 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 1075 update_pci_byte(chip->pci, 1076 NVIDIA_HDA_ISTRM_COH, 1077 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1078 update_pci_byte(chip->pci, 1079 NVIDIA_HDA_OSTRM_COH, 1080 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1081 break; 1082 case AZX_DRIVER_SCH: 1083 case AZX_DRIVER_PCH: 1084 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 1085 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) { 1086 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, 1087 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP)); 1088 pci_read_config_word(chip->pci, 1089 INTEL_SCH_HDA_DEVC, &snoop); 1090 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n", 1091 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) 1092 ? "Failed" : "OK"); 1093 } 1094 break; 1095 default: 1096 /* AMD Hudson needs the similar snoop, as it seems... */ 1097 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1098 update_pci_byte(chip->pci, 1099 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 1100 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP); 1101 break; 1102 } 1103 } 1104 1105 1106 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 1107 1108 /* 1109 * interrupt handler 1110 */ 1111 static irqreturn_t azx_interrupt(int irq, void *dev_id) 1112 { 1113 struct azx *chip = dev_id; 1114 struct azx_dev *azx_dev; 1115 u32 status; 1116 u8 sd_status; 1117 int i, ok; 1118 1119 spin_lock(&chip->reg_lock); 1120 1121 status = azx_readl(chip, INTSTS); 1122 if (status == 0) { 1123 spin_unlock(&chip->reg_lock); 1124 return IRQ_NONE; 1125 } 1126 1127 for (i = 0; i < chip->num_streams; i++) { 1128 azx_dev = &chip->azx_dev[i]; 1129 if (status & azx_dev->sd_int_sta_mask) { 1130 sd_status = azx_sd_readb(azx_dev, SD_STS); 1131 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1132 if (!azx_dev->substream || !azx_dev->running || 1133 !(sd_status & SD_INT_COMPLETE)) 1134 continue; 1135 /* check whether this IRQ is really acceptable */ 1136 ok = azx_position_ok(chip, azx_dev); 1137 if (ok == 1) { 1138 azx_dev->irq_pending = 0; 1139 spin_unlock(&chip->reg_lock); 1140 snd_pcm_period_elapsed(azx_dev->substream); 1141 spin_lock(&chip->reg_lock); 1142 } else if (ok == 0 && chip->bus && chip->bus->workq) { 1143 /* bogus IRQ, process it later */ 1144 azx_dev->irq_pending = 1; 1145 queue_work(chip->bus->workq, 1146 &chip->irq_pending_work); 1147 } 1148 } 1149 } 1150 1151 /* clear rirb int */ 1152 status = azx_readb(chip, RIRBSTS); 1153 if (status & RIRB_INT_MASK) { 1154 if (status & RIRB_INT_RESPONSE) { 1155 if (chip->driver_type == AZX_DRIVER_CTX) 1156 udelay(80); 1157 azx_update_rirb(chip); 1158 } 1159 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1160 } 1161 1162 #if 0 1163 /* clear state status int */ 1164 if (azx_readb(chip, STATESTS) & 0x04) 1165 azx_writeb(chip, STATESTS, 0x04); 1166 #endif 1167 spin_unlock(&chip->reg_lock); 1168 1169 return IRQ_HANDLED; 1170 } 1171 1172 1173 /* 1174 * set up a BDL entry 1175 */ 1176 static int setup_bdle(struct snd_pcm_substream *substream, 1177 struct azx_dev *azx_dev, u32 **bdlp, 1178 int ofs, int size, int with_ioc) 1179 { 1180 u32 *bdl = *bdlp; 1181 1182 while (size > 0) { 1183 dma_addr_t addr; 1184 int chunk; 1185 1186 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 1187 return -EINVAL; 1188 1189 addr = snd_pcm_sgbuf_get_addr(substream, ofs); 1190 /* program the address field of the BDL entry */ 1191 bdl[0] = cpu_to_le32((u32)addr); 1192 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 1193 /* program the size field of the BDL entry */ 1194 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size); 1195 bdl[2] = cpu_to_le32(chunk); 1196 /* program the IOC to enable interrupt 1197 * only when the whole fragment is processed 1198 */ 1199 size -= chunk; 1200 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 1201 bdl += 4; 1202 azx_dev->frags++; 1203 ofs += chunk; 1204 } 1205 *bdlp = bdl; 1206 return ofs; 1207 } 1208 1209 /* 1210 * set up BDL entries 1211 */ 1212 static int azx_setup_periods(struct azx *chip, 1213 struct snd_pcm_substream *substream, 1214 struct azx_dev *azx_dev) 1215 { 1216 u32 *bdl; 1217 int i, ofs, periods, period_bytes; 1218 int pos_adj; 1219 1220 /* reset BDL address */ 1221 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1222 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1223 1224 period_bytes = azx_dev->period_bytes; 1225 periods = azx_dev->bufsize / period_bytes; 1226 1227 /* program the initial BDL entries */ 1228 bdl = (u32 *)azx_dev->bdl.area; 1229 ofs = 0; 1230 azx_dev->frags = 0; 1231 pos_adj = bdl_pos_adj[chip->dev_index]; 1232 if (pos_adj > 0) { 1233 struct snd_pcm_runtime *runtime = substream->runtime; 1234 int pos_align = pos_adj; 1235 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 1236 if (!pos_adj) 1237 pos_adj = pos_align; 1238 else 1239 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 1240 pos_align; 1241 pos_adj = frames_to_bytes(runtime, pos_adj); 1242 if (pos_adj >= period_bytes) { 1243 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n", 1244 bdl_pos_adj[chip->dev_index]); 1245 pos_adj = 0; 1246 } else { 1247 ofs = setup_bdle(substream, azx_dev, 1248 &bdl, ofs, pos_adj, 1249 !substream->runtime->no_period_wakeup); 1250 if (ofs < 0) 1251 goto error; 1252 } 1253 } else 1254 pos_adj = 0; 1255 for (i = 0; i < periods; i++) { 1256 if (i == periods - 1 && pos_adj) 1257 ofs = setup_bdle(substream, azx_dev, &bdl, ofs, 1258 period_bytes - pos_adj, 0); 1259 else 1260 ofs = setup_bdle(substream, azx_dev, &bdl, ofs, 1261 period_bytes, 1262 !substream->runtime->no_period_wakeup); 1263 if (ofs < 0) 1264 goto error; 1265 } 1266 return 0; 1267 1268 error: 1269 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n", 1270 azx_dev->bufsize, period_bytes); 1271 return -EINVAL; 1272 } 1273 1274 /* reset stream */ 1275 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) 1276 { 1277 unsigned char val; 1278 int timeout; 1279 1280 azx_stream_clear(chip, azx_dev); 1281 1282 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1283 SD_CTL_STREAM_RESET); 1284 udelay(3); 1285 timeout = 300; 1286 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1287 --timeout) 1288 ; 1289 val &= ~SD_CTL_STREAM_RESET; 1290 azx_sd_writeb(azx_dev, SD_CTL, val); 1291 udelay(3); 1292 1293 timeout = 300; 1294 /* waiting for hardware to report that the stream is out of reset */ 1295 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1296 --timeout) 1297 ; 1298 1299 /* reset first position - may not be synced with hw at this time */ 1300 *azx_dev->posbuf = 0; 1301 } 1302 1303 /* 1304 * set up the SD for streaming 1305 */ 1306 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) 1307 { 1308 /* make sure the run bit is zero for SD */ 1309 azx_stream_clear(chip, azx_dev); 1310 /* program the stream_tag */ 1311 azx_sd_writel(azx_dev, SD_CTL, 1312 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)| 1313 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); 1314 1315 /* program the length of samples in cyclic buffer */ 1316 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); 1317 1318 /* program the stream format */ 1319 /* this value needs to be the same as the one programmed */ 1320 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 1321 1322 /* program the stream LVI (last valid index) of the BDL */ 1323 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 1324 1325 /* program the BDL address */ 1326 /* lower BDL address */ 1327 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 1328 /* upper BDL address */ 1329 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); 1330 1331 /* enable the position buffer */ 1332 if (chip->position_fix[0] != POS_FIX_LPIB || 1333 chip->position_fix[1] != POS_FIX_LPIB) { 1334 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 1335 azx_writel(chip, DPLBASE, 1336 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 1337 } 1338 1339 /* set the interrupt enable bits in the descriptor control register */ 1340 azx_sd_writel(azx_dev, SD_CTL, 1341 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); 1342 1343 return 0; 1344 } 1345 1346 /* 1347 * Probe the given codec address 1348 */ 1349 static int probe_codec(struct azx *chip, int addr) 1350 { 1351 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 1352 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 1353 unsigned int res; 1354 1355 mutex_lock(&chip->bus->cmd_mutex); 1356 chip->probing = 1; 1357 azx_send_cmd(chip->bus, cmd); 1358 res = azx_get_response(chip->bus, addr); 1359 chip->probing = 0; 1360 mutex_unlock(&chip->bus->cmd_mutex); 1361 if (res == -1) 1362 return -EIO; 1363 snd_printdd(SFX "codec #%d probed OK\n", addr); 1364 return 0; 1365 } 1366 1367 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 1368 struct hda_pcm *cpcm); 1369 static void azx_stop_chip(struct azx *chip); 1370 1371 static void azx_bus_reset(struct hda_bus *bus) 1372 { 1373 struct azx *chip = bus->private_data; 1374 1375 bus->in_reset = 1; 1376 azx_stop_chip(chip); 1377 azx_init_chip(chip, 1); 1378 #ifdef CONFIG_PM 1379 if (chip->initialized) { 1380 int i; 1381 1382 for (i = 0; i < HDA_MAX_PCMS; i++) 1383 snd_pcm_suspend_all(chip->pcm[i]); 1384 snd_hda_suspend(chip->bus); 1385 snd_hda_resume(chip->bus); 1386 } 1387 #endif 1388 bus->in_reset = 0; 1389 } 1390 1391 /* 1392 * Codec initialization 1393 */ 1394 1395 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1396 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = { 1397 [AZX_DRIVER_NVIDIA] = 8, 1398 [AZX_DRIVER_TERA] = 1, 1399 }; 1400 1401 static int __devinit azx_codec_create(struct azx *chip, const char *model) 1402 { 1403 struct hda_bus_template bus_temp; 1404 int c, codecs, err; 1405 int max_slots; 1406 1407 memset(&bus_temp, 0, sizeof(bus_temp)); 1408 bus_temp.private_data = chip; 1409 bus_temp.modelname = model; 1410 bus_temp.pci = chip->pci; 1411 bus_temp.ops.command = azx_send_cmd; 1412 bus_temp.ops.get_response = azx_get_response; 1413 bus_temp.ops.attach_pcm = azx_attach_pcm_stream; 1414 bus_temp.ops.bus_reset = azx_bus_reset; 1415 #ifdef CONFIG_SND_HDA_POWER_SAVE 1416 bus_temp.power_save = &power_save; 1417 bus_temp.ops.pm_notify = azx_power_notify; 1418 #endif 1419 1420 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); 1421 if (err < 0) 1422 return err; 1423 1424 if (chip->driver_type == AZX_DRIVER_NVIDIA) 1425 chip->bus->needs_damn_long_delay = 1; 1426 1427 codecs = 0; 1428 max_slots = azx_max_codecs[chip->driver_type]; 1429 if (!max_slots) 1430 max_slots = AZX_DEFAULT_CODECS; 1431 1432 /* First try to probe all given codec slots */ 1433 for (c = 0; c < max_slots; c++) { 1434 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1435 if (probe_codec(chip, c) < 0) { 1436 /* Some BIOSen give you wrong codec addresses 1437 * that don't exist 1438 */ 1439 snd_printk(KERN_WARNING SFX 1440 "Codec #%d probe error; " 1441 "disabling it...\n", c); 1442 chip->codec_mask &= ~(1 << c); 1443 /* More badly, accessing to a non-existing 1444 * codec often screws up the controller chip, 1445 * and disturbs the further communications. 1446 * Thus if an error occurs during probing, 1447 * better to reset the controller chip to 1448 * get back to the sanity state. 1449 */ 1450 azx_stop_chip(chip); 1451 azx_init_chip(chip, 1); 1452 } 1453 } 1454 } 1455 1456 /* AMD chipsets often cause the communication stalls upon certain 1457 * sequence like the pin-detection. It seems that forcing the synced 1458 * access works around the stall. Grrr... 1459 */ 1460 if (chip->pci->vendor == PCI_VENDOR_ID_AMD || 1461 chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1462 snd_printk(KERN_INFO SFX "Enable sync_write for AMD chipset\n"); 1463 chip->bus->sync_write = 1; 1464 chip->bus->allow_bus_reset = 1; 1465 } 1466 1467 /* Then create codec instances */ 1468 for (c = 0; c < max_slots; c++) { 1469 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1470 struct hda_codec *codec; 1471 err = snd_hda_codec_new(chip->bus, c, &codec); 1472 if (err < 0) 1473 continue; 1474 codec->beep_mode = chip->beep_mode; 1475 codecs++; 1476 } 1477 } 1478 if (!codecs) { 1479 snd_printk(KERN_ERR SFX "no codecs initialized\n"); 1480 return -ENXIO; 1481 } 1482 return 0; 1483 } 1484 1485 /* configure each codec instance */ 1486 static int __devinit azx_codec_configure(struct azx *chip) 1487 { 1488 struct hda_codec *codec; 1489 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1490 snd_hda_codec_configure(codec); 1491 } 1492 return 0; 1493 } 1494 1495 1496 /* 1497 * PCM support 1498 */ 1499 1500 /* assign a stream for the PCM */ 1501 static inline struct azx_dev * 1502 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) 1503 { 1504 int dev, i, nums; 1505 struct azx_dev *res = NULL; 1506 1507 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1508 dev = chip->playback_index_offset; 1509 nums = chip->playback_streams; 1510 } else { 1511 dev = chip->capture_index_offset; 1512 nums = chip->capture_streams; 1513 } 1514 for (i = 0; i < nums; i++, dev++) 1515 if (!chip->azx_dev[dev].opened) { 1516 res = &chip->azx_dev[dev]; 1517 if (res->device == substream->pcm->device) 1518 break; 1519 } 1520 if (res) { 1521 res->opened = 1; 1522 res->device = substream->pcm->device; 1523 } 1524 return res; 1525 } 1526 1527 /* release the assigned stream */ 1528 static inline void azx_release_device(struct azx_dev *azx_dev) 1529 { 1530 azx_dev->opened = 0; 1531 } 1532 1533 static struct snd_pcm_hardware azx_pcm_hw = { 1534 .info = (SNDRV_PCM_INFO_MMAP | 1535 SNDRV_PCM_INFO_INTERLEAVED | 1536 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1537 SNDRV_PCM_INFO_MMAP_VALID | 1538 /* No full-resume yet implemented */ 1539 /* SNDRV_PCM_INFO_RESUME |*/ 1540 SNDRV_PCM_INFO_PAUSE | 1541 SNDRV_PCM_INFO_SYNC_START | 1542 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 1543 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1544 .rates = SNDRV_PCM_RATE_48000, 1545 .rate_min = 48000, 1546 .rate_max = 48000, 1547 .channels_min = 2, 1548 .channels_max = 2, 1549 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 1550 .period_bytes_min = 128, 1551 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 1552 .periods_min = 2, 1553 .periods_max = AZX_MAX_FRAG, 1554 .fifo_size = 0, 1555 }; 1556 1557 struct azx_pcm { 1558 struct azx *chip; 1559 struct hda_codec *codec; 1560 struct hda_pcm_stream *hinfo[2]; 1561 }; 1562 1563 static int azx_pcm_open(struct snd_pcm_substream *substream) 1564 { 1565 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1566 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1567 struct azx *chip = apcm->chip; 1568 struct azx_dev *azx_dev; 1569 struct snd_pcm_runtime *runtime = substream->runtime; 1570 unsigned long flags; 1571 int err; 1572 1573 mutex_lock(&chip->open_mutex); 1574 azx_dev = azx_assign_device(chip, substream); 1575 if (azx_dev == NULL) { 1576 mutex_unlock(&chip->open_mutex); 1577 return -EBUSY; 1578 } 1579 runtime->hw = azx_pcm_hw; 1580 runtime->hw.channels_min = hinfo->channels_min; 1581 runtime->hw.channels_max = hinfo->channels_max; 1582 runtime->hw.formats = hinfo->formats; 1583 runtime->hw.rates = hinfo->rates; 1584 snd_pcm_limit_hw_rates(runtime); 1585 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1586 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1587 128); 1588 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1589 128); 1590 snd_hda_power_up(apcm->codec); 1591 err = hinfo->ops.open(hinfo, apcm->codec, substream); 1592 if (err < 0) { 1593 azx_release_device(azx_dev); 1594 snd_hda_power_down(apcm->codec); 1595 mutex_unlock(&chip->open_mutex); 1596 return err; 1597 } 1598 snd_pcm_limit_hw_rates(runtime); 1599 /* sanity check */ 1600 if (snd_BUG_ON(!runtime->hw.channels_min) || 1601 snd_BUG_ON(!runtime->hw.channels_max) || 1602 snd_BUG_ON(!runtime->hw.formats) || 1603 snd_BUG_ON(!runtime->hw.rates)) { 1604 azx_release_device(azx_dev); 1605 hinfo->ops.close(hinfo, apcm->codec, substream); 1606 snd_hda_power_down(apcm->codec); 1607 mutex_unlock(&chip->open_mutex); 1608 return -EINVAL; 1609 } 1610 spin_lock_irqsave(&chip->reg_lock, flags); 1611 azx_dev->substream = substream; 1612 azx_dev->running = 0; 1613 spin_unlock_irqrestore(&chip->reg_lock, flags); 1614 1615 runtime->private_data = azx_dev; 1616 snd_pcm_set_sync(substream); 1617 mutex_unlock(&chip->open_mutex); 1618 return 0; 1619 } 1620 1621 static int azx_pcm_close(struct snd_pcm_substream *substream) 1622 { 1623 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1624 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1625 struct azx *chip = apcm->chip; 1626 struct azx_dev *azx_dev = get_azx_dev(substream); 1627 unsigned long flags; 1628 1629 mutex_lock(&chip->open_mutex); 1630 spin_lock_irqsave(&chip->reg_lock, flags); 1631 azx_dev->substream = NULL; 1632 azx_dev->running = 0; 1633 spin_unlock_irqrestore(&chip->reg_lock, flags); 1634 azx_release_device(azx_dev); 1635 hinfo->ops.close(hinfo, apcm->codec, substream); 1636 snd_hda_power_down(apcm->codec); 1637 mutex_unlock(&chip->open_mutex); 1638 return 0; 1639 } 1640 1641 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, 1642 struct snd_pcm_hw_params *hw_params) 1643 { 1644 struct azx_dev *azx_dev = get_azx_dev(substream); 1645 1646 azx_dev->bufsize = 0; 1647 azx_dev->period_bytes = 0; 1648 azx_dev->format_val = 0; 1649 return snd_pcm_lib_malloc_pages(substream, 1650 params_buffer_bytes(hw_params)); 1651 } 1652 1653 static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 1654 { 1655 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1656 struct azx_dev *azx_dev = get_azx_dev(substream); 1657 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1658 1659 /* reset BDL address */ 1660 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1661 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1662 azx_sd_writel(azx_dev, SD_CTL, 0); 1663 azx_dev->bufsize = 0; 1664 azx_dev->period_bytes = 0; 1665 azx_dev->format_val = 0; 1666 1667 snd_hda_codec_cleanup(apcm->codec, hinfo, substream); 1668 1669 return snd_pcm_lib_free_pages(substream); 1670 } 1671 1672 static int azx_pcm_prepare(struct snd_pcm_substream *substream) 1673 { 1674 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1675 struct azx *chip = apcm->chip; 1676 struct azx_dev *azx_dev = get_azx_dev(substream); 1677 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1678 struct snd_pcm_runtime *runtime = substream->runtime; 1679 unsigned int bufsize, period_bytes, format_val, stream_tag; 1680 int err; 1681 1682 azx_stream_reset(chip, azx_dev); 1683 format_val = snd_hda_calc_stream_format(runtime->rate, 1684 runtime->channels, 1685 runtime->format, 1686 hinfo->maxbps, 1687 apcm->codec->spdif_ctls); 1688 if (!format_val) { 1689 snd_printk(KERN_ERR SFX 1690 "invalid format_val, rate=%d, ch=%d, format=%d\n", 1691 runtime->rate, runtime->channels, runtime->format); 1692 return -EINVAL; 1693 } 1694 1695 bufsize = snd_pcm_lib_buffer_bytes(substream); 1696 period_bytes = snd_pcm_lib_period_bytes(substream); 1697 1698 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", 1699 bufsize, format_val); 1700 1701 if (bufsize != azx_dev->bufsize || 1702 period_bytes != azx_dev->period_bytes || 1703 format_val != azx_dev->format_val) { 1704 azx_dev->bufsize = bufsize; 1705 azx_dev->period_bytes = period_bytes; 1706 azx_dev->format_val = format_val; 1707 err = azx_setup_periods(chip, substream, azx_dev); 1708 if (err < 0) 1709 return err; 1710 } 1711 1712 /* wallclk has 24Mhz clock source */ 1713 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 1714 runtime->rate) * 1000); 1715 azx_setup_controller(chip, azx_dev); 1716 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1717 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 1718 else 1719 azx_dev->fifo_size = 0; 1720 1721 stream_tag = azx_dev->stream_tag; 1722 /* CA-IBG chips need the playback stream starting from 1 */ 1723 if (chip->driver_type == AZX_DRIVER_CTX && 1724 stream_tag > chip->capture_streams) 1725 stream_tag -= chip->capture_streams; 1726 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, 1727 azx_dev->format_val, substream); 1728 } 1729 1730 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1731 { 1732 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1733 struct azx *chip = apcm->chip; 1734 struct azx_dev *azx_dev; 1735 struct snd_pcm_substream *s; 1736 int rstart = 0, start, nsync = 0, sbits = 0; 1737 int nwait, timeout; 1738 1739 switch (cmd) { 1740 case SNDRV_PCM_TRIGGER_START: 1741 rstart = 1; 1742 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1743 case SNDRV_PCM_TRIGGER_RESUME: 1744 start = 1; 1745 break; 1746 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1747 case SNDRV_PCM_TRIGGER_SUSPEND: 1748 case SNDRV_PCM_TRIGGER_STOP: 1749 start = 0; 1750 break; 1751 default: 1752 return -EINVAL; 1753 } 1754 1755 snd_pcm_group_for_each_entry(s, substream) { 1756 if (s->pcm->card != substream->pcm->card) 1757 continue; 1758 azx_dev = get_azx_dev(s); 1759 sbits |= 1 << azx_dev->index; 1760 nsync++; 1761 snd_pcm_trigger_done(s, substream); 1762 } 1763 1764 spin_lock(&chip->reg_lock); 1765 if (nsync > 1) { 1766 /* first, set SYNC bits of corresponding streams */ 1767 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits); 1768 } 1769 snd_pcm_group_for_each_entry(s, substream) { 1770 if (s->pcm->card != substream->pcm->card) 1771 continue; 1772 azx_dev = get_azx_dev(s); 1773 if (start) { 1774 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); 1775 if (!rstart) 1776 azx_dev->start_wallclk -= 1777 azx_dev->period_wallclk; 1778 azx_stream_start(chip, azx_dev); 1779 } else { 1780 azx_stream_stop(chip, azx_dev); 1781 } 1782 azx_dev->running = start; 1783 } 1784 spin_unlock(&chip->reg_lock); 1785 if (start) { 1786 if (nsync == 1) 1787 return 0; 1788 /* wait until all FIFOs get ready */ 1789 for (timeout = 5000; timeout; timeout--) { 1790 nwait = 0; 1791 snd_pcm_group_for_each_entry(s, substream) { 1792 if (s->pcm->card != substream->pcm->card) 1793 continue; 1794 azx_dev = get_azx_dev(s); 1795 if (!(azx_sd_readb(azx_dev, SD_STS) & 1796 SD_STS_FIFO_READY)) 1797 nwait++; 1798 } 1799 if (!nwait) 1800 break; 1801 cpu_relax(); 1802 } 1803 } else { 1804 /* wait until all RUN bits are cleared */ 1805 for (timeout = 5000; timeout; timeout--) { 1806 nwait = 0; 1807 snd_pcm_group_for_each_entry(s, substream) { 1808 if (s->pcm->card != substream->pcm->card) 1809 continue; 1810 azx_dev = get_azx_dev(s); 1811 if (azx_sd_readb(azx_dev, SD_CTL) & 1812 SD_CTL_DMA_START) 1813 nwait++; 1814 } 1815 if (!nwait) 1816 break; 1817 cpu_relax(); 1818 } 1819 } 1820 if (nsync > 1) { 1821 spin_lock(&chip->reg_lock); 1822 /* reset SYNC bits */ 1823 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits); 1824 spin_unlock(&chip->reg_lock); 1825 } 1826 return 0; 1827 } 1828 1829 /* get the current DMA position with correction on VIA chips */ 1830 static unsigned int azx_via_get_position(struct azx *chip, 1831 struct azx_dev *azx_dev) 1832 { 1833 unsigned int link_pos, mini_pos, bound_pos; 1834 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 1835 unsigned int fifo_size; 1836 1837 link_pos = azx_sd_readl(azx_dev, SD_LPIB); 1838 if (azx_dev->index >= 4) { 1839 /* Playback, no problem using link position */ 1840 return link_pos; 1841 } 1842 1843 /* Capture */ 1844 /* For new chipset, 1845 * use mod to get the DMA position just like old chipset 1846 */ 1847 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 1848 mod_dma_pos %= azx_dev->period_bytes; 1849 1850 /* azx_dev->fifo_size can't get FIFO size of in stream. 1851 * Get from base address + offset. 1852 */ 1853 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 1854 1855 if (azx_dev->insufficient) { 1856 /* Link position never gather than FIFO size */ 1857 if (link_pos <= fifo_size) 1858 return 0; 1859 1860 azx_dev->insufficient = 0; 1861 } 1862 1863 if (link_pos <= fifo_size) 1864 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 1865 else 1866 mini_pos = link_pos - fifo_size; 1867 1868 /* Find nearest previous boudary */ 1869 mod_mini_pos = mini_pos % azx_dev->period_bytes; 1870 mod_link_pos = link_pos % azx_dev->period_bytes; 1871 if (mod_link_pos >= fifo_size) 1872 bound_pos = link_pos - mod_link_pos; 1873 else if (mod_dma_pos >= mod_mini_pos) 1874 bound_pos = mini_pos - mod_mini_pos; 1875 else { 1876 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 1877 if (bound_pos >= azx_dev->bufsize) 1878 bound_pos = 0; 1879 } 1880 1881 /* Calculate real DMA position we want */ 1882 return bound_pos + mod_dma_pos; 1883 } 1884 1885 static unsigned int azx_get_position(struct azx *chip, 1886 struct azx_dev *azx_dev) 1887 { 1888 unsigned int pos; 1889 int stream = azx_dev->substream->stream; 1890 1891 switch (chip->position_fix[stream]) { 1892 case POS_FIX_LPIB: 1893 /* read LPIB */ 1894 pos = azx_sd_readl(azx_dev, SD_LPIB); 1895 break; 1896 case POS_FIX_VIACOMBO: 1897 pos = azx_via_get_position(chip, azx_dev); 1898 break; 1899 default: 1900 /* use the position buffer */ 1901 pos = le32_to_cpu(*azx_dev->posbuf); 1902 } 1903 1904 if (pos >= azx_dev->bufsize) 1905 pos = 0; 1906 return pos; 1907 } 1908 1909 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 1910 { 1911 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1912 struct azx *chip = apcm->chip; 1913 struct azx_dev *azx_dev = get_azx_dev(substream); 1914 return bytes_to_frames(substream->runtime, 1915 azx_get_position(chip, azx_dev)); 1916 } 1917 1918 /* 1919 * Check whether the current DMA position is acceptable for updating 1920 * periods. Returns non-zero if it's OK. 1921 * 1922 * Many HD-audio controllers appear pretty inaccurate about 1923 * the update-IRQ timing. The IRQ is issued before actually the 1924 * data is processed. So, we need to process it afterwords in a 1925 * workqueue. 1926 */ 1927 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 1928 { 1929 u32 wallclk; 1930 unsigned int pos; 1931 int stream; 1932 1933 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 1934 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 1935 return -1; /* bogus (too early) interrupt */ 1936 1937 stream = azx_dev->substream->stream; 1938 pos = azx_get_position(chip, azx_dev); 1939 if (chip->position_fix[stream] == POS_FIX_AUTO) { 1940 if (!pos) { 1941 printk(KERN_WARNING 1942 "hda-intel: Invalid position buffer, " 1943 "using LPIB read method instead.\n"); 1944 chip->position_fix[stream] = POS_FIX_LPIB; 1945 pos = azx_get_position(chip, azx_dev); 1946 } else 1947 chip->position_fix[stream] = POS_FIX_POSBUF; 1948 } 1949 1950 if (WARN_ONCE(!azx_dev->period_bytes, 1951 "hda-intel: zero azx_dev->period_bytes")) 1952 return -1; /* this shouldn't happen! */ 1953 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 1954 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 1955 /* NG - it's below the first next period boundary */ 1956 return bdl_pos_adj[chip->dev_index] ? 0 : -1; 1957 azx_dev->start_wallclk += wallclk; 1958 return 1; /* OK, it's fine */ 1959 } 1960 1961 /* 1962 * The work for pending PCM period updates. 1963 */ 1964 static void azx_irq_pending_work(struct work_struct *work) 1965 { 1966 struct azx *chip = container_of(work, struct azx, irq_pending_work); 1967 int i, pending, ok; 1968 1969 if (!chip->irq_pending_warned) { 1970 printk(KERN_WARNING 1971 "hda-intel: IRQ timing workaround is activated " 1972 "for card #%d. Suggest a bigger bdl_pos_adj.\n", 1973 chip->card->number); 1974 chip->irq_pending_warned = 1; 1975 } 1976 1977 for (;;) { 1978 pending = 0; 1979 spin_lock_irq(&chip->reg_lock); 1980 for (i = 0; i < chip->num_streams; i++) { 1981 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1982 if (!azx_dev->irq_pending || 1983 !azx_dev->substream || 1984 !azx_dev->running) 1985 continue; 1986 ok = azx_position_ok(chip, azx_dev); 1987 if (ok > 0) { 1988 azx_dev->irq_pending = 0; 1989 spin_unlock(&chip->reg_lock); 1990 snd_pcm_period_elapsed(azx_dev->substream); 1991 spin_lock(&chip->reg_lock); 1992 } else if (ok < 0) { 1993 pending = 0; /* too early */ 1994 } else 1995 pending++; 1996 } 1997 spin_unlock_irq(&chip->reg_lock); 1998 if (!pending) 1999 return; 2000 msleep(1); 2001 } 2002 } 2003 2004 /* clear irq_pending flags and assure no on-going workq */ 2005 static void azx_clear_irq_pending(struct azx *chip) 2006 { 2007 int i; 2008 2009 spin_lock_irq(&chip->reg_lock); 2010 for (i = 0; i < chip->num_streams; i++) 2011 chip->azx_dev[i].irq_pending = 0; 2012 spin_unlock_irq(&chip->reg_lock); 2013 } 2014 2015 static struct snd_pcm_ops azx_pcm_ops = { 2016 .open = azx_pcm_open, 2017 .close = azx_pcm_close, 2018 .ioctl = snd_pcm_lib_ioctl, 2019 .hw_params = azx_pcm_hw_params, 2020 .hw_free = azx_pcm_hw_free, 2021 .prepare = azx_pcm_prepare, 2022 .trigger = azx_pcm_trigger, 2023 .pointer = azx_pcm_pointer, 2024 .page = snd_pcm_sgbuf_ops_page, 2025 }; 2026 2027 static void azx_pcm_free(struct snd_pcm *pcm) 2028 { 2029 struct azx_pcm *apcm = pcm->private_data; 2030 if (apcm) { 2031 apcm->chip->pcm[pcm->device] = NULL; 2032 kfree(apcm); 2033 } 2034 } 2035 2036 static int 2037 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 2038 struct hda_pcm *cpcm) 2039 { 2040 struct azx *chip = bus->private_data; 2041 struct snd_pcm *pcm; 2042 struct azx_pcm *apcm; 2043 int pcm_dev = cpcm->device; 2044 int s, err; 2045 2046 if (pcm_dev >= HDA_MAX_PCMS) { 2047 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n", 2048 pcm_dev); 2049 return -EINVAL; 2050 } 2051 if (chip->pcm[pcm_dev]) { 2052 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev); 2053 return -EBUSY; 2054 } 2055 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, 2056 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, 2057 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, 2058 &pcm); 2059 if (err < 0) 2060 return err; 2061 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); 2062 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); 2063 if (apcm == NULL) 2064 return -ENOMEM; 2065 apcm->chip = chip; 2066 apcm->codec = codec; 2067 pcm->private_data = apcm; 2068 pcm->private_free = azx_pcm_free; 2069 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) 2070 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 2071 chip->pcm[pcm_dev] = pcm; 2072 cpcm->pcm = pcm; 2073 for (s = 0; s < 2; s++) { 2074 apcm->hinfo[s] = &cpcm->stream[s]; 2075 if (cpcm->stream[s].substreams) 2076 snd_pcm_set_ops(pcm, s, &azx_pcm_ops); 2077 } 2078 /* buffer pre-allocation */ 2079 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 2080 snd_dma_pci_data(chip->pci), 2081 1024 * 64, 32 * 1024 * 1024); 2082 return 0; 2083 } 2084 2085 /* 2086 * mixer creation - all stuff is implemented in hda module 2087 */ 2088 static int __devinit azx_mixer_create(struct azx *chip) 2089 { 2090 return snd_hda_build_controls(chip->bus); 2091 } 2092 2093 2094 /* 2095 * initialize SD streams 2096 */ 2097 static int __devinit azx_init_stream(struct azx *chip) 2098 { 2099 int i; 2100 2101 /* initialize each stream (aka device) 2102 * assign the starting bdl address to each stream (device) 2103 * and initialize 2104 */ 2105 for (i = 0; i < chip->num_streams; i++) { 2106 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2107 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); 2108 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 2109 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); 2110 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 2111 azx_dev->sd_int_sta_mask = 1 << i; 2112 /* stream tag: must be non-zero and unique */ 2113 azx_dev->index = i; 2114 azx_dev->stream_tag = i + 1; 2115 } 2116 2117 return 0; 2118 } 2119 2120 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 2121 { 2122 if (request_irq(chip->pci->irq, azx_interrupt, 2123 chip->msi ? 0 : IRQF_SHARED, 2124 "hda_intel", chip)) { 2125 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " 2126 "disabling device\n", chip->pci->irq); 2127 if (do_disconnect) 2128 snd_card_disconnect(chip->card); 2129 return -1; 2130 } 2131 chip->irq = chip->pci->irq; 2132 pci_intx(chip->pci, !chip->msi); 2133 return 0; 2134 } 2135 2136 2137 static void azx_stop_chip(struct azx *chip) 2138 { 2139 if (!chip->initialized) 2140 return; 2141 2142 /* disable interrupts */ 2143 azx_int_disable(chip); 2144 azx_int_clear(chip); 2145 2146 /* disable CORB/RIRB */ 2147 azx_free_cmd_io(chip); 2148 2149 /* disable position buffer */ 2150 azx_writel(chip, DPLBASE, 0); 2151 azx_writel(chip, DPUBASE, 0); 2152 2153 chip->initialized = 0; 2154 } 2155 2156 #ifdef CONFIG_SND_HDA_POWER_SAVE 2157 /* power-up/down the controller */ 2158 static void azx_power_notify(struct hda_bus *bus) 2159 { 2160 struct azx *chip = bus->private_data; 2161 struct hda_codec *c; 2162 int power_on = 0; 2163 2164 list_for_each_entry(c, &bus->codec_list, list) { 2165 if (c->power_on) { 2166 power_on = 1; 2167 break; 2168 } 2169 } 2170 if (power_on) 2171 azx_init_chip(chip, 1); 2172 else if (chip->running && power_save_controller && 2173 !bus->power_keep_link_on) 2174 azx_stop_chip(chip); 2175 } 2176 #endif /* CONFIG_SND_HDA_POWER_SAVE */ 2177 2178 #ifdef CONFIG_PM 2179 /* 2180 * power management 2181 */ 2182 2183 static int snd_hda_codecs_inuse(struct hda_bus *bus) 2184 { 2185 struct hda_codec *codec; 2186 2187 list_for_each_entry(codec, &bus->codec_list, list) { 2188 if (snd_hda_codec_needs_resume(codec)) 2189 return 1; 2190 } 2191 return 0; 2192 } 2193 2194 static int azx_suspend(struct pci_dev *pci, pm_message_t state) 2195 { 2196 struct snd_card *card = pci_get_drvdata(pci); 2197 struct azx *chip = card->private_data; 2198 int i; 2199 2200 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2201 azx_clear_irq_pending(chip); 2202 for (i = 0; i < HDA_MAX_PCMS; i++) 2203 snd_pcm_suspend_all(chip->pcm[i]); 2204 if (chip->initialized) 2205 snd_hda_suspend(chip->bus); 2206 azx_stop_chip(chip); 2207 if (chip->irq >= 0) { 2208 free_irq(chip->irq, chip); 2209 chip->irq = -1; 2210 } 2211 if (chip->msi) 2212 pci_disable_msi(chip->pci); 2213 pci_disable_device(pci); 2214 pci_save_state(pci); 2215 pci_set_power_state(pci, pci_choose_state(pci, state)); 2216 return 0; 2217 } 2218 2219 static int azx_resume(struct pci_dev *pci) 2220 { 2221 struct snd_card *card = pci_get_drvdata(pci); 2222 struct azx *chip = card->private_data; 2223 2224 pci_set_power_state(pci, PCI_D0); 2225 pci_restore_state(pci); 2226 if (pci_enable_device(pci) < 0) { 2227 printk(KERN_ERR "hda-intel: pci_enable_device failed, " 2228 "disabling device\n"); 2229 snd_card_disconnect(card); 2230 return -EIO; 2231 } 2232 pci_set_master(pci); 2233 if (chip->msi) 2234 if (pci_enable_msi(pci) < 0) 2235 chip->msi = 0; 2236 if (azx_acquire_irq(chip, 1) < 0) 2237 return -EIO; 2238 azx_init_pci(chip); 2239 2240 if (snd_hda_codecs_inuse(chip->bus)) 2241 azx_init_chip(chip, 1); 2242 2243 snd_hda_resume(chip->bus); 2244 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2245 return 0; 2246 } 2247 #endif /* CONFIG_PM */ 2248 2249 2250 /* 2251 * reboot notifier for hang-up problem at power-down 2252 */ 2253 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) 2254 { 2255 struct azx *chip = container_of(nb, struct azx, reboot_notifier); 2256 snd_hda_bus_reboot_notify(chip->bus); 2257 azx_stop_chip(chip); 2258 return NOTIFY_OK; 2259 } 2260 2261 static void azx_notifier_register(struct azx *chip) 2262 { 2263 chip->reboot_notifier.notifier_call = azx_halt; 2264 register_reboot_notifier(&chip->reboot_notifier); 2265 } 2266 2267 static void azx_notifier_unregister(struct azx *chip) 2268 { 2269 if (chip->reboot_notifier.notifier_call) 2270 unregister_reboot_notifier(&chip->reboot_notifier); 2271 } 2272 2273 /* 2274 * destructor 2275 */ 2276 static int azx_free(struct azx *chip) 2277 { 2278 int i; 2279 2280 azx_notifier_unregister(chip); 2281 2282 if (chip->initialized) { 2283 azx_clear_irq_pending(chip); 2284 for (i = 0; i < chip->num_streams; i++) 2285 azx_stream_stop(chip, &chip->azx_dev[i]); 2286 azx_stop_chip(chip); 2287 } 2288 2289 if (chip->irq >= 0) 2290 free_irq(chip->irq, (void*)chip); 2291 if (chip->msi) 2292 pci_disable_msi(chip->pci); 2293 if (chip->remap_addr) 2294 iounmap(chip->remap_addr); 2295 2296 if (chip->azx_dev) { 2297 for (i = 0; i < chip->num_streams; i++) 2298 if (chip->azx_dev[i].bdl.area) 2299 snd_dma_free_pages(&chip->azx_dev[i].bdl); 2300 } 2301 if (chip->rb.area) 2302 snd_dma_free_pages(&chip->rb); 2303 if (chip->posbuf.area) 2304 snd_dma_free_pages(&chip->posbuf); 2305 pci_release_regions(chip->pci); 2306 pci_disable_device(chip->pci); 2307 kfree(chip->azx_dev); 2308 kfree(chip); 2309 2310 return 0; 2311 } 2312 2313 static int azx_dev_free(struct snd_device *device) 2314 { 2315 return azx_free(device->device_data); 2316 } 2317 2318 /* 2319 * white/black-listing for position_fix 2320 */ 2321 static struct snd_pci_quirk position_fix_list[] __devinitdata = { 2322 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB), 2323 SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB), 2324 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 2325 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 2326 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB), 2327 SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB), 2328 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 2329 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 2330 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 2331 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 2332 SND_PCI_QUIRK(0x1043, 0x8410, "ASUS", POS_FIX_LPIB), 2333 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 2334 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB), 2335 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB), 2336 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 2337 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 2338 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 2339 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB), 2340 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 2341 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 2342 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 2343 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB), 2344 {} 2345 }; 2346 2347 static int __devinit check_position_fix(struct azx *chip, int fix) 2348 { 2349 const struct snd_pci_quirk *q; 2350 2351 switch (fix) { 2352 case POS_FIX_LPIB: 2353 case POS_FIX_POSBUF: 2354 case POS_FIX_VIACOMBO: 2355 return fix; 2356 } 2357 2358 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 2359 if (q) { 2360 printk(KERN_INFO 2361 "hda_intel: position_fix set to %d " 2362 "for device %04x:%04x\n", 2363 q->value, q->subvendor, q->subdevice); 2364 return q->value; 2365 } 2366 2367 /* Check VIA/ATI HD Audio Controller exist */ 2368 switch (chip->driver_type) { 2369 case AZX_DRIVER_VIA: 2370 /* Use link position directly, avoid any transfer problem. */ 2371 return POS_FIX_VIACOMBO; 2372 case AZX_DRIVER_ATI: 2373 /* ATI chipsets don't work well with position-buffer */ 2374 return POS_FIX_LPIB; 2375 case AZX_DRIVER_GENERIC: 2376 /* AMD chipsets also don't work with position-buffer */ 2377 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 2378 return POS_FIX_LPIB; 2379 break; 2380 } 2381 2382 return POS_FIX_AUTO; 2383 } 2384 2385 /* 2386 * black-lists for probe_mask 2387 */ 2388 static struct snd_pci_quirk probe_mask_list[] __devinitdata = { 2389 /* Thinkpad often breaks the controller communication when accessing 2390 * to the non-working (or non-existing) modem codec slot. 2391 */ 2392 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 2393 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 2394 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 2395 /* broken BIOS */ 2396 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 2397 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 2398 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 2399 /* forced codec slots */ 2400 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 2401 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 2402 {} 2403 }; 2404 2405 #define AZX_FORCE_CODEC_MASK 0x100 2406 2407 static void __devinit check_probe_mask(struct azx *chip, int dev) 2408 { 2409 const struct snd_pci_quirk *q; 2410 2411 chip->codec_probe_mask = probe_mask[dev]; 2412 if (chip->codec_probe_mask == -1) { 2413 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 2414 if (q) { 2415 printk(KERN_INFO 2416 "hda_intel: probe_mask set to 0x%x " 2417 "for device %04x:%04x\n", 2418 q->value, q->subvendor, q->subdevice); 2419 chip->codec_probe_mask = q->value; 2420 } 2421 } 2422 2423 /* check forced option */ 2424 if (chip->codec_probe_mask != -1 && 2425 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 2426 chip->codec_mask = chip->codec_probe_mask & 0xff; 2427 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", 2428 chip->codec_mask); 2429 } 2430 } 2431 2432 /* 2433 * white/black-list for enable_msi 2434 */ 2435 static struct snd_pci_quirk msi_black_list[] __devinitdata = { 2436 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 2437 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 2438 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 2439 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 2440 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 2441 {} 2442 }; 2443 2444 static void __devinit check_msi(struct azx *chip) 2445 { 2446 const struct snd_pci_quirk *q; 2447 2448 if (enable_msi >= 0) { 2449 chip->msi = !!enable_msi; 2450 return; 2451 } 2452 chip->msi = 1; /* enable MSI as default */ 2453 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 2454 if (q) { 2455 printk(KERN_INFO 2456 "hda_intel: msi for device %04x:%04x set to %d\n", 2457 q->subvendor, q->subdevice, q->value); 2458 chip->msi = q->value; 2459 return; 2460 } 2461 2462 /* NVidia chipsets seem to cause troubles with MSI */ 2463 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 2464 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n"); 2465 chip->msi = 0; 2466 } 2467 } 2468 2469 2470 /* 2471 * constructor 2472 */ 2473 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, 2474 int dev, int driver_type, 2475 struct azx **rchip) 2476 { 2477 struct azx *chip; 2478 int i, err; 2479 unsigned short gcap; 2480 static struct snd_device_ops ops = { 2481 .dev_free = azx_dev_free, 2482 }; 2483 2484 *rchip = NULL; 2485 2486 err = pci_enable_device(pci); 2487 if (err < 0) 2488 return err; 2489 2490 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2491 if (!chip) { 2492 snd_printk(KERN_ERR SFX "cannot allocate chip\n"); 2493 pci_disable_device(pci); 2494 return -ENOMEM; 2495 } 2496 2497 spin_lock_init(&chip->reg_lock); 2498 mutex_init(&chip->open_mutex); 2499 chip->card = card; 2500 chip->pci = pci; 2501 chip->irq = -1; 2502 chip->driver_type = driver_type; 2503 check_msi(chip); 2504 chip->dev_index = dev; 2505 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); 2506 2507 chip->position_fix[0] = chip->position_fix[1] = 2508 check_position_fix(chip, position_fix[dev]); 2509 check_probe_mask(chip, dev); 2510 2511 chip->single_cmd = single_cmd; 2512 2513 if (bdl_pos_adj[dev] < 0) { 2514 switch (chip->driver_type) { 2515 case AZX_DRIVER_ICH: 2516 case AZX_DRIVER_PCH: 2517 bdl_pos_adj[dev] = 1; 2518 break; 2519 default: 2520 bdl_pos_adj[dev] = 32; 2521 break; 2522 } 2523 } 2524 2525 #if BITS_PER_LONG != 64 2526 /* Fix up base address on ULI M5461 */ 2527 if (chip->driver_type == AZX_DRIVER_ULI) { 2528 u16 tmp3; 2529 pci_read_config_word(pci, 0x40, &tmp3); 2530 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 2531 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 2532 } 2533 #endif 2534 2535 err = pci_request_regions(pci, "ICH HD audio"); 2536 if (err < 0) { 2537 kfree(chip); 2538 pci_disable_device(pci); 2539 return err; 2540 } 2541 2542 chip->addr = pci_resource_start(pci, 0); 2543 chip->remap_addr = pci_ioremap_bar(pci, 0); 2544 if (chip->remap_addr == NULL) { 2545 snd_printk(KERN_ERR SFX "ioremap error\n"); 2546 err = -ENXIO; 2547 goto errout; 2548 } 2549 2550 if (chip->msi) 2551 if (pci_enable_msi(pci) < 0) 2552 chip->msi = 0; 2553 2554 if (azx_acquire_irq(chip, 0) < 0) { 2555 err = -EBUSY; 2556 goto errout; 2557 } 2558 2559 pci_set_master(pci); 2560 synchronize_irq(chip->irq); 2561 2562 gcap = azx_readw(chip, GCAP); 2563 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap); 2564 2565 /* disable SB600 64bit support for safety */ 2566 if ((chip->driver_type == AZX_DRIVER_ATI) || 2567 (chip->driver_type == AZX_DRIVER_ATIHDMI)) { 2568 struct pci_dev *p_smbus; 2569 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 2570 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 2571 NULL); 2572 if (p_smbus) { 2573 if (p_smbus->revision < 0x30) 2574 gcap &= ~ICH6_GCAP_64OK; 2575 pci_dev_put(p_smbus); 2576 } 2577 } else { 2578 /* FIXME: not sure whether this is really needed, but 2579 * Hudson isn't stable enough for allowing everything... 2580 * let's check later again. 2581 */ 2582 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 2583 gcap &= ~ICH6_GCAP_64OK; 2584 } 2585 2586 /* disable 64bit DMA address for Teradici */ 2587 /* it does not work with device 6549:1200 subsys e4a2:040b */ 2588 if (chip->driver_type == AZX_DRIVER_TERA) 2589 gcap &= ~ICH6_GCAP_64OK; 2590 2591 /* allow 64bit DMA address if supported by H/W */ 2592 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 2593 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 2594 else { 2595 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 2596 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 2597 } 2598 2599 /* read number of streams from GCAP register instead of using 2600 * hardcoded value 2601 */ 2602 chip->capture_streams = (gcap >> 8) & 0x0f; 2603 chip->playback_streams = (gcap >> 12) & 0x0f; 2604 if (!chip->playback_streams && !chip->capture_streams) { 2605 /* gcap didn't give any info, switching to old method */ 2606 2607 switch (chip->driver_type) { 2608 case AZX_DRIVER_ULI: 2609 chip->playback_streams = ULI_NUM_PLAYBACK; 2610 chip->capture_streams = ULI_NUM_CAPTURE; 2611 break; 2612 case AZX_DRIVER_ATIHDMI: 2613 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 2614 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 2615 break; 2616 case AZX_DRIVER_GENERIC: 2617 default: 2618 chip->playback_streams = ICH6_NUM_PLAYBACK; 2619 chip->capture_streams = ICH6_NUM_CAPTURE; 2620 break; 2621 } 2622 } 2623 chip->capture_index_offset = 0; 2624 chip->playback_index_offset = chip->capture_streams; 2625 chip->num_streams = chip->playback_streams + chip->capture_streams; 2626 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 2627 GFP_KERNEL); 2628 if (!chip->azx_dev) { 2629 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n"); 2630 goto errout; 2631 } 2632 2633 for (i = 0; i < chip->num_streams; i++) { 2634 /* allocate memory for the BDL for each stream */ 2635 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 2636 snd_dma_pci_data(chip->pci), 2637 BDL_SIZE, &chip->azx_dev[i].bdl); 2638 if (err < 0) { 2639 snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); 2640 goto errout; 2641 } 2642 } 2643 /* allocate memory for the position buffer */ 2644 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 2645 snd_dma_pci_data(chip->pci), 2646 chip->num_streams * 8, &chip->posbuf); 2647 if (err < 0) { 2648 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); 2649 goto errout; 2650 } 2651 /* allocate CORB/RIRB */ 2652 err = azx_alloc_cmd_io(chip); 2653 if (err < 0) 2654 goto errout; 2655 2656 /* initialize streams */ 2657 azx_init_stream(chip); 2658 2659 /* initialize chip */ 2660 azx_init_pci(chip); 2661 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 2662 2663 /* codec detection */ 2664 if (!chip->codec_mask) { 2665 snd_printk(KERN_ERR SFX "no codecs found!\n"); 2666 err = -ENODEV; 2667 goto errout; 2668 } 2669 2670 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 2671 if (err <0) { 2672 snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); 2673 goto errout; 2674 } 2675 2676 strcpy(card->driver, "HDA-Intel"); 2677 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2678 sizeof(card->shortname)); 2679 snprintf(card->longname, sizeof(card->longname), 2680 "%s at 0x%lx irq %i", 2681 card->shortname, chip->addr, chip->irq); 2682 2683 *rchip = chip; 2684 return 0; 2685 2686 errout: 2687 azx_free(chip); 2688 return err; 2689 } 2690 2691 static void power_down_all_codecs(struct azx *chip) 2692 { 2693 #ifdef CONFIG_SND_HDA_POWER_SAVE 2694 /* The codecs were powered up in snd_hda_codec_new(). 2695 * Now all initialization done, so turn them down if possible 2696 */ 2697 struct hda_codec *codec; 2698 list_for_each_entry(codec, &chip->bus->codec_list, list) { 2699 snd_hda_power_down(codec); 2700 } 2701 #endif 2702 } 2703 2704 static int __devinit azx_probe(struct pci_dev *pci, 2705 const struct pci_device_id *pci_id) 2706 { 2707 static int dev; 2708 struct snd_card *card; 2709 struct azx *chip; 2710 int err; 2711 2712 if (dev >= SNDRV_CARDS) 2713 return -ENODEV; 2714 if (!enable[dev]) { 2715 dev++; 2716 return -ENOENT; 2717 } 2718 2719 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 2720 if (err < 0) { 2721 snd_printk(KERN_ERR SFX "Error creating card!\n"); 2722 return err; 2723 } 2724 2725 /* set this here since it's referred in snd_hda_load_patch() */ 2726 snd_card_set_dev(card, &pci->dev); 2727 2728 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2729 if (err < 0) 2730 goto out_free; 2731 card->private_data = chip; 2732 2733 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2734 chip->beep_mode = beep_mode[dev]; 2735 #endif 2736 2737 /* create codec instances */ 2738 err = azx_codec_create(chip, model[dev]); 2739 if (err < 0) 2740 goto out_free; 2741 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2742 if (patch[dev] && *patch[dev]) { 2743 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n", 2744 patch[dev]); 2745 err = snd_hda_load_patch(chip->bus, patch[dev]); 2746 if (err < 0) 2747 goto out_free; 2748 } 2749 #endif 2750 if ((probe_only[dev] & 1) == 0) { 2751 err = azx_codec_configure(chip); 2752 if (err < 0) 2753 goto out_free; 2754 } 2755 2756 /* create PCM streams */ 2757 err = snd_hda_build_pcms(chip->bus); 2758 if (err < 0) 2759 goto out_free; 2760 2761 /* create mixer controls */ 2762 err = azx_mixer_create(chip); 2763 if (err < 0) 2764 goto out_free; 2765 2766 err = snd_card_register(card); 2767 if (err < 0) 2768 goto out_free; 2769 2770 pci_set_drvdata(pci, card); 2771 chip->running = 1; 2772 power_down_all_codecs(chip); 2773 azx_notifier_register(chip); 2774 2775 dev++; 2776 return err; 2777 out_free: 2778 snd_card_free(card); 2779 return err; 2780 } 2781 2782 static void __devexit azx_remove(struct pci_dev *pci) 2783 { 2784 snd_card_free(pci_get_drvdata(pci)); 2785 pci_set_drvdata(pci, NULL); 2786 } 2787 2788 /* PCI IDs */ 2789 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { 2790 /* CPT */ 2791 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH }, 2792 /* PBG */ 2793 { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH }, 2794 /* Panther Point */ 2795 { PCI_DEVICE(0x8086, 0x1e20), .driver_data = AZX_DRIVER_PCH }, 2796 /* SCH */ 2797 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH }, 2798 /* Generic Intel */ 2799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2800 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2801 .class_mask = 0xffffff, 2802 .driver_data = AZX_DRIVER_ICH }, 2803 /* ATI SB 450/600 */ 2804 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI }, 2805 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI }, 2806 /* ATI HDMI */ 2807 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI }, 2808 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI }, 2809 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI }, 2810 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI }, 2811 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI }, 2812 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI }, 2813 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI }, 2814 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI }, 2815 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI }, 2816 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI }, 2817 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI }, 2818 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI }, 2819 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI }, 2820 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI }, 2821 /* VIA VT8251/VT8237A */ 2822 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2823 /* SIS966 */ 2824 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2825 /* ULI M5461 */ 2826 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2827 /* NVIDIA MCP */ 2828 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2829 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2830 .class_mask = 0xffffff, 2831 .driver_data = AZX_DRIVER_NVIDIA }, 2832 /* Teradici */ 2833 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA }, 2834 /* Creative X-Fi (CA0110-IBG) */ 2835 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE) 2836 /* the following entry conflicts with snd-ctxfi driver, 2837 * as ctxfi driver mutates from HD-audio to native mode with 2838 * a special command sequence. 2839 */ 2840 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2841 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2842 .class_mask = 0xffffff, 2843 .driver_data = AZX_DRIVER_CTX }, 2844 #else 2845 /* this entry seems still valid -- i.e. without emu20kx chip */ 2846 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX }, 2847 #endif 2848 /* Vortex86MX */ 2849 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2850 /* VMware HDAudio */ 2851 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2852 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2853 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2854 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2855 .class_mask = 0xffffff, 2856 .driver_data = AZX_DRIVER_GENERIC }, 2857 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2858 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2859 .class_mask = 0xffffff, 2860 .driver_data = AZX_DRIVER_GENERIC }, 2861 { 0, } 2862 }; 2863 MODULE_DEVICE_TABLE(pci, azx_ids); 2864 2865 /* pci_driver definition */ 2866 static struct pci_driver driver = { 2867 .name = "HDA Intel", 2868 .id_table = azx_ids, 2869 .probe = azx_probe, 2870 .remove = __devexit_p(azx_remove), 2871 #ifdef CONFIG_PM 2872 .suspend = azx_suspend, 2873 .resume = azx_resume, 2874 #endif 2875 }; 2876 2877 static int __init alsa_card_azx_init(void) 2878 { 2879 return pci_register_driver(&driver); 2880 } 2881 2882 static void __exit alsa_card_azx_exit(void) 2883 { 2884 pci_unregister_driver(&driver); 2885 } 2886 2887 module_init(alsa_card_azx_init) 2888 module_exit(alsa_card_azx_exit) 2889