1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* Define VIA HD Audio Device ID*/ 90 #define VIA_HDAC_DEVICE_ID 0x3288 91 92 /* max number of SDs */ 93 /* ICH, ATI and VIA have 4 playback and 4 capture */ 94 #define ICH6_NUM_CAPTURE 4 95 #define ICH6_NUM_PLAYBACK 4 96 97 /* ULI has 6 playback and 5 capture */ 98 #define ULI_NUM_CAPTURE 5 99 #define ULI_NUM_PLAYBACK 6 100 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 102 #define ATIHDMI_NUM_CAPTURE 0 103 #define ATIHDMI_NUM_PLAYBACK 8 104 105 /* TERA has 4 playback and 3 capture */ 106 #define TERA_NUM_CAPTURE 3 107 #define TERA_NUM_PLAYBACK 4 108 109 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113 static char *model[SNDRV_CARDS]; 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117 static int probe_only[SNDRV_CARDS]; 118 static int jackpoll_ms[SNDRV_CARDS]; 119 static int single_cmd = -1; 120 static int enable_msi = -1; 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER 122 static char *patch[SNDRV_CARDS]; 123 #endif 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127 #endif 128 static bool dmic_detect = 1; 129 130 module_param_array(index, int, NULL, 0444); 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132 module_param_array(id, charp, NULL, 0444); 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134 module_param_array(enable, bool, NULL, 0444); 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136 module_param_array(model, charp, NULL, 0444); 137 MODULE_PARM_DESC(model, "Use the given board model."); 138 module_param_array(position_fix, int, NULL, 0444); 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141 module_param_array(bdl_pos_adj, int, NULL, 0644); 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143 module_param_array(probe_mask, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145 module_param_array(probe_only, int, NULL, 0444); 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147 module_param_array(jackpoll_ms, int, NULL, 0444); 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149 module_param(single_cmd, bint, 0444); 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152 module_param(enable_msi, bint, 0444); 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER 155 module_param_array(patch, charp, NULL, 0444); 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157 #endif 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP 159 module_param_array(beep_mode, bool, NULL, 0444); 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162 #endif 163 module_param(dmic_detect, bool, 0444); 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1); " 166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 167 168 #ifdef CONFIG_PM 169 static int param_set_xint(const char *val, const struct kernel_param *kp); 170 static const struct kernel_param_ops param_ops_xint = { 171 .set = param_set_xint, 172 .get = param_get_int, 173 }; 174 #define param_check_xint param_check_int 175 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 177 module_param(power_save, xint, 0644); 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 179 "(in second, 0 = disable)."); 180 181 static bool pm_blacklist = true; 182 module_param(pm_blacklist, bool, 0644); 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 184 185 /* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189 static bool power_save_controller = 1; 190 module_param(power_save_controller, bool, 0644); 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192 #else 193 #define power_save 0 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 212 "{Intel, ICH6M}," 213 "{Intel, ICH7}," 214 "{Intel, ESB2}," 215 "{Intel, ICH8}," 216 "{Intel, ICH9}," 217 "{Intel, ICH10}," 218 "{Intel, PCH}," 219 "{Intel, CPT}," 220 "{Intel, PPT}," 221 "{Intel, LPT}," 222 "{Intel, LPT_LP}," 223 "{Intel, WPT_LP}," 224 "{Intel, SPT}," 225 "{Intel, SPT_LP}," 226 "{Intel, HPT}," 227 "{Intel, PBG}," 228 "{Intel, SCH}," 229 "{ATI, SB450}," 230 "{ATI, SB600}," 231 "{ATI, RS600}," 232 "{ATI, RS690}," 233 "{ATI, RS780}," 234 "{ATI, R600}," 235 "{ATI, RV630}," 236 "{ATI, RV610}," 237 "{ATI, RV670}," 238 "{ATI, RV635}," 239 "{ATI, RV620}," 240 "{ATI, RV770}," 241 "{VIA, VT8251}," 242 "{VIA, VT8237A}," 243 "{SiS, SIS966}," 244 "{ULI, M5461}}"); 245 MODULE_DESCRIPTION("Intel HDA driver"); 246 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 249 #define SUPPORT_VGA_SWITCHEROO 250 #endif 251 #endif 252 253 254 /* 255 */ 256 257 /* driver types */ 258 enum { 259 AZX_DRIVER_ICH, 260 AZX_DRIVER_PCH, 261 AZX_DRIVER_SCH, 262 AZX_DRIVER_SKL, 263 AZX_DRIVER_HDMI, 264 AZX_DRIVER_ATI, 265 AZX_DRIVER_ATIHDMI, 266 AZX_DRIVER_ATIHDMI_NS, 267 AZX_DRIVER_VIA, 268 AZX_DRIVER_SIS, 269 AZX_DRIVER_ULI, 270 AZX_DRIVER_NVIDIA, 271 AZX_DRIVER_TERA, 272 AZX_DRIVER_CTX, 273 AZX_DRIVER_CTHDA, 274 AZX_DRIVER_CMEDIA, 275 AZX_DRIVER_ZHAOXIN, 276 AZX_DRIVER_GENERIC, 277 AZX_NUM_DRIVERS, /* keep this as last entry */ 278 }; 279 280 #define azx_get_snoop_type(chip) \ 281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 283 284 /* quirks for old Intel chipsets */ 285 #define AZX_DCAPS_INTEL_ICH \ 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\ 287 AZX_DCAPS_SYNC_WRITE) 288 289 /* quirks for Intel PCH */ 290 #define AZX_DCAPS_INTEL_PCH_BASE \ 291 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 292 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 293 294 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 295 #define AZX_DCAPS_INTEL_PCH_NOPM \ 296 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 297 298 /* PCH for HSW/BDW; with runtime PM */ 299 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 300 #define AZX_DCAPS_INTEL_PCH \ 301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 302 AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP) 303 304 /* HSW HDMI */ 305 #define AZX_DCAPS_INTEL_HASWELL \ 306 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 307 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 308 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 309 310 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 311 #define AZX_DCAPS_INTEL_BROADWELL \ 312 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 313 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 314 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 315 316 #define AZX_DCAPS_INTEL_BAYTRAIL \ 317 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 318 319 #define AZX_DCAPS_INTEL_BRASWELL \ 320 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 321 AZX_DCAPS_I915_COMPONENT) 322 323 #define AZX_DCAPS_INTEL_SKYLAKE \ 324 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 325 AZX_DCAPS_SYNC_WRITE |\ 326 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 327 328 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 329 330 /* quirks for ATI SB / AMD Hudson */ 331 #define AZX_DCAPS_PRESET_ATI_SB \ 332 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 333 AZX_DCAPS_SNOOP_TYPE(ATI)) 334 335 /* quirks for ATI/AMD HDMI */ 336 #define AZX_DCAPS_PRESET_ATI_HDMI \ 337 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 338 AZX_DCAPS_NO_MSI64) 339 340 /* quirks for ATI HDMI with snoop off */ 341 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 342 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 343 344 /* quirks for AMD SB */ 345 #define AZX_DCAPS_PRESET_AMD_SB \ 346 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\ 347 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) 348 349 /* quirks for Nvidia */ 350 #define AZX_DCAPS_PRESET_NVIDIA \ 351 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 352 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 353 354 #define AZX_DCAPS_PRESET_CTHDA \ 355 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 356 AZX_DCAPS_NO_64BIT |\ 357 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 358 359 /* 360 * vga_switcheroo support 361 */ 362 #ifdef SUPPORT_VGA_SWITCHEROO 363 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 364 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 365 #else 366 #define use_vga_switcheroo(chip) 0 367 #define needs_eld_notify_link(chip) false 368 #endif 369 370 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 371 ((pci)->device == 0x0c0c) || \ 372 ((pci)->device == 0x0d0c) || \ 373 ((pci)->device == 0x160c)) 374 375 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 376 377 static const char * const driver_short_names[] = { 378 [AZX_DRIVER_ICH] = "HDA Intel", 379 [AZX_DRIVER_PCH] = "HDA Intel PCH", 380 [AZX_DRIVER_SCH] = "HDA Intel MID", 381 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 382 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 383 [AZX_DRIVER_ATI] = "HDA ATI SB", 384 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 385 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 386 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 387 [AZX_DRIVER_SIS] = "HDA SIS966", 388 [AZX_DRIVER_ULI] = "HDA ULI M5461", 389 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 390 [AZX_DRIVER_TERA] = "HDA Teradici", 391 [AZX_DRIVER_CTX] = "HDA Creative", 392 [AZX_DRIVER_CTHDA] = "HDA Creative", 393 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 394 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 395 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 396 }; 397 398 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 399 static void set_default_power_save(struct azx *chip); 400 401 /* 402 * initialize the PCI registers 403 */ 404 /* update bits in a PCI register byte */ 405 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 406 unsigned char mask, unsigned char val) 407 { 408 unsigned char data; 409 410 pci_read_config_byte(pci, reg, &data); 411 data &= ~mask; 412 data |= (val & mask); 413 pci_write_config_byte(pci, reg, data); 414 } 415 416 static void azx_init_pci(struct azx *chip) 417 { 418 int snoop_type = azx_get_snoop_type(chip); 419 420 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 421 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 422 * Ensuring these bits are 0 clears playback static on some HD Audio 423 * codecs. 424 * The PCI register TCSEL is defined in the Intel manuals. 425 */ 426 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 427 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 428 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 429 } 430 431 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 432 * we need to enable snoop. 433 */ 434 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 435 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 436 azx_snoop(chip)); 437 update_pci_byte(chip->pci, 438 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 439 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 440 } 441 442 /* For NVIDIA HDA, enable snoop */ 443 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 444 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 445 azx_snoop(chip)); 446 update_pci_byte(chip->pci, 447 NVIDIA_HDA_TRANSREG_ADDR, 448 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 449 update_pci_byte(chip->pci, 450 NVIDIA_HDA_ISTRM_COH, 451 0x01, NVIDIA_HDA_ENABLE_COHBIT); 452 update_pci_byte(chip->pci, 453 NVIDIA_HDA_OSTRM_COH, 454 0x01, NVIDIA_HDA_ENABLE_COHBIT); 455 } 456 457 /* Enable SCH/PCH snoop if needed */ 458 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 459 unsigned short snoop; 460 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 461 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 462 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 463 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 464 if (!azx_snoop(chip)) 465 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 466 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 467 pci_read_config_word(chip->pci, 468 INTEL_SCH_HDA_DEVC, &snoop); 469 } 470 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 471 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 472 "Disabled" : "Enabled"); 473 } 474 } 475 476 /* 477 * In BXT-P A0, HD-Audio DMA requests is later than expected, 478 * and makes an audio stream sensitive to system latencies when 479 * 24/32 bits are playing. 480 * Adjusting threshold of DMA fifo to force the DMA request 481 * sooner to improve latency tolerance at the expense of power. 482 */ 483 static void bxt_reduce_dma_latency(struct azx *chip) 484 { 485 u32 val; 486 487 val = azx_readl(chip, VS_EM4L); 488 val &= (0x3 << 20); 489 azx_writel(chip, VS_EM4L, val); 490 } 491 492 /* 493 * ML_LCAP bits: 494 * bit 0: 6 MHz Supported 495 * bit 1: 12 MHz Supported 496 * bit 2: 24 MHz Supported 497 * bit 3: 48 MHz Supported 498 * bit 4: 96 MHz Supported 499 * bit 5: 192 MHz Supported 500 */ 501 static int intel_get_lctl_scf(struct azx *chip) 502 { 503 struct hdac_bus *bus = azx_bus(chip); 504 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 505 u32 val, t; 506 int i; 507 508 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 509 510 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 511 t = preferred_bits[i]; 512 if (val & (1 << t)) 513 return t; 514 } 515 516 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 517 return 0; 518 } 519 520 static int intel_ml_lctl_set_power(struct azx *chip, int state) 521 { 522 struct hdac_bus *bus = azx_bus(chip); 523 u32 val; 524 int timeout; 525 526 /* 527 * the codecs are sharing the first link setting by default 528 * If other links are enabled for stream, they need similar fix 529 */ 530 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 531 val &= ~AZX_MLCTL_SPA; 532 val |= state << AZX_MLCTL_SPA_SHIFT; 533 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 534 /* wait for CPA */ 535 timeout = 50; 536 while (timeout) { 537 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 538 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 539 return 0; 540 timeout--; 541 udelay(10); 542 } 543 544 return -1; 545 } 546 547 static void intel_init_lctl(struct azx *chip) 548 { 549 struct hdac_bus *bus = azx_bus(chip); 550 u32 val; 551 int ret; 552 553 /* 0. check lctl register value is correct or not */ 554 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 555 /* if SCF is already set, let's use it */ 556 if ((val & ML_LCTL_SCF_MASK) != 0) 557 return; 558 559 /* 560 * Before operating on SPA, CPA must match SPA. 561 * Any deviation may result in undefined behavior. 562 */ 563 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 564 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 565 return; 566 567 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 568 ret = intel_ml_lctl_set_power(chip, 0); 569 udelay(100); 570 if (ret) 571 goto set_spa; 572 573 /* 2. update SCF to select a properly audio clock*/ 574 val &= ~ML_LCTL_SCF_MASK; 575 val |= intel_get_lctl_scf(chip); 576 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 577 578 set_spa: 579 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 580 intel_ml_lctl_set_power(chip, 1); 581 udelay(100); 582 } 583 584 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 585 { 586 struct hdac_bus *bus = azx_bus(chip); 587 struct pci_dev *pci = chip->pci; 588 u32 val; 589 590 snd_hdac_set_codec_wakeup(bus, true); 591 if (chip->driver_type == AZX_DRIVER_SKL) { 592 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 593 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 594 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 595 } 596 azx_init_chip(chip, full_reset); 597 if (chip->driver_type == AZX_DRIVER_SKL) { 598 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 599 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 600 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 601 } 602 603 snd_hdac_set_codec_wakeup(bus, false); 604 605 /* reduce dma latency to avoid noise */ 606 if (IS_BXT(pci)) 607 bxt_reduce_dma_latency(chip); 608 609 if (bus->mlcap != NULL) 610 intel_init_lctl(chip); 611 } 612 613 /* calculate runtime delay from LPIB */ 614 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 615 unsigned int pos) 616 { 617 struct snd_pcm_substream *substream = azx_dev->core.substream; 618 int stream = substream->stream; 619 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 620 int delay; 621 622 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 623 delay = pos - lpib_pos; 624 else 625 delay = lpib_pos - pos; 626 if (delay < 0) { 627 if (delay >= azx_dev->core.delay_negative_threshold) 628 delay = 0; 629 else 630 delay += azx_dev->core.bufsize; 631 } 632 633 if (delay >= azx_dev->core.period_bytes) { 634 dev_info(chip->card->dev, 635 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 636 delay, azx_dev->core.period_bytes); 637 delay = 0; 638 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 639 chip->get_delay[stream] = NULL; 640 } 641 642 return bytes_to_frames(substream->runtime, delay); 643 } 644 645 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 646 647 /* called from IRQ */ 648 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 649 { 650 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 651 int ok; 652 653 ok = azx_position_ok(chip, azx_dev); 654 if (ok == 1) { 655 azx_dev->irq_pending = 0; 656 return ok; 657 } else if (ok == 0) { 658 /* bogus IRQ, process it later */ 659 azx_dev->irq_pending = 1; 660 schedule_work(&hda->irq_pending_work); 661 } 662 return 0; 663 } 664 665 #define display_power(chip, enable) \ 666 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 667 668 /* 669 * Check whether the current DMA position is acceptable for updating 670 * periods. Returns non-zero if it's OK. 671 * 672 * Many HD-audio controllers appear pretty inaccurate about 673 * the update-IRQ timing. The IRQ is issued before actually the 674 * data is processed. So, we need to process it afterwords in a 675 * workqueue. 676 */ 677 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 678 { 679 struct snd_pcm_substream *substream = azx_dev->core.substream; 680 int stream = substream->stream; 681 u32 wallclk; 682 unsigned int pos; 683 684 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 685 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 686 return -1; /* bogus (too early) interrupt */ 687 688 if (chip->get_position[stream]) 689 pos = chip->get_position[stream](chip, azx_dev); 690 else { /* use the position buffer as default */ 691 pos = azx_get_pos_posbuf(chip, azx_dev); 692 if (!pos || pos == (u32)-1) { 693 dev_info(chip->card->dev, 694 "Invalid position buffer, using LPIB read method instead.\n"); 695 chip->get_position[stream] = azx_get_pos_lpib; 696 if (chip->get_position[0] == azx_get_pos_lpib && 697 chip->get_position[1] == azx_get_pos_lpib) 698 azx_bus(chip)->use_posbuf = false; 699 pos = azx_get_pos_lpib(chip, azx_dev); 700 chip->get_delay[stream] = NULL; 701 } else { 702 chip->get_position[stream] = azx_get_pos_posbuf; 703 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 704 chip->get_delay[stream] = azx_get_delay_from_lpib; 705 } 706 } 707 708 if (pos >= azx_dev->core.bufsize) 709 pos = 0; 710 711 if (WARN_ONCE(!azx_dev->core.period_bytes, 712 "hda-intel: zero azx_dev->period_bytes")) 713 return -1; /* this shouldn't happen! */ 714 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 715 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 716 /* NG - it's below the first next period boundary */ 717 return chip->bdl_pos_adj ? 0 : -1; 718 azx_dev->core.start_wallclk += wallclk; 719 return 1; /* OK, it's fine */ 720 } 721 722 /* 723 * The work for pending PCM period updates. 724 */ 725 static void azx_irq_pending_work(struct work_struct *work) 726 { 727 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 728 struct azx *chip = &hda->chip; 729 struct hdac_bus *bus = azx_bus(chip); 730 struct hdac_stream *s; 731 int pending, ok; 732 733 if (!hda->irq_pending_warned) { 734 dev_info(chip->card->dev, 735 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 736 chip->card->number); 737 hda->irq_pending_warned = 1; 738 } 739 740 for (;;) { 741 pending = 0; 742 spin_lock_irq(&bus->reg_lock); 743 list_for_each_entry(s, &bus->stream_list, list) { 744 struct azx_dev *azx_dev = stream_to_azx_dev(s); 745 if (!azx_dev->irq_pending || 746 !s->substream || 747 !s->running) 748 continue; 749 ok = azx_position_ok(chip, azx_dev); 750 if (ok > 0) { 751 azx_dev->irq_pending = 0; 752 spin_unlock(&bus->reg_lock); 753 snd_pcm_period_elapsed(s->substream); 754 spin_lock(&bus->reg_lock); 755 } else if (ok < 0) { 756 pending = 0; /* too early */ 757 } else 758 pending++; 759 } 760 spin_unlock_irq(&bus->reg_lock); 761 if (!pending) 762 return; 763 msleep(1); 764 } 765 } 766 767 /* clear irq_pending flags and assure no on-going workq */ 768 static void azx_clear_irq_pending(struct azx *chip) 769 { 770 struct hdac_bus *bus = azx_bus(chip); 771 struct hdac_stream *s; 772 773 spin_lock_irq(&bus->reg_lock); 774 list_for_each_entry(s, &bus->stream_list, list) { 775 struct azx_dev *azx_dev = stream_to_azx_dev(s); 776 azx_dev->irq_pending = 0; 777 } 778 spin_unlock_irq(&bus->reg_lock); 779 } 780 781 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 782 { 783 struct hdac_bus *bus = azx_bus(chip); 784 785 if (request_irq(chip->pci->irq, azx_interrupt, 786 chip->msi ? 0 : IRQF_SHARED, 787 chip->card->irq_descr, chip)) { 788 dev_err(chip->card->dev, 789 "unable to grab IRQ %d, disabling device\n", 790 chip->pci->irq); 791 if (do_disconnect) 792 snd_card_disconnect(chip->card); 793 return -1; 794 } 795 bus->irq = chip->pci->irq; 796 chip->card->sync_irq = bus->irq; 797 pci_intx(chip->pci, !chip->msi); 798 return 0; 799 } 800 801 /* get the current DMA position with correction on VIA chips */ 802 static unsigned int azx_via_get_position(struct azx *chip, 803 struct azx_dev *azx_dev) 804 { 805 unsigned int link_pos, mini_pos, bound_pos; 806 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 807 unsigned int fifo_size; 808 809 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 810 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 811 /* Playback, no problem using link position */ 812 return link_pos; 813 } 814 815 /* Capture */ 816 /* For new chipset, 817 * use mod to get the DMA position just like old chipset 818 */ 819 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 820 mod_dma_pos %= azx_dev->core.period_bytes; 821 822 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 823 824 if (azx_dev->insufficient) { 825 /* Link position never gather than FIFO size */ 826 if (link_pos <= fifo_size) 827 return 0; 828 829 azx_dev->insufficient = 0; 830 } 831 832 if (link_pos <= fifo_size) 833 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 834 else 835 mini_pos = link_pos - fifo_size; 836 837 /* Find nearest previous boudary */ 838 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 839 mod_link_pos = link_pos % azx_dev->core.period_bytes; 840 if (mod_link_pos >= fifo_size) 841 bound_pos = link_pos - mod_link_pos; 842 else if (mod_dma_pos >= mod_mini_pos) 843 bound_pos = mini_pos - mod_mini_pos; 844 else { 845 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 846 if (bound_pos >= azx_dev->core.bufsize) 847 bound_pos = 0; 848 } 849 850 /* Calculate real DMA position we want */ 851 return bound_pos + mod_dma_pos; 852 } 853 854 #define AMD_FIFO_SIZE 32 855 856 /* get the current DMA position with FIFO size correction */ 857 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 858 { 859 struct snd_pcm_substream *substream = azx_dev->core.substream; 860 struct snd_pcm_runtime *runtime = substream->runtime; 861 unsigned int pos, delay; 862 863 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 864 if (!runtime) 865 return pos; 866 867 runtime->delay = AMD_FIFO_SIZE; 868 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 869 if (azx_dev->insufficient) { 870 if (pos < delay) { 871 delay = pos; 872 runtime->delay = bytes_to_frames(runtime, pos); 873 } else { 874 azx_dev->insufficient = 0; 875 } 876 } 877 878 /* correct the DMA position for capture stream */ 879 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 880 if (pos < delay) 881 pos += azx_dev->core.bufsize; 882 pos -= delay; 883 } 884 885 return pos; 886 } 887 888 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 889 unsigned int pos) 890 { 891 struct snd_pcm_substream *substream = azx_dev->core.substream; 892 893 /* just read back the calculated value in the above */ 894 return substream->runtime->delay; 895 } 896 897 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 898 struct azx_dev *azx_dev) 899 { 900 return _snd_hdac_chip_readl(azx_bus(chip), 901 AZX_REG_VS_SDXDPIB_XBASE + 902 (AZX_REG_VS_SDXDPIB_XINTERVAL * 903 azx_dev->core.index)); 904 } 905 906 /* get the current DMA position with correction on SKL+ chips */ 907 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 908 { 909 /* DPIB register gives a more accurate position for playback */ 910 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 911 return azx_skl_get_dpib_pos(chip, azx_dev); 912 913 /* For capture, we need to read posbuf, but it requires a delay 914 * for the possible boundary overlap; the read of DPIB fetches the 915 * actual posbuf 916 */ 917 udelay(20); 918 azx_skl_get_dpib_pos(chip, azx_dev); 919 return azx_get_pos_posbuf(chip, azx_dev); 920 } 921 922 #ifdef CONFIG_PM 923 static DEFINE_MUTEX(card_list_lock); 924 static LIST_HEAD(card_list); 925 926 static void azx_add_card_list(struct azx *chip) 927 { 928 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 929 mutex_lock(&card_list_lock); 930 list_add(&hda->list, &card_list); 931 mutex_unlock(&card_list_lock); 932 } 933 934 static void azx_del_card_list(struct azx *chip) 935 { 936 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 937 mutex_lock(&card_list_lock); 938 list_del_init(&hda->list); 939 mutex_unlock(&card_list_lock); 940 } 941 942 /* trigger power-save check at writing parameter */ 943 static int param_set_xint(const char *val, const struct kernel_param *kp) 944 { 945 struct hda_intel *hda; 946 struct azx *chip; 947 int prev = power_save; 948 int ret = param_set_int(val, kp); 949 950 if (ret || prev == power_save) 951 return ret; 952 953 mutex_lock(&card_list_lock); 954 list_for_each_entry(hda, &card_list, list) { 955 chip = &hda->chip; 956 if (!hda->probe_continued || chip->disabled) 957 continue; 958 snd_hda_set_power_save(&chip->bus, power_save * 1000); 959 } 960 mutex_unlock(&card_list_lock); 961 return 0; 962 } 963 964 /* 965 * power management 966 */ 967 static bool azx_is_pm_ready(struct snd_card *card) 968 { 969 struct azx *chip; 970 struct hda_intel *hda; 971 972 if (!card) 973 return false; 974 chip = card->private_data; 975 hda = container_of(chip, struct hda_intel, chip); 976 if (chip->disabled || hda->init_failed || !chip->running) 977 return false; 978 return true; 979 } 980 981 static void __azx_runtime_suspend(struct azx *chip) 982 { 983 azx_stop_chip(chip); 984 azx_enter_link_reset(chip); 985 azx_clear_irq_pending(chip); 986 display_power(chip, false); 987 } 988 989 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 990 { 991 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 992 struct hdac_bus *bus = azx_bus(chip); 993 struct hda_codec *codec; 994 int status; 995 996 display_power(chip, true); 997 if (hda->need_i915_power) 998 snd_hdac_i915_set_bclk(bus); 999 1000 /* Read STATESTS before controller reset */ 1001 status = azx_readw(chip, STATESTS); 1002 1003 azx_init_pci(chip); 1004 hda_intel_init_chip(chip, true); 1005 1006 if (status && from_rt) { 1007 list_for_each_codec(codec, &chip->bus) 1008 if (!codec->relaxed_resume && 1009 (status & (1 << codec->addr))) 1010 schedule_delayed_work(&codec->jackpoll_work, 1011 codec->jackpoll_interval); 1012 } 1013 1014 /* power down again for link-controlled chips */ 1015 if (!hda->need_i915_power) 1016 display_power(chip, false); 1017 } 1018 1019 #ifdef CONFIG_PM_SLEEP 1020 static int azx_suspend(struct device *dev) 1021 { 1022 struct snd_card *card = dev_get_drvdata(dev); 1023 struct azx *chip; 1024 struct hdac_bus *bus; 1025 1026 if (!azx_is_pm_ready(card)) 1027 return 0; 1028 1029 chip = card->private_data; 1030 bus = azx_bus(chip); 1031 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1032 /* An ugly workaround: direct call of __azx_runtime_suspend() and 1033 * __azx_runtime_resume() for old Intel platforms that suffer from 1034 * spurious wakeups after S3 suspend 1035 */ 1036 if (chip->driver_caps & AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP) 1037 __azx_runtime_suspend(chip); 1038 else 1039 pm_runtime_force_suspend(dev); 1040 if (bus->irq >= 0) { 1041 free_irq(bus->irq, chip); 1042 bus->irq = -1; 1043 chip->card->sync_irq = -1; 1044 } 1045 1046 if (chip->msi) 1047 pci_disable_msi(chip->pci); 1048 1049 trace_azx_suspend(chip); 1050 return 0; 1051 } 1052 1053 static int azx_resume(struct device *dev) 1054 { 1055 struct snd_card *card = dev_get_drvdata(dev); 1056 struct azx *chip; 1057 1058 if (!azx_is_pm_ready(card)) 1059 return 0; 1060 1061 chip = card->private_data; 1062 if (chip->msi) 1063 if (pci_enable_msi(chip->pci) < 0) 1064 chip->msi = 0; 1065 if (azx_acquire_irq(chip, 1) < 0) 1066 return -EIO; 1067 1068 if (chip->driver_caps & AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP) 1069 __azx_runtime_resume(chip, false); 1070 else 1071 pm_runtime_force_resume(dev); 1072 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1073 1074 trace_azx_resume(chip); 1075 return 0; 1076 } 1077 1078 /* put codec down to D3 at hibernation for Intel SKL+; 1079 * otherwise BIOS may still access the codec and screw up the driver 1080 */ 1081 static int azx_freeze_noirq(struct device *dev) 1082 { 1083 struct snd_card *card = dev_get_drvdata(dev); 1084 struct azx *chip = card->private_data; 1085 struct pci_dev *pci = to_pci_dev(dev); 1086 1087 if (!azx_is_pm_ready(card)) 1088 return 0; 1089 if (chip->driver_type == AZX_DRIVER_SKL) 1090 pci_set_power_state(pci, PCI_D3hot); 1091 1092 return 0; 1093 } 1094 1095 static int azx_thaw_noirq(struct device *dev) 1096 { 1097 struct snd_card *card = dev_get_drvdata(dev); 1098 struct azx *chip = card->private_data; 1099 struct pci_dev *pci = to_pci_dev(dev); 1100 1101 if (!azx_is_pm_ready(card)) 1102 return 0; 1103 if (chip->driver_type == AZX_DRIVER_SKL) 1104 pci_set_power_state(pci, PCI_D0); 1105 1106 return 0; 1107 } 1108 #endif /* CONFIG_PM_SLEEP */ 1109 1110 static int azx_runtime_suspend(struct device *dev) 1111 { 1112 struct snd_card *card = dev_get_drvdata(dev); 1113 struct azx *chip; 1114 1115 if (!azx_is_pm_ready(card)) 1116 return 0; 1117 chip = card->private_data; 1118 1119 /* enable controller wake up event */ 1120 if (snd_power_get_state(card) == SNDRV_CTL_POWER_D0) { 1121 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1122 STATESTS_INT_MASK); 1123 } 1124 1125 __azx_runtime_suspend(chip); 1126 trace_azx_runtime_suspend(chip); 1127 return 0; 1128 } 1129 1130 static int azx_runtime_resume(struct device *dev) 1131 { 1132 struct snd_card *card = dev_get_drvdata(dev); 1133 struct azx *chip; 1134 bool from_rt = snd_power_get_state(card) == SNDRV_CTL_POWER_D0; 1135 1136 if (!azx_is_pm_ready(card)) 1137 return 0; 1138 chip = card->private_data; 1139 __azx_runtime_resume(chip, from_rt); 1140 1141 /* disable controller Wake Up event*/ 1142 if (from_rt) { 1143 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1144 ~STATESTS_INT_MASK); 1145 } 1146 1147 trace_azx_runtime_resume(chip); 1148 return 0; 1149 } 1150 1151 static int azx_runtime_idle(struct device *dev) 1152 { 1153 struct snd_card *card = dev_get_drvdata(dev); 1154 struct azx *chip; 1155 struct hda_intel *hda; 1156 1157 if (!card) 1158 return 0; 1159 1160 chip = card->private_data; 1161 hda = container_of(chip, struct hda_intel, chip); 1162 if (chip->disabled || hda->init_failed) 1163 return 0; 1164 1165 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1166 azx_bus(chip)->codec_powered || !chip->running) 1167 return -EBUSY; 1168 1169 /* ELD notification gets broken when HD-audio bus is off */ 1170 if (needs_eld_notify_link(chip)) 1171 return -EBUSY; 1172 1173 return 0; 1174 } 1175 1176 static const struct dev_pm_ops azx_pm = { 1177 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1178 #ifdef CONFIG_PM_SLEEP 1179 .freeze_noirq = azx_freeze_noirq, 1180 .thaw_noirq = azx_thaw_noirq, 1181 #endif 1182 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1183 }; 1184 1185 #define AZX_PM_OPS &azx_pm 1186 #else 1187 #define azx_add_card_list(chip) /* NOP */ 1188 #define azx_del_card_list(chip) /* NOP */ 1189 #define AZX_PM_OPS NULL 1190 #endif /* CONFIG_PM */ 1191 1192 1193 static int azx_probe_continue(struct azx *chip); 1194 1195 #ifdef SUPPORT_VGA_SWITCHEROO 1196 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1197 1198 static void azx_vs_set_state(struct pci_dev *pci, 1199 enum vga_switcheroo_state state) 1200 { 1201 struct snd_card *card = pci_get_drvdata(pci); 1202 struct azx *chip = card->private_data; 1203 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1204 struct hda_codec *codec; 1205 bool disabled; 1206 1207 wait_for_completion(&hda->probe_wait); 1208 if (hda->init_failed) 1209 return; 1210 1211 disabled = (state == VGA_SWITCHEROO_OFF); 1212 if (chip->disabled == disabled) 1213 return; 1214 1215 if (!hda->probe_continued) { 1216 chip->disabled = disabled; 1217 if (!disabled) { 1218 dev_info(chip->card->dev, 1219 "Start delayed initialization\n"); 1220 if (azx_probe_continue(chip) < 0) 1221 dev_err(chip->card->dev, "initialization error\n"); 1222 } 1223 } else { 1224 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1225 disabled ? "Disabling" : "Enabling"); 1226 if (disabled) { 1227 list_for_each_codec(codec, &chip->bus) { 1228 pm_runtime_suspend(hda_codec_dev(codec)); 1229 pm_runtime_disable(hda_codec_dev(codec)); 1230 } 1231 pm_runtime_suspend(card->dev); 1232 pm_runtime_disable(card->dev); 1233 /* when we get suspended by vga_switcheroo we end up in D3cold, 1234 * however we have no ACPI handle, so pci/acpi can't put us there, 1235 * put ourselves there */ 1236 pci->current_state = PCI_D3cold; 1237 chip->disabled = true; 1238 if (snd_hda_lock_devices(&chip->bus)) 1239 dev_warn(chip->card->dev, 1240 "Cannot lock devices!\n"); 1241 } else { 1242 snd_hda_unlock_devices(&chip->bus); 1243 chip->disabled = false; 1244 pm_runtime_enable(card->dev); 1245 list_for_each_codec(codec, &chip->bus) { 1246 pm_runtime_enable(hda_codec_dev(codec)); 1247 pm_runtime_resume(hda_codec_dev(codec)); 1248 } 1249 } 1250 } 1251 } 1252 1253 static bool azx_vs_can_switch(struct pci_dev *pci) 1254 { 1255 struct snd_card *card = pci_get_drvdata(pci); 1256 struct azx *chip = card->private_data; 1257 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1258 1259 wait_for_completion(&hda->probe_wait); 1260 if (hda->init_failed) 1261 return false; 1262 if (chip->disabled || !hda->probe_continued) 1263 return true; 1264 if (snd_hda_lock_devices(&chip->bus)) 1265 return false; 1266 snd_hda_unlock_devices(&chip->bus); 1267 return true; 1268 } 1269 1270 /* 1271 * The discrete GPU cannot power down unless the HDA controller runtime 1272 * suspends, so activate runtime PM on codecs even if power_save == 0. 1273 */ 1274 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1275 { 1276 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1277 struct hda_codec *codec; 1278 1279 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1280 list_for_each_codec(codec, &chip->bus) 1281 codec->auto_runtime_pm = 1; 1282 /* reset the power save setup */ 1283 if (chip->running) 1284 set_default_power_save(chip); 1285 } 1286 } 1287 1288 static void azx_vs_gpu_bound(struct pci_dev *pci, 1289 enum vga_switcheroo_client_id client_id) 1290 { 1291 struct snd_card *card = pci_get_drvdata(pci); 1292 struct azx *chip = card->private_data; 1293 1294 if (client_id == VGA_SWITCHEROO_DIS) 1295 chip->bus.keep_power = 0; 1296 setup_vga_switcheroo_runtime_pm(chip); 1297 } 1298 1299 static void init_vga_switcheroo(struct azx *chip) 1300 { 1301 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1302 struct pci_dev *p = get_bound_vga(chip->pci); 1303 struct pci_dev *parent; 1304 if (p) { 1305 dev_info(chip->card->dev, 1306 "Handle vga_switcheroo audio client\n"); 1307 hda->use_vga_switcheroo = 1; 1308 1309 /* cleared in either gpu_bound op or codec probe, or when its 1310 * upstream port has _PR3 (i.e. dGPU). 1311 */ 1312 parent = pci_upstream_bridge(p); 1313 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1314 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1315 pci_dev_put(p); 1316 } 1317 } 1318 1319 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1320 .set_gpu_state = azx_vs_set_state, 1321 .can_switch = azx_vs_can_switch, 1322 .gpu_bound = azx_vs_gpu_bound, 1323 }; 1324 1325 static int register_vga_switcheroo(struct azx *chip) 1326 { 1327 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1328 struct pci_dev *p; 1329 int err; 1330 1331 if (!hda->use_vga_switcheroo) 1332 return 0; 1333 1334 p = get_bound_vga(chip->pci); 1335 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1336 pci_dev_put(p); 1337 1338 if (err < 0) 1339 return err; 1340 hda->vga_switcheroo_registered = 1; 1341 1342 return 0; 1343 } 1344 #else 1345 #define init_vga_switcheroo(chip) /* NOP */ 1346 #define register_vga_switcheroo(chip) 0 1347 #define check_hdmi_disabled(pci) false 1348 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1349 #endif /* SUPPORT_VGA_SWITCHER */ 1350 1351 /* 1352 * destructor 1353 */ 1354 static void azx_free(struct azx *chip) 1355 { 1356 struct pci_dev *pci = chip->pci; 1357 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1358 struct hdac_bus *bus = azx_bus(chip); 1359 1360 if (hda->freed) 1361 return; 1362 1363 if (azx_has_pm_runtime(chip) && chip->running) 1364 pm_runtime_get_noresume(&pci->dev); 1365 chip->running = 0; 1366 1367 azx_del_card_list(chip); 1368 1369 hda->init_failed = 1; /* to be sure */ 1370 complete_all(&hda->probe_wait); 1371 1372 if (use_vga_switcheroo(hda)) { 1373 if (chip->disabled && hda->probe_continued) 1374 snd_hda_unlock_devices(&chip->bus); 1375 if (hda->vga_switcheroo_registered) 1376 vga_switcheroo_unregister_client(chip->pci); 1377 } 1378 1379 if (bus->chip_init) { 1380 azx_clear_irq_pending(chip); 1381 azx_stop_all_streams(chip); 1382 azx_stop_chip(chip); 1383 } 1384 1385 if (bus->irq >= 0) 1386 free_irq(bus->irq, (void*)chip); 1387 if (chip->msi) 1388 pci_disable_msi(chip->pci); 1389 iounmap(bus->remap_addr); 1390 1391 azx_free_stream_pages(chip); 1392 azx_free_streams(chip); 1393 snd_hdac_bus_exit(bus); 1394 1395 if (chip->region_requested) 1396 pci_release_regions(chip->pci); 1397 1398 pci_disable_device(chip->pci); 1399 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1400 release_firmware(chip->fw); 1401 #endif 1402 display_power(chip, false); 1403 1404 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1405 snd_hdac_i915_exit(bus); 1406 1407 hda->freed = 1; 1408 } 1409 1410 static int azx_dev_disconnect(struct snd_device *device) 1411 { 1412 struct azx *chip = device->device_data; 1413 struct hdac_bus *bus = azx_bus(chip); 1414 1415 chip->bus.shutdown = 1; 1416 cancel_work_sync(&bus->unsol_work); 1417 1418 return 0; 1419 } 1420 1421 static int azx_dev_free(struct snd_device *device) 1422 { 1423 azx_free(device->device_data); 1424 return 0; 1425 } 1426 1427 #ifdef SUPPORT_VGA_SWITCHEROO 1428 #ifdef CONFIG_ACPI 1429 /* ATPX is in the integrated GPU's namespace */ 1430 static bool atpx_present(void) 1431 { 1432 struct pci_dev *pdev = NULL; 1433 acpi_handle dhandle, atpx_handle; 1434 acpi_status status; 1435 1436 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1437 dhandle = ACPI_HANDLE(&pdev->dev); 1438 if (dhandle) { 1439 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1440 if (!ACPI_FAILURE(status)) { 1441 pci_dev_put(pdev); 1442 return true; 1443 } 1444 } 1445 } 1446 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1447 dhandle = ACPI_HANDLE(&pdev->dev); 1448 if (dhandle) { 1449 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1450 if (!ACPI_FAILURE(status)) { 1451 pci_dev_put(pdev); 1452 return true; 1453 } 1454 } 1455 } 1456 return false; 1457 } 1458 #else 1459 static bool atpx_present(void) 1460 { 1461 return false; 1462 } 1463 #endif 1464 1465 /* 1466 * Check of disabled HDMI controller by vga_switcheroo 1467 */ 1468 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1469 { 1470 struct pci_dev *p; 1471 1472 /* check only discrete GPU */ 1473 switch (pci->vendor) { 1474 case PCI_VENDOR_ID_ATI: 1475 case PCI_VENDOR_ID_AMD: 1476 if (pci->devfn == 1) { 1477 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1478 pci->bus->number, 0); 1479 if (p) { 1480 /* ATPX is in the integrated GPU's ACPI namespace 1481 * rather than the dGPU's namespace. However, 1482 * the dGPU is the one who is involved in 1483 * vgaswitcheroo. 1484 */ 1485 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1486 atpx_present()) 1487 return p; 1488 pci_dev_put(p); 1489 } 1490 } 1491 break; 1492 case PCI_VENDOR_ID_NVIDIA: 1493 if (pci->devfn == 1) { 1494 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1495 pci->bus->number, 0); 1496 if (p) { 1497 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1498 return p; 1499 pci_dev_put(p); 1500 } 1501 } 1502 break; 1503 } 1504 return NULL; 1505 } 1506 1507 static bool check_hdmi_disabled(struct pci_dev *pci) 1508 { 1509 bool vga_inactive = false; 1510 struct pci_dev *p = get_bound_vga(pci); 1511 1512 if (p) { 1513 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1514 vga_inactive = true; 1515 pci_dev_put(p); 1516 } 1517 return vga_inactive; 1518 } 1519 #endif /* SUPPORT_VGA_SWITCHEROO */ 1520 1521 /* 1522 * white/black-listing for position_fix 1523 */ 1524 static const struct snd_pci_quirk position_fix_list[] = { 1525 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1526 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1527 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1528 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1529 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1530 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1531 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1532 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1533 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1534 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1535 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1536 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1537 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1538 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1539 {} 1540 }; 1541 1542 static int check_position_fix(struct azx *chip, int fix) 1543 { 1544 const struct snd_pci_quirk *q; 1545 1546 switch (fix) { 1547 case POS_FIX_AUTO: 1548 case POS_FIX_LPIB: 1549 case POS_FIX_POSBUF: 1550 case POS_FIX_VIACOMBO: 1551 case POS_FIX_COMBO: 1552 case POS_FIX_SKL: 1553 case POS_FIX_FIFO: 1554 return fix; 1555 } 1556 1557 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1558 if (q) { 1559 dev_info(chip->card->dev, 1560 "position_fix set to %d for device %04x:%04x\n", 1561 q->value, q->subvendor, q->subdevice); 1562 return q->value; 1563 } 1564 1565 /* Check VIA/ATI HD Audio Controller exist */ 1566 if (chip->driver_type == AZX_DRIVER_VIA) { 1567 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1568 return POS_FIX_VIACOMBO; 1569 } 1570 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1571 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1572 return POS_FIX_FIFO; 1573 } 1574 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1575 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1576 return POS_FIX_LPIB; 1577 } 1578 if (chip->driver_type == AZX_DRIVER_SKL) { 1579 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1580 return POS_FIX_SKL; 1581 } 1582 return POS_FIX_AUTO; 1583 } 1584 1585 static void assign_position_fix(struct azx *chip, int fix) 1586 { 1587 static const azx_get_pos_callback_t callbacks[] = { 1588 [POS_FIX_AUTO] = NULL, 1589 [POS_FIX_LPIB] = azx_get_pos_lpib, 1590 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1591 [POS_FIX_VIACOMBO] = azx_via_get_position, 1592 [POS_FIX_COMBO] = azx_get_pos_lpib, 1593 [POS_FIX_SKL] = azx_get_pos_skl, 1594 [POS_FIX_FIFO] = azx_get_pos_fifo, 1595 }; 1596 1597 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1598 1599 /* combo mode uses LPIB only for playback */ 1600 if (fix == POS_FIX_COMBO) 1601 chip->get_position[1] = NULL; 1602 1603 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1604 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1605 chip->get_delay[0] = chip->get_delay[1] = 1606 azx_get_delay_from_lpib; 1607 } 1608 1609 if (fix == POS_FIX_FIFO) 1610 chip->get_delay[0] = chip->get_delay[1] = 1611 azx_get_delay_from_fifo; 1612 } 1613 1614 /* 1615 * black-lists for probe_mask 1616 */ 1617 static const struct snd_pci_quirk probe_mask_list[] = { 1618 /* Thinkpad often breaks the controller communication when accessing 1619 * to the non-working (or non-existing) modem codec slot. 1620 */ 1621 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1622 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1623 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1624 /* broken BIOS */ 1625 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1626 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1627 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1628 /* forced codec slots */ 1629 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1630 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1631 /* WinFast VP200 H (Teradici) user reported broken communication */ 1632 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1633 {} 1634 }; 1635 1636 #define AZX_FORCE_CODEC_MASK 0x100 1637 1638 static void check_probe_mask(struct azx *chip, int dev) 1639 { 1640 const struct snd_pci_quirk *q; 1641 1642 chip->codec_probe_mask = probe_mask[dev]; 1643 if (chip->codec_probe_mask == -1) { 1644 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1645 if (q) { 1646 dev_info(chip->card->dev, 1647 "probe_mask set to 0x%x for device %04x:%04x\n", 1648 q->value, q->subvendor, q->subdevice); 1649 chip->codec_probe_mask = q->value; 1650 } 1651 } 1652 1653 /* check forced option */ 1654 if (chip->codec_probe_mask != -1 && 1655 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1656 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1657 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1658 (int)azx_bus(chip)->codec_mask); 1659 } 1660 } 1661 1662 /* 1663 * white/black-list for enable_msi 1664 */ 1665 static const struct snd_pci_quirk msi_black_list[] = { 1666 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1667 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1668 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1669 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1670 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1671 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1672 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1673 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1674 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1675 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1676 {} 1677 }; 1678 1679 static void check_msi(struct azx *chip) 1680 { 1681 const struct snd_pci_quirk *q; 1682 1683 if (enable_msi >= 0) { 1684 chip->msi = !!enable_msi; 1685 return; 1686 } 1687 chip->msi = 1; /* enable MSI as default */ 1688 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1689 if (q) { 1690 dev_info(chip->card->dev, 1691 "msi for device %04x:%04x set to %d\n", 1692 q->subvendor, q->subdevice, q->value); 1693 chip->msi = q->value; 1694 return; 1695 } 1696 1697 /* NVidia chipsets seem to cause troubles with MSI */ 1698 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1699 dev_info(chip->card->dev, "Disabling MSI\n"); 1700 chip->msi = 0; 1701 } 1702 } 1703 1704 /* check the snoop mode availability */ 1705 static void azx_check_snoop_available(struct azx *chip) 1706 { 1707 int snoop = hda_snoop; 1708 1709 if (snoop >= 0) { 1710 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1711 snoop ? "snoop" : "non-snoop"); 1712 chip->snoop = snoop; 1713 chip->uc_buffer = !snoop; 1714 return; 1715 } 1716 1717 snoop = true; 1718 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1719 chip->driver_type == AZX_DRIVER_VIA) { 1720 /* force to non-snoop mode for a new VIA controller 1721 * when BIOS is set 1722 */ 1723 u8 val; 1724 pci_read_config_byte(chip->pci, 0x42, &val); 1725 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1726 chip->pci->revision == 0x20)) 1727 snoop = false; 1728 } 1729 1730 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1731 snoop = false; 1732 1733 chip->snoop = snoop; 1734 if (!snoop) { 1735 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1736 /* C-Media requires non-cached pages only for CORB/RIRB */ 1737 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1738 chip->uc_buffer = true; 1739 } 1740 } 1741 1742 static void azx_probe_work(struct work_struct *work) 1743 { 1744 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1745 azx_probe_continue(&hda->chip); 1746 } 1747 1748 static int default_bdl_pos_adj(struct azx *chip) 1749 { 1750 /* some exceptions: Atoms seem problematic with value 1 */ 1751 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1752 switch (chip->pci->device) { 1753 case 0x0f04: /* Baytrail */ 1754 case 0x2284: /* Braswell */ 1755 return 32; 1756 } 1757 } 1758 1759 switch (chip->driver_type) { 1760 case AZX_DRIVER_ICH: 1761 case AZX_DRIVER_PCH: 1762 return 1; 1763 default: 1764 return 32; 1765 } 1766 } 1767 1768 /* 1769 * constructor 1770 */ 1771 static const struct hda_controller_ops pci_hda_ops; 1772 1773 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1774 int dev, unsigned int driver_caps, 1775 struct azx **rchip) 1776 { 1777 static const struct snd_device_ops ops = { 1778 .dev_disconnect = azx_dev_disconnect, 1779 .dev_free = azx_dev_free, 1780 }; 1781 struct hda_intel *hda; 1782 struct azx *chip; 1783 int err; 1784 1785 *rchip = NULL; 1786 1787 err = pci_enable_device(pci); 1788 if (err < 0) 1789 return err; 1790 1791 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1792 if (!hda) { 1793 pci_disable_device(pci); 1794 return -ENOMEM; 1795 } 1796 1797 chip = &hda->chip; 1798 mutex_init(&chip->open_mutex); 1799 chip->card = card; 1800 chip->pci = pci; 1801 chip->ops = &pci_hda_ops; 1802 chip->driver_caps = driver_caps; 1803 chip->driver_type = driver_caps & 0xff; 1804 check_msi(chip); 1805 chip->dev_index = dev; 1806 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1807 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1808 INIT_LIST_HEAD(&chip->pcm_list); 1809 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1810 INIT_LIST_HEAD(&hda->list); 1811 init_vga_switcheroo(chip); 1812 init_completion(&hda->probe_wait); 1813 1814 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1815 1816 check_probe_mask(chip, dev); 1817 1818 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1819 chip->fallback_to_single_cmd = 1; 1820 else /* explicitly set to single_cmd or not */ 1821 chip->single_cmd = single_cmd; 1822 1823 azx_check_snoop_available(chip); 1824 1825 if (bdl_pos_adj[dev] < 0) 1826 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1827 else 1828 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1829 1830 err = azx_bus_init(chip, model[dev]); 1831 if (err < 0) { 1832 pci_disable_device(pci); 1833 return err; 1834 } 1835 1836 /* use the non-cached pages in non-snoop mode */ 1837 if (!azx_snoop(chip)) 1838 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1839 1840 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1841 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1842 chip->bus.core.needs_damn_long_delay = 1; 1843 } 1844 1845 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1846 if (err < 0) { 1847 dev_err(card->dev, "Error creating device [card]!\n"); 1848 azx_free(chip); 1849 return err; 1850 } 1851 1852 /* continue probing in work context as may trigger request module */ 1853 INIT_WORK(&hda->probe_work, azx_probe_work); 1854 1855 *rchip = chip; 1856 1857 return 0; 1858 } 1859 1860 static int azx_first_init(struct azx *chip) 1861 { 1862 int dev = chip->dev_index; 1863 struct pci_dev *pci = chip->pci; 1864 struct snd_card *card = chip->card; 1865 struct hdac_bus *bus = azx_bus(chip); 1866 int err; 1867 unsigned short gcap; 1868 unsigned int dma_bits = 64; 1869 1870 #if BITS_PER_LONG != 64 1871 /* Fix up base address on ULI M5461 */ 1872 if (chip->driver_type == AZX_DRIVER_ULI) { 1873 u16 tmp3; 1874 pci_read_config_word(pci, 0x40, &tmp3); 1875 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1876 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1877 } 1878 #endif 1879 1880 err = pci_request_regions(pci, "ICH HD audio"); 1881 if (err < 0) 1882 return err; 1883 chip->region_requested = 1; 1884 1885 bus->addr = pci_resource_start(pci, 0); 1886 bus->remap_addr = pci_ioremap_bar(pci, 0); 1887 if (bus->remap_addr == NULL) { 1888 dev_err(card->dev, "ioremap error\n"); 1889 return -ENXIO; 1890 } 1891 1892 if (chip->driver_type == AZX_DRIVER_SKL) 1893 snd_hdac_bus_parse_capabilities(bus); 1894 1895 /* 1896 * Some Intel CPUs has always running timer (ART) feature and 1897 * controller may have Global time sync reporting capability, so 1898 * check both of these before declaring synchronized time reporting 1899 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1900 */ 1901 chip->gts_present = false; 1902 1903 #ifdef CONFIG_X86 1904 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1905 chip->gts_present = true; 1906 #endif 1907 1908 if (chip->msi) { 1909 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1910 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1911 pci->no_64bit_msi = true; 1912 } 1913 if (pci_enable_msi(pci) < 0) 1914 chip->msi = 0; 1915 } 1916 1917 pci_set_master(pci); 1918 1919 gcap = azx_readw(chip, GCAP); 1920 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1921 1922 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1923 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1924 dma_bits = 40; 1925 1926 /* disable SB600 64bit support for safety */ 1927 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1928 struct pci_dev *p_smbus; 1929 dma_bits = 40; 1930 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1931 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1932 NULL); 1933 if (p_smbus) { 1934 if (p_smbus->revision < 0x30) 1935 gcap &= ~AZX_GCAP_64OK; 1936 pci_dev_put(p_smbus); 1937 } 1938 } 1939 1940 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1941 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1942 dma_bits = 40; 1943 1944 /* disable 64bit DMA address on some devices */ 1945 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1946 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1947 gcap &= ~AZX_GCAP_64OK; 1948 } 1949 1950 /* disable buffer size rounding to 128-byte multiples if supported */ 1951 if (align_buffer_size >= 0) 1952 chip->align_buffer_size = !!align_buffer_size; 1953 else { 1954 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1955 chip->align_buffer_size = 0; 1956 else 1957 chip->align_buffer_size = 1; 1958 } 1959 1960 /* allow 64bit DMA address if supported by H/W */ 1961 if (!(gcap & AZX_GCAP_64OK)) 1962 dma_bits = 32; 1963 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1964 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1965 } else { 1966 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1967 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1968 } 1969 1970 /* read number of streams from GCAP register instead of using 1971 * hardcoded value 1972 */ 1973 chip->capture_streams = (gcap >> 8) & 0x0f; 1974 chip->playback_streams = (gcap >> 12) & 0x0f; 1975 if (!chip->playback_streams && !chip->capture_streams) { 1976 /* gcap didn't give any info, switching to old method */ 1977 1978 switch (chip->driver_type) { 1979 case AZX_DRIVER_ULI: 1980 chip->playback_streams = ULI_NUM_PLAYBACK; 1981 chip->capture_streams = ULI_NUM_CAPTURE; 1982 break; 1983 case AZX_DRIVER_ATIHDMI: 1984 case AZX_DRIVER_ATIHDMI_NS: 1985 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1986 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1987 break; 1988 case AZX_DRIVER_GENERIC: 1989 default: 1990 chip->playback_streams = ICH6_NUM_PLAYBACK; 1991 chip->capture_streams = ICH6_NUM_CAPTURE; 1992 break; 1993 } 1994 } 1995 chip->capture_index_offset = 0; 1996 chip->playback_index_offset = chip->capture_streams; 1997 chip->num_streams = chip->playback_streams + chip->capture_streams; 1998 1999 /* sanity check for the SDxCTL.STRM field overflow */ 2000 if (chip->num_streams > 15 && 2001 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 2002 dev_warn(chip->card->dev, "number of I/O streams is %d, " 2003 "forcing separate stream tags", chip->num_streams); 2004 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 2005 } 2006 2007 /* initialize streams */ 2008 err = azx_init_streams(chip); 2009 if (err < 0) 2010 return err; 2011 2012 err = azx_alloc_stream_pages(chip); 2013 if (err < 0) 2014 return err; 2015 2016 /* initialize chip */ 2017 azx_init_pci(chip); 2018 2019 snd_hdac_i915_set_bclk(bus); 2020 2021 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2022 2023 /* codec detection */ 2024 if (!azx_bus(chip)->codec_mask) { 2025 dev_err(card->dev, "no codecs found!\n"); 2026 /* keep running the rest for the runtime PM */ 2027 } 2028 2029 if (azx_acquire_irq(chip, 0) < 0) 2030 return -EBUSY; 2031 2032 strcpy(card->driver, "HDA-Intel"); 2033 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2034 sizeof(card->shortname)); 2035 snprintf(card->longname, sizeof(card->longname), 2036 "%s at 0x%lx irq %i", 2037 card->shortname, bus->addr, bus->irq); 2038 2039 return 0; 2040 } 2041 2042 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2043 /* callback from request_firmware_nowait() */ 2044 static void azx_firmware_cb(const struct firmware *fw, void *context) 2045 { 2046 struct snd_card *card = context; 2047 struct azx *chip = card->private_data; 2048 2049 if (fw) 2050 chip->fw = fw; 2051 else 2052 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2053 if (!chip->disabled) { 2054 /* continue probing */ 2055 azx_probe_continue(chip); 2056 } 2057 } 2058 #endif 2059 2060 static int disable_msi_reset_irq(struct azx *chip) 2061 { 2062 struct hdac_bus *bus = azx_bus(chip); 2063 int err; 2064 2065 free_irq(bus->irq, chip); 2066 bus->irq = -1; 2067 chip->card->sync_irq = -1; 2068 pci_disable_msi(chip->pci); 2069 chip->msi = 0; 2070 err = azx_acquire_irq(chip, 1); 2071 if (err < 0) 2072 return err; 2073 2074 return 0; 2075 } 2076 2077 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2078 struct vm_area_struct *area) 2079 { 2080 #ifdef CONFIG_X86 2081 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2082 struct azx *chip = apcm->chip; 2083 if (chip->uc_buffer) 2084 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2085 #endif 2086 } 2087 2088 /* Blacklist for skipping the whole probe: 2089 * some HD-audio PCI entries are exposed without any codecs, and such devices 2090 * should be ignored from the beginning. 2091 */ 2092 static const struct pci_device_id driver_blacklist[] = { 2093 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2094 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2095 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2096 {} 2097 }; 2098 2099 static const struct hda_controller_ops pci_hda_ops = { 2100 .disable_msi_reset_irq = disable_msi_reset_irq, 2101 .pcm_mmap_prepare = pcm_mmap_prepare, 2102 .position_check = azx_position_check, 2103 }; 2104 2105 static int azx_probe(struct pci_dev *pci, 2106 const struct pci_device_id *pci_id) 2107 { 2108 static int dev; 2109 struct snd_card *card; 2110 struct hda_intel *hda; 2111 struct azx *chip; 2112 bool schedule_probe; 2113 int err; 2114 2115 if (pci_match_id(driver_blacklist, pci)) { 2116 dev_info(&pci->dev, "Skipping the blacklisted device\n"); 2117 return -ENODEV; 2118 } 2119 2120 if (dev >= SNDRV_CARDS) 2121 return -ENODEV; 2122 if (!enable[dev]) { 2123 dev++; 2124 return -ENOENT; 2125 } 2126 2127 /* 2128 * stop probe if another Intel's DSP driver should be activated 2129 */ 2130 if (dmic_detect) { 2131 err = snd_intel_dsp_driver_probe(pci); 2132 if (err != SND_INTEL_DSP_DRIVER_ANY && 2133 err != SND_INTEL_DSP_DRIVER_LEGACY) 2134 return -ENODEV; 2135 } else { 2136 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2137 } 2138 2139 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2140 0, &card); 2141 if (err < 0) { 2142 dev_err(&pci->dev, "Error creating card!\n"); 2143 return err; 2144 } 2145 2146 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2147 if (err < 0) 2148 goto out_free; 2149 card->private_data = chip; 2150 hda = container_of(chip, struct hda_intel, chip); 2151 2152 pci_set_drvdata(pci, card); 2153 2154 err = register_vga_switcheroo(chip); 2155 if (err < 0) { 2156 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2157 goto out_free; 2158 } 2159 2160 if (check_hdmi_disabled(pci)) { 2161 dev_info(card->dev, "VGA controller is disabled\n"); 2162 dev_info(card->dev, "Delaying initialization\n"); 2163 chip->disabled = true; 2164 } 2165 2166 schedule_probe = !chip->disabled; 2167 2168 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2169 if (patch[dev] && *patch[dev]) { 2170 dev_info(card->dev, "Applying patch firmware '%s'\n", 2171 patch[dev]); 2172 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2173 &pci->dev, GFP_KERNEL, card, 2174 azx_firmware_cb); 2175 if (err < 0) 2176 goto out_free; 2177 schedule_probe = false; /* continued in azx_firmware_cb() */ 2178 } 2179 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2180 2181 #ifndef CONFIG_SND_HDA_I915 2182 if (CONTROLLER_IN_GPU(pci)) 2183 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2184 #endif 2185 2186 if (schedule_probe) 2187 schedule_work(&hda->probe_work); 2188 2189 dev++; 2190 if (chip->disabled) 2191 complete_all(&hda->probe_wait); 2192 return 0; 2193 2194 out_free: 2195 snd_card_free(card); 2196 return err; 2197 } 2198 2199 #ifdef CONFIG_PM 2200 /* On some boards setting power_save to a non 0 value leads to clicking / 2201 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2202 * figure out how to avoid these sounds, but that is not always feasible. 2203 * So we keep a list of devices where we disable powersaving as its known 2204 * to causes problems on these devices. 2205 */ 2206 static const struct snd_pci_quirk power_save_blacklist[] = { 2207 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2208 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2209 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2210 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2211 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2212 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2213 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2214 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2215 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2216 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2217 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2218 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0), 2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2220 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2221 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2222 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2223 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2224 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2225 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2226 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2227 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2228 /* https://bugs.launchpad.net/bugs/1821663 */ 2229 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2230 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2231 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2232 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2233 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2234 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2235 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2236 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2237 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2238 /* https://bugs.launchpad.net/bugs/1821663 */ 2239 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2240 {} 2241 }; 2242 #endif /* CONFIG_PM */ 2243 2244 static void set_default_power_save(struct azx *chip) 2245 { 2246 int val = power_save; 2247 2248 #ifdef CONFIG_PM 2249 if (pm_blacklist) { 2250 const struct snd_pci_quirk *q; 2251 2252 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2253 if (q && val) { 2254 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2255 q->subvendor, q->subdevice); 2256 val = 0; 2257 } 2258 } 2259 #endif /* CONFIG_PM */ 2260 snd_hda_set_power_save(&chip->bus, val * 1000); 2261 } 2262 2263 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2264 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2265 [AZX_DRIVER_NVIDIA] = 8, 2266 [AZX_DRIVER_TERA] = 1, 2267 }; 2268 2269 static int azx_probe_continue(struct azx *chip) 2270 { 2271 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2272 struct hdac_bus *bus = azx_bus(chip); 2273 struct pci_dev *pci = chip->pci; 2274 int dev = chip->dev_index; 2275 int err; 2276 2277 to_hda_bus(bus)->bus_probing = 1; 2278 hda->probe_continued = 1; 2279 2280 /* bind with i915 if needed */ 2281 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2282 err = snd_hdac_i915_init(bus); 2283 if (err < 0) { 2284 /* if the controller is bound only with HDMI/DP 2285 * (for HSW and BDW), we need to abort the probe; 2286 * for other chips, still continue probing as other 2287 * codecs can be on the same link. 2288 */ 2289 if (CONTROLLER_IN_GPU(pci)) { 2290 dev_err(chip->card->dev, 2291 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2292 goto out_free; 2293 } else { 2294 /* don't bother any longer */ 2295 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2296 } 2297 } 2298 2299 /* HSW/BDW controllers need this power */ 2300 if (CONTROLLER_IN_GPU(pci)) 2301 hda->need_i915_power = 1; 2302 } 2303 2304 /* Request display power well for the HDA controller or codec. For 2305 * Haswell/Broadwell, both the display HDA controller and codec need 2306 * this power. For other platforms, like Baytrail/Braswell, only the 2307 * display codec needs the power and it can be released after probe. 2308 */ 2309 display_power(chip, true); 2310 2311 err = azx_first_init(chip); 2312 if (err < 0) 2313 goto out_free; 2314 2315 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2316 chip->beep_mode = beep_mode[dev]; 2317 #endif 2318 2319 /* create codec instances */ 2320 if (bus->codec_mask) { 2321 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2322 if (err < 0) 2323 goto out_free; 2324 } 2325 2326 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2327 if (chip->fw) { 2328 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2329 chip->fw->data); 2330 if (err < 0) 2331 goto out_free; 2332 #ifndef CONFIG_PM 2333 release_firmware(chip->fw); /* no longer needed */ 2334 chip->fw = NULL; 2335 #endif 2336 } 2337 #endif 2338 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2339 err = azx_codec_configure(chip); 2340 if (err < 0) 2341 goto out_free; 2342 } 2343 2344 err = snd_card_register(chip->card); 2345 if (err < 0) 2346 goto out_free; 2347 2348 setup_vga_switcheroo_runtime_pm(chip); 2349 2350 chip->running = 1; 2351 azx_add_card_list(chip); 2352 2353 set_default_power_save(chip); 2354 2355 if (azx_has_pm_runtime(chip)) { 2356 pm_runtime_use_autosuspend(&pci->dev); 2357 pm_runtime_allow(&pci->dev); 2358 pm_runtime_put_autosuspend(&pci->dev); 2359 } 2360 2361 out_free: 2362 if (err < 0) { 2363 azx_free(chip); 2364 return err; 2365 } 2366 2367 if (!hda->need_i915_power) 2368 display_power(chip, false); 2369 complete_all(&hda->probe_wait); 2370 to_hda_bus(bus)->bus_probing = 0; 2371 return 0; 2372 } 2373 2374 static void azx_remove(struct pci_dev *pci) 2375 { 2376 struct snd_card *card = pci_get_drvdata(pci); 2377 struct azx *chip; 2378 struct hda_intel *hda; 2379 2380 if (card) { 2381 /* cancel the pending probing work */ 2382 chip = card->private_data; 2383 hda = container_of(chip, struct hda_intel, chip); 2384 /* FIXME: below is an ugly workaround. 2385 * Both device_release_driver() and driver_probe_device() 2386 * take *both* the device's and its parent's lock before 2387 * calling the remove() and probe() callbacks. The codec 2388 * probe takes the locks of both the codec itself and its 2389 * parent, i.e. the PCI controller dev. Meanwhile, when 2390 * the PCI controller is unbound, it takes its lock, too 2391 * ==> ouch, a deadlock! 2392 * As a workaround, we unlock temporarily here the controller 2393 * device during cancel_work_sync() call. 2394 */ 2395 device_unlock(&pci->dev); 2396 cancel_work_sync(&hda->probe_work); 2397 device_lock(&pci->dev); 2398 2399 snd_card_free(card); 2400 } 2401 } 2402 2403 static void azx_shutdown(struct pci_dev *pci) 2404 { 2405 struct snd_card *card = pci_get_drvdata(pci); 2406 struct azx *chip; 2407 2408 if (!card) 2409 return; 2410 chip = card->private_data; 2411 if (chip && chip->running) 2412 azx_stop_chip(chip); 2413 } 2414 2415 /* PCI IDs */ 2416 static const struct pci_device_id azx_ids[] = { 2417 /* CPT */ 2418 { PCI_DEVICE(0x8086, 0x1c20), 2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2420 /* PBG */ 2421 { PCI_DEVICE(0x8086, 0x1d20), 2422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2423 /* Panther Point */ 2424 { PCI_DEVICE(0x8086, 0x1e20), 2425 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2426 /* Lynx Point */ 2427 { PCI_DEVICE(0x8086, 0x8c20), 2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2429 /* 9 Series */ 2430 { PCI_DEVICE(0x8086, 0x8ca0), 2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2432 /* Wellsburg */ 2433 { PCI_DEVICE(0x8086, 0x8d20), 2434 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2435 { PCI_DEVICE(0x8086, 0x8d21), 2436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2437 /* Lewisburg */ 2438 { PCI_DEVICE(0x8086, 0xa1f0), 2439 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2440 { PCI_DEVICE(0x8086, 0xa270), 2441 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2442 /* Lynx Point-LP */ 2443 { PCI_DEVICE(0x8086, 0x9c20), 2444 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2445 /* Lynx Point-LP */ 2446 { PCI_DEVICE(0x8086, 0x9c21), 2447 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2448 /* Wildcat Point-LP */ 2449 { PCI_DEVICE(0x8086, 0x9ca0), 2450 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2451 /* Sunrise Point */ 2452 { PCI_DEVICE(0x8086, 0xa170), 2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2454 /* Sunrise Point-LP */ 2455 { PCI_DEVICE(0x8086, 0x9d70), 2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2457 /* Kabylake */ 2458 { PCI_DEVICE(0x8086, 0xa171), 2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2460 /* Kabylake-LP */ 2461 { PCI_DEVICE(0x8086, 0x9d71), 2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2463 /* Kabylake-H */ 2464 { PCI_DEVICE(0x8086, 0xa2f0), 2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2466 /* Coffelake */ 2467 { PCI_DEVICE(0x8086, 0xa348), 2468 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2469 /* Cannonlake */ 2470 { PCI_DEVICE(0x8086, 0x9dc8), 2471 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2472 /* CometLake-LP */ 2473 { PCI_DEVICE(0x8086, 0x02C8), 2474 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2475 /* CometLake-H */ 2476 { PCI_DEVICE(0x8086, 0x06C8), 2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2478 /* CometLake-S */ 2479 { PCI_DEVICE(0x8086, 0xa3f0), 2480 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2481 /* Icelake */ 2482 { PCI_DEVICE(0x8086, 0x34c8), 2483 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2484 /* Icelake-H */ 2485 { PCI_DEVICE(0x8086, 0x3dc8), 2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2487 /* Jasperlake */ 2488 { PCI_DEVICE(0x8086, 0x38c8), 2489 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2490 { PCI_DEVICE(0x8086, 0x4dc8), 2491 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2492 /* Tigerlake */ 2493 { PCI_DEVICE(0x8086, 0xa0c8), 2494 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2495 /* Tigerlake-H */ 2496 { PCI_DEVICE(0x8086, 0x43c8), 2497 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2498 /* Elkhart Lake */ 2499 { PCI_DEVICE(0x8086, 0x4b55), 2500 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2501 { PCI_DEVICE(0x8086, 0x4b58), 2502 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2503 /* Broxton-P(Apollolake) */ 2504 { PCI_DEVICE(0x8086, 0x5a98), 2505 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2506 /* Broxton-T */ 2507 { PCI_DEVICE(0x8086, 0x1a98), 2508 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2509 /* Gemini-Lake */ 2510 { PCI_DEVICE(0x8086, 0x3198), 2511 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2512 /* Haswell */ 2513 { PCI_DEVICE(0x8086, 0x0a0c), 2514 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2515 { PCI_DEVICE(0x8086, 0x0c0c), 2516 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2517 { PCI_DEVICE(0x8086, 0x0d0c), 2518 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2519 /* Broadwell */ 2520 { PCI_DEVICE(0x8086, 0x160c), 2521 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2522 /* 5 Series/3400 */ 2523 { PCI_DEVICE(0x8086, 0x3b56), 2524 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2525 /* Poulsbo */ 2526 { PCI_DEVICE(0x8086, 0x811b), 2527 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2528 /* Oaktrail */ 2529 { PCI_DEVICE(0x8086, 0x080a), 2530 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2531 /* BayTrail */ 2532 { PCI_DEVICE(0x8086, 0x0f04), 2533 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2534 /* Braswell */ 2535 { PCI_DEVICE(0x8086, 0x2284), 2536 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2537 /* ICH6 */ 2538 { PCI_DEVICE(0x8086, 0x2668), 2539 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2540 /* ICH7 */ 2541 { PCI_DEVICE(0x8086, 0x27d8), 2542 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2543 /* ESB2 */ 2544 { PCI_DEVICE(0x8086, 0x269a), 2545 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2546 /* ICH8 */ 2547 { PCI_DEVICE(0x8086, 0x284b), 2548 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2549 /* ICH9 */ 2550 { PCI_DEVICE(0x8086, 0x293e), 2551 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2552 /* ICH9 */ 2553 { PCI_DEVICE(0x8086, 0x293f), 2554 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2555 /* ICH10 */ 2556 { PCI_DEVICE(0x8086, 0x3a3e), 2557 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2558 /* ICH10 */ 2559 { PCI_DEVICE(0x8086, 0x3a6e), 2560 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2561 /* Generic Intel */ 2562 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2563 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2564 .class_mask = 0xffffff, 2565 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2566 /* ATI SB 450/600/700/800/900 */ 2567 { PCI_DEVICE(0x1002, 0x437b), 2568 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2569 { PCI_DEVICE(0x1002, 0x4383), 2570 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2571 /* AMD Hudson */ 2572 { PCI_DEVICE(0x1022, 0x780d), 2573 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2574 /* AMD, X370 & co */ 2575 { PCI_DEVICE(0x1022, 0x1457), 2576 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2577 /* AMD, X570 & co */ 2578 { PCI_DEVICE(0x1022, 0x1487), 2579 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2580 /* AMD Stoney */ 2581 { PCI_DEVICE(0x1022, 0x157a), 2582 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2583 AZX_DCAPS_PM_RUNTIME }, 2584 /* AMD Raven */ 2585 { PCI_DEVICE(0x1022, 0x15e3), 2586 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2587 /* ATI HDMI */ 2588 { PCI_DEVICE(0x1002, 0x0002), 2589 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2590 { PCI_DEVICE(0x1002, 0x1308), 2591 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2592 { PCI_DEVICE(0x1002, 0x157a), 2593 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2594 { PCI_DEVICE(0x1002, 0x15b3), 2595 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2596 { PCI_DEVICE(0x1002, 0x793b), 2597 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2598 { PCI_DEVICE(0x1002, 0x7919), 2599 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2600 { PCI_DEVICE(0x1002, 0x960f), 2601 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2602 { PCI_DEVICE(0x1002, 0x970f), 2603 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2604 { PCI_DEVICE(0x1002, 0x9840), 2605 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2606 { PCI_DEVICE(0x1002, 0xaa00), 2607 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2608 { PCI_DEVICE(0x1002, 0xaa08), 2609 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2610 { PCI_DEVICE(0x1002, 0xaa10), 2611 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2612 { PCI_DEVICE(0x1002, 0xaa18), 2613 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2614 { PCI_DEVICE(0x1002, 0xaa20), 2615 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2616 { PCI_DEVICE(0x1002, 0xaa28), 2617 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2618 { PCI_DEVICE(0x1002, 0xaa30), 2619 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2620 { PCI_DEVICE(0x1002, 0xaa38), 2621 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2622 { PCI_DEVICE(0x1002, 0xaa40), 2623 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2624 { PCI_DEVICE(0x1002, 0xaa48), 2625 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2626 { PCI_DEVICE(0x1002, 0xaa50), 2627 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2628 { PCI_DEVICE(0x1002, 0xaa58), 2629 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2630 { PCI_DEVICE(0x1002, 0xaa60), 2631 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2632 { PCI_DEVICE(0x1002, 0xaa68), 2633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2634 { PCI_DEVICE(0x1002, 0xaa80), 2635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2636 { PCI_DEVICE(0x1002, 0xaa88), 2637 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2638 { PCI_DEVICE(0x1002, 0xaa90), 2639 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2640 { PCI_DEVICE(0x1002, 0xaa98), 2641 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2642 { PCI_DEVICE(0x1002, 0x9902), 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2644 { PCI_DEVICE(0x1002, 0xaaa0), 2645 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2646 { PCI_DEVICE(0x1002, 0xaaa8), 2647 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2648 { PCI_DEVICE(0x1002, 0xaab0), 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2650 { PCI_DEVICE(0x1002, 0xaac0), 2651 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2652 { PCI_DEVICE(0x1002, 0xaac8), 2653 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2654 { PCI_DEVICE(0x1002, 0xaad8), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2656 AZX_DCAPS_PM_RUNTIME }, 2657 { PCI_DEVICE(0x1002, 0xaae0), 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2659 AZX_DCAPS_PM_RUNTIME }, 2660 { PCI_DEVICE(0x1002, 0xaae8), 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2662 AZX_DCAPS_PM_RUNTIME }, 2663 { PCI_DEVICE(0x1002, 0xaaf0), 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2665 AZX_DCAPS_PM_RUNTIME }, 2666 { PCI_DEVICE(0x1002, 0xaaf8), 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2668 AZX_DCAPS_PM_RUNTIME }, 2669 { PCI_DEVICE(0x1002, 0xab00), 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2671 AZX_DCAPS_PM_RUNTIME }, 2672 { PCI_DEVICE(0x1002, 0xab08), 2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2674 AZX_DCAPS_PM_RUNTIME }, 2675 { PCI_DEVICE(0x1002, 0xab10), 2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2677 AZX_DCAPS_PM_RUNTIME }, 2678 { PCI_DEVICE(0x1002, 0xab18), 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2680 AZX_DCAPS_PM_RUNTIME }, 2681 { PCI_DEVICE(0x1002, 0xab20), 2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2683 AZX_DCAPS_PM_RUNTIME }, 2684 { PCI_DEVICE(0x1002, 0xab28), 2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2686 AZX_DCAPS_PM_RUNTIME }, 2687 { PCI_DEVICE(0x1002, 0xab38), 2688 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2689 AZX_DCAPS_PM_RUNTIME }, 2690 /* VIA VT8251/VT8237A */ 2691 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2692 /* VIA GFX VT7122/VX900 */ 2693 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2694 /* VIA GFX VT6122/VX11 */ 2695 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2696 /* SIS966 */ 2697 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2698 /* ULI M5461 */ 2699 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2700 /* NVIDIA MCP */ 2701 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2702 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2703 .class_mask = 0xffffff, 2704 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2705 /* Teradici */ 2706 { PCI_DEVICE(0x6549, 0x1200), 2707 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2708 { PCI_DEVICE(0x6549, 0x2200), 2709 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2710 /* Creative X-Fi (CA0110-IBG) */ 2711 /* CTHDA chips */ 2712 { PCI_DEVICE(0x1102, 0x0010), 2713 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2714 { PCI_DEVICE(0x1102, 0x0012), 2715 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2716 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2717 /* the following entry conflicts with snd-ctxfi driver, 2718 * as ctxfi driver mutates from HD-audio to native mode with 2719 * a special command sequence. 2720 */ 2721 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2722 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2723 .class_mask = 0xffffff, 2724 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2725 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2726 #else 2727 /* this entry seems still valid -- i.e. without emu20kx chip */ 2728 { PCI_DEVICE(0x1102, 0x0009), 2729 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2730 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2731 #endif 2732 /* CM8888 */ 2733 { PCI_DEVICE(0x13f6, 0x5011), 2734 .driver_data = AZX_DRIVER_CMEDIA | 2735 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2736 /* Vortex86MX */ 2737 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2738 /* VMware HDAudio */ 2739 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2740 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2741 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2742 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2743 .class_mask = 0xffffff, 2744 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2745 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2746 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2747 .class_mask = 0xffffff, 2748 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2749 /* Zhaoxin */ 2750 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2751 { 0, } 2752 }; 2753 MODULE_DEVICE_TABLE(pci, azx_ids); 2754 2755 /* pci_driver definition */ 2756 static struct pci_driver azx_driver = { 2757 .name = KBUILD_MODNAME, 2758 .id_table = azx_ids, 2759 .probe = azx_probe, 2760 .remove = azx_remove, 2761 .shutdown = azx_shutdown, 2762 .driver = { 2763 .pm = AZX_PM_OPS, 2764 }, 2765 }; 2766 2767 module_pci_driver(azx_driver); 2768