1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <sound/hdaudio.h> 61 #include <sound/hda_i915.h> 62 #include <linux/vgaarb.h> 63 #include <linux/vga_switcheroo.h> 64 #include <linux/firmware.h> 65 #include "hda_codec.h" 66 #include "hda_controller.h" 67 #include "hda_intel.h" 68 69 #define CREATE_TRACE_POINTS 70 #include "hda_intel_trace.h" 71 72 /* position fix mode */ 73 enum { 74 POS_FIX_AUTO, 75 POS_FIX_LPIB, 76 POS_FIX_POSBUF, 77 POS_FIX_VIACOMBO, 78 POS_FIX_COMBO, 79 }; 80 81 /* Defines for ATI HD Audio support in SB450 south bridge */ 82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 84 85 /* Defines for Nvidia HDA support */ 86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 88 #define NVIDIA_HDA_ISTRM_COH 0x4d 89 #define NVIDIA_HDA_OSTRM_COH 0x4c 90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 91 92 /* Defines for Intel SCH HDA snoop control */ 93 #define INTEL_SCH_HDA_DEVC 0x78 94 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 95 96 /* Define IN stream 0 FIFO size offset in VIA controller */ 97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 98 /* Define VIA HD Audio Device ID*/ 99 #define VIA_HDAC_DEVICE_ID 0x3288 100 101 /* max number of SDs */ 102 /* ICH, ATI and VIA have 4 playback and 4 capture */ 103 #define ICH6_NUM_CAPTURE 4 104 #define ICH6_NUM_PLAYBACK 4 105 106 /* ULI has 6 playback and 5 capture */ 107 #define ULI_NUM_CAPTURE 5 108 #define ULI_NUM_PLAYBACK 6 109 110 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 111 #define ATIHDMI_NUM_CAPTURE 0 112 #define ATIHDMI_NUM_PLAYBACK 8 113 114 /* TERA has 4 playback and 3 capture */ 115 #define TERA_NUM_CAPTURE 3 116 #define TERA_NUM_PLAYBACK 4 117 118 119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 122 static char *model[SNDRV_CARDS]; 123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 126 static int probe_only[SNDRV_CARDS]; 127 static int jackpoll_ms[SNDRV_CARDS]; 128 static bool single_cmd; 129 static int enable_msi = -1; 130 #ifdef CONFIG_SND_HDA_PATCH_LOADER 131 static char *patch[SNDRV_CARDS]; 132 #endif 133 #ifdef CONFIG_SND_HDA_INPUT_BEEP 134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 135 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 136 #endif 137 138 module_param_array(index, int, NULL, 0444); 139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 140 module_param_array(id, charp, NULL, 0444); 141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 142 module_param_array(enable, bool, NULL, 0444); 143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 144 module_param_array(model, charp, NULL, 0444); 145 MODULE_PARM_DESC(model, "Use the given board model."); 146 module_param_array(position_fix, int, NULL, 0444); 147 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 149 module_param_array(bdl_pos_adj, int, NULL, 0644); 150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 151 module_param_array(probe_mask, int, NULL, 0444); 152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 153 module_param_array(probe_only, int, NULL, 0444); 154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 155 module_param_array(jackpoll_ms, int, NULL, 0444); 156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 157 module_param(single_cmd, bool, 0444); 158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 159 "(for debugging only)."); 160 module_param(enable_msi, bint, 0444); 161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 162 #ifdef CONFIG_SND_HDA_PATCH_LOADER 163 module_param_array(patch, charp, NULL, 0444); 164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 165 #endif 166 #ifdef CONFIG_SND_HDA_INPUT_BEEP 167 module_param_array(beep_mode, bool, NULL, 0444); 168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 169 "(0=off, 1=on) (default=1)."); 170 #endif 171 172 #ifdef CONFIG_PM 173 static int param_set_xint(const char *val, const struct kernel_param *kp); 174 static struct kernel_param_ops param_ops_xint = { 175 .set = param_set_xint, 176 .get = param_get_int, 177 }; 178 #define param_check_xint param_check_int 179 180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 181 module_param(power_save, xint, 0644); 182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 183 "(in second, 0 = disable)."); 184 185 /* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189 static bool power_save_controller = 1; 190 module_param(power_save_controller, bool, 0644); 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192 #else 193 #define power_save 0 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 212 "{Intel, ICH6M}," 213 "{Intel, ICH7}," 214 "{Intel, ESB2}," 215 "{Intel, ICH8}," 216 "{Intel, ICH9}," 217 "{Intel, ICH10}," 218 "{Intel, PCH}," 219 "{Intel, CPT}," 220 "{Intel, PPT}," 221 "{Intel, LPT}," 222 "{Intel, LPT_LP}," 223 "{Intel, WPT_LP}," 224 "{Intel, SPT}," 225 "{Intel, SPT_LP}," 226 "{Intel, HPT}," 227 "{Intel, PBG}," 228 "{Intel, SCH}," 229 "{ATI, SB450}," 230 "{ATI, SB600}," 231 "{ATI, RS600}," 232 "{ATI, RS690}," 233 "{ATI, RS780}," 234 "{ATI, R600}," 235 "{ATI, RV630}," 236 "{ATI, RV610}," 237 "{ATI, RV670}," 238 "{ATI, RV635}," 239 "{ATI, RV620}," 240 "{ATI, RV770}," 241 "{VIA, VT8251}," 242 "{VIA, VT8237A}," 243 "{SiS, SIS966}," 244 "{ULI, M5461}}"); 245 MODULE_DESCRIPTION("Intel HDA driver"); 246 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 249 #define SUPPORT_VGA_SWITCHEROO 250 #endif 251 #endif 252 253 254 /* 255 */ 256 257 /* driver types */ 258 enum { 259 AZX_DRIVER_ICH, 260 AZX_DRIVER_PCH, 261 AZX_DRIVER_SCH, 262 AZX_DRIVER_HDMI, 263 AZX_DRIVER_ATI, 264 AZX_DRIVER_ATIHDMI, 265 AZX_DRIVER_ATIHDMI_NS, 266 AZX_DRIVER_VIA, 267 AZX_DRIVER_SIS, 268 AZX_DRIVER_ULI, 269 AZX_DRIVER_NVIDIA, 270 AZX_DRIVER_TERA, 271 AZX_DRIVER_CTX, 272 AZX_DRIVER_CTHDA, 273 AZX_DRIVER_CMEDIA, 274 AZX_DRIVER_GENERIC, 275 AZX_NUM_DRIVERS, /* keep this as last entry */ 276 }; 277 278 #define azx_get_snoop_type(chip) \ 279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 281 282 /* quirks for old Intel chipsets */ 283 #define AZX_DCAPS_INTEL_ICH \ 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 285 286 /* quirks for Intel PCH */ 287 #define AZX_DCAPS_INTEL_PCH_NOPM \ 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH)) 290 291 #define AZX_DCAPS_INTEL_PCH \ 292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 293 294 #define AZX_DCAPS_INTEL_HASWELL \ 295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 297 AZX_DCAPS_SNOOP_TYPE(SCH)) 298 299 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 300 #define AZX_DCAPS_INTEL_BROADWELL \ 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 303 AZX_DCAPS_SNOOP_TYPE(SCH)) 304 305 #define AZX_DCAPS_INTEL_BAYTRAIL \ 306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL) 307 308 #define AZX_DCAPS_INTEL_BRASWELL \ 309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL) 310 311 #define AZX_DCAPS_INTEL_SKYLAKE \ 312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 313 AZX_DCAPS_I915_POWERWELL) 314 315 /* quirks for ATI SB / AMD Hudson */ 316 #define AZX_DCAPS_PRESET_ATI_SB \ 317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 318 AZX_DCAPS_SNOOP_TYPE(ATI)) 319 320 /* quirks for ATI/AMD HDMI */ 321 #define AZX_DCAPS_PRESET_ATI_HDMI \ 322 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 323 AZX_DCAPS_NO_MSI64) 324 325 /* quirks for ATI HDMI with snoop off */ 326 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 327 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 328 329 /* quirks for Nvidia */ 330 #define AZX_DCAPS_PRESET_NVIDIA \ 331 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 332 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 333 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 334 335 #define AZX_DCAPS_PRESET_CTHDA \ 336 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 337 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 338 339 /* 340 * VGA-switcher support 341 */ 342 #ifdef SUPPORT_VGA_SWITCHEROO 343 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 344 #else 345 #define use_vga_switcheroo(chip) 0 346 #endif 347 348 static char *driver_short_names[] = { 349 [AZX_DRIVER_ICH] = "HDA Intel", 350 [AZX_DRIVER_PCH] = "HDA Intel PCH", 351 [AZX_DRIVER_SCH] = "HDA Intel MID", 352 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 353 [AZX_DRIVER_ATI] = "HDA ATI SB", 354 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 355 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 356 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 357 [AZX_DRIVER_SIS] = "HDA SIS966", 358 [AZX_DRIVER_ULI] = "HDA ULI M5461", 359 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 360 [AZX_DRIVER_TERA] = "HDA Teradici", 361 [AZX_DRIVER_CTX] = "HDA Creative", 362 [AZX_DRIVER_CTHDA] = "HDA Creative", 363 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 364 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 365 }; 366 367 #ifdef CONFIG_X86 368 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 369 { 370 int pages; 371 372 if (azx_snoop(chip)) 373 return; 374 if (!dmab || !dmab->area || !dmab->bytes) 375 return; 376 377 #ifdef CONFIG_SND_DMA_SGBUF 378 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 379 struct snd_sg_buf *sgbuf = dmab->private_data; 380 if (chip->driver_type == AZX_DRIVER_CMEDIA) 381 return; /* deal with only CORB/RIRB buffers */ 382 if (on) 383 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 384 else 385 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 386 return; 387 } 388 #endif 389 390 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 391 if (on) 392 set_memory_wc((unsigned long)dmab->area, pages); 393 else 394 set_memory_wb((unsigned long)dmab->area, pages); 395 } 396 397 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 398 bool on) 399 { 400 __mark_pages_wc(chip, buf, on); 401 } 402 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 403 struct snd_pcm_substream *substream, bool on) 404 { 405 if (azx_dev->wc_marked != on) { 406 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 407 azx_dev->wc_marked = on; 408 } 409 } 410 #else 411 /* NOP for other archs */ 412 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 413 bool on) 414 { 415 } 416 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 417 struct snd_pcm_substream *substream, bool on) 418 { 419 } 420 #endif 421 422 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 423 424 /* 425 * initialize the PCI registers 426 */ 427 /* update bits in a PCI register byte */ 428 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 429 unsigned char mask, unsigned char val) 430 { 431 unsigned char data; 432 433 pci_read_config_byte(pci, reg, &data); 434 data &= ~mask; 435 data |= (val & mask); 436 pci_write_config_byte(pci, reg, data); 437 } 438 439 static void azx_init_pci(struct azx *chip) 440 { 441 int snoop_type = azx_get_snoop_type(chip); 442 443 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 444 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 445 * Ensuring these bits are 0 clears playback static on some HD Audio 446 * codecs. 447 * The PCI register TCSEL is defined in the Intel manuals. 448 */ 449 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 450 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 451 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 452 } 453 454 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 455 * we need to enable snoop. 456 */ 457 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 458 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 459 azx_snoop(chip)); 460 update_pci_byte(chip->pci, 461 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 462 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 463 } 464 465 /* For NVIDIA HDA, enable snoop */ 466 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 467 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 468 azx_snoop(chip)); 469 update_pci_byte(chip->pci, 470 NVIDIA_HDA_TRANSREG_ADDR, 471 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 472 update_pci_byte(chip->pci, 473 NVIDIA_HDA_ISTRM_COH, 474 0x01, NVIDIA_HDA_ENABLE_COHBIT); 475 update_pci_byte(chip->pci, 476 NVIDIA_HDA_OSTRM_COH, 477 0x01, NVIDIA_HDA_ENABLE_COHBIT); 478 } 479 480 /* Enable SCH/PCH snoop if needed */ 481 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 482 unsigned short snoop; 483 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 484 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 485 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 486 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 487 if (!azx_snoop(chip)) 488 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 489 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 490 pci_read_config_word(chip->pci, 491 INTEL_SCH_HDA_DEVC, &snoop); 492 } 493 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 494 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 495 "Disabled" : "Enabled"); 496 } 497 } 498 499 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 500 { 501 struct hdac_bus *bus = azx_bus(chip); 502 503 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 504 snd_hdac_set_codec_wakeup(bus, true); 505 azx_init_chip(chip, full_reset); 506 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 507 snd_hdac_set_codec_wakeup(bus, false); 508 } 509 510 /* calculate runtime delay from LPIB */ 511 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 512 unsigned int pos) 513 { 514 struct snd_pcm_substream *substream = azx_dev->core.substream; 515 int stream = substream->stream; 516 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 517 int delay; 518 519 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 520 delay = pos - lpib_pos; 521 else 522 delay = lpib_pos - pos; 523 if (delay < 0) { 524 if (delay >= azx_dev->core.delay_negative_threshold) 525 delay = 0; 526 else 527 delay += azx_dev->core.bufsize; 528 } 529 530 if (delay >= azx_dev->core.period_bytes) { 531 dev_info(chip->card->dev, 532 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 533 delay, azx_dev->core.period_bytes); 534 delay = 0; 535 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 536 chip->get_delay[stream] = NULL; 537 } 538 539 return bytes_to_frames(substream->runtime, delay); 540 } 541 542 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 543 544 /* called from IRQ */ 545 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 546 { 547 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 548 int ok; 549 550 ok = azx_position_ok(chip, azx_dev); 551 if (ok == 1) { 552 azx_dev->irq_pending = 0; 553 return ok; 554 } else if (ok == 0) { 555 /* bogus IRQ, process it later */ 556 azx_dev->irq_pending = 1; 557 schedule_work(&hda->irq_pending_work); 558 } 559 return 0; 560 } 561 562 /* Enable/disable i915 display power for the link */ 563 static int azx_intel_link_power(struct azx *chip, bool enable) 564 { 565 struct hdac_bus *bus = azx_bus(chip); 566 567 return snd_hdac_display_power(bus, enable); 568 } 569 570 /* 571 * Check whether the current DMA position is acceptable for updating 572 * periods. Returns non-zero if it's OK. 573 * 574 * Many HD-audio controllers appear pretty inaccurate about 575 * the update-IRQ timing. The IRQ is issued before actually the 576 * data is processed. So, we need to process it afterwords in a 577 * workqueue. 578 */ 579 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 580 { 581 struct snd_pcm_substream *substream = azx_dev->core.substream; 582 int stream = substream->stream; 583 u32 wallclk; 584 unsigned int pos; 585 586 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 587 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 588 return -1; /* bogus (too early) interrupt */ 589 590 if (chip->get_position[stream]) 591 pos = chip->get_position[stream](chip, azx_dev); 592 else { /* use the position buffer as default */ 593 pos = azx_get_pos_posbuf(chip, azx_dev); 594 if (!pos || pos == (u32)-1) { 595 dev_info(chip->card->dev, 596 "Invalid position buffer, using LPIB read method instead.\n"); 597 chip->get_position[stream] = azx_get_pos_lpib; 598 if (chip->get_position[0] == azx_get_pos_lpib && 599 chip->get_position[1] == azx_get_pos_lpib) 600 azx_bus(chip)->use_posbuf = false; 601 pos = azx_get_pos_lpib(chip, azx_dev); 602 chip->get_delay[stream] = NULL; 603 } else { 604 chip->get_position[stream] = azx_get_pos_posbuf; 605 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 606 chip->get_delay[stream] = azx_get_delay_from_lpib; 607 } 608 } 609 610 if (pos >= azx_dev->core.bufsize) 611 pos = 0; 612 613 if (WARN_ONCE(!azx_dev->core.period_bytes, 614 "hda-intel: zero azx_dev->period_bytes")) 615 return -1; /* this shouldn't happen! */ 616 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 617 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 618 /* NG - it's below the first next period boundary */ 619 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; 620 azx_dev->core.start_wallclk += wallclk; 621 return 1; /* OK, it's fine */ 622 } 623 624 /* 625 * The work for pending PCM period updates. 626 */ 627 static void azx_irq_pending_work(struct work_struct *work) 628 { 629 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 630 struct azx *chip = &hda->chip; 631 struct hdac_bus *bus = azx_bus(chip); 632 struct hdac_stream *s; 633 int pending, ok; 634 635 if (!hda->irq_pending_warned) { 636 dev_info(chip->card->dev, 637 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 638 chip->card->number); 639 hda->irq_pending_warned = 1; 640 } 641 642 for (;;) { 643 pending = 0; 644 spin_lock_irq(&bus->reg_lock); 645 list_for_each_entry(s, &bus->stream_list, list) { 646 struct azx_dev *azx_dev = stream_to_azx_dev(s); 647 if (!azx_dev->irq_pending || 648 !s->substream || 649 !s->running) 650 continue; 651 ok = azx_position_ok(chip, azx_dev); 652 if (ok > 0) { 653 azx_dev->irq_pending = 0; 654 spin_unlock(&bus->reg_lock); 655 snd_pcm_period_elapsed(s->substream); 656 spin_lock(&bus->reg_lock); 657 } else if (ok < 0) { 658 pending = 0; /* too early */ 659 } else 660 pending++; 661 } 662 spin_unlock_irq(&bus->reg_lock); 663 if (!pending) 664 return; 665 msleep(1); 666 } 667 } 668 669 /* clear irq_pending flags and assure no on-going workq */ 670 static void azx_clear_irq_pending(struct azx *chip) 671 { 672 struct hdac_bus *bus = azx_bus(chip); 673 struct hdac_stream *s; 674 675 spin_lock_irq(&bus->reg_lock); 676 list_for_each_entry(s, &bus->stream_list, list) { 677 struct azx_dev *azx_dev = stream_to_azx_dev(s); 678 azx_dev->irq_pending = 0; 679 } 680 spin_unlock_irq(&bus->reg_lock); 681 } 682 683 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 684 { 685 struct hdac_bus *bus = azx_bus(chip); 686 687 if (request_irq(chip->pci->irq, azx_interrupt, 688 chip->msi ? 0 : IRQF_SHARED, 689 KBUILD_MODNAME, chip)) { 690 dev_err(chip->card->dev, 691 "unable to grab IRQ %d, disabling device\n", 692 chip->pci->irq); 693 if (do_disconnect) 694 snd_card_disconnect(chip->card); 695 return -1; 696 } 697 bus->irq = chip->pci->irq; 698 pci_intx(chip->pci, !chip->msi); 699 return 0; 700 } 701 702 /* get the current DMA position with correction on VIA chips */ 703 static unsigned int azx_via_get_position(struct azx *chip, 704 struct azx_dev *azx_dev) 705 { 706 unsigned int link_pos, mini_pos, bound_pos; 707 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 708 unsigned int fifo_size; 709 710 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 711 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 712 /* Playback, no problem using link position */ 713 return link_pos; 714 } 715 716 /* Capture */ 717 /* For new chipset, 718 * use mod to get the DMA position just like old chipset 719 */ 720 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 721 mod_dma_pos %= azx_dev->core.period_bytes; 722 723 /* azx_dev->fifo_size can't get FIFO size of in stream. 724 * Get from base address + offset. 725 */ 726 fifo_size = readw(azx_bus(chip)->remap_addr + 727 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 728 729 if (azx_dev->insufficient) { 730 /* Link position never gather than FIFO size */ 731 if (link_pos <= fifo_size) 732 return 0; 733 734 azx_dev->insufficient = 0; 735 } 736 737 if (link_pos <= fifo_size) 738 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 739 else 740 mini_pos = link_pos - fifo_size; 741 742 /* Find nearest previous boudary */ 743 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 744 mod_link_pos = link_pos % azx_dev->core.period_bytes; 745 if (mod_link_pos >= fifo_size) 746 bound_pos = link_pos - mod_link_pos; 747 else if (mod_dma_pos >= mod_mini_pos) 748 bound_pos = mini_pos - mod_mini_pos; 749 else { 750 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 751 if (bound_pos >= azx_dev->core.bufsize) 752 bound_pos = 0; 753 } 754 755 /* Calculate real DMA position we want */ 756 return bound_pos + mod_dma_pos; 757 } 758 759 #ifdef CONFIG_PM 760 static DEFINE_MUTEX(card_list_lock); 761 static LIST_HEAD(card_list); 762 763 static void azx_add_card_list(struct azx *chip) 764 { 765 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 766 mutex_lock(&card_list_lock); 767 list_add(&hda->list, &card_list); 768 mutex_unlock(&card_list_lock); 769 } 770 771 static void azx_del_card_list(struct azx *chip) 772 { 773 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 774 mutex_lock(&card_list_lock); 775 list_del_init(&hda->list); 776 mutex_unlock(&card_list_lock); 777 } 778 779 /* trigger power-save check at writing parameter */ 780 static int param_set_xint(const char *val, const struct kernel_param *kp) 781 { 782 struct hda_intel *hda; 783 struct azx *chip; 784 int prev = power_save; 785 int ret = param_set_int(val, kp); 786 787 if (ret || prev == power_save) 788 return ret; 789 790 mutex_lock(&card_list_lock); 791 list_for_each_entry(hda, &card_list, list) { 792 chip = &hda->chip; 793 if (!hda->probe_continued || chip->disabled) 794 continue; 795 snd_hda_set_power_save(&chip->bus, power_save * 1000); 796 } 797 mutex_unlock(&card_list_lock); 798 return 0; 799 } 800 #else 801 #define azx_add_card_list(chip) /* NOP */ 802 #define azx_del_card_list(chip) /* NOP */ 803 #endif /* CONFIG_PM */ 804 805 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK 806 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value) 807 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK: 808 * BCLK = CDCLK * M / N 809 * The values will be lost when the display power well is disabled and need to 810 * be restored to avoid abnormal playback speed. 811 */ 812 static void haswell_set_bclk(struct hda_intel *hda) 813 { 814 struct azx *chip = &hda->chip; 815 int cdclk_freq; 816 unsigned int bclk_m, bclk_n; 817 818 if (!hda->need_i915_power) 819 return; 820 821 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip)); 822 switch (cdclk_freq) { 823 case 337500: 824 bclk_m = 16; 825 bclk_n = 225; 826 break; 827 828 case 450000: 829 default: /* default CDCLK 450MHz */ 830 bclk_m = 4; 831 bclk_n = 75; 832 break; 833 834 case 540000: 835 bclk_m = 4; 836 bclk_n = 90; 837 break; 838 839 case 675000: 840 bclk_m = 8; 841 bclk_n = 225; 842 break; 843 } 844 845 azx_writew(chip, HSW_EM4, bclk_m); 846 azx_writew(chip, HSW_EM5, bclk_n); 847 } 848 849 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 850 /* 851 * power management 852 */ 853 static int azx_suspend(struct device *dev) 854 { 855 struct snd_card *card = dev_get_drvdata(dev); 856 struct azx *chip; 857 struct hda_intel *hda; 858 struct hdac_bus *bus; 859 860 if (!card) 861 return 0; 862 863 chip = card->private_data; 864 hda = container_of(chip, struct hda_intel, chip); 865 if (chip->disabled || hda->init_failed) 866 return 0; 867 868 bus = azx_bus(chip); 869 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 870 azx_clear_irq_pending(chip); 871 azx_stop_chip(chip); 872 azx_enter_link_reset(chip); 873 if (bus->irq >= 0) { 874 free_irq(bus->irq, chip); 875 bus->irq = -1; 876 } 877 878 if (chip->msi) 879 pci_disable_msi(chip->pci); 880 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 881 && hda->need_i915_power) 882 snd_hdac_display_power(bus, false); 883 884 trace_azx_suspend(chip); 885 return 0; 886 } 887 888 static int azx_resume(struct device *dev) 889 { 890 struct pci_dev *pci = to_pci_dev(dev); 891 struct snd_card *card = dev_get_drvdata(dev); 892 struct azx *chip; 893 struct hda_intel *hda; 894 895 if (!card) 896 return 0; 897 898 chip = card->private_data; 899 hda = container_of(chip, struct hda_intel, chip); 900 if (chip->disabled || hda->init_failed) 901 return 0; 902 903 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 904 && hda->need_i915_power) { 905 snd_hdac_display_power(azx_bus(chip), true); 906 haswell_set_bclk(hda); 907 } 908 if (chip->msi) 909 if (pci_enable_msi(pci) < 0) 910 chip->msi = 0; 911 if (azx_acquire_irq(chip, 1) < 0) 912 return -EIO; 913 azx_init_pci(chip); 914 915 hda_intel_init_chip(chip, true); 916 917 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 918 919 trace_azx_resume(chip); 920 return 0; 921 } 922 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 923 924 #ifdef CONFIG_PM 925 static int azx_runtime_suspend(struct device *dev) 926 { 927 struct snd_card *card = dev_get_drvdata(dev); 928 struct azx *chip; 929 struct hda_intel *hda; 930 931 if (!card) 932 return 0; 933 934 chip = card->private_data; 935 hda = container_of(chip, struct hda_intel, chip); 936 if (chip->disabled || hda->init_failed) 937 return 0; 938 939 if (!azx_has_pm_runtime(chip)) 940 return 0; 941 942 /* enable controller wake up event */ 943 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 944 STATESTS_INT_MASK); 945 946 azx_stop_chip(chip); 947 azx_enter_link_reset(chip); 948 azx_clear_irq_pending(chip); 949 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 950 && hda->need_i915_power) 951 snd_hdac_display_power(azx_bus(chip), false); 952 953 trace_azx_runtime_suspend(chip); 954 return 0; 955 } 956 957 static int azx_runtime_resume(struct device *dev) 958 { 959 struct snd_card *card = dev_get_drvdata(dev); 960 struct azx *chip; 961 struct hda_intel *hda; 962 struct hdac_bus *bus; 963 struct hda_codec *codec; 964 int status; 965 966 if (!card) 967 return 0; 968 969 chip = card->private_data; 970 hda = container_of(chip, struct hda_intel, chip); 971 if (chip->disabled || hda->init_failed) 972 return 0; 973 974 if (!azx_has_pm_runtime(chip)) 975 return 0; 976 977 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 978 && hda->need_i915_power) { 979 bus = azx_bus(chip); 980 snd_hdac_display_power(bus, true); 981 haswell_set_bclk(hda); 982 /* toggle codec wakeup bit for STATESTS read */ 983 snd_hdac_set_codec_wakeup(bus, true); 984 snd_hdac_set_codec_wakeup(bus, false); 985 } 986 987 /* Read STATESTS before controller reset */ 988 status = azx_readw(chip, STATESTS); 989 990 azx_init_pci(chip); 991 hda_intel_init_chip(chip, true); 992 993 if (status) { 994 list_for_each_codec(codec, &chip->bus) 995 if (status & (1 << codec->addr)) 996 schedule_delayed_work(&codec->jackpoll_work, 997 codec->jackpoll_interval); 998 } 999 1000 /* disable controller Wake Up event*/ 1001 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1002 ~STATESTS_INT_MASK); 1003 1004 trace_azx_runtime_resume(chip); 1005 return 0; 1006 } 1007 1008 static int azx_runtime_idle(struct device *dev) 1009 { 1010 struct snd_card *card = dev_get_drvdata(dev); 1011 struct azx *chip; 1012 struct hda_intel *hda; 1013 1014 if (!card) 1015 return 0; 1016 1017 chip = card->private_data; 1018 hda = container_of(chip, struct hda_intel, chip); 1019 if (chip->disabled || hda->init_failed) 1020 return 0; 1021 1022 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1023 azx_bus(chip)->codec_powered) 1024 return -EBUSY; 1025 1026 return 0; 1027 } 1028 1029 static const struct dev_pm_ops azx_pm = { 1030 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1031 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1032 }; 1033 1034 #define AZX_PM_OPS &azx_pm 1035 #else 1036 #define AZX_PM_OPS NULL 1037 #endif /* CONFIG_PM */ 1038 1039 1040 static int azx_probe_continue(struct azx *chip); 1041 1042 #ifdef SUPPORT_VGA_SWITCHEROO 1043 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1044 1045 static void azx_vs_set_state(struct pci_dev *pci, 1046 enum vga_switcheroo_state state) 1047 { 1048 struct snd_card *card = pci_get_drvdata(pci); 1049 struct azx *chip = card->private_data; 1050 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1051 bool disabled; 1052 1053 wait_for_completion(&hda->probe_wait); 1054 if (hda->init_failed) 1055 return; 1056 1057 disabled = (state == VGA_SWITCHEROO_OFF); 1058 if (chip->disabled == disabled) 1059 return; 1060 1061 if (!hda->probe_continued) { 1062 chip->disabled = disabled; 1063 if (!disabled) { 1064 dev_info(chip->card->dev, 1065 "Start delayed initialization\n"); 1066 if (azx_probe_continue(chip) < 0) { 1067 dev_err(chip->card->dev, "initialization error\n"); 1068 hda->init_failed = true; 1069 } 1070 } 1071 } else { 1072 dev_info(chip->card->dev, "%s via VGA-switcheroo\n", 1073 disabled ? "Disabling" : "Enabling"); 1074 if (disabled) { 1075 pm_runtime_put_sync_suspend(card->dev); 1076 azx_suspend(card->dev); 1077 /* when we get suspended by vga switcheroo we end up in D3cold, 1078 * however we have no ACPI handle, so pci/acpi can't put us there, 1079 * put ourselves there */ 1080 pci->current_state = PCI_D3cold; 1081 chip->disabled = true; 1082 if (snd_hda_lock_devices(&chip->bus)) 1083 dev_warn(chip->card->dev, 1084 "Cannot lock devices!\n"); 1085 } else { 1086 snd_hda_unlock_devices(&chip->bus); 1087 pm_runtime_get_noresume(card->dev); 1088 chip->disabled = false; 1089 azx_resume(card->dev); 1090 } 1091 } 1092 } 1093 1094 static bool azx_vs_can_switch(struct pci_dev *pci) 1095 { 1096 struct snd_card *card = pci_get_drvdata(pci); 1097 struct azx *chip = card->private_data; 1098 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1099 1100 wait_for_completion(&hda->probe_wait); 1101 if (hda->init_failed) 1102 return false; 1103 if (chip->disabled || !hda->probe_continued) 1104 return true; 1105 if (snd_hda_lock_devices(&chip->bus)) 1106 return false; 1107 snd_hda_unlock_devices(&chip->bus); 1108 return true; 1109 } 1110 1111 static void init_vga_switcheroo(struct azx *chip) 1112 { 1113 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1114 struct pci_dev *p = get_bound_vga(chip->pci); 1115 if (p) { 1116 dev_info(chip->card->dev, 1117 "Handle VGA-switcheroo audio client\n"); 1118 hda->use_vga_switcheroo = 1; 1119 pci_dev_put(p); 1120 } 1121 } 1122 1123 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1124 .set_gpu_state = azx_vs_set_state, 1125 .can_switch = azx_vs_can_switch, 1126 }; 1127 1128 static int register_vga_switcheroo(struct azx *chip) 1129 { 1130 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1131 int err; 1132 1133 if (!hda->use_vga_switcheroo) 1134 return 0; 1135 /* FIXME: currently only handling DIS controller 1136 * is there any machine with two switchable HDMI audio controllers? 1137 */ 1138 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1139 VGA_SWITCHEROO_DIS, 1140 hda->probe_continued); 1141 if (err < 0) 1142 return err; 1143 hda->vga_switcheroo_registered = 1; 1144 1145 /* register as an optimus hdmi audio power domain */ 1146 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1147 &hda->hdmi_pm_domain); 1148 return 0; 1149 } 1150 #else 1151 #define init_vga_switcheroo(chip) /* NOP */ 1152 #define register_vga_switcheroo(chip) 0 1153 #define check_hdmi_disabled(pci) false 1154 #endif /* SUPPORT_VGA_SWITCHER */ 1155 1156 /* 1157 * destructor 1158 */ 1159 static int azx_free(struct azx *chip) 1160 { 1161 struct pci_dev *pci = chip->pci; 1162 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1163 struct hdac_bus *bus = azx_bus(chip); 1164 1165 if (azx_has_pm_runtime(chip) && chip->running) 1166 pm_runtime_get_noresume(&pci->dev); 1167 1168 azx_del_card_list(chip); 1169 1170 hda->init_failed = 1; /* to be sure */ 1171 complete_all(&hda->probe_wait); 1172 1173 if (use_vga_switcheroo(hda)) { 1174 if (chip->disabled && hda->probe_continued) 1175 snd_hda_unlock_devices(&chip->bus); 1176 if (hda->vga_switcheroo_registered) 1177 vga_switcheroo_unregister_client(chip->pci); 1178 } 1179 1180 if (bus->chip_init) { 1181 azx_clear_irq_pending(chip); 1182 azx_stop_all_streams(chip); 1183 azx_stop_chip(chip); 1184 } 1185 1186 if (bus->irq >= 0) 1187 free_irq(bus->irq, (void*)chip); 1188 if (chip->msi) 1189 pci_disable_msi(chip->pci); 1190 iounmap(bus->remap_addr); 1191 1192 azx_free_stream_pages(chip); 1193 azx_free_streams(chip); 1194 snd_hdac_bus_exit(bus); 1195 1196 if (chip->region_requested) 1197 pci_release_regions(chip->pci); 1198 1199 pci_disable_device(chip->pci); 1200 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1201 release_firmware(chip->fw); 1202 #endif 1203 1204 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1205 if (hda->need_i915_power) 1206 snd_hdac_display_power(bus, false); 1207 snd_hdac_i915_exit(bus); 1208 } 1209 kfree(hda); 1210 1211 return 0; 1212 } 1213 1214 static int azx_dev_disconnect(struct snd_device *device) 1215 { 1216 struct azx *chip = device->device_data; 1217 1218 chip->bus.shutdown = 1; 1219 return 0; 1220 } 1221 1222 static int azx_dev_free(struct snd_device *device) 1223 { 1224 return azx_free(device->device_data); 1225 } 1226 1227 #ifdef SUPPORT_VGA_SWITCHEROO 1228 /* 1229 * Check of disabled HDMI controller by vga-switcheroo 1230 */ 1231 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1232 { 1233 struct pci_dev *p; 1234 1235 /* check only discrete GPU */ 1236 switch (pci->vendor) { 1237 case PCI_VENDOR_ID_ATI: 1238 case PCI_VENDOR_ID_AMD: 1239 case PCI_VENDOR_ID_NVIDIA: 1240 if (pci->devfn == 1) { 1241 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1242 pci->bus->number, 0); 1243 if (p) { 1244 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1245 return p; 1246 pci_dev_put(p); 1247 } 1248 } 1249 break; 1250 } 1251 return NULL; 1252 } 1253 1254 static bool check_hdmi_disabled(struct pci_dev *pci) 1255 { 1256 bool vga_inactive = false; 1257 struct pci_dev *p = get_bound_vga(pci); 1258 1259 if (p) { 1260 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1261 vga_inactive = true; 1262 pci_dev_put(p); 1263 } 1264 return vga_inactive; 1265 } 1266 #endif /* SUPPORT_VGA_SWITCHEROO */ 1267 1268 /* 1269 * white/black-listing for position_fix 1270 */ 1271 static struct snd_pci_quirk position_fix_list[] = { 1272 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1273 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1274 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1275 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1276 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1277 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1278 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1279 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1280 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1281 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1282 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1283 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1284 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1285 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1286 {} 1287 }; 1288 1289 static int check_position_fix(struct azx *chip, int fix) 1290 { 1291 const struct snd_pci_quirk *q; 1292 1293 switch (fix) { 1294 case POS_FIX_AUTO: 1295 case POS_FIX_LPIB: 1296 case POS_FIX_POSBUF: 1297 case POS_FIX_VIACOMBO: 1298 case POS_FIX_COMBO: 1299 return fix; 1300 } 1301 1302 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1303 if (q) { 1304 dev_info(chip->card->dev, 1305 "position_fix set to %d for device %04x:%04x\n", 1306 q->value, q->subvendor, q->subdevice); 1307 return q->value; 1308 } 1309 1310 /* Check VIA/ATI HD Audio Controller exist */ 1311 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 1312 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1313 return POS_FIX_VIACOMBO; 1314 } 1315 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1316 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1317 return POS_FIX_LPIB; 1318 } 1319 return POS_FIX_AUTO; 1320 } 1321 1322 static void assign_position_fix(struct azx *chip, int fix) 1323 { 1324 static azx_get_pos_callback_t callbacks[] = { 1325 [POS_FIX_AUTO] = NULL, 1326 [POS_FIX_LPIB] = azx_get_pos_lpib, 1327 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1328 [POS_FIX_VIACOMBO] = azx_via_get_position, 1329 [POS_FIX_COMBO] = azx_get_pos_lpib, 1330 }; 1331 1332 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1333 1334 /* combo mode uses LPIB only for playback */ 1335 if (fix == POS_FIX_COMBO) 1336 chip->get_position[1] = NULL; 1337 1338 if (fix == POS_FIX_POSBUF && 1339 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1340 chip->get_delay[0] = chip->get_delay[1] = 1341 azx_get_delay_from_lpib; 1342 } 1343 1344 } 1345 1346 /* 1347 * black-lists for probe_mask 1348 */ 1349 static struct snd_pci_quirk probe_mask_list[] = { 1350 /* Thinkpad often breaks the controller communication when accessing 1351 * to the non-working (or non-existing) modem codec slot. 1352 */ 1353 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1354 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1355 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1356 /* broken BIOS */ 1357 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1358 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1359 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1360 /* forced codec slots */ 1361 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1362 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1363 /* WinFast VP200 H (Teradici) user reported broken communication */ 1364 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1365 {} 1366 }; 1367 1368 #define AZX_FORCE_CODEC_MASK 0x100 1369 1370 static void check_probe_mask(struct azx *chip, int dev) 1371 { 1372 const struct snd_pci_quirk *q; 1373 1374 chip->codec_probe_mask = probe_mask[dev]; 1375 if (chip->codec_probe_mask == -1) { 1376 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1377 if (q) { 1378 dev_info(chip->card->dev, 1379 "probe_mask set to 0x%x for device %04x:%04x\n", 1380 q->value, q->subvendor, q->subdevice); 1381 chip->codec_probe_mask = q->value; 1382 } 1383 } 1384 1385 /* check forced option */ 1386 if (chip->codec_probe_mask != -1 && 1387 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1388 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1389 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1390 (int)azx_bus(chip)->codec_mask); 1391 } 1392 } 1393 1394 /* 1395 * white/black-list for enable_msi 1396 */ 1397 static struct snd_pci_quirk msi_black_list[] = { 1398 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1399 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1400 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1401 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1402 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1403 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1404 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1405 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1406 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1407 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1408 {} 1409 }; 1410 1411 static void check_msi(struct azx *chip) 1412 { 1413 const struct snd_pci_quirk *q; 1414 1415 if (enable_msi >= 0) { 1416 chip->msi = !!enable_msi; 1417 return; 1418 } 1419 chip->msi = 1; /* enable MSI as default */ 1420 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1421 if (q) { 1422 dev_info(chip->card->dev, 1423 "msi for device %04x:%04x set to %d\n", 1424 q->subvendor, q->subdevice, q->value); 1425 chip->msi = q->value; 1426 return; 1427 } 1428 1429 /* NVidia chipsets seem to cause troubles with MSI */ 1430 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1431 dev_info(chip->card->dev, "Disabling MSI\n"); 1432 chip->msi = 0; 1433 } 1434 } 1435 1436 /* check the snoop mode availability */ 1437 static void azx_check_snoop_available(struct azx *chip) 1438 { 1439 int snoop = hda_snoop; 1440 1441 if (snoop >= 0) { 1442 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1443 snoop ? "snoop" : "non-snoop"); 1444 chip->snoop = snoop; 1445 return; 1446 } 1447 1448 snoop = true; 1449 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1450 chip->driver_type == AZX_DRIVER_VIA) { 1451 /* force to non-snoop mode for a new VIA controller 1452 * when BIOS is set 1453 */ 1454 u8 val; 1455 pci_read_config_byte(chip->pci, 0x42, &val); 1456 if (!(val & 0x80) && chip->pci->revision == 0x30) 1457 snoop = false; 1458 } 1459 1460 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1461 snoop = false; 1462 1463 chip->snoop = snoop; 1464 if (!snoop) 1465 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1466 } 1467 1468 static void azx_probe_work(struct work_struct *work) 1469 { 1470 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1471 azx_probe_continue(&hda->chip); 1472 } 1473 1474 /* 1475 * constructor 1476 */ 1477 static const struct hdac_io_ops pci_hda_io_ops; 1478 static const struct hda_controller_ops pci_hda_ops; 1479 1480 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1481 int dev, unsigned int driver_caps, 1482 struct azx **rchip) 1483 { 1484 static struct snd_device_ops ops = { 1485 .dev_disconnect = azx_dev_disconnect, 1486 .dev_free = azx_dev_free, 1487 }; 1488 struct hda_intel *hda; 1489 struct azx *chip; 1490 int err; 1491 1492 *rchip = NULL; 1493 1494 err = pci_enable_device(pci); 1495 if (err < 0) 1496 return err; 1497 1498 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1499 if (!hda) { 1500 pci_disable_device(pci); 1501 return -ENOMEM; 1502 } 1503 1504 chip = &hda->chip; 1505 mutex_init(&chip->open_mutex); 1506 chip->card = card; 1507 chip->pci = pci; 1508 chip->ops = &pci_hda_ops; 1509 chip->driver_caps = driver_caps; 1510 chip->driver_type = driver_caps & 0xff; 1511 check_msi(chip); 1512 chip->dev_index = dev; 1513 chip->jackpoll_ms = jackpoll_ms; 1514 INIT_LIST_HEAD(&chip->pcm_list); 1515 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1516 INIT_LIST_HEAD(&hda->list); 1517 init_vga_switcheroo(chip); 1518 init_completion(&hda->probe_wait); 1519 1520 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1521 1522 check_probe_mask(chip, dev); 1523 1524 chip->single_cmd = single_cmd; 1525 azx_check_snoop_available(chip); 1526 1527 if (bdl_pos_adj[dev] < 0) { 1528 switch (chip->driver_type) { 1529 case AZX_DRIVER_ICH: 1530 case AZX_DRIVER_PCH: 1531 bdl_pos_adj[dev] = 1; 1532 break; 1533 default: 1534 bdl_pos_adj[dev] = 32; 1535 break; 1536 } 1537 } 1538 chip->bdl_pos_adj = bdl_pos_adj; 1539 1540 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1541 if (err < 0) { 1542 kfree(hda); 1543 pci_disable_device(pci); 1544 return err; 1545 } 1546 1547 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1548 if (err < 0) { 1549 dev_err(card->dev, "Error creating device [card]!\n"); 1550 azx_free(chip); 1551 return err; 1552 } 1553 1554 /* continue probing in work context as may trigger request module */ 1555 INIT_WORK(&hda->probe_work, azx_probe_work); 1556 1557 *rchip = chip; 1558 1559 return 0; 1560 } 1561 1562 static int azx_first_init(struct azx *chip) 1563 { 1564 int dev = chip->dev_index; 1565 struct pci_dev *pci = chip->pci; 1566 struct snd_card *card = chip->card; 1567 struct hdac_bus *bus = azx_bus(chip); 1568 int err; 1569 unsigned short gcap; 1570 unsigned int dma_bits = 64; 1571 1572 #if BITS_PER_LONG != 64 1573 /* Fix up base address on ULI M5461 */ 1574 if (chip->driver_type == AZX_DRIVER_ULI) { 1575 u16 tmp3; 1576 pci_read_config_word(pci, 0x40, &tmp3); 1577 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1578 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1579 } 1580 #endif 1581 1582 err = pci_request_regions(pci, "ICH HD audio"); 1583 if (err < 0) 1584 return err; 1585 chip->region_requested = 1; 1586 1587 bus->addr = pci_resource_start(pci, 0); 1588 bus->remap_addr = pci_ioremap_bar(pci, 0); 1589 if (bus->remap_addr == NULL) { 1590 dev_err(card->dev, "ioremap error\n"); 1591 return -ENXIO; 1592 } 1593 1594 if (chip->msi) { 1595 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1596 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1597 pci->no_64bit_msi = true; 1598 } 1599 if (pci_enable_msi(pci) < 0) 1600 chip->msi = 0; 1601 } 1602 1603 if (azx_acquire_irq(chip, 0) < 0) 1604 return -EBUSY; 1605 1606 pci_set_master(pci); 1607 synchronize_irq(bus->irq); 1608 1609 gcap = azx_readw(chip, GCAP); 1610 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1611 1612 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1613 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1614 dma_bits = 40; 1615 1616 /* disable SB600 64bit support for safety */ 1617 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1618 struct pci_dev *p_smbus; 1619 dma_bits = 40; 1620 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1621 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1622 NULL); 1623 if (p_smbus) { 1624 if (p_smbus->revision < 0x30) 1625 gcap &= ~AZX_GCAP_64OK; 1626 pci_dev_put(p_smbus); 1627 } 1628 } 1629 1630 /* disable 64bit DMA address on some devices */ 1631 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1632 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1633 gcap &= ~AZX_GCAP_64OK; 1634 } 1635 1636 /* disable buffer size rounding to 128-byte multiples if supported */ 1637 if (align_buffer_size >= 0) 1638 chip->align_buffer_size = !!align_buffer_size; 1639 else { 1640 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1641 chip->align_buffer_size = 0; 1642 else 1643 chip->align_buffer_size = 1; 1644 } 1645 1646 /* allow 64bit DMA address if supported by H/W */ 1647 if (!(gcap & AZX_GCAP_64OK)) 1648 dma_bits = 32; 1649 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1650 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1651 } else { 1652 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1653 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1654 } 1655 1656 /* read number of streams from GCAP register instead of using 1657 * hardcoded value 1658 */ 1659 chip->capture_streams = (gcap >> 8) & 0x0f; 1660 chip->playback_streams = (gcap >> 12) & 0x0f; 1661 if (!chip->playback_streams && !chip->capture_streams) { 1662 /* gcap didn't give any info, switching to old method */ 1663 1664 switch (chip->driver_type) { 1665 case AZX_DRIVER_ULI: 1666 chip->playback_streams = ULI_NUM_PLAYBACK; 1667 chip->capture_streams = ULI_NUM_CAPTURE; 1668 break; 1669 case AZX_DRIVER_ATIHDMI: 1670 case AZX_DRIVER_ATIHDMI_NS: 1671 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1672 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1673 break; 1674 case AZX_DRIVER_GENERIC: 1675 default: 1676 chip->playback_streams = ICH6_NUM_PLAYBACK; 1677 chip->capture_streams = ICH6_NUM_CAPTURE; 1678 break; 1679 } 1680 } 1681 chip->capture_index_offset = 0; 1682 chip->playback_index_offset = chip->capture_streams; 1683 chip->num_streams = chip->playback_streams + chip->capture_streams; 1684 1685 /* initialize streams */ 1686 err = azx_init_streams(chip); 1687 if (err < 0) 1688 return err; 1689 1690 err = azx_alloc_stream_pages(chip); 1691 if (err < 0) 1692 return err; 1693 1694 /* initialize chip */ 1695 azx_init_pci(chip); 1696 1697 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1698 struct hda_intel *hda; 1699 1700 hda = container_of(chip, struct hda_intel, chip); 1701 haswell_set_bclk(hda); 1702 } 1703 1704 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1705 1706 /* codec detection */ 1707 if (!azx_bus(chip)->codec_mask) { 1708 dev_err(card->dev, "no codecs found!\n"); 1709 return -ENODEV; 1710 } 1711 1712 strcpy(card->driver, "HDA-Intel"); 1713 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1714 sizeof(card->shortname)); 1715 snprintf(card->longname, sizeof(card->longname), 1716 "%s at 0x%lx irq %i", 1717 card->shortname, bus->addr, bus->irq); 1718 1719 return 0; 1720 } 1721 1722 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1723 /* callback from request_firmware_nowait() */ 1724 static void azx_firmware_cb(const struct firmware *fw, void *context) 1725 { 1726 struct snd_card *card = context; 1727 struct azx *chip = card->private_data; 1728 struct pci_dev *pci = chip->pci; 1729 1730 if (!fw) { 1731 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1732 goto error; 1733 } 1734 1735 chip->fw = fw; 1736 if (!chip->disabled) { 1737 /* continue probing */ 1738 if (azx_probe_continue(chip)) 1739 goto error; 1740 } 1741 return; /* OK */ 1742 1743 error: 1744 snd_card_free(card); 1745 pci_set_drvdata(pci, NULL); 1746 } 1747 #endif 1748 1749 /* 1750 * HDA controller ops. 1751 */ 1752 1753 /* PCI register access. */ 1754 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1755 { 1756 writel(value, addr); 1757 } 1758 1759 static u32 pci_azx_readl(u32 __iomem *addr) 1760 { 1761 return readl(addr); 1762 } 1763 1764 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1765 { 1766 writew(value, addr); 1767 } 1768 1769 static u16 pci_azx_readw(u16 __iomem *addr) 1770 { 1771 return readw(addr); 1772 } 1773 1774 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1775 { 1776 writeb(value, addr); 1777 } 1778 1779 static u8 pci_azx_readb(u8 __iomem *addr) 1780 { 1781 return readb(addr); 1782 } 1783 1784 static int disable_msi_reset_irq(struct azx *chip) 1785 { 1786 struct hdac_bus *bus = azx_bus(chip); 1787 int err; 1788 1789 free_irq(bus->irq, chip); 1790 bus->irq = -1; 1791 pci_disable_msi(chip->pci); 1792 chip->msi = 0; 1793 err = azx_acquire_irq(chip, 1); 1794 if (err < 0) 1795 return err; 1796 1797 return 0; 1798 } 1799 1800 /* DMA page allocation helpers. */ 1801 static int dma_alloc_pages(struct hdac_bus *bus, 1802 int type, 1803 size_t size, 1804 struct snd_dma_buffer *buf) 1805 { 1806 struct azx *chip = bus_to_azx(bus); 1807 int err; 1808 1809 err = snd_dma_alloc_pages(type, 1810 bus->dev, 1811 size, buf); 1812 if (err < 0) 1813 return err; 1814 mark_pages_wc(chip, buf, true); 1815 return 0; 1816 } 1817 1818 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 1819 { 1820 struct azx *chip = bus_to_azx(bus); 1821 1822 mark_pages_wc(chip, buf, false); 1823 snd_dma_free_pages(buf); 1824 } 1825 1826 static int substream_alloc_pages(struct azx *chip, 1827 struct snd_pcm_substream *substream, 1828 size_t size) 1829 { 1830 struct azx_dev *azx_dev = get_azx_dev(substream); 1831 int ret; 1832 1833 mark_runtime_wc(chip, azx_dev, substream, false); 1834 ret = snd_pcm_lib_malloc_pages(substream, size); 1835 if (ret < 0) 1836 return ret; 1837 mark_runtime_wc(chip, azx_dev, substream, true); 1838 return 0; 1839 } 1840 1841 static int substream_free_pages(struct azx *chip, 1842 struct snd_pcm_substream *substream) 1843 { 1844 struct azx_dev *azx_dev = get_azx_dev(substream); 1845 mark_runtime_wc(chip, azx_dev, substream, false); 1846 return snd_pcm_lib_free_pages(substream); 1847 } 1848 1849 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1850 struct vm_area_struct *area) 1851 { 1852 #ifdef CONFIG_X86 1853 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1854 struct azx *chip = apcm->chip; 1855 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1856 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1857 #endif 1858 } 1859 1860 static const struct hdac_io_ops pci_hda_io_ops = { 1861 .reg_writel = pci_azx_writel, 1862 .reg_readl = pci_azx_readl, 1863 .reg_writew = pci_azx_writew, 1864 .reg_readw = pci_azx_readw, 1865 .reg_writeb = pci_azx_writeb, 1866 .reg_readb = pci_azx_readb, 1867 .dma_alloc_pages = dma_alloc_pages, 1868 .dma_free_pages = dma_free_pages, 1869 }; 1870 1871 static const struct hda_controller_ops pci_hda_ops = { 1872 .disable_msi_reset_irq = disable_msi_reset_irq, 1873 .substream_alloc_pages = substream_alloc_pages, 1874 .substream_free_pages = substream_free_pages, 1875 .pcm_mmap_prepare = pcm_mmap_prepare, 1876 .position_check = azx_position_check, 1877 .link_power = azx_intel_link_power, 1878 }; 1879 1880 static int azx_probe(struct pci_dev *pci, 1881 const struct pci_device_id *pci_id) 1882 { 1883 static int dev; 1884 struct snd_card *card; 1885 struct hda_intel *hda; 1886 struct azx *chip; 1887 bool schedule_probe; 1888 int err; 1889 1890 if (dev >= SNDRV_CARDS) 1891 return -ENODEV; 1892 if (!enable[dev]) { 1893 dev++; 1894 return -ENOENT; 1895 } 1896 1897 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1898 0, &card); 1899 if (err < 0) { 1900 dev_err(&pci->dev, "Error creating card!\n"); 1901 return err; 1902 } 1903 1904 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 1905 if (err < 0) 1906 goto out_free; 1907 card->private_data = chip; 1908 hda = container_of(chip, struct hda_intel, chip); 1909 1910 pci_set_drvdata(pci, card); 1911 1912 err = register_vga_switcheroo(chip); 1913 if (err < 0) { 1914 dev_err(card->dev, "Error registering VGA-switcheroo client\n"); 1915 goto out_free; 1916 } 1917 1918 if (check_hdmi_disabled(pci)) { 1919 dev_info(card->dev, "VGA controller is disabled\n"); 1920 dev_info(card->dev, "Delaying initialization\n"); 1921 chip->disabled = true; 1922 } 1923 1924 schedule_probe = !chip->disabled; 1925 1926 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1927 if (patch[dev] && *patch[dev]) { 1928 dev_info(card->dev, "Applying patch firmware '%s'\n", 1929 patch[dev]); 1930 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1931 &pci->dev, GFP_KERNEL, card, 1932 azx_firmware_cb); 1933 if (err < 0) 1934 goto out_free; 1935 schedule_probe = false; /* continued in azx_firmware_cb() */ 1936 } 1937 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1938 1939 #ifndef CONFIG_SND_HDA_I915 1940 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1941 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); 1942 #endif 1943 1944 if (schedule_probe) 1945 schedule_work(&hda->probe_work); 1946 1947 dev++; 1948 if (chip->disabled) 1949 complete_all(&hda->probe_wait); 1950 return 0; 1951 1952 out_free: 1953 snd_card_free(card); 1954 return err; 1955 } 1956 1957 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1958 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1959 [AZX_DRIVER_NVIDIA] = 8, 1960 [AZX_DRIVER_TERA] = 1, 1961 }; 1962 1963 static int azx_probe_continue(struct azx *chip) 1964 { 1965 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1966 struct hdac_bus *bus = azx_bus(chip); 1967 struct pci_dev *pci = chip->pci; 1968 int dev = chip->dev_index; 1969 int err; 1970 1971 hda->probe_continued = 1; 1972 1973 /* Request display power well for the HDA controller or codec. For 1974 * Haswell/Broadwell, both the display HDA controller and codec need 1975 * this power. For other platforms, like Baytrail/Braswell, only the 1976 * display codec needs the power and it can be released after probe. 1977 */ 1978 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1979 /* Baytral/Braswell controllers don't need this power */ 1980 if (pci->device != 0x0f04 && pci->device != 0x2284) 1981 hda->need_i915_power = 1; 1982 1983 err = snd_hdac_i915_init(bus); 1984 if (err < 0) 1985 goto i915_power_fail; 1986 1987 err = snd_hdac_display_power(bus, true); 1988 if (err < 0) { 1989 dev_err(chip->card->dev, 1990 "Cannot turn on display power on i915\n"); 1991 goto i915_power_fail; 1992 } 1993 } 1994 1995 err = azx_first_init(chip); 1996 if (err < 0) 1997 goto out_free; 1998 1999 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2000 chip->beep_mode = beep_mode[dev]; 2001 #endif 2002 2003 /* create codec instances */ 2004 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2005 if (err < 0) 2006 goto out_free; 2007 2008 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2009 if (chip->fw) { 2010 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2011 chip->fw->data); 2012 if (err < 0) 2013 goto out_free; 2014 #ifndef CONFIG_PM 2015 release_firmware(chip->fw); /* no longer needed */ 2016 chip->fw = NULL; 2017 #endif 2018 } 2019 #endif 2020 if ((probe_only[dev] & 1) == 0) { 2021 err = azx_codec_configure(chip); 2022 if (err < 0) 2023 goto out_free; 2024 } 2025 2026 err = snd_card_register(chip->card); 2027 if (err < 0) 2028 goto out_free; 2029 2030 chip->running = 1; 2031 azx_add_card_list(chip); 2032 snd_hda_set_power_save(&chip->bus, power_save * 1000); 2033 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 2034 pm_runtime_put_noidle(&pci->dev); 2035 2036 out_free: 2037 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 2038 && !hda->need_i915_power) 2039 snd_hdac_display_power(bus, false); 2040 2041 i915_power_fail: 2042 if (err < 0) 2043 hda->init_failed = 1; 2044 complete_all(&hda->probe_wait); 2045 return err; 2046 } 2047 2048 static void azx_remove(struct pci_dev *pci) 2049 { 2050 struct snd_card *card = pci_get_drvdata(pci); 2051 2052 if (card) 2053 snd_card_free(card); 2054 } 2055 2056 static void azx_shutdown(struct pci_dev *pci) 2057 { 2058 struct snd_card *card = pci_get_drvdata(pci); 2059 struct azx *chip; 2060 2061 if (!card) 2062 return; 2063 chip = card->private_data; 2064 if (chip && chip->running) 2065 azx_stop_chip(chip); 2066 } 2067 2068 /* PCI IDs */ 2069 static const struct pci_device_id azx_ids[] = { 2070 /* CPT */ 2071 { PCI_DEVICE(0x8086, 0x1c20), 2072 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2073 /* PBG */ 2074 { PCI_DEVICE(0x8086, 0x1d20), 2075 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2076 /* Panther Point */ 2077 { PCI_DEVICE(0x8086, 0x1e20), 2078 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2079 /* Lynx Point */ 2080 { PCI_DEVICE(0x8086, 0x8c20), 2081 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2082 /* 9 Series */ 2083 { PCI_DEVICE(0x8086, 0x8ca0), 2084 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2085 /* Wellsburg */ 2086 { PCI_DEVICE(0x8086, 0x8d20), 2087 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2088 { PCI_DEVICE(0x8086, 0x8d21), 2089 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2090 /* Lynx Point-LP */ 2091 { PCI_DEVICE(0x8086, 0x9c20), 2092 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2093 /* Lynx Point-LP */ 2094 { PCI_DEVICE(0x8086, 0x9c21), 2095 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2096 /* Wildcat Point-LP */ 2097 { PCI_DEVICE(0x8086, 0x9ca0), 2098 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2099 /* Sunrise Point */ 2100 { PCI_DEVICE(0x8086, 0xa170), 2101 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2102 /* Sunrise Point-LP */ 2103 { PCI_DEVICE(0x8086, 0x9d70), 2104 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2105 /* Haswell */ 2106 { PCI_DEVICE(0x8086, 0x0a0c), 2107 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2108 { PCI_DEVICE(0x8086, 0x0c0c), 2109 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2110 { PCI_DEVICE(0x8086, 0x0d0c), 2111 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2112 /* Broadwell */ 2113 { PCI_DEVICE(0x8086, 0x160c), 2114 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2115 /* 5 Series/3400 */ 2116 { PCI_DEVICE(0x8086, 0x3b56), 2117 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2118 /* Poulsbo */ 2119 { PCI_DEVICE(0x8086, 0x811b), 2120 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2121 /* Oaktrail */ 2122 { PCI_DEVICE(0x8086, 0x080a), 2123 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2124 /* BayTrail */ 2125 { PCI_DEVICE(0x8086, 0x0f04), 2126 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2127 /* Braswell */ 2128 { PCI_DEVICE(0x8086, 0x2284), 2129 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2130 /* ICH6 */ 2131 { PCI_DEVICE(0x8086, 0x2668), 2132 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2133 /* ICH7 */ 2134 { PCI_DEVICE(0x8086, 0x27d8), 2135 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2136 /* ESB2 */ 2137 { PCI_DEVICE(0x8086, 0x269a), 2138 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2139 /* ICH8 */ 2140 { PCI_DEVICE(0x8086, 0x284b), 2141 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2142 /* ICH9 */ 2143 { PCI_DEVICE(0x8086, 0x293e), 2144 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2145 /* ICH9 */ 2146 { PCI_DEVICE(0x8086, 0x293f), 2147 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2148 /* ICH10 */ 2149 { PCI_DEVICE(0x8086, 0x3a3e), 2150 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2151 /* ICH10 */ 2152 { PCI_DEVICE(0x8086, 0x3a6e), 2153 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2154 /* Generic Intel */ 2155 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2156 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2157 .class_mask = 0xffffff, 2158 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2159 /* ATI SB 450/600/700/800/900 */ 2160 { PCI_DEVICE(0x1002, 0x437b), 2161 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2162 { PCI_DEVICE(0x1002, 0x4383), 2163 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2164 /* AMD Hudson */ 2165 { PCI_DEVICE(0x1022, 0x780d), 2166 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2167 /* ATI HDMI */ 2168 { PCI_DEVICE(0x1002, 0x793b), 2169 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2170 { PCI_DEVICE(0x1002, 0x7919), 2171 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2172 { PCI_DEVICE(0x1002, 0x960f), 2173 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2174 { PCI_DEVICE(0x1002, 0x970f), 2175 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2176 { PCI_DEVICE(0x1002, 0xaa00), 2177 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2178 { PCI_DEVICE(0x1002, 0xaa08), 2179 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2180 { PCI_DEVICE(0x1002, 0xaa10), 2181 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2182 { PCI_DEVICE(0x1002, 0xaa18), 2183 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2184 { PCI_DEVICE(0x1002, 0xaa20), 2185 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2186 { PCI_DEVICE(0x1002, 0xaa28), 2187 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2188 { PCI_DEVICE(0x1002, 0xaa30), 2189 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2190 { PCI_DEVICE(0x1002, 0xaa38), 2191 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2192 { PCI_DEVICE(0x1002, 0xaa40), 2193 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2194 { PCI_DEVICE(0x1002, 0xaa48), 2195 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2196 { PCI_DEVICE(0x1002, 0xaa50), 2197 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2198 { PCI_DEVICE(0x1002, 0xaa58), 2199 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2200 { PCI_DEVICE(0x1002, 0xaa60), 2201 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2202 { PCI_DEVICE(0x1002, 0xaa68), 2203 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2204 { PCI_DEVICE(0x1002, 0xaa80), 2205 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2206 { PCI_DEVICE(0x1002, 0xaa88), 2207 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2208 { PCI_DEVICE(0x1002, 0xaa90), 2209 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2210 { PCI_DEVICE(0x1002, 0xaa98), 2211 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2212 { PCI_DEVICE(0x1002, 0x9902), 2213 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2214 { PCI_DEVICE(0x1002, 0xaaa0), 2215 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2216 { PCI_DEVICE(0x1002, 0xaaa8), 2217 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2218 { PCI_DEVICE(0x1002, 0xaab0), 2219 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2220 /* VIA VT8251/VT8237A */ 2221 { PCI_DEVICE(0x1106, 0x3288), 2222 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 2223 /* VIA GFX VT7122/VX900 */ 2224 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2225 /* VIA GFX VT6122/VX11 */ 2226 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2227 /* SIS966 */ 2228 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2229 /* ULI M5461 */ 2230 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2231 /* NVIDIA MCP */ 2232 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2233 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2234 .class_mask = 0xffffff, 2235 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2236 /* Teradici */ 2237 { PCI_DEVICE(0x6549, 0x1200), 2238 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2239 { PCI_DEVICE(0x6549, 0x2200), 2240 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2241 /* Creative X-Fi (CA0110-IBG) */ 2242 /* CTHDA chips */ 2243 { PCI_DEVICE(0x1102, 0x0010), 2244 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2245 { PCI_DEVICE(0x1102, 0x0012), 2246 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2247 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2248 /* the following entry conflicts with snd-ctxfi driver, 2249 * as ctxfi driver mutates from HD-audio to native mode with 2250 * a special command sequence. 2251 */ 2252 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2253 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2254 .class_mask = 0xffffff, 2255 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2256 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2257 #else 2258 /* this entry seems still valid -- i.e. without emu20kx chip */ 2259 { PCI_DEVICE(0x1102, 0x0009), 2260 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2261 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2262 #endif 2263 /* CM8888 */ 2264 { PCI_DEVICE(0x13f6, 0x5011), 2265 .driver_data = AZX_DRIVER_CMEDIA | 2266 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2267 /* Vortex86MX */ 2268 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2269 /* VMware HDAudio */ 2270 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2271 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2272 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2273 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2274 .class_mask = 0xffffff, 2275 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2276 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2277 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2278 .class_mask = 0xffffff, 2279 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2280 { 0, } 2281 }; 2282 MODULE_DEVICE_TABLE(pci, azx_ids); 2283 2284 /* pci_driver definition */ 2285 static struct pci_driver azx_driver = { 2286 .name = KBUILD_MODNAME, 2287 .id_table = azx_ids, 2288 .probe = azx_probe, 2289 .remove = azx_remove, 2290 .shutdown = azx_shutdown, 2291 .driver = { 2292 .pm = AZX_PM_OPS, 2293 }, 2294 }; 2295 2296 module_pci_driver(azx_driver); 2297