1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/set_memory.h> 57 #include <asm/cpufeature.h> 58 #endif 59 #include <sound/core.h> 60 #include <sound/initval.h> 61 #include <sound/hdaudio.h> 62 #include <sound/hda_i915.h> 63 #include <linux/vgaarb.h> 64 #include <linux/vga_switcheroo.h> 65 #include <linux/firmware.h> 66 #include <sound/hda_codec.h> 67 #include "hda_controller.h" 68 #include "hda_intel.h" 69 70 #define CREATE_TRACE_POINTS 71 #include "hda_intel_trace.h" 72 73 /* position fix mode */ 74 enum { 75 POS_FIX_AUTO, 76 POS_FIX_LPIB, 77 POS_FIX_POSBUF, 78 POS_FIX_VIACOMBO, 79 POS_FIX_COMBO, 80 POS_FIX_SKL, 81 }; 82 83 /* Defines for ATI HD Audio support in SB450 south bridge */ 84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 86 87 /* Defines for Nvidia HDA support */ 88 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 89 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 90 #define NVIDIA_HDA_ISTRM_COH 0x4d 91 #define NVIDIA_HDA_OSTRM_COH 0x4c 92 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 93 94 /* Defines for Intel SCH HDA snoop control */ 95 #define INTEL_HDA_CGCTL 0x48 96 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 97 #define INTEL_SCH_HDA_DEVC 0x78 98 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 99 100 /* Define IN stream 0 FIFO size offset in VIA controller */ 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 102 /* Define VIA HD Audio Device ID*/ 103 #define VIA_HDAC_DEVICE_ID 0x3288 104 105 /* max number of SDs */ 106 /* ICH, ATI and VIA have 4 playback and 4 capture */ 107 #define ICH6_NUM_CAPTURE 4 108 #define ICH6_NUM_PLAYBACK 4 109 110 /* ULI has 6 playback and 5 capture */ 111 #define ULI_NUM_CAPTURE 5 112 #define ULI_NUM_PLAYBACK 6 113 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 115 #define ATIHDMI_NUM_CAPTURE 0 116 #define ATIHDMI_NUM_PLAYBACK 8 117 118 /* TERA has 4 playback and 3 capture */ 119 #define TERA_NUM_CAPTURE 3 120 #define TERA_NUM_PLAYBACK 4 121 122 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 126 static char *model[SNDRV_CARDS]; 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 130 static int probe_only[SNDRV_CARDS]; 131 static int jackpoll_ms[SNDRV_CARDS]; 132 static int single_cmd = -1; 133 static int enable_msi = -1; 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER 135 static char *patch[SNDRV_CARDS]; 136 #endif 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 139 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 140 #endif 141 142 module_param_array(index, int, NULL, 0444); 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 144 module_param_array(id, charp, NULL, 0444); 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 146 module_param_array(enable, bool, NULL, 0444); 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 148 module_param_array(model, charp, NULL, 0444); 149 MODULE_PARM_DESC(model, "Use the given board model."); 150 module_param_array(position_fix, int, NULL, 0444); 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+)."); 153 module_param_array(bdl_pos_adj, int, NULL, 0644); 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 155 module_param_array(probe_mask, int, NULL, 0444); 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 157 module_param_array(probe_only, int, NULL, 0444); 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 159 module_param_array(jackpoll_ms, int, NULL, 0444); 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 161 module_param(single_cmd, bint, 0444); 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 163 "(for debugging only)."); 164 module_param(enable_msi, bint, 0444); 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER 167 module_param_array(patch, charp, NULL, 0444); 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 169 #endif 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP 171 module_param_array(beep_mode, bool, NULL, 0444); 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 173 "(0=off, 1=on) (default=1)."); 174 #endif 175 176 #ifdef CONFIG_PM 177 static int param_set_xint(const char *val, const struct kernel_param *kp); 178 static const struct kernel_param_ops param_ops_xint = { 179 .set = param_set_xint, 180 .get = param_get_int, 181 }; 182 #define param_check_xint param_check_int 183 184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 185 module_param(power_save, xint, 0644); 186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 187 "(in second, 0 = disable)."); 188 189 static bool pm_blacklist = true; 190 module_param(pm_blacklist, bool, 0644); 191 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 192 193 /* reset the HD-audio controller in power save mode. 194 * this may give more power-saving, but will take longer time to 195 * wake up. 196 */ 197 static bool power_save_controller = 1; 198 module_param(power_save_controller, bool, 0644); 199 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 200 #else 201 #define power_save 0 202 #endif /* CONFIG_PM */ 203 204 static int align_buffer_size = -1; 205 module_param(align_buffer_size, bint, 0644); 206 MODULE_PARM_DESC(align_buffer_size, 207 "Force buffer and period sizes to be multiple of 128 bytes."); 208 209 #ifdef CONFIG_X86 210 static int hda_snoop = -1; 211 module_param_named(snoop, hda_snoop, bint, 0444); 212 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 213 #else 214 #define hda_snoop true 215 #endif 216 217 218 MODULE_LICENSE("GPL"); 219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 220 "{Intel, ICH6M}," 221 "{Intel, ICH7}," 222 "{Intel, ESB2}," 223 "{Intel, ICH8}," 224 "{Intel, ICH9}," 225 "{Intel, ICH10}," 226 "{Intel, PCH}," 227 "{Intel, CPT}," 228 "{Intel, PPT}," 229 "{Intel, LPT}," 230 "{Intel, LPT_LP}," 231 "{Intel, WPT_LP}," 232 "{Intel, SPT}," 233 "{Intel, SPT_LP}," 234 "{Intel, HPT}," 235 "{Intel, PBG}," 236 "{Intel, SCH}," 237 "{ATI, SB450}," 238 "{ATI, SB600}," 239 "{ATI, RS600}," 240 "{ATI, RS690}," 241 "{ATI, RS780}," 242 "{ATI, R600}," 243 "{ATI, RV630}," 244 "{ATI, RV610}," 245 "{ATI, RV670}," 246 "{ATI, RV635}," 247 "{ATI, RV620}," 248 "{ATI, RV770}," 249 "{VIA, VT8251}," 250 "{VIA, VT8237A}," 251 "{SiS, SIS966}," 252 "{ULI, M5461}}"); 253 MODULE_DESCRIPTION("Intel HDA driver"); 254 255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 257 #define SUPPORT_VGA_SWITCHEROO 258 #endif 259 #endif 260 261 262 /* 263 */ 264 265 /* driver types */ 266 enum { 267 AZX_DRIVER_ICH, 268 AZX_DRIVER_PCH, 269 AZX_DRIVER_SCH, 270 AZX_DRIVER_SKL, 271 AZX_DRIVER_HDMI, 272 AZX_DRIVER_ATI, 273 AZX_DRIVER_ATIHDMI, 274 AZX_DRIVER_ATIHDMI_NS, 275 AZX_DRIVER_VIA, 276 AZX_DRIVER_SIS, 277 AZX_DRIVER_ULI, 278 AZX_DRIVER_NVIDIA, 279 AZX_DRIVER_TERA, 280 AZX_DRIVER_CTX, 281 AZX_DRIVER_CTHDA, 282 AZX_DRIVER_CMEDIA, 283 AZX_DRIVER_GENERIC, 284 AZX_NUM_DRIVERS, /* keep this as last entry */ 285 }; 286 287 #define azx_get_snoop_type(chip) \ 288 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 290 291 /* quirks for old Intel chipsets */ 292 #define AZX_DCAPS_INTEL_ICH \ 293 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 294 295 /* quirks for Intel PCH */ 296 #define AZX_DCAPS_INTEL_PCH_BASE \ 297 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 298 AZX_DCAPS_SNOOP_TYPE(SCH)) 299 300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 301 #define AZX_DCAPS_INTEL_PCH_NOPM \ 302 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 303 304 /* PCH for HSW/BDW; with runtime PM */ 305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 306 #define AZX_DCAPS_INTEL_PCH \ 307 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 308 309 /* HSW HDMI */ 310 #define AZX_DCAPS_INTEL_HASWELL \ 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 313 AZX_DCAPS_SNOOP_TYPE(SCH)) 314 315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 316 #define AZX_DCAPS_INTEL_BROADWELL \ 317 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 318 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 319 AZX_DCAPS_SNOOP_TYPE(SCH)) 320 321 #define AZX_DCAPS_INTEL_BAYTRAIL \ 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 323 324 #define AZX_DCAPS_INTEL_BRASWELL \ 325 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 326 AZX_DCAPS_I915_COMPONENT) 327 328 #define AZX_DCAPS_INTEL_SKYLAKE \ 329 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 330 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 331 332 #define AZX_DCAPS_INTEL_BROXTON \ 333 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 334 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 335 336 /* quirks for ATI SB / AMD Hudson */ 337 #define AZX_DCAPS_PRESET_ATI_SB \ 338 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 339 AZX_DCAPS_SNOOP_TYPE(ATI)) 340 341 /* quirks for ATI/AMD HDMI */ 342 #define AZX_DCAPS_PRESET_ATI_HDMI \ 343 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 344 AZX_DCAPS_NO_MSI64) 345 346 /* quirks for ATI HDMI with snoop off */ 347 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 348 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 349 350 /* quirks for Nvidia */ 351 #define AZX_DCAPS_PRESET_NVIDIA \ 352 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 353 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 354 355 #define AZX_DCAPS_PRESET_CTHDA \ 356 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 357 AZX_DCAPS_NO_64BIT |\ 358 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 359 360 /* 361 * vga_switcheroo support 362 */ 363 #ifdef SUPPORT_VGA_SWITCHEROO 364 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 365 #define needs_eld_notify_link(chip) ((chip)->need_eld_notify_link) 366 #else 367 #define use_vga_switcheroo(chip) 0 368 #define needs_eld_notify_link(chip) false 369 #endif 370 371 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 372 ((pci)->device == 0x0c0c) || \ 373 ((pci)->device == 0x0d0c) || \ 374 ((pci)->device == 0x160c)) 375 376 static char *driver_short_names[] = { 377 [AZX_DRIVER_ICH] = "HDA Intel", 378 [AZX_DRIVER_PCH] = "HDA Intel PCH", 379 [AZX_DRIVER_SCH] = "HDA Intel MID", 380 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 381 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 382 [AZX_DRIVER_ATI] = "HDA ATI SB", 383 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 384 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 386 [AZX_DRIVER_SIS] = "HDA SIS966", 387 [AZX_DRIVER_ULI] = "HDA ULI M5461", 388 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 389 [AZX_DRIVER_TERA] = "HDA Teradici", 390 [AZX_DRIVER_CTX] = "HDA Creative", 391 [AZX_DRIVER_CTHDA] = "HDA Creative", 392 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 393 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 394 }; 395 396 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 397 static void set_default_power_save(struct azx *chip); 398 399 /* 400 * initialize the PCI registers 401 */ 402 /* update bits in a PCI register byte */ 403 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 404 unsigned char mask, unsigned char val) 405 { 406 unsigned char data; 407 408 pci_read_config_byte(pci, reg, &data); 409 data &= ~mask; 410 data |= (val & mask); 411 pci_write_config_byte(pci, reg, data); 412 } 413 414 static void azx_init_pci(struct azx *chip) 415 { 416 int snoop_type = azx_get_snoop_type(chip); 417 418 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 419 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 420 * Ensuring these bits are 0 clears playback static on some HD Audio 421 * codecs. 422 * The PCI register TCSEL is defined in the Intel manuals. 423 */ 424 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 425 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 426 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 427 } 428 429 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 430 * we need to enable snoop. 431 */ 432 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 433 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 434 azx_snoop(chip)); 435 update_pci_byte(chip->pci, 436 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 437 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 438 } 439 440 /* For NVIDIA HDA, enable snoop */ 441 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 442 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 443 azx_snoop(chip)); 444 update_pci_byte(chip->pci, 445 NVIDIA_HDA_TRANSREG_ADDR, 446 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 447 update_pci_byte(chip->pci, 448 NVIDIA_HDA_ISTRM_COH, 449 0x01, NVIDIA_HDA_ENABLE_COHBIT); 450 update_pci_byte(chip->pci, 451 NVIDIA_HDA_OSTRM_COH, 452 0x01, NVIDIA_HDA_ENABLE_COHBIT); 453 } 454 455 /* Enable SCH/PCH snoop if needed */ 456 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 457 unsigned short snoop; 458 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 459 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 460 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 461 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 462 if (!azx_snoop(chip)) 463 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 464 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 465 pci_read_config_word(chip->pci, 466 INTEL_SCH_HDA_DEVC, &snoop); 467 } 468 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 469 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 470 "Disabled" : "Enabled"); 471 } 472 } 473 474 /* 475 * In BXT-P A0, HD-Audio DMA requests is later than expected, 476 * and makes an audio stream sensitive to system latencies when 477 * 24/32 bits are playing. 478 * Adjusting threshold of DMA fifo to force the DMA request 479 * sooner to improve latency tolerance at the expense of power. 480 */ 481 static void bxt_reduce_dma_latency(struct azx *chip) 482 { 483 u32 val; 484 485 val = azx_readl(chip, VS_EM4L); 486 val &= (0x3 << 20); 487 azx_writel(chip, VS_EM4L, val); 488 } 489 490 /* 491 * ML_LCAP bits: 492 * bit 0: 6 MHz Supported 493 * bit 1: 12 MHz Supported 494 * bit 2: 24 MHz Supported 495 * bit 3: 48 MHz Supported 496 * bit 4: 96 MHz Supported 497 * bit 5: 192 MHz Supported 498 */ 499 static int intel_get_lctl_scf(struct azx *chip) 500 { 501 struct hdac_bus *bus = azx_bus(chip); 502 static int preferred_bits[] = { 2, 3, 1, 4, 5 }; 503 u32 val, t; 504 int i; 505 506 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 507 508 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 509 t = preferred_bits[i]; 510 if (val & (1 << t)) 511 return t; 512 } 513 514 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 515 return 0; 516 } 517 518 static int intel_ml_lctl_set_power(struct azx *chip, int state) 519 { 520 struct hdac_bus *bus = azx_bus(chip); 521 u32 val; 522 int timeout; 523 524 /* 525 * the codecs are sharing the first link setting by default 526 * If other links are enabled for stream, they need similar fix 527 */ 528 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 529 val &= ~AZX_MLCTL_SPA; 530 val |= state << AZX_MLCTL_SPA_SHIFT; 531 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 532 /* wait for CPA */ 533 timeout = 50; 534 while (timeout) { 535 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 536 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 537 return 0; 538 timeout--; 539 udelay(10); 540 } 541 542 return -1; 543 } 544 545 static void intel_init_lctl(struct azx *chip) 546 { 547 struct hdac_bus *bus = azx_bus(chip); 548 u32 val; 549 int ret; 550 551 /* 0. check lctl register value is correct or not */ 552 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 553 /* if SCF is already set, let's use it */ 554 if ((val & ML_LCTL_SCF_MASK) != 0) 555 return; 556 557 /* 558 * Before operating on SPA, CPA must match SPA. 559 * Any deviation may result in undefined behavior. 560 */ 561 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 562 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 563 return; 564 565 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 566 ret = intel_ml_lctl_set_power(chip, 0); 567 udelay(100); 568 if (ret) 569 goto set_spa; 570 571 /* 2. update SCF to select a properly audio clock*/ 572 val &= ~ML_LCTL_SCF_MASK; 573 val |= intel_get_lctl_scf(chip); 574 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 575 576 set_spa: 577 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 578 intel_ml_lctl_set_power(chip, 1); 579 udelay(100); 580 } 581 582 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 583 { 584 struct hdac_bus *bus = azx_bus(chip); 585 struct pci_dev *pci = chip->pci; 586 u32 val; 587 588 snd_hdac_set_codec_wakeup(bus, true); 589 if (chip->driver_type == AZX_DRIVER_SKL) { 590 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 591 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 592 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 593 } 594 azx_init_chip(chip, full_reset); 595 if (chip->driver_type == AZX_DRIVER_SKL) { 596 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 597 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 598 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 599 } 600 601 snd_hdac_set_codec_wakeup(bus, false); 602 603 /* reduce dma latency to avoid noise */ 604 if (IS_BXT(pci)) 605 bxt_reduce_dma_latency(chip); 606 607 if (bus->mlcap != NULL) 608 intel_init_lctl(chip); 609 } 610 611 /* calculate runtime delay from LPIB */ 612 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 613 unsigned int pos) 614 { 615 struct snd_pcm_substream *substream = azx_dev->core.substream; 616 int stream = substream->stream; 617 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 618 int delay; 619 620 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 621 delay = pos - lpib_pos; 622 else 623 delay = lpib_pos - pos; 624 if (delay < 0) { 625 if (delay >= azx_dev->core.delay_negative_threshold) 626 delay = 0; 627 else 628 delay += azx_dev->core.bufsize; 629 } 630 631 if (delay >= azx_dev->core.period_bytes) { 632 dev_info(chip->card->dev, 633 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 634 delay, azx_dev->core.period_bytes); 635 delay = 0; 636 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 637 chip->get_delay[stream] = NULL; 638 } 639 640 return bytes_to_frames(substream->runtime, delay); 641 } 642 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 644 645 /* called from IRQ */ 646 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 647 { 648 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 649 int ok; 650 651 ok = azx_position_ok(chip, azx_dev); 652 if (ok == 1) { 653 azx_dev->irq_pending = 0; 654 return ok; 655 } else if (ok == 0) { 656 /* bogus IRQ, process it later */ 657 azx_dev->irq_pending = 1; 658 schedule_work(&hda->irq_pending_work); 659 } 660 return 0; 661 } 662 663 #define display_power(chip, enable) \ 664 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 665 666 /* 667 * Check whether the current DMA position is acceptable for updating 668 * periods. Returns non-zero if it's OK. 669 * 670 * Many HD-audio controllers appear pretty inaccurate about 671 * the update-IRQ timing. The IRQ is issued before actually the 672 * data is processed. So, we need to process it afterwords in a 673 * workqueue. 674 */ 675 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 676 { 677 struct snd_pcm_substream *substream = azx_dev->core.substream; 678 int stream = substream->stream; 679 u32 wallclk; 680 unsigned int pos; 681 682 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 683 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 684 return -1; /* bogus (too early) interrupt */ 685 686 if (chip->get_position[stream]) 687 pos = chip->get_position[stream](chip, azx_dev); 688 else { /* use the position buffer as default */ 689 pos = azx_get_pos_posbuf(chip, azx_dev); 690 if (!pos || pos == (u32)-1) { 691 dev_info(chip->card->dev, 692 "Invalid position buffer, using LPIB read method instead.\n"); 693 chip->get_position[stream] = azx_get_pos_lpib; 694 if (chip->get_position[0] == azx_get_pos_lpib && 695 chip->get_position[1] == azx_get_pos_lpib) 696 azx_bus(chip)->use_posbuf = false; 697 pos = azx_get_pos_lpib(chip, azx_dev); 698 chip->get_delay[stream] = NULL; 699 } else { 700 chip->get_position[stream] = azx_get_pos_posbuf; 701 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 702 chip->get_delay[stream] = azx_get_delay_from_lpib; 703 } 704 } 705 706 if (pos >= azx_dev->core.bufsize) 707 pos = 0; 708 709 if (WARN_ONCE(!azx_dev->core.period_bytes, 710 "hda-intel: zero azx_dev->period_bytes")) 711 return -1; /* this shouldn't happen! */ 712 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 713 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 714 /* NG - it's below the first next period boundary */ 715 return chip->bdl_pos_adj ? 0 : -1; 716 azx_dev->core.start_wallclk += wallclk; 717 return 1; /* OK, it's fine */ 718 } 719 720 /* 721 * The work for pending PCM period updates. 722 */ 723 static void azx_irq_pending_work(struct work_struct *work) 724 { 725 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 726 struct azx *chip = &hda->chip; 727 struct hdac_bus *bus = azx_bus(chip); 728 struct hdac_stream *s; 729 int pending, ok; 730 731 if (!hda->irq_pending_warned) { 732 dev_info(chip->card->dev, 733 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 734 chip->card->number); 735 hda->irq_pending_warned = 1; 736 } 737 738 for (;;) { 739 pending = 0; 740 spin_lock_irq(&bus->reg_lock); 741 list_for_each_entry(s, &bus->stream_list, list) { 742 struct azx_dev *azx_dev = stream_to_azx_dev(s); 743 if (!azx_dev->irq_pending || 744 !s->substream || 745 !s->running) 746 continue; 747 ok = azx_position_ok(chip, azx_dev); 748 if (ok > 0) { 749 azx_dev->irq_pending = 0; 750 spin_unlock(&bus->reg_lock); 751 snd_pcm_period_elapsed(s->substream); 752 spin_lock(&bus->reg_lock); 753 } else if (ok < 0) { 754 pending = 0; /* too early */ 755 } else 756 pending++; 757 } 758 spin_unlock_irq(&bus->reg_lock); 759 if (!pending) 760 return; 761 msleep(1); 762 } 763 } 764 765 /* clear irq_pending flags and assure no on-going workq */ 766 static void azx_clear_irq_pending(struct azx *chip) 767 { 768 struct hdac_bus *bus = azx_bus(chip); 769 struct hdac_stream *s; 770 771 spin_lock_irq(&bus->reg_lock); 772 list_for_each_entry(s, &bus->stream_list, list) { 773 struct azx_dev *azx_dev = stream_to_azx_dev(s); 774 azx_dev->irq_pending = 0; 775 } 776 spin_unlock_irq(&bus->reg_lock); 777 } 778 779 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 780 { 781 struct hdac_bus *bus = azx_bus(chip); 782 783 if (request_irq(chip->pci->irq, azx_interrupt, 784 chip->msi ? 0 : IRQF_SHARED, 785 chip->card->irq_descr, chip)) { 786 dev_err(chip->card->dev, 787 "unable to grab IRQ %d, disabling device\n", 788 chip->pci->irq); 789 if (do_disconnect) 790 snd_card_disconnect(chip->card); 791 return -1; 792 } 793 bus->irq = chip->pci->irq; 794 pci_intx(chip->pci, !chip->msi); 795 return 0; 796 } 797 798 /* get the current DMA position with correction on VIA chips */ 799 static unsigned int azx_via_get_position(struct azx *chip, 800 struct azx_dev *azx_dev) 801 { 802 unsigned int link_pos, mini_pos, bound_pos; 803 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 804 unsigned int fifo_size; 805 806 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 807 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 808 /* Playback, no problem using link position */ 809 return link_pos; 810 } 811 812 /* Capture */ 813 /* For new chipset, 814 * use mod to get the DMA position just like old chipset 815 */ 816 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 817 mod_dma_pos %= azx_dev->core.period_bytes; 818 819 /* azx_dev->fifo_size can't get FIFO size of in stream. 820 * Get from base address + offset. 821 */ 822 fifo_size = readw(azx_bus(chip)->remap_addr + 823 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 824 825 if (azx_dev->insufficient) { 826 /* Link position never gather than FIFO size */ 827 if (link_pos <= fifo_size) 828 return 0; 829 830 azx_dev->insufficient = 0; 831 } 832 833 if (link_pos <= fifo_size) 834 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 835 else 836 mini_pos = link_pos - fifo_size; 837 838 /* Find nearest previous boudary */ 839 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 840 mod_link_pos = link_pos % azx_dev->core.period_bytes; 841 if (mod_link_pos >= fifo_size) 842 bound_pos = link_pos - mod_link_pos; 843 else if (mod_dma_pos >= mod_mini_pos) 844 bound_pos = mini_pos - mod_mini_pos; 845 else { 846 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 847 if (bound_pos >= azx_dev->core.bufsize) 848 bound_pos = 0; 849 } 850 851 /* Calculate real DMA position we want */ 852 return bound_pos + mod_dma_pos; 853 } 854 855 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 856 struct azx_dev *azx_dev) 857 { 858 return _snd_hdac_chip_readl(azx_bus(chip), 859 AZX_REG_VS_SDXDPIB_XBASE + 860 (AZX_REG_VS_SDXDPIB_XINTERVAL * 861 azx_dev->core.index)); 862 } 863 864 /* get the current DMA position with correction on SKL+ chips */ 865 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 866 { 867 /* DPIB register gives a more accurate position for playback */ 868 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 869 return azx_skl_get_dpib_pos(chip, azx_dev); 870 871 /* For capture, we need to read posbuf, but it requires a delay 872 * for the possible boundary overlap; the read of DPIB fetches the 873 * actual posbuf 874 */ 875 udelay(20); 876 azx_skl_get_dpib_pos(chip, azx_dev); 877 return azx_get_pos_posbuf(chip, azx_dev); 878 } 879 880 #ifdef CONFIG_PM 881 static DEFINE_MUTEX(card_list_lock); 882 static LIST_HEAD(card_list); 883 884 static void azx_add_card_list(struct azx *chip) 885 { 886 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 887 mutex_lock(&card_list_lock); 888 list_add(&hda->list, &card_list); 889 mutex_unlock(&card_list_lock); 890 } 891 892 static void azx_del_card_list(struct azx *chip) 893 { 894 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 895 mutex_lock(&card_list_lock); 896 list_del_init(&hda->list); 897 mutex_unlock(&card_list_lock); 898 } 899 900 /* trigger power-save check at writing parameter */ 901 static int param_set_xint(const char *val, const struct kernel_param *kp) 902 { 903 struct hda_intel *hda; 904 struct azx *chip; 905 int prev = power_save; 906 int ret = param_set_int(val, kp); 907 908 if (ret || prev == power_save) 909 return ret; 910 911 mutex_lock(&card_list_lock); 912 list_for_each_entry(hda, &card_list, list) { 913 chip = &hda->chip; 914 if (!hda->probe_continued || chip->disabled) 915 continue; 916 snd_hda_set_power_save(&chip->bus, power_save * 1000); 917 } 918 mutex_unlock(&card_list_lock); 919 return 0; 920 } 921 922 /* 923 * power management 924 */ 925 static bool azx_is_pm_ready(struct snd_card *card) 926 { 927 struct azx *chip; 928 struct hda_intel *hda; 929 930 if (!card) 931 return false; 932 chip = card->private_data; 933 hda = container_of(chip, struct hda_intel, chip); 934 if (chip->disabled || hda->init_failed || !chip->running) 935 return false; 936 return true; 937 } 938 939 static void __azx_runtime_suspend(struct azx *chip) 940 { 941 azx_stop_chip(chip); 942 azx_enter_link_reset(chip); 943 azx_clear_irq_pending(chip); 944 display_power(chip, false); 945 } 946 947 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 948 { 949 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 950 struct hdac_bus *bus = azx_bus(chip); 951 struct hda_codec *codec; 952 int status; 953 954 display_power(chip, true); 955 if (hda->need_i915_power) 956 snd_hdac_i915_set_bclk(bus); 957 958 /* Read STATESTS before controller reset */ 959 status = azx_readw(chip, STATESTS); 960 961 azx_init_pci(chip); 962 hda_intel_init_chip(chip, true); 963 964 if (status && from_rt) { 965 list_for_each_codec(codec, &chip->bus) 966 if (status & (1 << codec->addr)) 967 schedule_delayed_work(&codec->jackpoll_work, 968 codec->jackpoll_interval); 969 } 970 971 /* power down again for link-controlled chips */ 972 if (!hda->need_i915_power) 973 display_power(chip, false); 974 } 975 976 #ifdef CONFIG_PM_SLEEP 977 static int azx_suspend(struct device *dev) 978 { 979 struct snd_card *card = dev_get_drvdata(dev); 980 struct azx *chip; 981 struct hdac_bus *bus; 982 983 if (!azx_is_pm_ready(card)) 984 return 0; 985 986 chip = card->private_data; 987 bus = azx_bus(chip); 988 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 989 __azx_runtime_suspend(chip); 990 if (bus->irq >= 0) { 991 free_irq(bus->irq, chip); 992 bus->irq = -1; 993 } 994 995 if (chip->msi) 996 pci_disable_msi(chip->pci); 997 998 trace_azx_suspend(chip); 999 return 0; 1000 } 1001 1002 static int azx_resume(struct device *dev) 1003 { 1004 struct snd_card *card = dev_get_drvdata(dev); 1005 struct azx *chip; 1006 1007 if (!azx_is_pm_ready(card)) 1008 return 0; 1009 1010 chip = card->private_data; 1011 if (chip->msi) 1012 if (pci_enable_msi(chip->pci) < 0) 1013 chip->msi = 0; 1014 if (azx_acquire_irq(chip, 1) < 0) 1015 return -EIO; 1016 __azx_runtime_resume(chip, false); 1017 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1018 1019 trace_azx_resume(chip); 1020 return 0; 1021 } 1022 1023 /* put codec down to D3 at hibernation for Intel SKL+; 1024 * otherwise BIOS may still access the codec and screw up the driver 1025 */ 1026 static int azx_freeze_noirq(struct device *dev) 1027 { 1028 struct snd_card *card = dev_get_drvdata(dev); 1029 struct azx *chip = card->private_data; 1030 struct pci_dev *pci = to_pci_dev(dev); 1031 1032 if (chip->driver_type == AZX_DRIVER_SKL) 1033 pci_set_power_state(pci, PCI_D3hot); 1034 1035 return 0; 1036 } 1037 1038 static int azx_thaw_noirq(struct device *dev) 1039 { 1040 struct snd_card *card = dev_get_drvdata(dev); 1041 struct azx *chip = card->private_data; 1042 struct pci_dev *pci = to_pci_dev(dev); 1043 1044 if (chip->driver_type == AZX_DRIVER_SKL) 1045 pci_set_power_state(pci, PCI_D0); 1046 1047 return 0; 1048 } 1049 #endif /* CONFIG_PM_SLEEP */ 1050 1051 static int azx_runtime_suspend(struct device *dev) 1052 { 1053 struct snd_card *card = dev_get_drvdata(dev); 1054 struct azx *chip; 1055 1056 if (!azx_is_pm_ready(card)) 1057 return 0; 1058 chip = card->private_data; 1059 if (!azx_has_pm_runtime(chip)) 1060 return 0; 1061 1062 /* enable controller wake up event */ 1063 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1064 STATESTS_INT_MASK); 1065 1066 __azx_runtime_suspend(chip); 1067 trace_azx_runtime_suspend(chip); 1068 return 0; 1069 } 1070 1071 static int azx_runtime_resume(struct device *dev) 1072 { 1073 struct snd_card *card = dev_get_drvdata(dev); 1074 struct azx *chip; 1075 1076 if (!azx_is_pm_ready(card)) 1077 return 0; 1078 chip = card->private_data; 1079 if (!azx_has_pm_runtime(chip)) 1080 return 0; 1081 __azx_runtime_resume(chip, true); 1082 1083 /* disable controller Wake Up event*/ 1084 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1085 ~STATESTS_INT_MASK); 1086 1087 trace_azx_runtime_resume(chip); 1088 return 0; 1089 } 1090 1091 static int azx_runtime_idle(struct device *dev) 1092 { 1093 struct snd_card *card = dev_get_drvdata(dev); 1094 struct azx *chip; 1095 struct hda_intel *hda; 1096 1097 if (!card) 1098 return 0; 1099 1100 chip = card->private_data; 1101 hda = container_of(chip, struct hda_intel, chip); 1102 if (chip->disabled || hda->init_failed) 1103 return 0; 1104 1105 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1106 azx_bus(chip)->codec_powered || !chip->running) 1107 return -EBUSY; 1108 1109 /* ELD notification gets broken when HD-audio bus is off */ 1110 if (needs_eld_notify_link(hda)) 1111 return -EBUSY; 1112 1113 return 0; 1114 } 1115 1116 static const struct dev_pm_ops azx_pm = { 1117 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1118 #ifdef CONFIG_PM_SLEEP 1119 .freeze_noirq = azx_freeze_noirq, 1120 .thaw_noirq = azx_thaw_noirq, 1121 #endif 1122 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1123 }; 1124 1125 #define AZX_PM_OPS &azx_pm 1126 #else 1127 #define azx_add_card_list(chip) /* NOP */ 1128 #define azx_del_card_list(chip) /* NOP */ 1129 #define AZX_PM_OPS NULL 1130 #endif /* CONFIG_PM */ 1131 1132 1133 static int azx_probe_continue(struct azx *chip); 1134 1135 #ifdef SUPPORT_VGA_SWITCHEROO 1136 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1137 1138 static void azx_vs_set_state(struct pci_dev *pci, 1139 enum vga_switcheroo_state state) 1140 { 1141 struct snd_card *card = pci_get_drvdata(pci); 1142 struct azx *chip = card->private_data; 1143 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1144 struct hda_codec *codec; 1145 bool disabled; 1146 1147 wait_for_completion(&hda->probe_wait); 1148 if (hda->init_failed) 1149 return; 1150 1151 disabled = (state == VGA_SWITCHEROO_OFF); 1152 if (chip->disabled == disabled) 1153 return; 1154 1155 if (!hda->probe_continued) { 1156 chip->disabled = disabled; 1157 if (!disabled) { 1158 dev_info(chip->card->dev, 1159 "Start delayed initialization\n"); 1160 if (azx_probe_continue(chip) < 0) { 1161 dev_err(chip->card->dev, "initialization error\n"); 1162 hda->init_failed = true; 1163 } 1164 } 1165 } else { 1166 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1167 disabled ? "Disabling" : "Enabling"); 1168 if (disabled) { 1169 list_for_each_codec(codec, &chip->bus) { 1170 pm_runtime_suspend(hda_codec_dev(codec)); 1171 pm_runtime_disable(hda_codec_dev(codec)); 1172 } 1173 pm_runtime_suspend(card->dev); 1174 pm_runtime_disable(card->dev); 1175 /* when we get suspended by vga_switcheroo we end up in D3cold, 1176 * however we have no ACPI handle, so pci/acpi can't put us there, 1177 * put ourselves there */ 1178 pci->current_state = PCI_D3cold; 1179 chip->disabled = true; 1180 if (snd_hda_lock_devices(&chip->bus)) 1181 dev_warn(chip->card->dev, 1182 "Cannot lock devices!\n"); 1183 } else { 1184 snd_hda_unlock_devices(&chip->bus); 1185 chip->disabled = false; 1186 pm_runtime_enable(card->dev); 1187 list_for_each_codec(codec, &chip->bus) { 1188 pm_runtime_enable(hda_codec_dev(codec)); 1189 pm_runtime_resume(hda_codec_dev(codec)); 1190 } 1191 } 1192 } 1193 } 1194 1195 static bool azx_vs_can_switch(struct pci_dev *pci) 1196 { 1197 struct snd_card *card = pci_get_drvdata(pci); 1198 struct azx *chip = card->private_data; 1199 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1200 1201 wait_for_completion(&hda->probe_wait); 1202 if (hda->init_failed) 1203 return false; 1204 if (chip->disabled || !hda->probe_continued) 1205 return true; 1206 if (snd_hda_lock_devices(&chip->bus)) 1207 return false; 1208 snd_hda_unlock_devices(&chip->bus); 1209 return true; 1210 } 1211 1212 /* 1213 * The discrete GPU cannot power down unless the HDA controller runtime 1214 * suspends, so activate runtime PM on codecs even if power_save == 0. 1215 */ 1216 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1217 { 1218 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1219 struct hda_codec *codec; 1220 1221 if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) { 1222 list_for_each_codec(codec, &chip->bus) 1223 codec->auto_runtime_pm = 1; 1224 /* reset the power save setup */ 1225 if (chip->running) 1226 set_default_power_save(chip); 1227 } 1228 } 1229 1230 static void azx_vs_gpu_bound(struct pci_dev *pci, 1231 enum vga_switcheroo_client_id client_id) 1232 { 1233 struct snd_card *card = pci_get_drvdata(pci); 1234 struct azx *chip = card->private_data; 1235 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1236 1237 if (client_id == VGA_SWITCHEROO_DIS) 1238 hda->need_eld_notify_link = 0; 1239 setup_vga_switcheroo_runtime_pm(chip); 1240 } 1241 1242 static void init_vga_switcheroo(struct azx *chip) 1243 { 1244 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1245 struct pci_dev *p = get_bound_vga(chip->pci); 1246 if (p) { 1247 dev_info(chip->card->dev, 1248 "Handle vga_switcheroo audio client\n"); 1249 hda->use_vga_switcheroo = 1; 1250 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */ 1251 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1252 pci_dev_put(p); 1253 } 1254 } 1255 1256 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1257 .set_gpu_state = azx_vs_set_state, 1258 .can_switch = azx_vs_can_switch, 1259 .gpu_bound = azx_vs_gpu_bound, 1260 }; 1261 1262 static int register_vga_switcheroo(struct azx *chip) 1263 { 1264 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1265 struct pci_dev *p; 1266 int err; 1267 1268 if (!hda->use_vga_switcheroo) 1269 return 0; 1270 1271 p = get_bound_vga(chip->pci); 1272 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1273 pci_dev_put(p); 1274 1275 if (err < 0) 1276 return err; 1277 hda->vga_switcheroo_registered = 1; 1278 1279 return 0; 1280 } 1281 #else 1282 #define init_vga_switcheroo(chip) /* NOP */ 1283 #define register_vga_switcheroo(chip) 0 1284 #define check_hdmi_disabled(pci) false 1285 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1286 #endif /* SUPPORT_VGA_SWITCHER */ 1287 1288 /* 1289 * destructor 1290 */ 1291 static int azx_free(struct azx *chip) 1292 { 1293 struct pci_dev *pci = chip->pci; 1294 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1295 struct hdac_bus *bus = azx_bus(chip); 1296 1297 if (azx_has_pm_runtime(chip) && chip->running) 1298 pm_runtime_get_noresume(&pci->dev); 1299 chip->running = 0; 1300 1301 azx_del_card_list(chip); 1302 1303 hda->init_failed = 1; /* to be sure */ 1304 complete_all(&hda->probe_wait); 1305 1306 if (use_vga_switcheroo(hda)) { 1307 if (chip->disabled && hda->probe_continued) 1308 snd_hda_unlock_devices(&chip->bus); 1309 if (hda->vga_switcheroo_registered) 1310 vga_switcheroo_unregister_client(chip->pci); 1311 } 1312 1313 if (bus->chip_init) { 1314 azx_clear_irq_pending(chip); 1315 azx_stop_all_streams(chip); 1316 azx_stop_chip(chip); 1317 } 1318 1319 if (bus->irq >= 0) 1320 free_irq(bus->irq, (void*)chip); 1321 if (chip->msi) 1322 pci_disable_msi(chip->pci); 1323 iounmap(bus->remap_addr); 1324 1325 azx_free_stream_pages(chip); 1326 azx_free_streams(chip); 1327 snd_hdac_bus_exit(bus); 1328 1329 if (chip->region_requested) 1330 pci_release_regions(chip->pci); 1331 1332 pci_disable_device(chip->pci); 1333 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1334 release_firmware(chip->fw); 1335 #endif 1336 display_power(chip, false); 1337 1338 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1339 snd_hdac_i915_exit(bus); 1340 kfree(hda); 1341 1342 return 0; 1343 } 1344 1345 static int azx_dev_disconnect(struct snd_device *device) 1346 { 1347 struct azx *chip = device->device_data; 1348 1349 chip->bus.shutdown = 1; 1350 return 0; 1351 } 1352 1353 static int azx_dev_free(struct snd_device *device) 1354 { 1355 return azx_free(device->device_data); 1356 } 1357 1358 #ifdef SUPPORT_VGA_SWITCHEROO 1359 /* 1360 * Check of disabled HDMI controller by vga_switcheroo 1361 */ 1362 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1363 { 1364 struct pci_dev *p; 1365 1366 /* check only discrete GPU */ 1367 switch (pci->vendor) { 1368 case PCI_VENDOR_ID_ATI: 1369 case PCI_VENDOR_ID_AMD: 1370 case PCI_VENDOR_ID_NVIDIA: 1371 if (pci->devfn == 1) { 1372 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1373 pci->bus->number, 0); 1374 if (p) { 1375 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1376 return p; 1377 pci_dev_put(p); 1378 } 1379 } 1380 break; 1381 } 1382 return NULL; 1383 } 1384 1385 static bool check_hdmi_disabled(struct pci_dev *pci) 1386 { 1387 bool vga_inactive = false; 1388 struct pci_dev *p = get_bound_vga(pci); 1389 1390 if (p) { 1391 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1392 vga_inactive = true; 1393 pci_dev_put(p); 1394 } 1395 return vga_inactive; 1396 } 1397 #endif /* SUPPORT_VGA_SWITCHEROO */ 1398 1399 /* 1400 * white/black-listing for position_fix 1401 */ 1402 static struct snd_pci_quirk position_fix_list[] = { 1403 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1404 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1405 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1406 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1407 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1408 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1409 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1410 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1411 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1412 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1413 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1414 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1415 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1416 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1417 {} 1418 }; 1419 1420 static int check_position_fix(struct azx *chip, int fix) 1421 { 1422 const struct snd_pci_quirk *q; 1423 1424 switch (fix) { 1425 case POS_FIX_AUTO: 1426 case POS_FIX_LPIB: 1427 case POS_FIX_POSBUF: 1428 case POS_FIX_VIACOMBO: 1429 case POS_FIX_COMBO: 1430 case POS_FIX_SKL: 1431 return fix; 1432 } 1433 1434 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1435 if (q) { 1436 dev_info(chip->card->dev, 1437 "position_fix set to %d for device %04x:%04x\n", 1438 q->value, q->subvendor, q->subdevice); 1439 return q->value; 1440 } 1441 1442 /* Check VIA/ATI HD Audio Controller exist */ 1443 if (chip->driver_type == AZX_DRIVER_VIA) { 1444 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1445 return POS_FIX_VIACOMBO; 1446 } 1447 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1448 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1449 return POS_FIX_LPIB; 1450 } 1451 if (chip->driver_type == AZX_DRIVER_SKL) { 1452 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1453 return POS_FIX_SKL; 1454 } 1455 return POS_FIX_AUTO; 1456 } 1457 1458 static void assign_position_fix(struct azx *chip, int fix) 1459 { 1460 static azx_get_pos_callback_t callbacks[] = { 1461 [POS_FIX_AUTO] = NULL, 1462 [POS_FIX_LPIB] = azx_get_pos_lpib, 1463 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1464 [POS_FIX_VIACOMBO] = azx_via_get_position, 1465 [POS_FIX_COMBO] = azx_get_pos_lpib, 1466 [POS_FIX_SKL] = azx_get_pos_skl, 1467 }; 1468 1469 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1470 1471 /* combo mode uses LPIB only for playback */ 1472 if (fix == POS_FIX_COMBO) 1473 chip->get_position[1] = NULL; 1474 1475 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1476 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1477 chip->get_delay[0] = chip->get_delay[1] = 1478 azx_get_delay_from_lpib; 1479 } 1480 1481 } 1482 1483 /* 1484 * black-lists for probe_mask 1485 */ 1486 static struct snd_pci_quirk probe_mask_list[] = { 1487 /* Thinkpad often breaks the controller communication when accessing 1488 * to the non-working (or non-existing) modem codec slot. 1489 */ 1490 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1491 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1492 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1493 /* broken BIOS */ 1494 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1495 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1496 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1497 /* forced codec slots */ 1498 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1499 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1500 /* WinFast VP200 H (Teradici) user reported broken communication */ 1501 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1502 {} 1503 }; 1504 1505 #define AZX_FORCE_CODEC_MASK 0x100 1506 1507 static void check_probe_mask(struct azx *chip, int dev) 1508 { 1509 const struct snd_pci_quirk *q; 1510 1511 chip->codec_probe_mask = probe_mask[dev]; 1512 if (chip->codec_probe_mask == -1) { 1513 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1514 if (q) { 1515 dev_info(chip->card->dev, 1516 "probe_mask set to 0x%x for device %04x:%04x\n", 1517 q->value, q->subvendor, q->subdevice); 1518 chip->codec_probe_mask = q->value; 1519 } 1520 } 1521 1522 /* check forced option */ 1523 if (chip->codec_probe_mask != -1 && 1524 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1525 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1526 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1527 (int)azx_bus(chip)->codec_mask); 1528 } 1529 } 1530 1531 /* 1532 * white/black-list for enable_msi 1533 */ 1534 static struct snd_pci_quirk msi_black_list[] = { 1535 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1536 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1537 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1538 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1539 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1540 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1541 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1542 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1543 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1544 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1545 {} 1546 }; 1547 1548 static void check_msi(struct azx *chip) 1549 { 1550 const struct snd_pci_quirk *q; 1551 1552 if (enable_msi >= 0) { 1553 chip->msi = !!enable_msi; 1554 return; 1555 } 1556 chip->msi = 1; /* enable MSI as default */ 1557 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1558 if (q) { 1559 dev_info(chip->card->dev, 1560 "msi for device %04x:%04x set to %d\n", 1561 q->subvendor, q->subdevice, q->value); 1562 chip->msi = q->value; 1563 return; 1564 } 1565 1566 /* NVidia chipsets seem to cause troubles with MSI */ 1567 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1568 dev_info(chip->card->dev, "Disabling MSI\n"); 1569 chip->msi = 0; 1570 } 1571 } 1572 1573 /* check the snoop mode availability */ 1574 static void azx_check_snoop_available(struct azx *chip) 1575 { 1576 int snoop = hda_snoop; 1577 1578 if (snoop >= 0) { 1579 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1580 snoop ? "snoop" : "non-snoop"); 1581 chip->snoop = snoop; 1582 chip->uc_buffer = !snoop; 1583 return; 1584 } 1585 1586 snoop = true; 1587 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1588 chip->driver_type == AZX_DRIVER_VIA) { 1589 /* force to non-snoop mode for a new VIA controller 1590 * when BIOS is set 1591 */ 1592 u8 val; 1593 pci_read_config_byte(chip->pci, 0x42, &val); 1594 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1595 chip->pci->revision == 0x20)) 1596 snoop = false; 1597 } 1598 1599 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1600 snoop = false; 1601 1602 chip->snoop = snoop; 1603 if (!snoop) { 1604 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1605 /* C-Media requires non-cached pages only for CORB/RIRB */ 1606 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1607 chip->uc_buffer = true; 1608 } 1609 } 1610 1611 static void azx_probe_work(struct work_struct *work) 1612 { 1613 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1614 azx_probe_continue(&hda->chip); 1615 } 1616 1617 static int default_bdl_pos_adj(struct azx *chip) 1618 { 1619 /* some exceptions: Atoms seem problematic with value 1 */ 1620 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1621 switch (chip->pci->device) { 1622 case 0x0f04: /* Baytrail */ 1623 case 0x2284: /* Braswell */ 1624 return 32; 1625 } 1626 } 1627 1628 switch (chip->driver_type) { 1629 case AZX_DRIVER_ICH: 1630 case AZX_DRIVER_PCH: 1631 return 1; 1632 default: 1633 return 32; 1634 } 1635 } 1636 1637 /* 1638 * constructor 1639 */ 1640 static const struct hdac_io_ops pci_hda_io_ops; 1641 static const struct hda_controller_ops pci_hda_ops; 1642 1643 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1644 int dev, unsigned int driver_caps, 1645 struct azx **rchip) 1646 { 1647 static struct snd_device_ops ops = { 1648 .dev_disconnect = azx_dev_disconnect, 1649 .dev_free = azx_dev_free, 1650 }; 1651 struct hda_intel *hda; 1652 struct azx *chip; 1653 int err; 1654 1655 *rchip = NULL; 1656 1657 err = pci_enable_device(pci); 1658 if (err < 0) 1659 return err; 1660 1661 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1662 if (!hda) { 1663 pci_disable_device(pci); 1664 return -ENOMEM; 1665 } 1666 1667 chip = &hda->chip; 1668 mutex_init(&chip->open_mutex); 1669 chip->card = card; 1670 chip->pci = pci; 1671 chip->ops = &pci_hda_ops; 1672 chip->driver_caps = driver_caps; 1673 chip->driver_type = driver_caps & 0xff; 1674 check_msi(chip); 1675 chip->dev_index = dev; 1676 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1677 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1678 INIT_LIST_HEAD(&chip->pcm_list); 1679 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1680 INIT_LIST_HEAD(&hda->list); 1681 init_vga_switcheroo(chip); 1682 init_completion(&hda->probe_wait); 1683 1684 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1685 1686 check_probe_mask(chip, dev); 1687 1688 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1689 chip->fallback_to_single_cmd = 1; 1690 else /* explicitly set to single_cmd or not */ 1691 chip->single_cmd = single_cmd; 1692 1693 azx_check_snoop_available(chip); 1694 1695 if (bdl_pos_adj[dev] < 0) 1696 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1697 else 1698 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1699 1700 /* Workaround for a communication error on CFL (bko#199007) */ 1701 if (IS_CFL(pci)) 1702 chip->polling_mode = 1; 1703 1704 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1705 if (err < 0) { 1706 kfree(hda); 1707 pci_disable_device(pci); 1708 return err; 1709 } 1710 1711 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1712 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1713 chip->bus.needs_damn_long_delay = 1; 1714 } 1715 1716 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1717 if (err < 0) { 1718 dev_err(card->dev, "Error creating device [card]!\n"); 1719 azx_free(chip); 1720 return err; 1721 } 1722 1723 /* continue probing in work context as may trigger request module */ 1724 INIT_WORK(&hda->probe_work, azx_probe_work); 1725 1726 *rchip = chip; 1727 1728 return 0; 1729 } 1730 1731 static int azx_first_init(struct azx *chip) 1732 { 1733 int dev = chip->dev_index; 1734 struct pci_dev *pci = chip->pci; 1735 struct snd_card *card = chip->card; 1736 struct hdac_bus *bus = azx_bus(chip); 1737 int err; 1738 unsigned short gcap; 1739 unsigned int dma_bits = 64; 1740 1741 #if BITS_PER_LONG != 64 1742 /* Fix up base address on ULI M5461 */ 1743 if (chip->driver_type == AZX_DRIVER_ULI) { 1744 u16 tmp3; 1745 pci_read_config_word(pci, 0x40, &tmp3); 1746 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1747 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1748 } 1749 #endif 1750 1751 err = pci_request_regions(pci, "ICH HD audio"); 1752 if (err < 0) 1753 return err; 1754 chip->region_requested = 1; 1755 1756 bus->addr = pci_resource_start(pci, 0); 1757 bus->remap_addr = pci_ioremap_bar(pci, 0); 1758 if (bus->remap_addr == NULL) { 1759 dev_err(card->dev, "ioremap error\n"); 1760 return -ENXIO; 1761 } 1762 1763 if (chip->driver_type == AZX_DRIVER_SKL) 1764 snd_hdac_bus_parse_capabilities(bus); 1765 1766 /* 1767 * Some Intel CPUs has always running timer (ART) feature and 1768 * controller may have Global time sync reporting capability, so 1769 * check both of these before declaring synchronized time reporting 1770 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1771 */ 1772 chip->gts_present = false; 1773 1774 #ifdef CONFIG_X86 1775 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1776 chip->gts_present = true; 1777 #endif 1778 1779 if (chip->msi) { 1780 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1781 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1782 pci->no_64bit_msi = true; 1783 } 1784 if (pci_enable_msi(pci) < 0) 1785 chip->msi = 0; 1786 } 1787 1788 pci_set_master(pci); 1789 synchronize_irq(bus->irq); 1790 1791 gcap = azx_readw(chip, GCAP); 1792 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1793 1794 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1795 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1796 dma_bits = 40; 1797 1798 /* disable SB600 64bit support for safety */ 1799 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1800 struct pci_dev *p_smbus; 1801 dma_bits = 40; 1802 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1803 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1804 NULL); 1805 if (p_smbus) { 1806 if (p_smbus->revision < 0x30) 1807 gcap &= ~AZX_GCAP_64OK; 1808 pci_dev_put(p_smbus); 1809 } 1810 } 1811 1812 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1813 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1814 dma_bits = 40; 1815 1816 /* disable 64bit DMA address on some devices */ 1817 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1818 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1819 gcap &= ~AZX_GCAP_64OK; 1820 } 1821 1822 /* disable buffer size rounding to 128-byte multiples if supported */ 1823 if (align_buffer_size >= 0) 1824 chip->align_buffer_size = !!align_buffer_size; 1825 else { 1826 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1827 chip->align_buffer_size = 0; 1828 else 1829 chip->align_buffer_size = 1; 1830 } 1831 1832 /* allow 64bit DMA address if supported by H/W */ 1833 if (!(gcap & AZX_GCAP_64OK)) 1834 dma_bits = 32; 1835 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1836 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1837 } else { 1838 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1839 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1840 } 1841 1842 /* read number of streams from GCAP register instead of using 1843 * hardcoded value 1844 */ 1845 chip->capture_streams = (gcap >> 8) & 0x0f; 1846 chip->playback_streams = (gcap >> 12) & 0x0f; 1847 if (!chip->playback_streams && !chip->capture_streams) { 1848 /* gcap didn't give any info, switching to old method */ 1849 1850 switch (chip->driver_type) { 1851 case AZX_DRIVER_ULI: 1852 chip->playback_streams = ULI_NUM_PLAYBACK; 1853 chip->capture_streams = ULI_NUM_CAPTURE; 1854 break; 1855 case AZX_DRIVER_ATIHDMI: 1856 case AZX_DRIVER_ATIHDMI_NS: 1857 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1858 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1859 break; 1860 case AZX_DRIVER_GENERIC: 1861 default: 1862 chip->playback_streams = ICH6_NUM_PLAYBACK; 1863 chip->capture_streams = ICH6_NUM_CAPTURE; 1864 break; 1865 } 1866 } 1867 chip->capture_index_offset = 0; 1868 chip->playback_index_offset = chip->capture_streams; 1869 chip->num_streams = chip->playback_streams + chip->capture_streams; 1870 1871 /* sanity check for the SDxCTL.STRM field overflow */ 1872 if (chip->num_streams > 15 && 1873 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1874 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1875 "forcing separate stream tags", chip->num_streams); 1876 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1877 } 1878 1879 /* initialize streams */ 1880 err = azx_init_streams(chip); 1881 if (err < 0) 1882 return err; 1883 1884 err = azx_alloc_stream_pages(chip); 1885 if (err < 0) 1886 return err; 1887 1888 /* initialize chip */ 1889 azx_init_pci(chip); 1890 1891 snd_hdac_i915_set_bclk(bus); 1892 1893 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1894 1895 /* codec detection */ 1896 if (!azx_bus(chip)->codec_mask) { 1897 dev_err(card->dev, "no codecs found!\n"); 1898 return -ENODEV; 1899 } 1900 1901 if (azx_acquire_irq(chip, 0) < 0) 1902 return -EBUSY; 1903 1904 strcpy(card->driver, "HDA-Intel"); 1905 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1906 sizeof(card->shortname)); 1907 snprintf(card->longname, sizeof(card->longname), 1908 "%s at 0x%lx irq %i", 1909 card->shortname, bus->addr, bus->irq); 1910 1911 return 0; 1912 } 1913 1914 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1915 /* callback from request_firmware_nowait() */ 1916 static void azx_firmware_cb(const struct firmware *fw, void *context) 1917 { 1918 struct snd_card *card = context; 1919 struct azx *chip = card->private_data; 1920 struct pci_dev *pci = chip->pci; 1921 1922 if (!fw) { 1923 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1924 goto error; 1925 } 1926 1927 chip->fw = fw; 1928 if (!chip->disabled) { 1929 /* continue probing */ 1930 if (azx_probe_continue(chip)) 1931 goto error; 1932 } 1933 return; /* OK */ 1934 1935 error: 1936 snd_card_free(card); 1937 pci_set_drvdata(pci, NULL); 1938 } 1939 #endif 1940 1941 /* 1942 * HDA controller ops. 1943 */ 1944 1945 /* PCI register access. */ 1946 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1947 { 1948 writel(value, addr); 1949 } 1950 1951 static u32 pci_azx_readl(u32 __iomem *addr) 1952 { 1953 return readl(addr); 1954 } 1955 1956 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1957 { 1958 writew(value, addr); 1959 } 1960 1961 static u16 pci_azx_readw(u16 __iomem *addr) 1962 { 1963 return readw(addr); 1964 } 1965 1966 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1967 { 1968 writeb(value, addr); 1969 } 1970 1971 static u8 pci_azx_readb(u8 __iomem *addr) 1972 { 1973 return readb(addr); 1974 } 1975 1976 static int disable_msi_reset_irq(struct azx *chip) 1977 { 1978 struct hdac_bus *bus = azx_bus(chip); 1979 int err; 1980 1981 free_irq(bus->irq, chip); 1982 bus->irq = -1; 1983 pci_disable_msi(chip->pci); 1984 chip->msi = 0; 1985 err = azx_acquire_irq(chip, 1); 1986 if (err < 0) 1987 return err; 1988 1989 return 0; 1990 } 1991 1992 /* DMA page allocation helpers. */ 1993 static int dma_alloc_pages(struct hdac_bus *bus, 1994 int type, 1995 size_t size, 1996 struct snd_dma_buffer *buf) 1997 { 1998 struct azx *chip = bus_to_azx(bus); 1999 2000 if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV) 2001 type = SNDRV_DMA_TYPE_DEV_UC; 2002 return snd_dma_alloc_pages(type, bus->dev, size, buf); 2003 } 2004 2005 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 2006 { 2007 snd_dma_free_pages(buf); 2008 } 2009 2010 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2011 struct vm_area_struct *area) 2012 { 2013 #ifdef CONFIG_X86 2014 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2015 struct azx *chip = apcm->chip; 2016 if (chip->uc_buffer) 2017 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2018 #endif 2019 } 2020 2021 static const struct hdac_io_ops pci_hda_io_ops = { 2022 .reg_writel = pci_azx_writel, 2023 .reg_readl = pci_azx_readl, 2024 .reg_writew = pci_azx_writew, 2025 .reg_readw = pci_azx_readw, 2026 .reg_writeb = pci_azx_writeb, 2027 .reg_readb = pci_azx_readb, 2028 .dma_alloc_pages = dma_alloc_pages, 2029 .dma_free_pages = dma_free_pages, 2030 }; 2031 2032 static const struct hda_controller_ops pci_hda_ops = { 2033 .disable_msi_reset_irq = disable_msi_reset_irq, 2034 .pcm_mmap_prepare = pcm_mmap_prepare, 2035 .position_check = azx_position_check, 2036 }; 2037 2038 static int azx_probe(struct pci_dev *pci, 2039 const struct pci_device_id *pci_id) 2040 { 2041 static int dev; 2042 struct snd_card *card; 2043 struct hda_intel *hda; 2044 struct azx *chip; 2045 bool schedule_probe; 2046 int err; 2047 2048 if (dev >= SNDRV_CARDS) 2049 return -ENODEV; 2050 if (!enable[dev]) { 2051 dev++; 2052 return -ENOENT; 2053 } 2054 2055 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2056 0, &card); 2057 if (err < 0) { 2058 dev_err(&pci->dev, "Error creating card!\n"); 2059 return err; 2060 } 2061 2062 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2063 if (err < 0) 2064 goto out_free; 2065 card->private_data = chip; 2066 hda = container_of(chip, struct hda_intel, chip); 2067 2068 pci_set_drvdata(pci, card); 2069 2070 err = register_vga_switcheroo(chip); 2071 if (err < 0) { 2072 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2073 goto out_free; 2074 } 2075 2076 if (check_hdmi_disabled(pci)) { 2077 dev_info(card->dev, "VGA controller is disabled\n"); 2078 dev_info(card->dev, "Delaying initialization\n"); 2079 chip->disabled = true; 2080 } 2081 2082 schedule_probe = !chip->disabled; 2083 2084 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2085 if (patch[dev] && *patch[dev]) { 2086 dev_info(card->dev, "Applying patch firmware '%s'\n", 2087 patch[dev]); 2088 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2089 &pci->dev, GFP_KERNEL, card, 2090 azx_firmware_cb); 2091 if (err < 0) 2092 goto out_free; 2093 schedule_probe = false; /* continued in azx_firmware_cb() */ 2094 } 2095 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2096 2097 #ifndef CONFIG_SND_HDA_I915 2098 if (CONTROLLER_IN_GPU(pci)) 2099 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2100 #endif 2101 2102 if (schedule_probe) 2103 schedule_work(&hda->probe_work); 2104 2105 dev++; 2106 if (chip->disabled) 2107 complete_all(&hda->probe_wait); 2108 return 0; 2109 2110 out_free: 2111 snd_card_free(card); 2112 return err; 2113 } 2114 2115 #ifdef CONFIG_PM 2116 /* On some boards setting power_save to a non 0 value leads to clicking / 2117 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2118 * figure out how to avoid these sounds, but that is not always feasible. 2119 * So we keep a list of devices where we disable powersaving as its known 2120 * to causes problems on these devices. 2121 */ 2122 static struct snd_pci_quirk power_save_blacklist[] = { 2123 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2124 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2125 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2126 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2127 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2128 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2129 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2130 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2131 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2132 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2133 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2134 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2135 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2136 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2137 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2138 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2139 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2140 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2141 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2142 /* https://bugs.launchpad.net/bugs/1821663 */ 2143 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2144 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2145 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2146 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2147 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2148 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2149 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2150 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2151 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2152 /* https://bugs.launchpad.net/bugs/1821663 */ 2153 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2154 {} 2155 }; 2156 #endif /* CONFIG_PM */ 2157 2158 static void set_default_power_save(struct azx *chip) 2159 { 2160 int val = power_save; 2161 2162 #ifdef CONFIG_PM 2163 if (pm_blacklist) { 2164 const struct snd_pci_quirk *q; 2165 2166 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2167 if (q && val) { 2168 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2169 q->subvendor, q->subdevice); 2170 val = 0; 2171 } 2172 } 2173 #endif /* CONFIG_PM */ 2174 snd_hda_set_power_save(&chip->bus, val * 1000); 2175 } 2176 2177 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2178 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2179 [AZX_DRIVER_NVIDIA] = 8, 2180 [AZX_DRIVER_TERA] = 1, 2181 }; 2182 2183 static int azx_probe_continue(struct azx *chip) 2184 { 2185 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2186 struct hdac_bus *bus = azx_bus(chip); 2187 struct pci_dev *pci = chip->pci; 2188 int dev = chip->dev_index; 2189 int err; 2190 2191 to_hda_bus(bus)->bus_probing = 1; 2192 hda->probe_continued = 1; 2193 2194 /* bind with i915 if needed */ 2195 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2196 err = snd_hdac_i915_init(bus); 2197 if (err < 0) { 2198 /* if the controller is bound only with HDMI/DP 2199 * (for HSW and BDW), we need to abort the probe; 2200 * for other chips, still continue probing as other 2201 * codecs can be on the same link. 2202 */ 2203 if (CONTROLLER_IN_GPU(pci)) { 2204 dev_err(chip->card->dev, 2205 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2206 goto out_free; 2207 } else { 2208 /* don't bother any longer */ 2209 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2210 } 2211 } 2212 2213 /* HSW/BDW controllers need this power */ 2214 if (CONTROLLER_IN_GPU(pci)) 2215 hda->need_i915_power = 1; 2216 } 2217 2218 /* Request display power well for the HDA controller or codec. For 2219 * Haswell/Broadwell, both the display HDA controller and codec need 2220 * this power. For other platforms, like Baytrail/Braswell, only the 2221 * display codec needs the power and it can be released after probe. 2222 */ 2223 display_power(chip, true); 2224 2225 err = azx_first_init(chip); 2226 if (err < 0) 2227 goto out_free; 2228 2229 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2230 chip->beep_mode = beep_mode[dev]; 2231 #endif 2232 2233 /* create codec instances */ 2234 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2235 if (err < 0) 2236 goto out_free; 2237 2238 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2239 if (chip->fw) { 2240 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2241 chip->fw->data); 2242 if (err < 0) 2243 goto out_free; 2244 #ifndef CONFIG_PM 2245 release_firmware(chip->fw); /* no longer needed */ 2246 chip->fw = NULL; 2247 #endif 2248 } 2249 #endif 2250 if ((probe_only[dev] & 1) == 0) { 2251 err = azx_codec_configure(chip); 2252 if (err < 0) 2253 goto out_free; 2254 } 2255 2256 err = snd_card_register(chip->card); 2257 if (err < 0) 2258 goto out_free; 2259 2260 setup_vga_switcheroo_runtime_pm(chip); 2261 2262 chip->running = 1; 2263 azx_add_card_list(chip); 2264 2265 set_default_power_save(chip); 2266 2267 if (azx_has_pm_runtime(chip)) 2268 pm_runtime_put_autosuspend(&pci->dev); 2269 2270 out_free: 2271 if (err < 0 || !hda->need_i915_power) 2272 display_power(chip, false); 2273 if (err < 0) 2274 hda->init_failed = 1; 2275 complete_all(&hda->probe_wait); 2276 to_hda_bus(bus)->bus_probing = 0; 2277 return err; 2278 } 2279 2280 static void azx_remove(struct pci_dev *pci) 2281 { 2282 struct snd_card *card = pci_get_drvdata(pci); 2283 struct azx *chip; 2284 struct hda_intel *hda; 2285 2286 if (card) { 2287 /* cancel the pending probing work */ 2288 chip = card->private_data; 2289 hda = container_of(chip, struct hda_intel, chip); 2290 /* FIXME: below is an ugly workaround. 2291 * Both device_release_driver() and driver_probe_device() 2292 * take *both* the device's and its parent's lock before 2293 * calling the remove() and probe() callbacks. The codec 2294 * probe takes the locks of both the codec itself and its 2295 * parent, i.e. the PCI controller dev. Meanwhile, when 2296 * the PCI controller is unbound, it takes its lock, too 2297 * ==> ouch, a deadlock! 2298 * As a workaround, we unlock temporarily here the controller 2299 * device during cancel_work_sync() call. 2300 */ 2301 device_unlock(&pci->dev); 2302 cancel_work_sync(&hda->probe_work); 2303 device_lock(&pci->dev); 2304 2305 snd_card_free(card); 2306 } 2307 } 2308 2309 static void azx_shutdown(struct pci_dev *pci) 2310 { 2311 struct snd_card *card = pci_get_drvdata(pci); 2312 struct azx *chip; 2313 2314 if (!card) 2315 return; 2316 chip = card->private_data; 2317 if (chip && chip->running) 2318 azx_stop_chip(chip); 2319 } 2320 2321 /* PCI IDs */ 2322 static const struct pci_device_id azx_ids[] = { 2323 /* CPT */ 2324 { PCI_DEVICE(0x8086, 0x1c20), 2325 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2326 /* PBG */ 2327 { PCI_DEVICE(0x8086, 0x1d20), 2328 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2329 /* Panther Point */ 2330 { PCI_DEVICE(0x8086, 0x1e20), 2331 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2332 /* Lynx Point */ 2333 { PCI_DEVICE(0x8086, 0x8c20), 2334 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2335 /* 9 Series */ 2336 { PCI_DEVICE(0x8086, 0x8ca0), 2337 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2338 /* Wellsburg */ 2339 { PCI_DEVICE(0x8086, 0x8d20), 2340 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2341 { PCI_DEVICE(0x8086, 0x8d21), 2342 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2343 /* Lewisburg */ 2344 { PCI_DEVICE(0x8086, 0xa1f0), 2345 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2346 { PCI_DEVICE(0x8086, 0xa270), 2347 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2348 /* Lynx Point-LP */ 2349 { PCI_DEVICE(0x8086, 0x9c20), 2350 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2351 /* Lynx Point-LP */ 2352 { PCI_DEVICE(0x8086, 0x9c21), 2353 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2354 /* Wildcat Point-LP */ 2355 { PCI_DEVICE(0x8086, 0x9ca0), 2356 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2357 /* Sunrise Point */ 2358 { PCI_DEVICE(0x8086, 0xa170), 2359 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2360 /* Sunrise Point-LP */ 2361 { PCI_DEVICE(0x8086, 0x9d70), 2362 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2363 /* Kabylake */ 2364 { PCI_DEVICE(0x8086, 0xa171), 2365 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2366 /* Kabylake-LP */ 2367 { PCI_DEVICE(0x8086, 0x9d71), 2368 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2369 /* Kabylake-H */ 2370 { PCI_DEVICE(0x8086, 0xa2f0), 2371 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2372 /* Coffelake */ 2373 { PCI_DEVICE(0x8086, 0xa348), 2374 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2375 /* Cannonlake */ 2376 { PCI_DEVICE(0x8086, 0x9dc8), 2377 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2378 /* CometLake-LP */ 2379 { PCI_DEVICE(0x8086, 0x02C8), 2380 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2381 /* CometLake-H */ 2382 { PCI_DEVICE(0x8086, 0x06C8), 2383 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2384 /* Icelake */ 2385 { PCI_DEVICE(0x8086, 0x34c8), 2386 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2387 /* Broxton-P(Apollolake) */ 2388 { PCI_DEVICE(0x8086, 0x5a98), 2389 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2390 /* Broxton-T */ 2391 { PCI_DEVICE(0x8086, 0x1a98), 2392 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2393 /* Gemini-Lake */ 2394 { PCI_DEVICE(0x8086, 0x3198), 2395 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2396 /* Haswell */ 2397 { PCI_DEVICE(0x8086, 0x0a0c), 2398 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2399 { PCI_DEVICE(0x8086, 0x0c0c), 2400 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2401 { PCI_DEVICE(0x8086, 0x0d0c), 2402 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2403 /* Broadwell */ 2404 { PCI_DEVICE(0x8086, 0x160c), 2405 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2406 /* 5 Series/3400 */ 2407 { PCI_DEVICE(0x8086, 0x3b56), 2408 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2409 /* Poulsbo */ 2410 { PCI_DEVICE(0x8086, 0x811b), 2411 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2412 /* Oaktrail */ 2413 { PCI_DEVICE(0x8086, 0x080a), 2414 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2415 /* BayTrail */ 2416 { PCI_DEVICE(0x8086, 0x0f04), 2417 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2418 /* Braswell */ 2419 { PCI_DEVICE(0x8086, 0x2284), 2420 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2421 /* ICH6 */ 2422 { PCI_DEVICE(0x8086, 0x2668), 2423 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2424 /* ICH7 */ 2425 { PCI_DEVICE(0x8086, 0x27d8), 2426 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2427 /* ESB2 */ 2428 { PCI_DEVICE(0x8086, 0x269a), 2429 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2430 /* ICH8 */ 2431 { PCI_DEVICE(0x8086, 0x284b), 2432 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2433 /* ICH9 */ 2434 { PCI_DEVICE(0x8086, 0x293e), 2435 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2436 /* ICH9 */ 2437 { PCI_DEVICE(0x8086, 0x293f), 2438 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2439 /* ICH10 */ 2440 { PCI_DEVICE(0x8086, 0x3a3e), 2441 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2442 /* ICH10 */ 2443 { PCI_DEVICE(0x8086, 0x3a6e), 2444 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2445 /* Generic Intel */ 2446 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2447 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2448 .class_mask = 0xffffff, 2449 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2450 /* ATI SB 450/600/700/800/900 */ 2451 { PCI_DEVICE(0x1002, 0x437b), 2452 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2453 { PCI_DEVICE(0x1002, 0x4383), 2454 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2455 /* AMD Hudson */ 2456 { PCI_DEVICE(0x1022, 0x780d), 2457 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2458 /* AMD Stoney */ 2459 { PCI_DEVICE(0x1022, 0x157a), 2460 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2461 AZX_DCAPS_PM_RUNTIME }, 2462 /* AMD Raven */ 2463 { PCI_DEVICE(0x1022, 0x15e3), 2464 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2465 AZX_DCAPS_PM_RUNTIME }, 2466 /* ATI HDMI */ 2467 { PCI_DEVICE(0x1002, 0x0002), 2468 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2469 { PCI_DEVICE(0x1002, 0x1308), 2470 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2471 { PCI_DEVICE(0x1002, 0x157a), 2472 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2473 { PCI_DEVICE(0x1002, 0x15b3), 2474 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2475 { PCI_DEVICE(0x1002, 0x793b), 2476 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2477 { PCI_DEVICE(0x1002, 0x7919), 2478 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2479 { PCI_DEVICE(0x1002, 0x960f), 2480 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2481 { PCI_DEVICE(0x1002, 0x970f), 2482 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2483 { PCI_DEVICE(0x1002, 0x9840), 2484 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2485 { PCI_DEVICE(0x1002, 0xaa00), 2486 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2487 { PCI_DEVICE(0x1002, 0xaa08), 2488 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2489 { PCI_DEVICE(0x1002, 0xaa10), 2490 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2491 { PCI_DEVICE(0x1002, 0xaa18), 2492 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2493 { PCI_DEVICE(0x1002, 0xaa20), 2494 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2495 { PCI_DEVICE(0x1002, 0xaa28), 2496 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2497 { PCI_DEVICE(0x1002, 0xaa30), 2498 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2499 { PCI_DEVICE(0x1002, 0xaa38), 2500 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2501 { PCI_DEVICE(0x1002, 0xaa40), 2502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2503 { PCI_DEVICE(0x1002, 0xaa48), 2504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2505 { PCI_DEVICE(0x1002, 0xaa50), 2506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2507 { PCI_DEVICE(0x1002, 0xaa58), 2508 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2509 { PCI_DEVICE(0x1002, 0xaa60), 2510 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2511 { PCI_DEVICE(0x1002, 0xaa68), 2512 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2513 { PCI_DEVICE(0x1002, 0xaa80), 2514 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2515 { PCI_DEVICE(0x1002, 0xaa88), 2516 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2517 { PCI_DEVICE(0x1002, 0xaa90), 2518 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2519 { PCI_DEVICE(0x1002, 0xaa98), 2520 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2521 { PCI_DEVICE(0x1002, 0x9902), 2522 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2523 { PCI_DEVICE(0x1002, 0xaaa0), 2524 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2525 { PCI_DEVICE(0x1002, 0xaaa8), 2526 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2527 { PCI_DEVICE(0x1002, 0xaab0), 2528 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2529 { PCI_DEVICE(0x1002, 0xaac0), 2530 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2531 { PCI_DEVICE(0x1002, 0xaac8), 2532 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2533 { PCI_DEVICE(0x1002, 0xaad8), 2534 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2535 { PCI_DEVICE(0x1002, 0xaae8), 2536 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2537 { PCI_DEVICE(0x1002, 0xaae0), 2538 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2539 { PCI_DEVICE(0x1002, 0xaaf0), 2540 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2541 /* VIA VT8251/VT8237A */ 2542 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2543 /* VIA GFX VT7122/VX900 */ 2544 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2545 /* VIA GFX VT6122/VX11 */ 2546 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2547 /* SIS966 */ 2548 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2549 /* ULI M5461 */ 2550 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2551 /* NVIDIA MCP */ 2552 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2553 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2554 .class_mask = 0xffffff, 2555 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2556 /* Teradici */ 2557 { PCI_DEVICE(0x6549, 0x1200), 2558 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2559 { PCI_DEVICE(0x6549, 0x2200), 2560 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2561 /* Creative X-Fi (CA0110-IBG) */ 2562 /* CTHDA chips */ 2563 { PCI_DEVICE(0x1102, 0x0010), 2564 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2565 { PCI_DEVICE(0x1102, 0x0012), 2566 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2567 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2568 /* the following entry conflicts with snd-ctxfi driver, 2569 * as ctxfi driver mutates from HD-audio to native mode with 2570 * a special command sequence. 2571 */ 2572 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2573 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2574 .class_mask = 0xffffff, 2575 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2576 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2577 #else 2578 /* this entry seems still valid -- i.e. without emu20kx chip */ 2579 { PCI_DEVICE(0x1102, 0x0009), 2580 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2581 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2582 #endif 2583 /* CM8888 */ 2584 { PCI_DEVICE(0x13f6, 0x5011), 2585 .driver_data = AZX_DRIVER_CMEDIA | 2586 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2587 /* Vortex86MX */ 2588 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2589 /* VMware HDAudio */ 2590 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2591 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2592 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2593 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2594 .class_mask = 0xffffff, 2595 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2596 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2597 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2598 .class_mask = 0xffffff, 2599 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2600 { 0, } 2601 }; 2602 MODULE_DEVICE_TABLE(pci, azx_ids); 2603 2604 /* pci_driver definition */ 2605 static struct pci_driver azx_driver = { 2606 .name = KBUILD_MODNAME, 2607 .id_table = azx_ids, 2608 .probe = azx_probe, 2609 .remove = azx_remove, 2610 .shutdown = azx_shutdown, 2611 .driver = { 2612 .pm = AZX_PM_OPS, 2613 }, 2614 }; 2615 2616 module_pci_driver(azx_driver); 2617