1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <linux/vgaarb.h> 61 #include <linux/vga_switcheroo.h> 62 #include <linux/firmware.h> 63 #include "hda_codec.h" 64 #include "hda_controller.h" 65 #include "hda_priv.h" 66 #include "hda_i915.h" 67 68 /* position fix mode */ 69 enum { 70 POS_FIX_AUTO, 71 POS_FIX_LPIB, 72 POS_FIX_POSBUF, 73 POS_FIX_VIACOMBO, 74 POS_FIX_COMBO, 75 }; 76 77 /* Defines for ATI HD Audio support in SB450 south bridge */ 78 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 79 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 80 81 /* Defines for Nvidia HDA support */ 82 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 83 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 84 #define NVIDIA_HDA_ISTRM_COH 0x4d 85 #define NVIDIA_HDA_OSTRM_COH 0x4c 86 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 87 88 /* Defines for Intel SCH HDA snoop control */ 89 #define INTEL_SCH_HDA_DEVC 0x78 90 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 91 92 /* Define IN stream 0 FIFO size offset in VIA controller */ 93 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 94 /* Define VIA HD Audio Device ID*/ 95 #define VIA_HDAC_DEVICE_ID 0x3288 96 97 /* max number of SDs */ 98 /* ICH, ATI and VIA have 4 playback and 4 capture */ 99 #define ICH6_NUM_CAPTURE 4 100 #define ICH6_NUM_PLAYBACK 4 101 102 /* ULI has 6 playback and 5 capture */ 103 #define ULI_NUM_CAPTURE 5 104 #define ULI_NUM_PLAYBACK 6 105 106 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 107 #define ATIHDMI_NUM_CAPTURE 0 108 #define ATIHDMI_NUM_PLAYBACK 8 109 110 /* TERA has 4 playback and 3 capture */ 111 #define TERA_NUM_CAPTURE 3 112 #define TERA_NUM_PLAYBACK 4 113 114 115 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 116 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 117 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 118 static char *model[SNDRV_CARDS]; 119 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 120 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 121 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 122 static int probe_only[SNDRV_CARDS]; 123 static int jackpoll_ms[SNDRV_CARDS]; 124 static bool single_cmd; 125 static int enable_msi = -1; 126 #ifdef CONFIG_SND_HDA_PATCH_LOADER 127 static char *patch[SNDRV_CARDS]; 128 #endif 129 #ifdef CONFIG_SND_HDA_INPUT_BEEP 130 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 131 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 132 #endif 133 134 module_param_array(index, int, NULL, 0444); 135 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 136 module_param_array(id, charp, NULL, 0444); 137 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 138 module_param_array(enable, bool, NULL, 0444); 139 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 140 module_param_array(model, charp, NULL, 0444); 141 MODULE_PARM_DESC(model, "Use the given board model."); 142 module_param_array(position_fix, int, NULL, 0444); 143 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 145 module_param_array(bdl_pos_adj, int, NULL, 0644); 146 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 147 module_param_array(probe_mask, int, NULL, 0444); 148 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 149 module_param_array(probe_only, int, NULL, 0444); 150 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 151 module_param_array(jackpoll_ms, int, NULL, 0444); 152 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 153 module_param(single_cmd, bool, 0444); 154 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 155 "(for debugging only)."); 156 module_param(enable_msi, bint, 0444); 157 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 158 #ifdef CONFIG_SND_HDA_PATCH_LOADER 159 module_param_array(patch, charp, NULL, 0444); 160 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 161 #endif 162 #ifdef CONFIG_SND_HDA_INPUT_BEEP 163 module_param_array(beep_mode, bool, NULL, 0444); 164 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 165 "(0=off, 1=on) (default=1)."); 166 #endif 167 168 #ifdef CONFIG_PM 169 static int param_set_xint(const char *val, const struct kernel_param *kp); 170 static struct kernel_param_ops param_ops_xint = { 171 .set = param_set_xint, 172 .get = param_get_int, 173 }; 174 #define param_check_xint param_check_int 175 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 177 static int *power_save_addr = &power_save; 178 module_param(power_save, xint, 0644); 179 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 180 "(in second, 0 = disable)."); 181 182 /* reset the HD-audio controller in power save mode. 183 * this may give more power-saving, but will take longer time to 184 * wake up. 185 */ 186 static bool power_save_controller = 1; 187 module_param(power_save_controller, bool, 0644); 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 189 #else 190 static int *power_save_addr; 191 #endif /* CONFIG_PM */ 192 193 static int align_buffer_size = -1; 194 module_param(align_buffer_size, bint, 0644); 195 MODULE_PARM_DESC(align_buffer_size, 196 "Force buffer and period sizes to be multiple of 128 bytes."); 197 198 #ifdef CONFIG_X86 199 static bool hda_snoop = true; 200 module_param_named(snoop, hda_snoop, bool, 0444); 201 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 202 #else 203 #define hda_snoop true 204 #endif 205 206 207 MODULE_LICENSE("GPL"); 208 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 209 "{Intel, ICH6M}," 210 "{Intel, ICH7}," 211 "{Intel, ESB2}," 212 "{Intel, ICH8}," 213 "{Intel, ICH9}," 214 "{Intel, ICH10}," 215 "{Intel, PCH}," 216 "{Intel, CPT}," 217 "{Intel, PPT}," 218 "{Intel, LPT}," 219 "{Intel, LPT_LP}," 220 "{Intel, WPT_LP}," 221 "{Intel, SPT}," 222 "{Intel, HPT}," 223 "{Intel, PBG}," 224 "{Intel, SCH}," 225 "{ATI, SB450}," 226 "{ATI, SB600}," 227 "{ATI, RS600}," 228 "{ATI, RS690}," 229 "{ATI, RS780}," 230 "{ATI, R600}," 231 "{ATI, RV630}," 232 "{ATI, RV610}," 233 "{ATI, RV670}," 234 "{ATI, RV635}," 235 "{ATI, RV620}," 236 "{ATI, RV770}," 237 "{VIA, VT8251}," 238 "{VIA, VT8237A}," 239 "{SiS, SIS966}," 240 "{ULI, M5461}}"); 241 MODULE_DESCRIPTION("Intel HDA driver"); 242 243 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 244 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 245 #define SUPPORT_VGA_SWITCHEROO 246 #endif 247 #endif 248 249 250 /* 251 */ 252 253 /* driver types */ 254 enum { 255 AZX_DRIVER_ICH, 256 AZX_DRIVER_PCH, 257 AZX_DRIVER_SCH, 258 AZX_DRIVER_HDMI, 259 AZX_DRIVER_ATI, 260 AZX_DRIVER_ATIHDMI, 261 AZX_DRIVER_ATIHDMI_NS, 262 AZX_DRIVER_VIA, 263 AZX_DRIVER_SIS, 264 AZX_DRIVER_ULI, 265 AZX_DRIVER_NVIDIA, 266 AZX_DRIVER_TERA, 267 AZX_DRIVER_CTX, 268 AZX_DRIVER_CTHDA, 269 AZX_DRIVER_CMEDIA, 270 AZX_DRIVER_GENERIC, 271 AZX_NUM_DRIVERS, /* keep this as last entry */ 272 }; 273 274 /* quirks for Intel PCH */ 275 #define AZX_DCAPS_INTEL_PCH_NOPM \ 276 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ 277 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_REVERSE_ASSIGN) 278 279 #define AZX_DCAPS_INTEL_PCH \ 280 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 281 282 #define AZX_DCAPS_INTEL_HASWELL \ 283 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \ 284 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \ 285 AZX_DCAPS_I915_POWERWELL) 286 287 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 288 #define AZX_DCAPS_INTEL_BROADWELL \ 289 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \ 290 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \ 291 AZX_DCAPS_I915_POWERWELL) 292 293 /* quirks for ATI SB / AMD Hudson */ 294 #define AZX_DCAPS_PRESET_ATI_SB \ 295 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \ 296 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 297 298 /* quirks for ATI/AMD HDMI */ 299 #define AZX_DCAPS_PRESET_ATI_HDMI \ 300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 301 302 /* quirks for Nvidia */ 303 #define AZX_DCAPS_PRESET_NVIDIA \ 304 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ 305 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\ 306 AZX_DCAPS_CORBRP_SELF_CLEAR) 307 308 #define AZX_DCAPS_PRESET_CTHDA \ 309 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) 310 311 /* 312 * VGA-switcher support 313 */ 314 #ifdef SUPPORT_VGA_SWITCHEROO 315 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 316 #else 317 #define use_vga_switcheroo(chip) 0 318 #endif 319 320 static char *driver_short_names[] = { 321 [AZX_DRIVER_ICH] = "HDA Intel", 322 [AZX_DRIVER_PCH] = "HDA Intel PCH", 323 [AZX_DRIVER_SCH] = "HDA Intel MID", 324 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 325 [AZX_DRIVER_ATI] = "HDA ATI SB", 326 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 327 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 328 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 329 [AZX_DRIVER_SIS] = "HDA SIS966", 330 [AZX_DRIVER_ULI] = "HDA ULI M5461", 331 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 332 [AZX_DRIVER_TERA] = "HDA Teradici", 333 [AZX_DRIVER_CTX] = "HDA Creative", 334 [AZX_DRIVER_CTHDA] = "HDA Creative", 335 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 336 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 337 }; 338 339 struct hda_intel { 340 struct azx chip; 341 342 /* for pending irqs */ 343 struct work_struct irq_pending_work; 344 345 /* sync probing */ 346 struct completion probe_wait; 347 struct work_struct probe_work; 348 349 /* card list (for power_save trigger) */ 350 struct list_head list; 351 352 /* extra flags */ 353 unsigned int irq_pending_warned:1; 354 355 /* VGA-switcheroo setup */ 356 unsigned int use_vga_switcheroo:1; 357 unsigned int vga_switcheroo_registered:1; 358 unsigned int init_failed:1; /* delayed init failed */ 359 360 /* secondary power domain for hdmi audio under vga device */ 361 struct dev_pm_domain hdmi_pm_domain; 362 }; 363 364 #ifdef CONFIG_X86 365 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 366 { 367 int pages; 368 369 if (azx_snoop(chip)) 370 return; 371 if (!dmab || !dmab->area || !dmab->bytes) 372 return; 373 374 #ifdef CONFIG_SND_DMA_SGBUF 375 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 376 struct snd_sg_buf *sgbuf = dmab->private_data; 377 if (on) 378 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 379 else 380 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 381 return; 382 } 383 #endif 384 385 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 386 if (on) 387 set_memory_wc((unsigned long)dmab->area, pages); 388 else 389 set_memory_wb((unsigned long)dmab->area, pages); 390 } 391 392 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 393 bool on) 394 { 395 __mark_pages_wc(chip, buf, on); 396 } 397 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 398 struct snd_pcm_substream *substream, bool on) 399 { 400 if (azx_dev->wc_marked != on) { 401 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 402 azx_dev->wc_marked = on; 403 } 404 } 405 #else 406 /* NOP for other archs */ 407 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 408 bool on) 409 { 410 } 411 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 412 struct snd_pcm_substream *substream, bool on) 413 { 414 } 415 #endif 416 417 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 418 419 /* 420 * initialize the PCI registers 421 */ 422 /* update bits in a PCI register byte */ 423 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 424 unsigned char mask, unsigned char val) 425 { 426 unsigned char data; 427 428 pci_read_config_byte(pci, reg, &data); 429 data &= ~mask; 430 data |= (val & mask); 431 pci_write_config_byte(pci, reg, data); 432 } 433 434 static void azx_init_pci(struct azx *chip) 435 { 436 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 437 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 438 * Ensuring these bits are 0 clears playback static on some HD Audio 439 * codecs. 440 * The PCI register TCSEL is defined in the Intel manuals. 441 */ 442 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 443 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 444 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 445 } 446 447 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 448 * we need to enable snoop. 449 */ 450 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) { 451 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 452 azx_snoop(chip)); 453 update_pci_byte(chip->pci, 454 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 455 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 456 } 457 458 /* For NVIDIA HDA, enable snoop */ 459 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) { 460 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 461 azx_snoop(chip)); 462 update_pci_byte(chip->pci, 463 NVIDIA_HDA_TRANSREG_ADDR, 464 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 465 update_pci_byte(chip->pci, 466 NVIDIA_HDA_ISTRM_COH, 467 0x01, NVIDIA_HDA_ENABLE_COHBIT); 468 update_pci_byte(chip->pci, 469 NVIDIA_HDA_OSTRM_COH, 470 0x01, NVIDIA_HDA_ENABLE_COHBIT); 471 } 472 473 /* Enable SCH/PCH snoop if needed */ 474 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) { 475 unsigned short snoop; 476 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 477 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 478 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 479 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 480 if (!azx_snoop(chip)) 481 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 482 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 483 pci_read_config_word(chip->pci, 484 INTEL_SCH_HDA_DEVC, &snoop); 485 } 486 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 487 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 488 "Disabled" : "Enabled"); 489 } 490 } 491 492 /* calculate runtime delay from LPIB */ 493 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 494 unsigned int pos) 495 { 496 struct snd_pcm_substream *substream = azx_dev->substream; 497 int stream = substream->stream; 498 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 499 int delay; 500 501 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 502 delay = pos - lpib_pos; 503 else 504 delay = lpib_pos - pos; 505 if (delay < 0) { 506 if (delay >= azx_dev->delay_negative_threshold) 507 delay = 0; 508 else 509 delay += azx_dev->bufsize; 510 } 511 512 if (delay >= azx_dev->period_bytes) { 513 dev_info(chip->card->dev, 514 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 515 delay, azx_dev->period_bytes); 516 delay = 0; 517 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 518 chip->get_delay[stream] = NULL; 519 } 520 521 return bytes_to_frames(substream->runtime, delay); 522 } 523 524 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 525 526 /* called from IRQ */ 527 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 528 { 529 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 530 int ok; 531 532 ok = azx_position_ok(chip, azx_dev); 533 if (ok == 1) { 534 azx_dev->irq_pending = 0; 535 return ok; 536 } else if (ok == 0 && chip->bus && chip->bus->workq) { 537 /* bogus IRQ, process it later */ 538 azx_dev->irq_pending = 1; 539 queue_work(chip->bus->workq, &hda->irq_pending_work); 540 } 541 return 0; 542 } 543 544 /* 545 * Check whether the current DMA position is acceptable for updating 546 * periods. Returns non-zero if it's OK. 547 * 548 * Many HD-audio controllers appear pretty inaccurate about 549 * the update-IRQ timing. The IRQ is issued before actually the 550 * data is processed. So, we need to process it afterwords in a 551 * workqueue. 552 */ 553 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 554 { 555 struct snd_pcm_substream *substream = azx_dev->substream; 556 int stream = substream->stream; 557 u32 wallclk; 558 unsigned int pos; 559 560 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 561 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 562 return -1; /* bogus (too early) interrupt */ 563 564 if (chip->get_position[stream]) 565 pos = chip->get_position[stream](chip, azx_dev); 566 else { /* use the position buffer as default */ 567 pos = azx_get_pos_posbuf(chip, azx_dev); 568 if (!pos || pos == (u32)-1) { 569 dev_info(chip->card->dev, 570 "Invalid position buffer, using LPIB read method instead.\n"); 571 chip->get_position[stream] = azx_get_pos_lpib; 572 pos = azx_get_pos_lpib(chip, azx_dev); 573 chip->get_delay[stream] = NULL; 574 } else { 575 chip->get_position[stream] = azx_get_pos_posbuf; 576 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 577 chip->get_delay[stream] = azx_get_delay_from_lpib; 578 } 579 } 580 581 if (pos >= azx_dev->bufsize) 582 pos = 0; 583 584 if (WARN_ONCE(!azx_dev->period_bytes, 585 "hda-intel: zero azx_dev->period_bytes")) 586 return -1; /* this shouldn't happen! */ 587 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 588 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 589 /* NG - it's below the first next period boundary */ 590 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; 591 azx_dev->start_wallclk += wallclk; 592 return 1; /* OK, it's fine */ 593 } 594 595 /* 596 * The work for pending PCM period updates. 597 */ 598 static void azx_irq_pending_work(struct work_struct *work) 599 { 600 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 601 struct azx *chip = &hda->chip; 602 int i, pending, ok; 603 604 if (!hda->irq_pending_warned) { 605 dev_info(chip->card->dev, 606 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 607 chip->card->number); 608 hda->irq_pending_warned = 1; 609 } 610 611 for (;;) { 612 pending = 0; 613 spin_lock_irq(&chip->reg_lock); 614 for (i = 0; i < chip->num_streams; i++) { 615 struct azx_dev *azx_dev = &chip->azx_dev[i]; 616 if (!azx_dev->irq_pending || 617 !azx_dev->substream || 618 !azx_dev->running) 619 continue; 620 ok = azx_position_ok(chip, azx_dev); 621 if (ok > 0) { 622 azx_dev->irq_pending = 0; 623 spin_unlock(&chip->reg_lock); 624 snd_pcm_period_elapsed(azx_dev->substream); 625 spin_lock(&chip->reg_lock); 626 } else if (ok < 0) { 627 pending = 0; /* too early */ 628 } else 629 pending++; 630 } 631 spin_unlock_irq(&chip->reg_lock); 632 if (!pending) 633 return; 634 msleep(1); 635 } 636 } 637 638 /* clear irq_pending flags and assure no on-going workq */ 639 static void azx_clear_irq_pending(struct azx *chip) 640 { 641 int i; 642 643 spin_lock_irq(&chip->reg_lock); 644 for (i = 0; i < chip->num_streams; i++) 645 chip->azx_dev[i].irq_pending = 0; 646 spin_unlock_irq(&chip->reg_lock); 647 } 648 649 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 650 { 651 if (request_irq(chip->pci->irq, azx_interrupt, 652 chip->msi ? 0 : IRQF_SHARED, 653 KBUILD_MODNAME, chip)) { 654 dev_err(chip->card->dev, 655 "unable to grab IRQ %d, disabling device\n", 656 chip->pci->irq); 657 if (do_disconnect) 658 snd_card_disconnect(chip->card); 659 return -1; 660 } 661 chip->irq = chip->pci->irq; 662 pci_intx(chip->pci, !chip->msi); 663 return 0; 664 } 665 666 /* get the current DMA position with correction on VIA chips */ 667 static unsigned int azx_via_get_position(struct azx *chip, 668 struct azx_dev *azx_dev) 669 { 670 unsigned int link_pos, mini_pos, bound_pos; 671 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 672 unsigned int fifo_size; 673 674 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); 675 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 676 /* Playback, no problem using link position */ 677 return link_pos; 678 } 679 680 /* Capture */ 681 /* For new chipset, 682 * use mod to get the DMA position just like old chipset 683 */ 684 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 685 mod_dma_pos %= azx_dev->period_bytes; 686 687 /* azx_dev->fifo_size can't get FIFO size of in stream. 688 * Get from base address + offset. 689 */ 690 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 691 692 if (azx_dev->insufficient) { 693 /* Link position never gather than FIFO size */ 694 if (link_pos <= fifo_size) 695 return 0; 696 697 azx_dev->insufficient = 0; 698 } 699 700 if (link_pos <= fifo_size) 701 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 702 else 703 mini_pos = link_pos - fifo_size; 704 705 /* Find nearest previous boudary */ 706 mod_mini_pos = mini_pos % azx_dev->period_bytes; 707 mod_link_pos = link_pos % azx_dev->period_bytes; 708 if (mod_link_pos >= fifo_size) 709 bound_pos = link_pos - mod_link_pos; 710 else if (mod_dma_pos >= mod_mini_pos) 711 bound_pos = mini_pos - mod_mini_pos; 712 else { 713 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 714 if (bound_pos >= azx_dev->bufsize) 715 bound_pos = 0; 716 } 717 718 /* Calculate real DMA position we want */ 719 return bound_pos + mod_dma_pos; 720 } 721 722 #ifdef CONFIG_PM 723 static DEFINE_MUTEX(card_list_lock); 724 static LIST_HEAD(card_list); 725 726 static void azx_add_card_list(struct azx *chip) 727 { 728 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 729 mutex_lock(&card_list_lock); 730 list_add(&hda->list, &card_list); 731 mutex_unlock(&card_list_lock); 732 } 733 734 static void azx_del_card_list(struct azx *chip) 735 { 736 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 737 mutex_lock(&card_list_lock); 738 list_del_init(&hda->list); 739 mutex_unlock(&card_list_lock); 740 } 741 742 /* trigger power-save check at writing parameter */ 743 static int param_set_xint(const char *val, const struct kernel_param *kp) 744 { 745 struct hda_intel *hda; 746 struct azx *chip; 747 struct hda_codec *c; 748 int prev = power_save; 749 int ret = param_set_int(val, kp); 750 751 if (ret || prev == power_save) 752 return ret; 753 754 mutex_lock(&card_list_lock); 755 list_for_each_entry(hda, &card_list, list) { 756 chip = &hda->chip; 757 if (!chip->bus || chip->disabled) 758 continue; 759 list_for_each_entry(c, &chip->bus->codec_list, list) 760 snd_hda_power_sync(c); 761 } 762 mutex_unlock(&card_list_lock); 763 return 0; 764 } 765 #else 766 #define azx_add_card_list(chip) /* NOP */ 767 #define azx_del_card_list(chip) /* NOP */ 768 #endif /* CONFIG_PM */ 769 770 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 771 /* 772 * power management 773 */ 774 static int azx_suspend(struct device *dev) 775 { 776 struct pci_dev *pci = to_pci_dev(dev); 777 struct snd_card *card = dev_get_drvdata(dev); 778 struct azx *chip; 779 struct hda_intel *hda; 780 struct azx_pcm *p; 781 782 if (!card) 783 return 0; 784 785 chip = card->private_data; 786 hda = container_of(chip, struct hda_intel, chip); 787 if (chip->disabled || hda->init_failed) 788 return 0; 789 790 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 791 azx_clear_irq_pending(chip); 792 list_for_each_entry(p, &chip->pcm_list, list) 793 snd_pcm_suspend_all(p->pcm); 794 if (chip->initialized) 795 snd_hda_suspend(chip->bus); 796 azx_stop_chip(chip); 797 azx_enter_link_reset(chip); 798 if (chip->irq >= 0) { 799 free_irq(chip->irq, chip); 800 chip->irq = -1; 801 } 802 803 if (chip->msi) 804 pci_disable_msi(chip->pci); 805 pci_disable_device(pci); 806 pci_save_state(pci); 807 pci_set_power_state(pci, PCI_D3hot); 808 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 809 hda_display_power(false); 810 return 0; 811 } 812 813 static int azx_resume(struct device *dev) 814 { 815 struct pci_dev *pci = to_pci_dev(dev); 816 struct snd_card *card = dev_get_drvdata(dev); 817 struct azx *chip; 818 struct hda_intel *hda; 819 820 if (!card) 821 return 0; 822 823 chip = card->private_data; 824 hda = container_of(chip, struct hda_intel, chip); 825 if (chip->disabled || hda->init_failed) 826 return 0; 827 828 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 829 hda_display_power(true); 830 haswell_set_bclk(chip); 831 } 832 pci_set_power_state(pci, PCI_D0); 833 pci_restore_state(pci); 834 if (pci_enable_device(pci) < 0) { 835 dev_err(chip->card->dev, 836 "pci_enable_device failed, disabling device\n"); 837 snd_card_disconnect(card); 838 return -EIO; 839 } 840 pci_set_master(pci); 841 if (chip->msi) 842 if (pci_enable_msi(pci) < 0) 843 chip->msi = 0; 844 if (azx_acquire_irq(chip, 1) < 0) 845 return -EIO; 846 azx_init_pci(chip); 847 848 azx_init_chip(chip, true); 849 850 snd_hda_resume(chip->bus); 851 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 852 return 0; 853 } 854 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 855 856 #ifdef CONFIG_PM_RUNTIME 857 static int azx_runtime_suspend(struct device *dev) 858 { 859 struct snd_card *card = dev_get_drvdata(dev); 860 struct azx *chip; 861 struct hda_intel *hda; 862 863 if (!card) 864 return 0; 865 866 chip = card->private_data; 867 hda = container_of(chip, struct hda_intel, chip); 868 if (chip->disabled || hda->init_failed) 869 return 0; 870 871 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 872 return 0; 873 874 /* enable controller wake up event */ 875 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 876 STATESTS_INT_MASK); 877 878 azx_stop_chip(chip); 879 azx_enter_link_reset(chip); 880 azx_clear_irq_pending(chip); 881 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 882 hda_display_power(false); 883 884 return 0; 885 } 886 887 static int azx_runtime_resume(struct device *dev) 888 { 889 struct snd_card *card = dev_get_drvdata(dev); 890 struct azx *chip; 891 struct hda_intel *hda; 892 struct hda_bus *bus; 893 struct hda_codec *codec; 894 int status; 895 896 if (!card) 897 return 0; 898 899 chip = card->private_data; 900 hda = container_of(chip, struct hda_intel, chip); 901 if (chip->disabled || hda->init_failed) 902 return 0; 903 904 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 905 return 0; 906 907 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 908 hda_display_power(true); 909 haswell_set_bclk(chip); 910 } 911 912 /* Read STATESTS before controller reset */ 913 status = azx_readw(chip, STATESTS); 914 915 azx_init_pci(chip); 916 azx_init_chip(chip, true); 917 918 bus = chip->bus; 919 if (status && bus) { 920 list_for_each_entry(codec, &bus->codec_list, list) 921 if (status & (1 << codec->addr)) 922 queue_delayed_work(codec->bus->workq, 923 &codec->jackpoll_work, codec->jackpoll_interval); 924 } 925 926 /* disable controller Wake Up event*/ 927 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 928 ~STATESTS_INT_MASK); 929 930 return 0; 931 } 932 933 static int azx_runtime_idle(struct device *dev) 934 { 935 struct snd_card *card = dev_get_drvdata(dev); 936 struct azx *chip; 937 struct hda_intel *hda; 938 939 if (!card) 940 return 0; 941 942 chip = card->private_data; 943 hda = container_of(chip, struct hda_intel, chip); 944 if (chip->disabled || hda->init_failed) 945 return 0; 946 947 if (!power_save_controller || 948 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 949 return -EBUSY; 950 951 return 0; 952 } 953 954 #endif /* CONFIG_PM_RUNTIME */ 955 956 #ifdef CONFIG_PM 957 static const struct dev_pm_ops azx_pm = { 958 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 959 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 960 }; 961 962 #define AZX_PM_OPS &azx_pm 963 #else 964 #define AZX_PM_OPS NULL 965 #endif /* CONFIG_PM */ 966 967 968 static int azx_probe_continue(struct azx *chip); 969 970 #ifdef SUPPORT_VGA_SWITCHEROO 971 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 972 973 static void azx_vs_set_state(struct pci_dev *pci, 974 enum vga_switcheroo_state state) 975 { 976 struct snd_card *card = pci_get_drvdata(pci); 977 struct azx *chip = card->private_data; 978 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 979 bool disabled; 980 981 wait_for_completion(&hda->probe_wait); 982 if (hda->init_failed) 983 return; 984 985 disabled = (state == VGA_SWITCHEROO_OFF); 986 if (chip->disabled == disabled) 987 return; 988 989 if (!chip->bus) { 990 chip->disabled = disabled; 991 if (!disabled) { 992 dev_info(chip->card->dev, 993 "Start delayed initialization\n"); 994 if (azx_probe_continue(chip) < 0) { 995 dev_err(chip->card->dev, "initialization error\n"); 996 hda->init_failed = true; 997 } 998 } 999 } else { 1000 dev_info(chip->card->dev, "%s via VGA-switcheroo\n", 1001 disabled ? "Disabling" : "Enabling"); 1002 if (disabled) { 1003 pm_runtime_put_sync_suspend(card->dev); 1004 azx_suspend(card->dev); 1005 /* when we get suspended by vga switcheroo we end up in D3cold, 1006 * however we have no ACPI handle, so pci/acpi can't put us there, 1007 * put ourselves there */ 1008 pci->current_state = PCI_D3cold; 1009 chip->disabled = true; 1010 if (snd_hda_lock_devices(chip->bus)) 1011 dev_warn(chip->card->dev, 1012 "Cannot lock devices!\n"); 1013 } else { 1014 snd_hda_unlock_devices(chip->bus); 1015 pm_runtime_get_noresume(card->dev); 1016 chip->disabled = false; 1017 azx_resume(card->dev); 1018 } 1019 } 1020 } 1021 1022 static bool azx_vs_can_switch(struct pci_dev *pci) 1023 { 1024 struct snd_card *card = pci_get_drvdata(pci); 1025 struct azx *chip = card->private_data; 1026 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1027 1028 wait_for_completion(&hda->probe_wait); 1029 if (hda->init_failed) 1030 return false; 1031 if (chip->disabled || !chip->bus) 1032 return true; 1033 if (snd_hda_lock_devices(chip->bus)) 1034 return false; 1035 snd_hda_unlock_devices(chip->bus); 1036 return true; 1037 } 1038 1039 static void init_vga_switcheroo(struct azx *chip) 1040 { 1041 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1042 struct pci_dev *p = get_bound_vga(chip->pci); 1043 if (p) { 1044 dev_info(chip->card->dev, 1045 "Handle VGA-switcheroo audio client\n"); 1046 hda->use_vga_switcheroo = 1; 1047 pci_dev_put(p); 1048 } 1049 } 1050 1051 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1052 .set_gpu_state = azx_vs_set_state, 1053 .can_switch = azx_vs_can_switch, 1054 }; 1055 1056 static int register_vga_switcheroo(struct azx *chip) 1057 { 1058 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1059 int err; 1060 1061 if (!hda->use_vga_switcheroo) 1062 return 0; 1063 /* FIXME: currently only handling DIS controller 1064 * is there any machine with two switchable HDMI audio controllers? 1065 */ 1066 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1067 VGA_SWITCHEROO_DIS, 1068 chip->bus != NULL); 1069 if (err < 0) 1070 return err; 1071 hda->vga_switcheroo_registered = 1; 1072 1073 /* register as an optimus hdmi audio power domain */ 1074 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1075 &hda->hdmi_pm_domain); 1076 return 0; 1077 } 1078 #else 1079 #define init_vga_switcheroo(chip) /* NOP */ 1080 #define register_vga_switcheroo(chip) 0 1081 #define check_hdmi_disabled(pci) false 1082 #endif /* SUPPORT_VGA_SWITCHER */ 1083 1084 /* 1085 * destructor 1086 */ 1087 static int azx_free(struct azx *chip) 1088 { 1089 struct pci_dev *pci = chip->pci; 1090 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1091 int i; 1092 1093 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) 1094 && chip->running) 1095 pm_runtime_get_noresume(&pci->dev); 1096 1097 azx_del_card_list(chip); 1098 1099 azx_notifier_unregister(chip); 1100 1101 hda->init_failed = 1; /* to be sure */ 1102 complete_all(&hda->probe_wait); 1103 1104 if (use_vga_switcheroo(hda)) { 1105 if (chip->disabled && chip->bus) 1106 snd_hda_unlock_devices(chip->bus); 1107 if (hda->vga_switcheroo_registered) 1108 vga_switcheroo_unregister_client(chip->pci); 1109 } 1110 1111 if (chip->initialized) { 1112 azx_clear_irq_pending(chip); 1113 for (i = 0; i < chip->num_streams; i++) 1114 azx_stream_stop(chip, &chip->azx_dev[i]); 1115 azx_stop_chip(chip); 1116 } 1117 1118 if (chip->irq >= 0) 1119 free_irq(chip->irq, (void*)chip); 1120 if (chip->msi) 1121 pci_disable_msi(chip->pci); 1122 if (chip->remap_addr) 1123 iounmap(chip->remap_addr); 1124 1125 azx_free_stream_pages(chip); 1126 if (chip->region_requested) 1127 pci_release_regions(chip->pci); 1128 pci_disable_device(chip->pci); 1129 kfree(chip->azx_dev); 1130 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1131 if (chip->fw) 1132 release_firmware(chip->fw); 1133 #endif 1134 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1135 hda_display_power(false); 1136 hda_i915_exit(); 1137 } 1138 kfree(hda); 1139 1140 return 0; 1141 } 1142 1143 static int azx_dev_free(struct snd_device *device) 1144 { 1145 return azx_free(device->device_data); 1146 } 1147 1148 #ifdef SUPPORT_VGA_SWITCHEROO 1149 /* 1150 * Check of disabled HDMI controller by vga-switcheroo 1151 */ 1152 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1153 { 1154 struct pci_dev *p; 1155 1156 /* check only discrete GPU */ 1157 switch (pci->vendor) { 1158 case PCI_VENDOR_ID_ATI: 1159 case PCI_VENDOR_ID_AMD: 1160 case PCI_VENDOR_ID_NVIDIA: 1161 if (pci->devfn == 1) { 1162 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1163 pci->bus->number, 0); 1164 if (p) { 1165 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1166 return p; 1167 pci_dev_put(p); 1168 } 1169 } 1170 break; 1171 } 1172 return NULL; 1173 } 1174 1175 static bool check_hdmi_disabled(struct pci_dev *pci) 1176 { 1177 bool vga_inactive = false; 1178 struct pci_dev *p = get_bound_vga(pci); 1179 1180 if (p) { 1181 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1182 vga_inactive = true; 1183 pci_dev_put(p); 1184 } 1185 return vga_inactive; 1186 } 1187 #endif /* SUPPORT_VGA_SWITCHEROO */ 1188 1189 /* 1190 * white/black-listing for position_fix 1191 */ 1192 static struct snd_pci_quirk position_fix_list[] = { 1193 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1194 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1195 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1196 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1197 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1198 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1199 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1200 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1201 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1202 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1203 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1204 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1205 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1206 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1207 {} 1208 }; 1209 1210 static int check_position_fix(struct azx *chip, int fix) 1211 { 1212 const struct snd_pci_quirk *q; 1213 1214 switch (fix) { 1215 case POS_FIX_AUTO: 1216 case POS_FIX_LPIB: 1217 case POS_FIX_POSBUF: 1218 case POS_FIX_VIACOMBO: 1219 case POS_FIX_COMBO: 1220 return fix; 1221 } 1222 1223 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1224 if (q) { 1225 dev_info(chip->card->dev, 1226 "position_fix set to %d for device %04x:%04x\n", 1227 q->value, q->subvendor, q->subdevice); 1228 return q->value; 1229 } 1230 1231 /* Check VIA/ATI HD Audio Controller exist */ 1232 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 1233 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1234 return POS_FIX_VIACOMBO; 1235 } 1236 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1237 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1238 return POS_FIX_LPIB; 1239 } 1240 return POS_FIX_AUTO; 1241 } 1242 1243 static void assign_position_fix(struct azx *chip, int fix) 1244 { 1245 static azx_get_pos_callback_t callbacks[] = { 1246 [POS_FIX_AUTO] = NULL, 1247 [POS_FIX_LPIB] = azx_get_pos_lpib, 1248 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1249 [POS_FIX_VIACOMBO] = azx_via_get_position, 1250 [POS_FIX_COMBO] = azx_get_pos_lpib, 1251 }; 1252 1253 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1254 1255 /* combo mode uses LPIB only for playback */ 1256 if (fix == POS_FIX_COMBO) 1257 chip->get_position[1] = NULL; 1258 1259 if (fix == POS_FIX_POSBUF && 1260 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1261 chip->get_delay[0] = chip->get_delay[1] = 1262 azx_get_delay_from_lpib; 1263 } 1264 1265 } 1266 1267 /* 1268 * black-lists for probe_mask 1269 */ 1270 static struct snd_pci_quirk probe_mask_list[] = { 1271 /* Thinkpad often breaks the controller communication when accessing 1272 * to the non-working (or non-existing) modem codec slot. 1273 */ 1274 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1275 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1276 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1277 /* broken BIOS */ 1278 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1279 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1280 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1281 /* forced codec slots */ 1282 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1283 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1284 /* WinFast VP200 H (Teradici) user reported broken communication */ 1285 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1286 {} 1287 }; 1288 1289 #define AZX_FORCE_CODEC_MASK 0x100 1290 1291 static void check_probe_mask(struct azx *chip, int dev) 1292 { 1293 const struct snd_pci_quirk *q; 1294 1295 chip->codec_probe_mask = probe_mask[dev]; 1296 if (chip->codec_probe_mask == -1) { 1297 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1298 if (q) { 1299 dev_info(chip->card->dev, 1300 "probe_mask set to 0x%x for device %04x:%04x\n", 1301 q->value, q->subvendor, q->subdevice); 1302 chip->codec_probe_mask = q->value; 1303 } 1304 } 1305 1306 /* check forced option */ 1307 if (chip->codec_probe_mask != -1 && 1308 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1309 chip->codec_mask = chip->codec_probe_mask & 0xff; 1310 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1311 chip->codec_mask); 1312 } 1313 } 1314 1315 /* 1316 * white/black-list for enable_msi 1317 */ 1318 static struct snd_pci_quirk msi_black_list[] = { 1319 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1320 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1321 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1322 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1323 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1324 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1325 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1326 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1327 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1328 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1329 {} 1330 }; 1331 1332 static void check_msi(struct azx *chip) 1333 { 1334 const struct snd_pci_quirk *q; 1335 1336 if (enable_msi >= 0) { 1337 chip->msi = !!enable_msi; 1338 return; 1339 } 1340 chip->msi = 1; /* enable MSI as default */ 1341 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1342 if (q) { 1343 dev_info(chip->card->dev, 1344 "msi for device %04x:%04x set to %d\n", 1345 q->subvendor, q->subdevice, q->value); 1346 chip->msi = q->value; 1347 return; 1348 } 1349 1350 /* NVidia chipsets seem to cause troubles with MSI */ 1351 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1352 dev_info(chip->card->dev, "Disabling MSI\n"); 1353 chip->msi = 0; 1354 } 1355 } 1356 1357 /* check the snoop mode availability */ 1358 static void azx_check_snoop_available(struct azx *chip) 1359 { 1360 bool snoop = chip->snoop; 1361 1362 switch (chip->driver_type) { 1363 case AZX_DRIVER_VIA: 1364 /* force to non-snoop mode for a new VIA controller 1365 * when BIOS is set 1366 */ 1367 if (snoop) { 1368 u8 val; 1369 pci_read_config_byte(chip->pci, 0x42, &val); 1370 if (!(val & 0x80) && chip->pci->revision == 0x30) 1371 snoop = false; 1372 } 1373 break; 1374 case AZX_DRIVER_ATIHDMI_NS: 1375 /* new ATI HDMI requires non-snoop */ 1376 snoop = false; 1377 break; 1378 case AZX_DRIVER_CTHDA: 1379 case AZX_DRIVER_CMEDIA: 1380 snoop = false; 1381 break; 1382 } 1383 1384 if (snoop != chip->snoop) { 1385 dev_info(chip->card->dev, "Force to %s mode\n", 1386 snoop ? "snoop" : "non-snoop"); 1387 chip->snoop = snoop; 1388 } 1389 } 1390 1391 static void azx_probe_work(struct work_struct *work) 1392 { 1393 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1394 azx_probe_continue(&hda->chip); 1395 } 1396 1397 /* 1398 * constructor 1399 */ 1400 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1401 int dev, unsigned int driver_caps, 1402 const struct hda_controller_ops *hda_ops, 1403 struct azx **rchip) 1404 { 1405 static struct snd_device_ops ops = { 1406 .dev_free = azx_dev_free, 1407 }; 1408 struct hda_intel *hda; 1409 struct azx *chip; 1410 int err; 1411 1412 *rchip = NULL; 1413 1414 err = pci_enable_device(pci); 1415 if (err < 0) 1416 return err; 1417 1418 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1419 if (!hda) { 1420 dev_err(card->dev, "Cannot allocate hda\n"); 1421 pci_disable_device(pci); 1422 return -ENOMEM; 1423 } 1424 1425 chip = &hda->chip; 1426 spin_lock_init(&chip->reg_lock); 1427 mutex_init(&chip->open_mutex); 1428 chip->card = card; 1429 chip->pci = pci; 1430 chip->ops = hda_ops; 1431 chip->irq = -1; 1432 chip->driver_caps = driver_caps; 1433 chip->driver_type = driver_caps & 0xff; 1434 check_msi(chip); 1435 chip->dev_index = dev; 1436 chip->jackpoll_ms = jackpoll_ms; 1437 INIT_LIST_HEAD(&chip->pcm_list); 1438 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1439 INIT_LIST_HEAD(&hda->list); 1440 init_vga_switcheroo(chip); 1441 init_completion(&hda->probe_wait); 1442 1443 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1444 1445 check_probe_mask(chip, dev); 1446 1447 chip->single_cmd = single_cmd; 1448 chip->snoop = hda_snoop; 1449 azx_check_snoop_available(chip); 1450 1451 if (bdl_pos_adj[dev] < 0) { 1452 switch (chip->driver_type) { 1453 case AZX_DRIVER_ICH: 1454 case AZX_DRIVER_PCH: 1455 bdl_pos_adj[dev] = 1; 1456 break; 1457 default: 1458 bdl_pos_adj[dev] = 32; 1459 break; 1460 } 1461 } 1462 chip->bdl_pos_adj = bdl_pos_adj; 1463 1464 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1465 if (err < 0) { 1466 dev_err(card->dev, "Error creating device [card]!\n"); 1467 azx_free(chip); 1468 return err; 1469 } 1470 1471 /* continue probing in work context as may trigger request module */ 1472 INIT_WORK(&hda->probe_work, azx_probe_work); 1473 1474 *rchip = chip; 1475 1476 return 0; 1477 } 1478 1479 static int azx_first_init(struct azx *chip) 1480 { 1481 int dev = chip->dev_index; 1482 struct pci_dev *pci = chip->pci; 1483 struct snd_card *card = chip->card; 1484 int err; 1485 unsigned short gcap; 1486 1487 #if BITS_PER_LONG != 64 1488 /* Fix up base address on ULI M5461 */ 1489 if (chip->driver_type == AZX_DRIVER_ULI) { 1490 u16 tmp3; 1491 pci_read_config_word(pci, 0x40, &tmp3); 1492 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1493 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1494 } 1495 #endif 1496 1497 err = pci_request_regions(pci, "ICH HD audio"); 1498 if (err < 0) 1499 return err; 1500 chip->region_requested = 1; 1501 1502 chip->addr = pci_resource_start(pci, 0); 1503 chip->remap_addr = pci_ioremap_bar(pci, 0); 1504 if (chip->remap_addr == NULL) { 1505 dev_err(card->dev, "ioremap error\n"); 1506 return -ENXIO; 1507 } 1508 1509 if (chip->msi) 1510 if (pci_enable_msi(pci) < 0) 1511 chip->msi = 0; 1512 1513 if (azx_acquire_irq(chip, 0) < 0) 1514 return -EBUSY; 1515 1516 pci_set_master(pci); 1517 synchronize_irq(chip->irq); 1518 1519 gcap = azx_readw(chip, GCAP); 1520 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1521 1522 /* disable SB600 64bit support for safety */ 1523 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1524 struct pci_dev *p_smbus; 1525 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1526 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1527 NULL); 1528 if (p_smbus) { 1529 if (p_smbus->revision < 0x30) 1530 gcap &= ~AZX_GCAP_64OK; 1531 pci_dev_put(p_smbus); 1532 } 1533 } 1534 1535 /* disable 64bit DMA address on some devices */ 1536 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1537 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1538 gcap &= ~AZX_GCAP_64OK; 1539 } 1540 1541 /* disable buffer size rounding to 128-byte multiples if supported */ 1542 if (align_buffer_size >= 0) 1543 chip->align_buffer_size = !!align_buffer_size; 1544 else { 1545 if (chip->driver_caps & AZX_DCAPS_BUFSIZE) 1546 chip->align_buffer_size = 0; 1547 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE) 1548 chip->align_buffer_size = 1; 1549 else 1550 chip->align_buffer_size = 1; 1551 } 1552 1553 /* allow 64bit DMA address if supported by H/W */ 1554 if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 1555 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 1556 else { 1557 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 1558 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 1559 } 1560 1561 /* read number of streams from GCAP register instead of using 1562 * hardcoded value 1563 */ 1564 chip->capture_streams = (gcap >> 8) & 0x0f; 1565 chip->playback_streams = (gcap >> 12) & 0x0f; 1566 if (!chip->playback_streams && !chip->capture_streams) { 1567 /* gcap didn't give any info, switching to old method */ 1568 1569 switch (chip->driver_type) { 1570 case AZX_DRIVER_ULI: 1571 chip->playback_streams = ULI_NUM_PLAYBACK; 1572 chip->capture_streams = ULI_NUM_CAPTURE; 1573 break; 1574 case AZX_DRIVER_ATIHDMI: 1575 case AZX_DRIVER_ATIHDMI_NS: 1576 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1577 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1578 break; 1579 case AZX_DRIVER_GENERIC: 1580 default: 1581 chip->playback_streams = ICH6_NUM_PLAYBACK; 1582 chip->capture_streams = ICH6_NUM_CAPTURE; 1583 break; 1584 } 1585 } 1586 chip->capture_index_offset = 0; 1587 chip->playback_index_offset = chip->capture_streams; 1588 chip->num_streams = chip->playback_streams + chip->capture_streams; 1589 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 1590 GFP_KERNEL); 1591 if (!chip->azx_dev) { 1592 dev_err(card->dev, "cannot malloc azx_dev\n"); 1593 return -ENOMEM; 1594 } 1595 1596 err = azx_alloc_stream_pages(chip); 1597 if (err < 0) 1598 return err; 1599 1600 /* initialize streams */ 1601 azx_init_stream(chip); 1602 1603 /* initialize chip */ 1604 azx_init_pci(chip); 1605 1606 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1607 haswell_set_bclk(chip); 1608 1609 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 1610 1611 /* codec detection */ 1612 if (!chip->codec_mask) { 1613 dev_err(card->dev, "no codecs found!\n"); 1614 return -ENODEV; 1615 } 1616 1617 strcpy(card->driver, "HDA-Intel"); 1618 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1619 sizeof(card->shortname)); 1620 snprintf(card->longname, sizeof(card->longname), 1621 "%s at 0x%lx irq %i", 1622 card->shortname, chip->addr, chip->irq); 1623 1624 return 0; 1625 } 1626 1627 static void power_down_all_codecs(struct azx *chip) 1628 { 1629 #ifdef CONFIG_PM 1630 /* The codecs were powered up in snd_hda_codec_new(). 1631 * Now all initialization done, so turn them down if possible 1632 */ 1633 struct hda_codec *codec; 1634 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1635 snd_hda_power_down(codec); 1636 } 1637 #endif 1638 } 1639 1640 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1641 /* callback from request_firmware_nowait() */ 1642 static void azx_firmware_cb(const struct firmware *fw, void *context) 1643 { 1644 struct snd_card *card = context; 1645 struct azx *chip = card->private_data; 1646 struct pci_dev *pci = chip->pci; 1647 1648 if (!fw) { 1649 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1650 goto error; 1651 } 1652 1653 chip->fw = fw; 1654 if (!chip->disabled) { 1655 /* continue probing */ 1656 if (azx_probe_continue(chip)) 1657 goto error; 1658 } 1659 return; /* OK */ 1660 1661 error: 1662 snd_card_free(card); 1663 pci_set_drvdata(pci, NULL); 1664 } 1665 #endif 1666 1667 /* 1668 * HDA controller ops. 1669 */ 1670 1671 /* PCI register access. */ 1672 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1673 { 1674 writel(value, addr); 1675 } 1676 1677 static u32 pci_azx_readl(u32 __iomem *addr) 1678 { 1679 return readl(addr); 1680 } 1681 1682 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1683 { 1684 writew(value, addr); 1685 } 1686 1687 static u16 pci_azx_readw(u16 __iomem *addr) 1688 { 1689 return readw(addr); 1690 } 1691 1692 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1693 { 1694 writeb(value, addr); 1695 } 1696 1697 static u8 pci_azx_readb(u8 __iomem *addr) 1698 { 1699 return readb(addr); 1700 } 1701 1702 static int disable_msi_reset_irq(struct azx *chip) 1703 { 1704 int err; 1705 1706 free_irq(chip->irq, chip); 1707 chip->irq = -1; 1708 pci_disable_msi(chip->pci); 1709 chip->msi = 0; 1710 err = azx_acquire_irq(chip, 1); 1711 if (err < 0) 1712 return err; 1713 1714 return 0; 1715 } 1716 1717 /* DMA page allocation helpers. */ 1718 static int dma_alloc_pages(struct azx *chip, 1719 int type, 1720 size_t size, 1721 struct snd_dma_buffer *buf) 1722 { 1723 int err; 1724 1725 err = snd_dma_alloc_pages(type, 1726 chip->card->dev, 1727 size, buf); 1728 if (err < 0) 1729 return err; 1730 mark_pages_wc(chip, buf, true); 1731 return 0; 1732 } 1733 1734 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) 1735 { 1736 mark_pages_wc(chip, buf, false); 1737 snd_dma_free_pages(buf); 1738 } 1739 1740 static int substream_alloc_pages(struct azx *chip, 1741 struct snd_pcm_substream *substream, 1742 size_t size) 1743 { 1744 struct azx_dev *azx_dev = get_azx_dev(substream); 1745 int ret; 1746 1747 mark_runtime_wc(chip, azx_dev, substream, false); 1748 azx_dev->bufsize = 0; 1749 azx_dev->period_bytes = 0; 1750 azx_dev->format_val = 0; 1751 ret = snd_pcm_lib_malloc_pages(substream, size); 1752 if (ret < 0) 1753 return ret; 1754 mark_runtime_wc(chip, azx_dev, substream, true); 1755 return 0; 1756 } 1757 1758 static int substream_free_pages(struct azx *chip, 1759 struct snd_pcm_substream *substream) 1760 { 1761 struct azx_dev *azx_dev = get_azx_dev(substream); 1762 mark_runtime_wc(chip, azx_dev, substream, false); 1763 return snd_pcm_lib_free_pages(substream); 1764 } 1765 1766 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1767 struct vm_area_struct *area) 1768 { 1769 #ifdef CONFIG_X86 1770 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1771 struct azx *chip = apcm->chip; 1772 if (!azx_snoop(chip)) 1773 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1774 #endif 1775 } 1776 1777 static const struct hda_controller_ops pci_hda_ops = { 1778 .reg_writel = pci_azx_writel, 1779 .reg_readl = pci_azx_readl, 1780 .reg_writew = pci_azx_writew, 1781 .reg_readw = pci_azx_readw, 1782 .reg_writeb = pci_azx_writeb, 1783 .reg_readb = pci_azx_readb, 1784 .disable_msi_reset_irq = disable_msi_reset_irq, 1785 .dma_alloc_pages = dma_alloc_pages, 1786 .dma_free_pages = dma_free_pages, 1787 .substream_alloc_pages = substream_alloc_pages, 1788 .substream_free_pages = substream_free_pages, 1789 .pcm_mmap_prepare = pcm_mmap_prepare, 1790 .position_check = azx_position_check, 1791 }; 1792 1793 static int azx_probe(struct pci_dev *pci, 1794 const struct pci_device_id *pci_id) 1795 { 1796 static int dev; 1797 struct snd_card *card; 1798 struct hda_intel *hda; 1799 struct azx *chip; 1800 bool schedule_probe; 1801 int err; 1802 1803 if (dev >= SNDRV_CARDS) 1804 return -ENODEV; 1805 if (!enable[dev]) { 1806 dev++; 1807 return -ENOENT; 1808 } 1809 1810 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1811 0, &card); 1812 if (err < 0) { 1813 dev_err(&pci->dev, "Error creating card!\n"); 1814 return err; 1815 } 1816 1817 err = azx_create(card, pci, dev, pci_id->driver_data, 1818 &pci_hda_ops, &chip); 1819 if (err < 0) 1820 goto out_free; 1821 card->private_data = chip; 1822 hda = container_of(chip, struct hda_intel, chip); 1823 1824 pci_set_drvdata(pci, card); 1825 1826 err = register_vga_switcheroo(chip); 1827 if (err < 0) { 1828 dev_err(card->dev, "Error registering VGA-switcheroo client\n"); 1829 goto out_free; 1830 } 1831 1832 if (check_hdmi_disabled(pci)) { 1833 dev_info(card->dev, "VGA controller is disabled\n"); 1834 dev_info(card->dev, "Delaying initialization\n"); 1835 chip->disabled = true; 1836 } 1837 1838 schedule_probe = !chip->disabled; 1839 1840 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1841 if (patch[dev] && *patch[dev]) { 1842 dev_info(card->dev, "Applying patch firmware '%s'\n", 1843 patch[dev]); 1844 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1845 &pci->dev, GFP_KERNEL, card, 1846 azx_firmware_cb); 1847 if (err < 0) 1848 goto out_free; 1849 schedule_probe = false; /* continued in azx_firmware_cb() */ 1850 } 1851 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1852 1853 #ifndef CONFIG_SND_HDA_I915 1854 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1855 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); 1856 #endif 1857 1858 if (schedule_probe) 1859 schedule_work(&hda->probe_work); 1860 1861 dev++; 1862 if (chip->disabled) 1863 complete_all(&hda->probe_wait); 1864 return 0; 1865 1866 out_free: 1867 snd_card_free(card); 1868 return err; 1869 } 1870 1871 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1872 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1873 [AZX_DRIVER_NVIDIA] = 8, 1874 [AZX_DRIVER_TERA] = 1, 1875 }; 1876 1877 static int azx_probe_continue(struct azx *chip) 1878 { 1879 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1880 struct pci_dev *pci = chip->pci; 1881 int dev = chip->dev_index; 1882 int err; 1883 1884 /* Request power well for Haswell HDA controller and codec */ 1885 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1886 #ifdef CONFIG_SND_HDA_I915 1887 err = hda_i915_init(); 1888 if (err < 0) { 1889 dev_err(chip->card->dev, 1890 "Error request power-well from i915\n"); 1891 goto out_free; 1892 } 1893 err = hda_display_power(true); 1894 if (err < 0) { 1895 dev_err(chip->card->dev, 1896 "Cannot turn on display power on i915\n"); 1897 goto out_free; 1898 } 1899 #endif 1900 } 1901 1902 err = azx_first_init(chip); 1903 if (err < 0) 1904 goto out_free; 1905 1906 #ifdef CONFIG_SND_HDA_INPUT_BEEP 1907 chip->beep_mode = beep_mode[dev]; 1908 #endif 1909 1910 /* create codec instances */ 1911 err = azx_codec_create(chip, model[dev], 1912 azx_max_codecs[chip->driver_type], 1913 power_save_addr); 1914 1915 if (err < 0) 1916 goto out_free; 1917 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1918 if (chip->fw) { 1919 err = snd_hda_load_patch(chip->bus, chip->fw->size, 1920 chip->fw->data); 1921 if (err < 0) 1922 goto out_free; 1923 #ifndef CONFIG_PM 1924 release_firmware(chip->fw); /* no longer needed */ 1925 chip->fw = NULL; 1926 #endif 1927 } 1928 #endif 1929 if ((probe_only[dev] & 1) == 0) { 1930 err = azx_codec_configure(chip); 1931 if (err < 0) 1932 goto out_free; 1933 } 1934 1935 /* create PCM streams */ 1936 err = snd_hda_build_pcms(chip->bus); 1937 if (err < 0) 1938 goto out_free; 1939 1940 /* create mixer controls */ 1941 err = azx_mixer_create(chip); 1942 if (err < 0) 1943 goto out_free; 1944 1945 err = snd_card_register(chip->card); 1946 if (err < 0) 1947 goto out_free; 1948 1949 chip->running = 1; 1950 power_down_all_codecs(chip); 1951 azx_notifier_register(chip); 1952 azx_add_card_list(chip); 1953 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo) 1954 pm_runtime_put_noidle(&pci->dev); 1955 1956 out_free: 1957 if (err < 0) 1958 hda->init_failed = 1; 1959 complete_all(&hda->probe_wait); 1960 return err; 1961 } 1962 1963 static void azx_remove(struct pci_dev *pci) 1964 { 1965 struct snd_card *card = pci_get_drvdata(pci); 1966 1967 if (card) 1968 snd_card_free(card); 1969 } 1970 1971 /* PCI IDs */ 1972 static const struct pci_device_id azx_ids[] = { 1973 /* CPT */ 1974 { PCI_DEVICE(0x8086, 0x1c20), 1975 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1976 /* PBG */ 1977 { PCI_DEVICE(0x8086, 0x1d20), 1978 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1979 /* Panther Point */ 1980 { PCI_DEVICE(0x8086, 0x1e20), 1981 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1982 /* Lynx Point */ 1983 { PCI_DEVICE(0x8086, 0x8c20), 1984 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1985 /* 9 Series */ 1986 { PCI_DEVICE(0x8086, 0x8ca0), 1987 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1988 /* Wellsburg */ 1989 { PCI_DEVICE(0x8086, 0x8d20), 1990 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1991 { PCI_DEVICE(0x8086, 0x8d21), 1992 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1993 /* Lynx Point-LP */ 1994 { PCI_DEVICE(0x8086, 0x9c20), 1995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1996 /* Lynx Point-LP */ 1997 { PCI_DEVICE(0x8086, 0x9c21), 1998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1999 /* Wildcat Point-LP */ 2000 { PCI_DEVICE(0x8086, 0x9ca0), 2001 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2002 /* Sunrise Point */ 2003 { PCI_DEVICE(0x8086, 0xa170), 2004 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2005 /* Haswell */ 2006 { PCI_DEVICE(0x8086, 0x0a0c), 2007 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2008 { PCI_DEVICE(0x8086, 0x0c0c), 2009 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2010 { PCI_DEVICE(0x8086, 0x0d0c), 2011 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2012 /* Broadwell */ 2013 { PCI_DEVICE(0x8086, 0x160c), 2014 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2015 /* 5 Series/3400 */ 2016 { PCI_DEVICE(0x8086, 0x3b56), 2017 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2018 /* Poulsbo */ 2019 { PCI_DEVICE(0x8086, 0x811b), 2020 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2021 /* Oaktrail */ 2022 { PCI_DEVICE(0x8086, 0x080a), 2023 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2024 /* BayTrail */ 2025 { PCI_DEVICE(0x8086, 0x0f04), 2026 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2027 /* Braswell */ 2028 { PCI_DEVICE(0x8086, 0x2284), 2029 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2030 /* ICH */ 2031 { PCI_DEVICE(0x8086, 0x2668), 2032 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2033 AZX_DCAPS_BUFSIZE }, /* ICH6 */ 2034 { PCI_DEVICE(0x8086, 0x27d8), 2035 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2036 AZX_DCAPS_BUFSIZE }, /* ICH7 */ 2037 { PCI_DEVICE(0x8086, 0x269a), 2038 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2039 AZX_DCAPS_BUFSIZE }, /* ESB2 */ 2040 { PCI_DEVICE(0x8086, 0x284b), 2041 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2042 AZX_DCAPS_BUFSIZE }, /* ICH8 */ 2043 { PCI_DEVICE(0x8086, 0x293e), 2044 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2045 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 2046 { PCI_DEVICE(0x8086, 0x293f), 2047 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2048 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 2049 { PCI_DEVICE(0x8086, 0x3a3e), 2050 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2051 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 2052 { PCI_DEVICE(0x8086, 0x3a6e), 2053 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2054 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 2055 /* Generic Intel */ 2056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2057 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2058 .class_mask = 0xffffff, 2059 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE }, 2060 /* ATI SB 450/600/700/800/900 */ 2061 { PCI_DEVICE(0x1002, 0x437b), 2062 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2063 { PCI_DEVICE(0x1002, 0x4383), 2064 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2065 /* AMD Hudson */ 2066 { PCI_DEVICE(0x1022, 0x780d), 2067 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2068 /* ATI HDMI */ 2069 { PCI_DEVICE(0x1002, 0x793b), 2070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2071 { PCI_DEVICE(0x1002, 0x7919), 2072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2073 { PCI_DEVICE(0x1002, 0x960f), 2074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2075 { PCI_DEVICE(0x1002, 0x970f), 2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2077 { PCI_DEVICE(0x1002, 0xaa00), 2078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2079 { PCI_DEVICE(0x1002, 0xaa08), 2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2081 { PCI_DEVICE(0x1002, 0xaa10), 2082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2083 { PCI_DEVICE(0x1002, 0xaa18), 2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2085 { PCI_DEVICE(0x1002, 0xaa20), 2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2087 { PCI_DEVICE(0x1002, 0xaa28), 2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2089 { PCI_DEVICE(0x1002, 0xaa30), 2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2091 { PCI_DEVICE(0x1002, 0xaa38), 2092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2093 { PCI_DEVICE(0x1002, 0xaa40), 2094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2095 { PCI_DEVICE(0x1002, 0xaa48), 2096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2097 { PCI_DEVICE(0x1002, 0xaa50), 2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2099 { PCI_DEVICE(0x1002, 0xaa58), 2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2101 { PCI_DEVICE(0x1002, 0xaa60), 2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2103 { PCI_DEVICE(0x1002, 0xaa68), 2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2105 { PCI_DEVICE(0x1002, 0xaa80), 2106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2107 { PCI_DEVICE(0x1002, 0xaa88), 2108 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2109 { PCI_DEVICE(0x1002, 0xaa90), 2110 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2111 { PCI_DEVICE(0x1002, 0xaa98), 2112 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2113 { PCI_DEVICE(0x1002, 0x9902), 2114 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 2115 { PCI_DEVICE(0x1002, 0xaaa0), 2116 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 2117 { PCI_DEVICE(0x1002, 0xaaa8), 2118 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 2119 { PCI_DEVICE(0x1002, 0xaab0), 2120 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 2121 /* VIA VT8251/VT8237A */ 2122 { PCI_DEVICE(0x1106, 0x3288), 2123 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 2124 /* VIA GFX VT7122/VX900 */ 2125 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2126 /* VIA GFX VT6122/VX11 */ 2127 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2128 /* SIS966 */ 2129 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2130 /* ULI M5461 */ 2131 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2132 /* NVIDIA MCP */ 2133 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2134 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2135 .class_mask = 0xffffff, 2136 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2137 /* Teradici */ 2138 { PCI_DEVICE(0x6549, 0x1200), 2139 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2140 { PCI_DEVICE(0x6549, 0x2200), 2141 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2142 /* Creative X-Fi (CA0110-IBG) */ 2143 /* CTHDA chips */ 2144 { PCI_DEVICE(0x1102, 0x0010), 2145 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2146 { PCI_DEVICE(0x1102, 0x0012), 2147 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2148 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2149 /* the following entry conflicts with snd-ctxfi driver, 2150 * as ctxfi driver mutates from HD-audio to native mode with 2151 * a special command sequence. 2152 */ 2153 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2154 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2155 .class_mask = 0xffffff, 2156 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2157 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2158 #else 2159 /* this entry seems still valid -- i.e. without emu20kx chip */ 2160 { PCI_DEVICE(0x1102, 0x0009), 2161 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2162 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2163 #endif 2164 /* CM8888 */ 2165 { PCI_DEVICE(0x13f6, 0x5011), 2166 .driver_data = AZX_DRIVER_CMEDIA | 2167 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB }, 2168 /* Vortex86MX */ 2169 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2170 /* VMware HDAudio */ 2171 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2172 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2173 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2174 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2175 .class_mask = 0xffffff, 2176 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2177 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2178 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2179 .class_mask = 0xffffff, 2180 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2181 { 0, } 2182 }; 2183 MODULE_DEVICE_TABLE(pci, azx_ids); 2184 2185 /* pci_driver definition */ 2186 static struct pci_driver azx_driver = { 2187 .name = KBUILD_MODNAME, 2188 .id_table = azx_ids, 2189 .probe = azx_probe, 2190 .remove = azx_remove, 2191 .driver = { 2192 .pm = AZX_PM_OPS, 2193 }, 2194 }; 2195 2196 module_pci_driver(azx_driver); 2197