1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 39 #ifdef CONFIG_X86 40 /* for snoop control */ 41 #include <asm/pgtable.h> 42 #include <asm/set_memory.h> 43 #include <asm/cpufeature.h> 44 #endif 45 #include <sound/core.h> 46 #include <sound/initval.h> 47 #include <sound/hdaudio.h> 48 #include <sound/hda_i915.h> 49 #include <sound/intel-dsp-config.h> 50 #include <linux/vgaarb.h> 51 #include <linux/vga_switcheroo.h> 52 #include <linux/firmware.h> 53 #include <sound/hda_codec.h> 54 #include "hda_controller.h" 55 #include "hda_intel.h" 56 57 #define CREATE_TRACE_POINTS 58 #include "hda_intel_trace.h" 59 60 /* position fix mode */ 61 enum { 62 POS_FIX_AUTO, 63 POS_FIX_LPIB, 64 POS_FIX_POSBUF, 65 POS_FIX_VIACOMBO, 66 POS_FIX_COMBO, 67 POS_FIX_SKL, 68 POS_FIX_FIFO, 69 }; 70 71 /* Defines for ATI HD Audio support in SB450 south bridge */ 72 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 73 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 74 75 /* Defines for Nvidia HDA support */ 76 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 77 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 78 #define NVIDIA_HDA_ISTRM_COH 0x4d 79 #define NVIDIA_HDA_OSTRM_COH 0x4c 80 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 81 82 /* Defines for Intel SCH HDA snoop control */ 83 #define INTEL_HDA_CGCTL 0x48 84 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 85 #define INTEL_SCH_HDA_DEVC 0x78 86 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 87 88 /* Define VIA HD Audio Device ID*/ 89 #define VIA_HDAC_DEVICE_ID 0x3288 90 91 /* max number of SDs */ 92 /* ICH, ATI and VIA have 4 playback and 4 capture */ 93 #define ICH6_NUM_CAPTURE 4 94 #define ICH6_NUM_PLAYBACK 4 95 96 /* ULI has 6 playback and 5 capture */ 97 #define ULI_NUM_CAPTURE 5 98 #define ULI_NUM_PLAYBACK 6 99 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 101 #define ATIHDMI_NUM_CAPTURE 0 102 #define ATIHDMI_NUM_PLAYBACK 8 103 104 /* TERA has 4 playback and 3 capture */ 105 #define TERA_NUM_CAPTURE 3 106 #define TERA_NUM_PLAYBACK 4 107 108 109 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 110 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 111 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 112 static char *model[SNDRV_CARDS]; 113 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 114 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_only[SNDRV_CARDS]; 117 static int jackpoll_ms[SNDRV_CARDS]; 118 static int single_cmd = -1; 119 static int enable_msi = -1; 120 #ifdef CONFIG_SND_HDA_PATCH_LOADER 121 static char *patch[SNDRV_CARDS]; 122 #endif 123 #ifdef CONFIG_SND_HDA_INPUT_BEEP 124 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 125 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 126 #endif 127 static bool dsp_driver = 1; 128 129 module_param_array(index, int, NULL, 0444); 130 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 131 module_param_array(id, charp, NULL, 0444); 132 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 133 module_param_array(enable, bool, NULL, 0444); 134 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 135 module_param_array(model, charp, NULL, 0444); 136 MODULE_PARM_DESC(model, "Use the given board model."); 137 module_param_array(position_fix, int, NULL, 0444); 138 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 139 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 140 module_param_array(bdl_pos_adj, int, NULL, 0644); 141 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 142 module_param_array(probe_mask, int, NULL, 0444); 143 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 144 module_param_array(probe_only, int, NULL, 0444); 145 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 146 module_param_array(jackpoll_ms, int, NULL, 0444); 147 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 148 module_param(single_cmd, bint, 0444); 149 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 150 "(for debugging only)."); 151 module_param(enable_msi, bint, 0444); 152 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 153 #ifdef CONFIG_SND_HDA_PATCH_LOADER 154 module_param_array(patch, charp, NULL, 0444); 155 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 156 #endif 157 #ifdef CONFIG_SND_HDA_INPUT_BEEP 158 module_param_array(beep_mode, bool, NULL, 0444); 159 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 160 "(0=off, 1=on) (default=1)."); 161 #endif 162 module_param(dsp_driver, bool, 0444); 163 MODULE_PARM_DESC(dsp_driver, "Allow DSP driver selection (bypass this driver) " 164 "(0=off, 1=on) (default=1)"); 165 166 #ifdef CONFIG_PM 167 static int param_set_xint(const char *val, const struct kernel_param *kp); 168 static const struct kernel_param_ops param_ops_xint = { 169 .set = param_set_xint, 170 .get = param_get_int, 171 }; 172 #define param_check_xint param_check_int 173 174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 175 module_param(power_save, xint, 0644); 176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 177 "(in second, 0 = disable)."); 178 179 static bool pm_blacklist = true; 180 module_param(pm_blacklist, bool, 0644); 181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 182 183 /* reset the HD-audio controller in power save mode. 184 * this may give more power-saving, but will take longer time to 185 * wake up. 186 */ 187 static bool power_save_controller = 1; 188 module_param(power_save_controller, bool, 0644); 189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 190 #else 191 #define power_save 0 192 #endif /* CONFIG_PM */ 193 194 static int align_buffer_size = -1; 195 module_param(align_buffer_size, bint, 0644); 196 MODULE_PARM_DESC(align_buffer_size, 197 "Force buffer and period sizes to be multiple of 128 bytes."); 198 199 #ifdef CONFIG_X86 200 static int hda_snoop = -1; 201 module_param_named(snoop, hda_snoop, bint, 0444); 202 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 203 #else 204 #define hda_snoop true 205 #endif 206 207 208 MODULE_LICENSE("GPL"); 209 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 210 "{Intel, ICH6M}," 211 "{Intel, ICH7}," 212 "{Intel, ESB2}," 213 "{Intel, ICH8}," 214 "{Intel, ICH9}," 215 "{Intel, ICH10}," 216 "{Intel, PCH}," 217 "{Intel, CPT}," 218 "{Intel, PPT}," 219 "{Intel, LPT}," 220 "{Intel, LPT_LP}," 221 "{Intel, WPT_LP}," 222 "{Intel, SPT}," 223 "{Intel, SPT_LP}," 224 "{Intel, HPT}," 225 "{Intel, PBG}," 226 "{Intel, SCH}," 227 "{ATI, SB450}," 228 "{ATI, SB600}," 229 "{ATI, RS600}," 230 "{ATI, RS690}," 231 "{ATI, RS780}," 232 "{ATI, R600}," 233 "{ATI, RV630}," 234 "{ATI, RV610}," 235 "{ATI, RV670}," 236 "{ATI, RV635}," 237 "{ATI, RV620}," 238 "{ATI, RV770}," 239 "{VIA, VT8251}," 240 "{VIA, VT8237A}," 241 "{SiS, SIS966}," 242 "{ULI, M5461}}"); 243 MODULE_DESCRIPTION("Intel HDA driver"); 244 245 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 246 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 247 #define SUPPORT_VGA_SWITCHEROO 248 #endif 249 #endif 250 251 252 /* 253 */ 254 255 /* driver types */ 256 enum { 257 AZX_DRIVER_ICH, 258 AZX_DRIVER_PCH, 259 AZX_DRIVER_SCH, 260 AZX_DRIVER_SKL, 261 AZX_DRIVER_HDMI, 262 AZX_DRIVER_ATI, 263 AZX_DRIVER_ATIHDMI, 264 AZX_DRIVER_ATIHDMI_NS, 265 AZX_DRIVER_VIA, 266 AZX_DRIVER_SIS, 267 AZX_DRIVER_ULI, 268 AZX_DRIVER_NVIDIA, 269 AZX_DRIVER_TERA, 270 AZX_DRIVER_CTX, 271 AZX_DRIVER_CTHDA, 272 AZX_DRIVER_CMEDIA, 273 AZX_DRIVER_ZHAOXIN, 274 AZX_DRIVER_GENERIC, 275 AZX_NUM_DRIVERS, /* keep this as last entry */ 276 }; 277 278 #define azx_get_snoop_type(chip) \ 279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 281 282 /* quirks for old Intel chipsets */ 283 #define AZX_DCAPS_INTEL_ICH \ 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 285 286 /* quirks for Intel PCH */ 287 #define AZX_DCAPS_INTEL_PCH_BASE \ 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 289 AZX_DCAPS_SNOOP_TYPE(SCH)) 290 291 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 292 #define AZX_DCAPS_INTEL_PCH_NOPM \ 293 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 294 295 /* PCH for HSW/BDW; with runtime PM */ 296 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 297 #define AZX_DCAPS_INTEL_PCH \ 298 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 299 300 /* HSW HDMI */ 301 #define AZX_DCAPS_INTEL_HASWELL \ 302 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 303 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 304 AZX_DCAPS_SNOOP_TYPE(SCH)) 305 306 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 307 #define AZX_DCAPS_INTEL_BROADWELL \ 308 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 309 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 310 AZX_DCAPS_SNOOP_TYPE(SCH)) 311 312 #define AZX_DCAPS_INTEL_BAYTRAIL \ 313 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 314 315 #define AZX_DCAPS_INTEL_BRASWELL \ 316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 317 AZX_DCAPS_I915_COMPONENT) 318 319 #define AZX_DCAPS_INTEL_SKYLAKE \ 320 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 321 AZX_DCAPS_SYNC_WRITE |\ 322 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 323 324 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 325 326 /* quirks for ATI SB / AMD Hudson */ 327 #define AZX_DCAPS_PRESET_ATI_SB \ 328 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 329 AZX_DCAPS_SNOOP_TYPE(ATI)) 330 331 /* quirks for ATI/AMD HDMI */ 332 #define AZX_DCAPS_PRESET_ATI_HDMI \ 333 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 334 AZX_DCAPS_NO_MSI64) 335 336 /* quirks for ATI HDMI with snoop off */ 337 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 338 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 339 340 /* quirks for AMD SB */ 341 #define AZX_DCAPS_PRESET_AMD_SB \ 342 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\ 343 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) 344 345 /* quirks for Nvidia */ 346 #define AZX_DCAPS_PRESET_NVIDIA \ 347 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 348 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 349 350 #define AZX_DCAPS_PRESET_CTHDA \ 351 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 352 AZX_DCAPS_NO_64BIT |\ 353 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 354 355 /* 356 * vga_switcheroo support 357 */ 358 #ifdef SUPPORT_VGA_SWITCHEROO 359 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 360 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 361 #else 362 #define use_vga_switcheroo(chip) 0 363 #define needs_eld_notify_link(chip) false 364 #endif 365 366 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 367 ((pci)->device == 0x0c0c) || \ 368 ((pci)->device == 0x0d0c) || \ 369 ((pci)->device == 0x160c)) 370 371 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 372 373 static char *driver_short_names[] = { 374 [AZX_DRIVER_ICH] = "HDA Intel", 375 [AZX_DRIVER_PCH] = "HDA Intel PCH", 376 [AZX_DRIVER_SCH] = "HDA Intel MID", 377 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 378 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 379 [AZX_DRIVER_ATI] = "HDA ATI SB", 380 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 381 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 382 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 383 [AZX_DRIVER_SIS] = "HDA SIS966", 384 [AZX_DRIVER_ULI] = "HDA ULI M5461", 385 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 386 [AZX_DRIVER_TERA] = "HDA Teradici", 387 [AZX_DRIVER_CTX] = "HDA Creative", 388 [AZX_DRIVER_CTHDA] = "HDA Creative", 389 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 390 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 391 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 392 }; 393 394 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 395 static void set_default_power_save(struct azx *chip); 396 397 /* 398 * initialize the PCI registers 399 */ 400 /* update bits in a PCI register byte */ 401 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 402 unsigned char mask, unsigned char val) 403 { 404 unsigned char data; 405 406 pci_read_config_byte(pci, reg, &data); 407 data &= ~mask; 408 data |= (val & mask); 409 pci_write_config_byte(pci, reg, data); 410 } 411 412 static void azx_init_pci(struct azx *chip) 413 { 414 int snoop_type = azx_get_snoop_type(chip); 415 416 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 417 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 418 * Ensuring these bits are 0 clears playback static on some HD Audio 419 * codecs. 420 * The PCI register TCSEL is defined in the Intel manuals. 421 */ 422 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 423 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 424 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 425 } 426 427 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 428 * we need to enable snoop. 429 */ 430 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 431 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 432 azx_snoop(chip)); 433 update_pci_byte(chip->pci, 434 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 435 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 436 } 437 438 /* For NVIDIA HDA, enable snoop */ 439 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 440 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 441 azx_snoop(chip)); 442 update_pci_byte(chip->pci, 443 NVIDIA_HDA_TRANSREG_ADDR, 444 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 445 update_pci_byte(chip->pci, 446 NVIDIA_HDA_ISTRM_COH, 447 0x01, NVIDIA_HDA_ENABLE_COHBIT); 448 update_pci_byte(chip->pci, 449 NVIDIA_HDA_OSTRM_COH, 450 0x01, NVIDIA_HDA_ENABLE_COHBIT); 451 } 452 453 /* Enable SCH/PCH snoop if needed */ 454 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 455 unsigned short snoop; 456 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 457 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 458 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 459 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 460 if (!azx_snoop(chip)) 461 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 462 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 463 pci_read_config_word(chip->pci, 464 INTEL_SCH_HDA_DEVC, &snoop); 465 } 466 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 467 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 468 "Disabled" : "Enabled"); 469 } 470 } 471 472 /* 473 * In BXT-P A0, HD-Audio DMA requests is later than expected, 474 * and makes an audio stream sensitive to system latencies when 475 * 24/32 bits are playing. 476 * Adjusting threshold of DMA fifo to force the DMA request 477 * sooner to improve latency tolerance at the expense of power. 478 */ 479 static void bxt_reduce_dma_latency(struct azx *chip) 480 { 481 u32 val; 482 483 val = azx_readl(chip, VS_EM4L); 484 val &= (0x3 << 20); 485 azx_writel(chip, VS_EM4L, val); 486 } 487 488 /* 489 * ML_LCAP bits: 490 * bit 0: 6 MHz Supported 491 * bit 1: 12 MHz Supported 492 * bit 2: 24 MHz Supported 493 * bit 3: 48 MHz Supported 494 * bit 4: 96 MHz Supported 495 * bit 5: 192 MHz Supported 496 */ 497 static int intel_get_lctl_scf(struct azx *chip) 498 { 499 struct hdac_bus *bus = azx_bus(chip); 500 static int preferred_bits[] = { 2, 3, 1, 4, 5 }; 501 u32 val, t; 502 int i; 503 504 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 505 506 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 507 t = preferred_bits[i]; 508 if (val & (1 << t)) 509 return t; 510 } 511 512 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 513 return 0; 514 } 515 516 static int intel_ml_lctl_set_power(struct azx *chip, int state) 517 { 518 struct hdac_bus *bus = azx_bus(chip); 519 u32 val; 520 int timeout; 521 522 /* 523 * the codecs are sharing the first link setting by default 524 * If other links are enabled for stream, they need similar fix 525 */ 526 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 527 val &= ~AZX_MLCTL_SPA; 528 val |= state << AZX_MLCTL_SPA_SHIFT; 529 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 530 /* wait for CPA */ 531 timeout = 50; 532 while (timeout) { 533 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 534 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 535 return 0; 536 timeout--; 537 udelay(10); 538 } 539 540 return -1; 541 } 542 543 static void intel_init_lctl(struct azx *chip) 544 { 545 struct hdac_bus *bus = azx_bus(chip); 546 u32 val; 547 int ret; 548 549 /* 0. check lctl register value is correct or not */ 550 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 551 /* if SCF is already set, let's use it */ 552 if ((val & ML_LCTL_SCF_MASK) != 0) 553 return; 554 555 /* 556 * Before operating on SPA, CPA must match SPA. 557 * Any deviation may result in undefined behavior. 558 */ 559 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 560 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 561 return; 562 563 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 564 ret = intel_ml_lctl_set_power(chip, 0); 565 udelay(100); 566 if (ret) 567 goto set_spa; 568 569 /* 2. update SCF to select a properly audio clock*/ 570 val &= ~ML_LCTL_SCF_MASK; 571 val |= intel_get_lctl_scf(chip); 572 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 573 574 set_spa: 575 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 576 intel_ml_lctl_set_power(chip, 1); 577 udelay(100); 578 } 579 580 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 581 { 582 struct hdac_bus *bus = azx_bus(chip); 583 struct pci_dev *pci = chip->pci; 584 u32 val; 585 586 snd_hdac_set_codec_wakeup(bus, true); 587 if (chip->driver_type == AZX_DRIVER_SKL) { 588 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 589 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 590 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 591 } 592 azx_init_chip(chip, full_reset); 593 if (chip->driver_type == AZX_DRIVER_SKL) { 594 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 595 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 596 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 597 } 598 599 snd_hdac_set_codec_wakeup(bus, false); 600 601 /* reduce dma latency to avoid noise */ 602 if (IS_BXT(pci)) 603 bxt_reduce_dma_latency(chip); 604 605 if (bus->mlcap != NULL) 606 intel_init_lctl(chip); 607 } 608 609 /* calculate runtime delay from LPIB */ 610 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 611 unsigned int pos) 612 { 613 struct snd_pcm_substream *substream = azx_dev->core.substream; 614 int stream = substream->stream; 615 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 616 int delay; 617 618 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 619 delay = pos - lpib_pos; 620 else 621 delay = lpib_pos - pos; 622 if (delay < 0) { 623 if (delay >= azx_dev->core.delay_negative_threshold) 624 delay = 0; 625 else 626 delay += azx_dev->core.bufsize; 627 } 628 629 if (delay >= azx_dev->core.period_bytes) { 630 dev_info(chip->card->dev, 631 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 632 delay, azx_dev->core.period_bytes); 633 delay = 0; 634 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 635 chip->get_delay[stream] = NULL; 636 } 637 638 return bytes_to_frames(substream->runtime, delay); 639 } 640 641 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 642 643 /* called from IRQ */ 644 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 645 { 646 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 647 int ok; 648 649 ok = azx_position_ok(chip, azx_dev); 650 if (ok == 1) { 651 azx_dev->irq_pending = 0; 652 return ok; 653 } else if (ok == 0) { 654 /* bogus IRQ, process it later */ 655 azx_dev->irq_pending = 1; 656 schedule_work(&hda->irq_pending_work); 657 } 658 return 0; 659 } 660 661 #define display_power(chip, enable) \ 662 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 663 664 /* 665 * Check whether the current DMA position is acceptable for updating 666 * periods. Returns non-zero if it's OK. 667 * 668 * Many HD-audio controllers appear pretty inaccurate about 669 * the update-IRQ timing. The IRQ is issued before actually the 670 * data is processed. So, we need to process it afterwords in a 671 * workqueue. 672 */ 673 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 674 { 675 struct snd_pcm_substream *substream = azx_dev->core.substream; 676 int stream = substream->stream; 677 u32 wallclk; 678 unsigned int pos; 679 680 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 681 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 682 return -1; /* bogus (too early) interrupt */ 683 684 if (chip->get_position[stream]) 685 pos = chip->get_position[stream](chip, azx_dev); 686 else { /* use the position buffer as default */ 687 pos = azx_get_pos_posbuf(chip, azx_dev); 688 if (!pos || pos == (u32)-1) { 689 dev_info(chip->card->dev, 690 "Invalid position buffer, using LPIB read method instead.\n"); 691 chip->get_position[stream] = azx_get_pos_lpib; 692 if (chip->get_position[0] == azx_get_pos_lpib && 693 chip->get_position[1] == azx_get_pos_lpib) 694 azx_bus(chip)->use_posbuf = false; 695 pos = azx_get_pos_lpib(chip, azx_dev); 696 chip->get_delay[stream] = NULL; 697 } else { 698 chip->get_position[stream] = azx_get_pos_posbuf; 699 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 700 chip->get_delay[stream] = azx_get_delay_from_lpib; 701 } 702 } 703 704 if (pos >= azx_dev->core.bufsize) 705 pos = 0; 706 707 if (WARN_ONCE(!azx_dev->core.period_bytes, 708 "hda-intel: zero azx_dev->period_bytes")) 709 return -1; /* this shouldn't happen! */ 710 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 711 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 712 /* NG - it's below the first next period boundary */ 713 return chip->bdl_pos_adj ? 0 : -1; 714 azx_dev->core.start_wallclk += wallclk; 715 return 1; /* OK, it's fine */ 716 } 717 718 /* 719 * The work for pending PCM period updates. 720 */ 721 static void azx_irq_pending_work(struct work_struct *work) 722 { 723 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 724 struct azx *chip = &hda->chip; 725 struct hdac_bus *bus = azx_bus(chip); 726 struct hdac_stream *s; 727 int pending, ok; 728 729 if (!hda->irq_pending_warned) { 730 dev_info(chip->card->dev, 731 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 732 chip->card->number); 733 hda->irq_pending_warned = 1; 734 } 735 736 for (;;) { 737 pending = 0; 738 spin_lock_irq(&bus->reg_lock); 739 list_for_each_entry(s, &bus->stream_list, list) { 740 struct azx_dev *azx_dev = stream_to_azx_dev(s); 741 if (!azx_dev->irq_pending || 742 !s->substream || 743 !s->running) 744 continue; 745 ok = azx_position_ok(chip, azx_dev); 746 if (ok > 0) { 747 azx_dev->irq_pending = 0; 748 spin_unlock(&bus->reg_lock); 749 snd_pcm_period_elapsed(s->substream); 750 spin_lock(&bus->reg_lock); 751 } else if (ok < 0) { 752 pending = 0; /* too early */ 753 } else 754 pending++; 755 } 756 spin_unlock_irq(&bus->reg_lock); 757 if (!pending) 758 return; 759 msleep(1); 760 } 761 } 762 763 /* clear irq_pending flags and assure no on-going workq */ 764 static void azx_clear_irq_pending(struct azx *chip) 765 { 766 struct hdac_bus *bus = azx_bus(chip); 767 struct hdac_stream *s; 768 769 spin_lock_irq(&bus->reg_lock); 770 list_for_each_entry(s, &bus->stream_list, list) { 771 struct azx_dev *azx_dev = stream_to_azx_dev(s); 772 azx_dev->irq_pending = 0; 773 } 774 spin_unlock_irq(&bus->reg_lock); 775 } 776 777 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 778 { 779 struct hdac_bus *bus = azx_bus(chip); 780 781 if (request_irq(chip->pci->irq, azx_interrupt, 782 chip->msi ? 0 : IRQF_SHARED, 783 chip->card->irq_descr, chip)) { 784 dev_err(chip->card->dev, 785 "unable to grab IRQ %d, disabling device\n", 786 chip->pci->irq); 787 if (do_disconnect) 788 snd_card_disconnect(chip->card); 789 return -1; 790 } 791 bus->irq = chip->pci->irq; 792 pci_intx(chip->pci, !chip->msi); 793 return 0; 794 } 795 796 /* get the current DMA position with correction on VIA chips */ 797 static unsigned int azx_via_get_position(struct azx *chip, 798 struct azx_dev *azx_dev) 799 { 800 unsigned int link_pos, mini_pos, bound_pos; 801 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 802 unsigned int fifo_size; 803 804 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 805 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 806 /* Playback, no problem using link position */ 807 return link_pos; 808 } 809 810 /* Capture */ 811 /* For new chipset, 812 * use mod to get the DMA position just like old chipset 813 */ 814 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 815 mod_dma_pos %= azx_dev->core.period_bytes; 816 817 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 818 819 if (azx_dev->insufficient) { 820 /* Link position never gather than FIFO size */ 821 if (link_pos <= fifo_size) 822 return 0; 823 824 azx_dev->insufficient = 0; 825 } 826 827 if (link_pos <= fifo_size) 828 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 829 else 830 mini_pos = link_pos - fifo_size; 831 832 /* Find nearest previous boudary */ 833 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 834 mod_link_pos = link_pos % azx_dev->core.period_bytes; 835 if (mod_link_pos >= fifo_size) 836 bound_pos = link_pos - mod_link_pos; 837 else if (mod_dma_pos >= mod_mini_pos) 838 bound_pos = mini_pos - mod_mini_pos; 839 else { 840 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 841 if (bound_pos >= azx_dev->core.bufsize) 842 bound_pos = 0; 843 } 844 845 /* Calculate real DMA position we want */ 846 return bound_pos + mod_dma_pos; 847 } 848 849 #define AMD_FIFO_SIZE 32 850 851 /* get the current DMA position with FIFO size correction */ 852 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 853 { 854 struct snd_pcm_substream *substream = azx_dev->core.substream; 855 struct snd_pcm_runtime *runtime = substream->runtime; 856 unsigned int pos, delay; 857 858 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 859 if (!runtime) 860 return pos; 861 862 runtime->delay = AMD_FIFO_SIZE; 863 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 864 if (azx_dev->insufficient) { 865 if (pos < delay) { 866 delay = pos; 867 runtime->delay = bytes_to_frames(runtime, pos); 868 } else { 869 azx_dev->insufficient = 0; 870 } 871 } 872 873 /* correct the DMA position for capture stream */ 874 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 875 if (pos < delay) 876 pos += azx_dev->core.bufsize; 877 pos -= delay; 878 } 879 880 return pos; 881 } 882 883 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 884 unsigned int pos) 885 { 886 struct snd_pcm_substream *substream = azx_dev->core.substream; 887 888 /* just read back the calculated value in the above */ 889 return substream->runtime->delay; 890 } 891 892 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 893 struct azx_dev *azx_dev) 894 { 895 return _snd_hdac_chip_readl(azx_bus(chip), 896 AZX_REG_VS_SDXDPIB_XBASE + 897 (AZX_REG_VS_SDXDPIB_XINTERVAL * 898 azx_dev->core.index)); 899 } 900 901 /* get the current DMA position with correction on SKL+ chips */ 902 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 903 { 904 /* DPIB register gives a more accurate position for playback */ 905 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 906 return azx_skl_get_dpib_pos(chip, azx_dev); 907 908 /* For capture, we need to read posbuf, but it requires a delay 909 * for the possible boundary overlap; the read of DPIB fetches the 910 * actual posbuf 911 */ 912 udelay(20); 913 azx_skl_get_dpib_pos(chip, azx_dev); 914 return azx_get_pos_posbuf(chip, azx_dev); 915 } 916 917 #ifdef CONFIG_PM 918 static DEFINE_MUTEX(card_list_lock); 919 static LIST_HEAD(card_list); 920 921 static void azx_add_card_list(struct azx *chip) 922 { 923 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 924 mutex_lock(&card_list_lock); 925 list_add(&hda->list, &card_list); 926 mutex_unlock(&card_list_lock); 927 } 928 929 static void azx_del_card_list(struct azx *chip) 930 { 931 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 932 mutex_lock(&card_list_lock); 933 list_del_init(&hda->list); 934 mutex_unlock(&card_list_lock); 935 } 936 937 /* trigger power-save check at writing parameter */ 938 static int param_set_xint(const char *val, const struct kernel_param *kp) 939 { 940 struct hda_intel *hda; 941 struct azx *chip; 942 int prev = power_save; 943 int ret = param_set_int(val, kp); 944 945 if (ret || prev == power_save) 946 return ret; 947 948 mutex_lock(&card_list_lock); 949 list_for_each_entry(hda, &card_list, list) { 950 chip = &hda->chip; 951 if (!hda->probe_continued || chip->disabled) 952 continue; 953 snd_hda_set_power_save(&chip->bus, power_save * 1000); 954 } 955 mutex_unlock(&card_list_lock); 956 return 0; 957 } 958 959 /* 960 * power management 961 */ 962 static bool azx_is_pm_ready(struct snd_card *card) 963 { 964 struct azx *chip; 965 struct hda_intel *hda; 966 967 if (!card) 968 return false; 969 chip = card->private_data; 970 hda = container_of(chip, struct hda_intel, chip); 971 if (chip->disabled || hda->init_failed || !chip->running) 972 return false; 973 return true; 974 } 975 976 static void __azx_runtime_suspend(struct azx *chip) 977 { 978 azx_stop_chip(chip); 979 azx_enter_link_reset(chip); 980 azx_clear_irq_pending(chip); 981 display_power(chip, false); 982 } 983 984 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 985 { 986 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 987 struct hdac_bus *bus = azx_bus(chip); 988 struct hda_codec *codec; 989 int status; 990 991 display_power(chip, true); 992 if (hda->need_i915_power) 993 snd_hdac_i915_set_bclk(bus); 994 995 /* Read STATESTS before controller reset */ 996 status = azx_readw(chip, STATESTS); 997 998 azx_init_pci(chip); 999 hda_intel_init_chip(chip, true); 1000 1001 if (status && from_rt) { 1002 list_for_each_codec(codec, &chip->bus) 1003 if (status & (1 << codec->addr)) 1004 schedule_delayed_work(&codec->jackpoll_work, 1005 codec->jackpoll_interval); 1006 } 1007 1008 /* power down again for link-controlled chips */ 1009 if (!hda->need_i915_power) 1010 display_power(chip, false); 1011 } 1012 1013 #ifdef CONFIG_PM_SLEEP 1014 static int azx_suspend(struct device *dev) 1015 { 1016 struct snd_card *card = dev_get_drvdata(dev); 1017 struct azx *chip; 1018 struct hdac_bus *bus; 1019 1020 if (!azx_is_pm_ready(card)) 1021 return 0; 1022 1023 chip = card->private_data; 1024 bus = azx_bus(chip); 1025 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1026 __azx_runtime_suspend(chip); 1027 if (bus->irq >= 0) { 1028 free_irq(bus->irq, chip); 1029 bus->irq = -1; 1030 } 1031 1032 if (chip->msi) 1033 pci_disable_msi(chip->pci); 1034 1035 trace_azx_suspend(chip); 1036 return 0; 1037 } 1038 1039 static int azx_resume(struct device *dev) 1040 { 1041 struct snd_card *card = dev_get_drvdata(dev); 1042 struct azx *chip; 1043 1044 if (!azx_is_pm_ready(card)) 1045 return 0; 1046 1047 chip = card->private_data; 1048 if (chip->msi) 1049 if (pci_enable_msi(chip->pci) < 0) 1050 chip->msi = 0; 1051 if (azx_acquire_irq(chip, 1) < 0) 1052 return -EIO; 1053 __azx_runtime_resume(chip, false); 1054 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1055 1056 trace_azx_resume(chip); 1057 return 0; 1058 } 1059 1060 /* put codec down to D3 at hibernation for Intel SKL+; 1061 * otherwise BIOS may still access the codec and screw up the driver 1062 */ 1063 static int azx_freeze_noirq(struct device *dev) 1064 { 1065 struct snd_card *card = dev_get_drvdata(dev); 1066 struct azx *chip = card->private_data; 1067 struct pci_dev *pci = to_pci_dev(dev); 1068 1069 if (chip->driver_type == AZX_DRIVER_SKL) 1070 pci_set_power_state(pci, PCI_D3hot); 1071 1072 return 0; 1073 } 1074 1075 static int azx_thaw_noirq(struct device *dev) 1076 { 1077 struct snd_card *card = dev_get_drvdata(dev); 1078 struct azx *chip = card->private_data; 1079 struct pci_dev *pci = to_pci_dev(dev); 1080 1081 if (chip->driver_type == AZX_DRIVER_SKL) 1082 pci_set_power_state(pci, PCI_D0); 1083 1084 return 0; 1085 } 1086 #endif /* CONFIG_PM_SLEEP */ 1087 1088 static int azx_runtime_suspend(struct device *dev) 1089 { 1090 struct snd_card *card = dev_get_drvdata(dev); 1091 struct azx *chip; 1092 1093 if (!azx_is_pm_ready(card)) 1094 return 0; 1095 chip = card->private_data; 1096 if (!azx_has_pm_runtime(chip)) 1097 return 0; 1098 1099 /* enable controller wake up event */ 1100 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1101 STATESTS_INT_MASK); 1102 1103 __azx_runtime_suspend(chip); 1104 trace_azx_runtime_suspend(chip); 1105 return 0; 1106 } 1107 1108 static int azx_runtime_resume(struct device *dev) 1109 { 1110 struct snd_card *card = dev_get_drvdata(dev); 1111 struct azx *chip; 1112 1113 if (!azx_is_pm_ready(card)) 1114 return 0; 1115 chip = card->private_data; 1116 if (!azx_has_pm_runtime(chip)) 1117 return 0; 1118 __azx_runtime_resume(chip, true); 1119 1120 /* disable controller Wake Up event*/ 1121 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1122 ~STATESTS_INT_MASK); 1123 1124 trace_azx_runtime_resume(chip); 1125 return 0; 1126 } 1127 1128 static int azx_runtime_idle(struct device *dev) 1129 { 1130 struct snd_card *card = dev_get_drvdata(dev); 1131 struct azx *chip; 1132 struct hda_intel *hda; 1133 1134 if (!card) 1135 return 0; 1136 1137 chip = card->private_data; 1138 hda = container_of(chip, struct hda_intel, chip); 1139 if (chip->disabled || hda->init_failed) 1140 return 0; 1141 1142 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1143 azx_bus(chip)->codec_powered || !chip->running) 1144 return -EBUSY; 1145 1146 /* ELD notification gets broken when HD-audio bus is off */ 1147 if (needs_eld_notify_link(chip)) 1148 return -EBUSY; 1149 1150 return 0; 1151 } 1152 1153 static const struct dev_pm_ops azx_pm = { 1154 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1155 #ifdef CONFIG_PM_SLEEP 1156 .freeze_noirq = azx_freeze_noirq, 1157 .thaw_noirq = azx_thaw_noirq, 1158 #endif 1159 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1160 }; 1161 1162 #define AZX_PM_OPS &azx_pm 1163 #else 1164 #define azx_add_card_list(chip) /* NOP */ 1165 #define azx_del_card_list(chip) /* NOP */ 1166 #define AZX_PM_OPS NULL 1167 #endif /* CONFIG_PM */ 1168 1169 1170 static int azx_probe_continue(struct azx *chip); 1171 1172 #ifdef SUPPORT_VGA_SWITCHEROO 1173 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1174 1175 static void azx_vs_set_state(struct pci_dev *pci, 1176 enum vga_switcheroo_state state) 1177 { 1178 struct snd_card *card = pci_get_drvdata(pci); 1179 struct azx *chip = card->private_data; 1180 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1181 struct hda_codec *codec; 1182 bool disabled; 1183 1184 wait_for_completion(&hda->probe_wait); 1185 if (hda->init_failed) 1186 return; 1187 1188 disabled = (state == VGA_SWITCHEROO_OFF); 1189 if (chip->disabled == disabled) 1190 return; 1191 1192 if (!hda->probe_continued) { 1193 chip->disabled = disabled; 1194 if (!disabled) { 1195 dev_info(chip->card->dev, 1196 "Start delayed initialization\n"); 1197 if (azx_probe_continue(chip) < 0) { 1198 dev_err(chip->card->dev, "initialization error\n"); 1199 hda->init_failed = true; 1200 } 1201 } 1202 } else { 1203 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1204 disabled ? "Disabling" : "Enabling"); 1205 if (disabled) { 1206 list_for_each_codec(codec, &chip->bus) { 1207 pm_runtime_suspend(hda_codec_dev(codec)); 1208 pm_runtime_disable(hda_codec_dev(codec)); 1209 } 1210 pm_runtime_suspend(card->dev); 1211 pm_runtime_disable(card->dev); 1212 /* when we get suspended by vga_switcheroo we end up in D3cold, 1213 * however we have no ACPI handle, so pci/acpi can't put us there, 1214 * put ourselves there */ 1215 pci->current_state = PCI_D3cold; 1216 chip->disabled = true; 1217 if (snd_hda_lock_devices(&chip->bus)) 1218 dev_warn(chip->card->dev, 1219 "Cannot lock devices!\n"); 1220 } else { 1221 snd_hda_unlock_devices(&chip->bus); 1222 chip->disabled = false; 1223 pm_runtime_enable(card->dev); 1224 list_for_each_codec(codec, &chip->bus) { 1225 pm_runtime_enable(hda_codec_dev(codec)); 1226 pm_runtime_resume(hda_codec_dev(codec)); 1227 } 1228 } 1229 } 1230 } 1231 1232 static bool azx_vs_can_switch(struct pci_dev *pci) 1233 { 1234 struct snd_card *card = pci_get_drvdata(pci); 1235 struct azx *chip = card->private_data; 1236 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1237 1238 wait_for_completion(&hda->probe_wait); 1239 if (hda->init_failed) 1240 return false; 1241 if (chip->disabled || !hda->probe_continued) 1242 return true; 1243 if (snd_hda_lock_devices(&chip->bus)) 1244 return false; 1245 snd_hda_unlock_devices(&chip->bus); 1246 return true; 1247 } 1248 1249 /* 1250 * The discrete GPU cannot power down unless the HDA controller runtime 1251 * suspends, so activate runtime PM on codecs even if power_save == 0. 1252 */ 1253 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1254 { 1255 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1256 struct hda_codec *codec; 1257 1258 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1259 list_for_each_codec(codec, &chip->bus) 1260 codec->auto_runtime_pm = 1; 1261 /* reset the power save setup */ 1262 if (chip->running) 1263 set_default_power_save(chip); 1264 } 1265 } 1266 1267 static void azx_vs_gpu_bound(struct pci_dev *pci, 1268 enum vga_switcheroo_client_id client_id) 1269 { 1270 struct snd_card *card = pci_get_drvdata(pci); 1271 struct azx *chip = card->private_data; 1272 1273 if (client_id == VGA_SWITCHEROO_DIS) 1274 chip->bus.keep_power = 0; 1275 setup_vga_switcheroo_runtime_pm(chip); 1276 } 1277 1278 static void init_vga_switcheroo(struct azx *chip) 1279 { 1280 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1281 struct pci_dev *p = get_bound_vga(chip->pci); 1282 struct pci_dev *parent; 1283 if (p) { 1284 dev_info(chip->card->dev, 1285 "Handle vga_switcheroo audio client\n"); 1286 hda->use_vga_switcheroo = 1; 1287 1288 /* cleared in either gpu_bound op or codec probe, or when its 1289 * upstream port has _PR3 (i.e. dGPU). 1290 */ 1291 parent = pci_upstream_bridge(p); 1292 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1293 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1294 pci_dev_put(p); 1295 } 1296 } 1297 1298 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1299 .set_gpu_state = azx_vs_set_state, 1300 .can_switch = azx_vs_can_switch, 1301 .gpu_bound = azx_vs_gpu_bound, 1302 }; 1303 1304 static int register_vga_switcheroo(struct azx *chip) 1305 { 1306 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1307 struct pci_dev *p; 1308 int err; 1309 1310 if (!hda->use_vga_switcheroo) 1311 return 0; 1312 1313 p = get_bound_vga(chip->pci); 1314 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1315 pci_dev_put(p); 1316 1317 if (err < 0) 1318 return err; 1319 hda->vga_switcheroo_registered = 1; 1320 1321 return 0; 1322 } 1323 #else 1324 #define init_vga_switcheroo(chip) /* NOP */ 1325 #define register_vga_switcheroo(chip) 0 1326 #define check_hdmi_disabled(pci) false 1327 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1328 #endif /* SUPPORT_VGA_SWITCHER */ 1329 1330 /* 1331 * destructor 1332 */ 1333 static int azx_free(struct azx *chip) 1334 { 1335 struct pci_dev *pci = chip->pci; 1336 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1337 struct hdac_bus *bus = azx_bus(chip); 1338 1339 if (azx_has_pm_runtime(chip) && chip->running) 1340 pm_runtime_get_noresume(&pci->dev); 1341 chip->running = 0; 1342 1343 azx_del_card_list(chip); 1344 1345 hda->init_failed = 1; /* to be sure */ 1346 complete_all(&hda->probe_wait); 1347 1348 if (use_vga_switcheroo(hda)) { 1349 if (chip->disabled && hda->probe_continued) 1350 snd_hda_unlock_devices(&chip->bus); 1351 if (hda->vga_switcheroo_registered) 1352 vga_switcheroo_unregister_client(chip->pci); 1353 } 1354 1355 if (bus->chip_init) { 1356 azx_clear_irq_pending(chip); 1357 azx_stop_all_streams(chip); 1358 azx_stop_chip(chip); 1359 } 1360 1361 if (bus->irq >= 0) 1362 free_irq(bus->irq, (void*)chip); 1363 if (chip->msi) 1364 pci_disable_msi(chip->pci); 1365 iounmap(bus->remap_addr); 1366 1367 azx_free_stream_pages(chip); 1368 azx_free_streams(chip); 1369 snd_hdac_bus_exit(bus); 1370 1371 if (chip->region_requested) 1372 pci_release_regions(chip->pci); 1373 1374 pci_disable_device(chip->pci); 1375 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1376 release_firmware(chip->fw); 1377 #endif 1378 display_power(chip, false); 1379 1380 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1381 snd_hdac_i915_exit(bus); 1382 kfree(hda); 1383 1384 return 0; 1385 } 1386 1387 static int azx_dev_disconnect(struct snd_device *device) 1388 { 1389 struct azx *chip = device->device_data; 1390 struct hdac_bus *bus = azx_bus(chip); 1391 1392 chip->bus.shutdown = 1; 1393 cancel_work_sync(&bus->unsol_work); 1394 1395 return 0; 1396 } 1397 1398 static int azx_dev_free(struct snd_device *device) 1399 { 1400 return azx_free(device->device_data); 1401 } 1402 1403 #ifdef SUPPORT_VGA_SWITCHEROO 1404 /* 1405 * Check of disabled HDMI controller by vga_switcheroo 1406 */ 1407 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1408 { 1409 struct pci_dev *p; 1410 1411 /* check only discrete GPU */ 1412 switch (pci->vendor) { 1413 case PCI_VENDOR_ID_ATI: 1414 case PCI_VENDOR_ID_AMD: 1415 case PCI_VENDOR_ID_NVIDIA: 1416 if (pci->devfn == 1) { 1417 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1418 pci->bus->number, 0); 1419 if (p) { 1420 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1421 return p; 1422 pci_dev_put(p); 1423 } 1424 } 1425 break; 1426 } 1427 return NULL; 1428 } 1429 1430 static bool check_hdmi_disabled(struct pci_dev *pci) 1431 { 1432 bool vga_inactive = false; 1433 struct pci_dev *p = get_bound_vga(pci); 1434 1435 if (p) { 1436 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1437 vga_inactive = true; 1438 pci_dev_put(p); 1439 } 1440 return vga_inactive; 1441 } 1442 #endif /* SUPPORT_VGA_SWITCHEROO */ 1443 1444 /* 1445 * white/black-listing for position_fix 1446 */ 1447 static struct snd_pci_quirk position_fix_list[] = { 1448 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1449 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1450 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1451 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1452 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1453 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1454 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1455 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1456 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1457 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1458 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1459 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1460 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1461 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1462 {} 1463 }; 1464 1465 static int check_position_fix(struct azx *chip, int fix) 1466 { 1467 const struct snd_pci_quirk *q; 1468 1469 switch (fix) { 1470 case POS_FIX_AUTO: 1471 case POS_FIX_LPIB: 1472 case POS_FIX_POSBUF: 1473 case POS_FIX_VIACOMBO: 1474 case POS_FIX_COMBO: 1475 case POS_FIX_SKL: 1476 case POS_FIX_FIFO: 1477 return fix; 1478 } 1479 1480 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1481 if (q) { 1482 dev_info(chip->card->dev, 1483 "position_fix set to %d for device %04x:%04x\n", 1484 q->value, q->subvendor, q->subdevice); 1485 return q->value; 1486 } 1487 1488 /* Check VIA/ATI HD Audio Controller exist */ 1489 if (chip->driver_type == AZX_DRIVER_VIA) { 1490 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1491 return POS_FIX_VIACOMBO; 1492 } 1493 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1494 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1495 return POS_FIX_FIFO; 1496 } 1497 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1498 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1499 return POS_FIX_LPIB; 1500 } 1501 if (chip->driver_type == AZX_DRIVER_SKL) { 1502 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1503 return POS_FIX_SKL; 1504 } 1505 return POS_FIX_AUTO; 1506 } 1507 1508 static void assign_position_fix(struct azx *chip, int fix) 1509 { 1510 static azx_get_pos_callback_t callbacks[] = { 1511 [POS_FIX_AUTO] = NULL, 1512 [POS_FIX_LPIB] = azx_get_pos_lpib, 1513 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1514 [POS_FIX_VIACOMBO] = azx_via_get_position, 1515 [POS_FIX_COMBO] = azx_get_pos_lpib, 1516 [POS_FIX_SKL] = azx_get_pos_skl, 1517 [POS_FIX_FIFO] = azx_get_pos_fifo, 1518 }; 1519 1520 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1521 1522 /* combo mode uses LPIB only for playback */ 1523 if (fix == POS_FIX_COMBO) 1524 chip->get_position[1] = NULL; 1525 1526 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1527 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1528 chip->get_delay[0] = chip->get_delay[1] = 1529 azx_get_delay_from_lpib; 1530 } 1531 1532 if (fix == POS_FIX_FIFO) 1533 chip->get_delay[0] = chip->get_delay[1] = 1534 azx_get_delay_from_fifo; 1535 } 1536 1537 /* 1538 * black-lists for probe_mask 1539 */ 1540 static struct snd_pci_quirk probe_mask_list[] = { 1541 /* Thinkpad often breaks the controller communication when accessing 1542 * to the non-working (or non-existing) modem codec slot. 1543 */ 1544 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1545 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1546 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1547 /* broken BIOS */ 1548 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1549 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1550 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1551 /* forced codec slots */ 1552 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1553 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1554 /* WinFast VP200 H (Teradici) user reported broken communication */ 1555 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1556 {} 1557 }; 1558 1559 #define AZX_FORCE_CODEC_MASK 0x100 1560 1561 static void check_probe_mask(struct azx *chip, int dev) 1562 { 1563 const struct snd_pci_quirk *q; 1564 1565 chip->codec_probe_mask = probe_mask[dev]; 1566 if (chip->codec_probe_mask == -1) { 1567 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1568 if (q) { 1569 dev_info(chip->card->dev, 1570 "probe_mask set to 0x%x for device %04x:%04x\n", 1571 q->value, q->subvendor, q->subdevice); 1572 chip->codec_probe_mask = q->value; 1573 } 1574 } 1575 1576 /* check forced option */ 1577 if (chip->codec_probe_mask != -1 && 1578 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1579 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1580 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1581 (int)azx_bus(chip)->codec_mask); 1582 } 1583 } 1584 1585 /* 1586 * white/black-list for enable_msi 1587 */ 1588 static struct snd_pci_quirk msi_black_list[] = { 1589 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1590 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1591 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1592 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1593 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1594 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1595 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1596 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1597 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1598 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1599 {} 1600 }; 1601 1602 static void check_msi(struct azx *chip) 1603 { 1604 const struct snd_pci_quirk *q; 1605 1606 if (enable_msi >= 0) { 1607 chip->msi = !!enable_msi; 1608 return; 1609 } 1610 chip->msi = 1; /* enable MSI as default */ 1611 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1612 if (q) { 1613 dev_info(chip->card->dev, 1614 "msi for device %04x:%04x set to %d\n", 1615 q->subvendor, q->subdevice, q->value); 1616 chip->msi = q->value; 1617 return; 1618 } 1619 1620 /* NVidia chipsets seem to cause troubles with MSI */ 1621 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1622 dev_info(chip->card->dev, "Disabling MSI\n"); 1623 chip->msi = 0; 1624 } 1625 } 1626 1627 /* check the snoop mode availability */ 1628 static void azx_check_snoop_available(struct azx *chip) 1629 { 1630 int snoop = hda_snoop; 1631 1632 if (snoop >= 0) { 1633 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1634 snoop ? "snoop" : "non-snoop"); 1635 chip->snoop = snoop; 1636 chip->uc_buffer = !snoop; 1637 return; 1638 } 1639 1640 snoop = true; 1641 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1642 chip->driver_type == AZX_DRIVER_VIA) { 1643 /* force to non-snoop mode for a new VIA controller 1644 * when BIOS is set 1645 */ 1646 u8 val; 1647 pci_read_config_byte(chip->pci, 0x42, &val); 1648 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1649 chip->pci->revision == 0x20)) 1650 snoop = false; 1651 } 1652 1653 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1654 snoop = false; 1655 1656 chip->snoop = snoop; 1657 if (!snoop) { 1658 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1659 /* C-Media requires non-cached pages only for CORB/RIRB */ 1660 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1661 chip->uc_buffer = true; 1662 } 1663 } 1664 1665 static void azx_probe_work(struct work_struct *work) 1666 { 1667 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1668 azx_probe_continue(&hda->chip); 1669 } 1670 1671 static int default_bdl_pos_adj(struct azx *chip) 1672 { 1673 /* some exceptions: Atoms seem problematic with value 1 */ 1674 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1675 switch (chip->pci->device) { 1676 case 0x0f04: /* Baytrail */ 1677 case 0x2284: /* Braswell */ 1678 return 32; 1679 } 1680 } 1681 1682 switch (chip->driver_type) { 1683 case AZX_DRIVER_ICH: 1684 case AZX_DRIVER_PCH: 1685 return 1; 1686 default: 1687 return 32; 1688 } 1689 } 1690 1691 /* 1692 * constructor 1693 */ 1694 static const struct hda_controller_ops pci_hda_ops; 1695 1696 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1697 int dev, unsigned int driver_caps, 1698 struct azx **rchip) 1699 { 1700 static struct snd_device_ops ops = { 1701 .dev_disconnect = azx_dev_disconnect, 1702 .dev_free = azx_dev_free, 1703 }; 1704 struct hda_intel *hda; 1705 struct azx *chip; 1706 int err; 1707 1708 *rchip = NULL; 1709 1710 err = pci_enable_device(pci); 1711 if (err < 0) 1712 return err; 1713 1714 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1715 if (!hda) { 1716 pci_disable_device(pci); 1717 return -ENOMEM; 1718 } 1719 1720 chip = &hda->chip; 1721 mutex_init(&chip->open_mutex); 1722 chip->card = card; 1723 chip->pci = pci; 1724 chip->ops = &pci_hda_ops; 1725 chip->driver_caps = driver_caps; 1726 chip->driver_type = driver_caps & 0xff; 1727 check_msi(chip); 1728 chip->dev_index = dev; 1729 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1730 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1731 INIT_LIST_HEAD(&chip->pcm_list); 1732 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1733 INIT_LIST_HEAD(&hda->list); 1734 init_vga_switcheroo(chip); 1735 init_completion(&hda->probe_wait); 1736 1737 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1738 1739 check_probe_mask(chip, dev); 1740 1741 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1742 chip->fallback_to_single_cmd = 1; 1743 else /* explicitly set to single_cmd or not */ 1744 chip->single_cmd = single_cmd; 1745 1746 azx_check_snoop_available(chip); 1747 1748 if (bdl_pos_adj[dev] < 0) 1749 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1750 else 1751 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1752 1753 err = azx_bus_init(chip, model[dev]); 1754 if (err < 0) { 1755 kfree(hda); 1756 pci_disable_device(pci); 1757 return err; 1758 } 1759 1760 /* use the non-cached pages in non-snoop mode */ 1761 if (!azx_snoop(chip)) 1762 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1763 1764 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1765 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1766 chip->bus.needs_damn_long_delay = 1; 1767 } 1768 1769 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1770 if (err < 0) { 1771 dev_err(card->dev, "Error creating device [card]!\n"); 1772 azx_free(chip); 1773 return err; 1774 } 1775 1776 /* continue probing in work context as may trigger request module */ 1777 INIT_WORK(&hda->probe_work, azx_probe_work); 1778 1779 *rchip = chip; 1780 1781 return 0; 1782 } 1783 1784 static int azx_first_init(struct azx *chip) 1785 { 1786 int dev = chip->dev_index; 1787 struct pci_dev *pci = chip->pci; 1788 struct snd_card *card = chip->card; 1789 struct hdac_bus *bus = azx_bus(chip); 1790 int err; 1791 unsigned short gcap; 1792 unsigned int dma_bits = 64; 1793 1794 #if BITS_PER_LONG != 64 1795 /* Fix up base address on ULI M5461 */ 1796 if (chip->driver_type == AZX_DRIVER_ULI) { 1797 u16 tmp3; 1798 pci_read_config_word(pci, 0x40, &tmp3); 1799 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1800 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1801 } 1802 #endif 1803 1804 err = pci_request_regions(pci, "ICH HD audio"); 1805 if (err < 0) 1806 return err; 1807 chip->region_requested = 1; 1808 1809 bus->addr = pci_resource_start(pci, 0); 1810 bus->remap_addr = pci_ioremap_bar(pci, 0); 1811 if (bus->remap_addr == NULL) { 1812 dev_err(card->dev, "ioremap error\n"); 1813 return -ENXIO; 1814 } 1815 1816 if (chip->driver_type == AZX_DRIVER_SKL) 1817 snd_hdac_bus_parse_capabilities(bus); 1818 1819 /* 1820 * Some Intel CPUs has always running timer (ART) feature and 1821 * controller may have Global time sync reporting capability, so 1822 * check both of these before declaring synchronized time reporting 1823 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1824 */ 1825 chip->gts_present = false; 1826 1827 #ifdef CONFIG_X86 1828 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1829 chip->gts_present = true; 1830 #endif 1831 1832 if (chip->msi) { 1833 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1834 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1835 pci->no_64bit_msi = true; 1836 } 1837 if (pci_enable_msi(pci) < 0) 1838 chip->msi = 0; 1839 } 1840 1841 pci_set_master(pci); 1842 synchronize_irq(bus->irq); 1843 1844 gcap = azx_readw(chip, GCAP); 1845 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1846 1847 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1848 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1849 dma_bits = 40; 1850 1851 /* disable SB600 64bit support for safety */ 1852 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1853 struct pci_dev *p_smbus; 1854 dma_bits = 40; 1855 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1856 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1857 NULL); 1858 if (p_smbus) { 1859 if (p_smbus->revision < 0x30) 1860 gcap &= ~AZX_GCAP_64OK; 1861 pci_dev_put(p_smbus); 1862 } 1863 } 1864 1865 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1866 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1867 dma_bits = 40; 1868 1869 /* disable 64bit DMA address on some devices */ 1870 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1871 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1872 gcap &= ~AZX_GCAP_64OK; 1873 } 1874 1875 /* disable buffer size rounding to 128-byte multiples if supported */ 1876 if (align_buffer_size >= 0) 1877 chip->align_buffer_size = !!align_buffer_size; 1878 else { 1879 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1880 chip->align_buffer_size = 0; 1881 else 1882 chip->align_buffer_size = 1; 1883 } 1884 1885 /* allow 64bit DMA address if supported by H/W */ 1886 if (!(gcap & AZX_GCAP_64OK)) 1887 dma_bits = 32; 1888 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1889 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1890 } else { 1891 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1892 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1893 } 1894 1895 /* read number of streams from GCAP register instead of using 1896 * hardcoded value 1897 */ 1898 chip->capture_streams = (gcap >> 8) & 0x0f; 1899 chip->playback_streams = (gcap >> 12) & 0x0f; 1900 if (!chip->playback_streams && !chip->capture_streams) { 1901 /* gcap didn't give any info, switching to old method */ 1902 1903 switch (chip->driver_type) { 1904 case AZX_DRIVER_ULI: 1905 chip->playback_streams = ULI_NUM_PLAYBACK; 1906 chip->capture_streams = ULI_NUM_CAPTURE; 1907 break; 1908 case AZX_DRIVER_ATIHDMI: 1909 case AZX_DRIVER_ATIHDMI_NS: 1910 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1911 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1912 break; 1913 case AZX_DRIVER_GENERIC: 1914 default: 1915 chip->playback_streams = ICH6_NUM_PLAYBACK; 1916 chip->capture_streams = ICH6_NUM_CAPTURE; 1917 break; 1918 } 1919 } 1920 chip->capture_index_offset = 0; 1921 chip->playback_index_offset = chip->capture_streams; 1922 chip->num_streams = chip->playback_streams + chip->capture_streams; 1923 1924 /* sanity check for the SDxCTL.STRM field overflow */ 1925 if (chip->num_streams > 15 && 1926 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1927 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1928 "forcing separate stream tags", chip->num_streams); 1929 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1930 } 1931 1932 /* initialize streams */ 1933 err = azx_init_streams(chip); 1934 if (err < 0) 1935 return err; 1936 1937 err = azx_alloc_stream_pages(chip); 1938 if (err < 0) 1939 return err; 1940 1941 /* initialize chip */ 1942 azx_init_pci(chip); 1943 1944 snd_hdac_i915_set_bclk(bus); 1945 1946 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1947 1948 /* codec detection */ 1949 if (!azx_bus(chip)->codec_mask) { 1950 dev_err(card->dev, "no codecs found!\n"); 1951 return -ENODEV; 1952 } 1953 1954 if (azx_acquire_irq(chip, 0) < 0) 1955 return -EBUSY; 1956 1957 strcpy(card->driver, "HDA-Intel"); 1958 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1959 sizeof(card->shortname)); 1960 snprintf(card->longname, sizeof(card->longname), 1961 "%s at 0x%lx irq %i", 1962 card->shortname, bus->addr, bus->irq); 1963 1964 return 0; 1965 } 1966 1967 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1968 /* callback from request_firmware_nowait() */ 1969 static void azx_firmware_cb(const struct firmware *fw, void *context) 1970 { 1971 struct snd_card *card = context; 1972 struct azx *chip = card->private_data; 1973 struct pci_dev *pci = chip->pci; 1974 1975 if (!fw) { 1976 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1977 goto error; 1978 } 1979 1980 chip->fw = fw; 1981 if (!chip->disabled) { 1982 /* continue probing */ 1983 if (azx_probe_continue(chip)) 1984 goto error; 1985 } 1986 return; /* OK */ 1987 1988 error: 1989 snd_card_free(card); 1990 pci_set_drvdata(pci, NULL); 1991 } 1992 #endif 1993 1994 static int disable_msi_reset_irq(struct azx *chip) 1995 { 1996 struct hdac_bus *bus = azx_bus(chip); 1997 int err; 1998 1999 free_irq(bus->irq, chip); 2000 bus->irq = -1; 2001 pci_disable_msi(chip->pci); 2002 chip->msi = 0; 2003 err = azx_acquire_irq(chip, 1); 2004 if (err < 0) 2005 return err; 2006 2007 return 0; 2008 } 2009 2010 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2011 struct vm_area_struct *area) 2012 { 2013 #ifdef CONFIG_X86 2014 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2015 struct azx *chip = apcm->chip; 2016 if (chip->uc_buffer) 2017 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2018 #endif 2019 } 2020 2021 static const struct hda_controller_ops pci_hda_ops = { 2022 .disable_msi_reset_irq = disable_msi_reset_irq, 2023 .pcm_mmap_prepare = pcm_mmap_prepare, 2024 .position_check = azx_position_check, 2025 }; 2026 2027 static int azx_probe(struct pci_dev *pci, 2028 const struct pci_device_id *pci_id) 2029 { 2030 static int dev; 2031 struct snd_card *card; 2032 struct hda_intel *hda; 2033 struct azx *chip; 2034 bool schedule_probe; 2035 int err; 2036 2037 if (dev >= SNDRV_CARDS) 2038 return -ENODEV; 2039 if (!enable[dev]) { 2040 dev++; 2041 return -ENOENT; 2042 } 2043 2044 /* 2045 * stop probe if another Intel's DSP driver should be activated 2046 */ 2047 if (dsp_driver) { 2048 err = snd_intel_dsp_driver_probe(pci); 2049 if (err != SND_INTEL_DSP_DRIVER_ANY && 2050 err != SND_INTEL_DSP_DRIVER_LEGACY) 2051 return -ENODEV; 2052 } 2053 2054 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2055 0, &card); 2056 if (err < 0) { 2057 dev_err(&pci->dev, "Error creating card!\n"); 2058 return err; 2059 } 2060 2061 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2062 if (err < 0) 2063 goto out_free; 2064 card->private_data = chip; 2065 hda = container_of(chip, struct hda_intel, chip); 2066 2067 pci_set_drvdata(pci, card); 2068 2069 err = register_vga_switcheroo(chip); 2070 if (err < 0) { 2071 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2072 goto out_free; 2073 } 2074 2075 if (check_hdmi_disabled(pci)) { 2076 dev_info(card->dev, "VGA controller is disabled\n"); 2077 dev_info(card->dev, "Delaying initialization\n"); 2078 chip->disabled = true; 2079 } 2080 2081 schedule_probe = !chip->disabled; 2082 2083 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2084 if (patch[dev] && *patch[dev]) { 2085 dev_info(card->dev, "Applying patch firmware '%s'\n", 2086 patch[dev]); 2087 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2088 &pci->dev, GFP_KERNEL, card, 2089 azx_firmware_cb); 2090 if (err < 0) 2091 goto out_free; 2092 schedule_probe = false; /* continued in azx_firmware_cb() */ 2093 } 2094 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2095 2096 #ifndef CONFIG_SND_HDA_I915 2097 if (CONTROLLER_IN_GPU(pci)) 2098 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2099 #endif 2100 2101 if (schedule_probe) 2102 schedule_work(&hda->probe_work); 2103 2104 dev++; 2105 if (chip->disabled) 2106 complete_all(&hda->probe_wait); 2107 return 0; 2108 2109 out_free: 2110 snd_card_free(card); 2111 return err; 2112 } 2113 2114 #ifdef CONFIG_PM 2115 /* On some boards setting power_save to a non 0 value leads to clicking / 2116 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2117 * figure out how to avoid these sounds, but that is not always feasible. 2118 * So we keep a list of devices where we disable powersaving as its known 2119 * to causes problems on these devices. 2120 */ 2121 static struct snd_pci_quirk power_save_blacklist[] = { 2122 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2123 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2124 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2125 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2126 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2127 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2128 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2129 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2130 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2131 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2132 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2133 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2134 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2135 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2136 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2137 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2138 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2139 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2140 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2141 /* https://bugs.launchpad.net/bugs/1821663 */ 2142 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2143 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2144 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2145 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2146 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2147 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2148 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2149 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2150 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2151 /* https://bugs.launchpad.net/bugs/1821663 */ 2152 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2153 {} 2154 }; 2155 #endif /* CONFIG_PM */ 2156 2157 static void set_default_power_save(struct azx *chip) 2158 { 2159 int val = power_save; 2160 2161 #ifdef CONFIG_PM 2162 if (pm_blacklist) { 2163 const struct snd_pci_quirk *q; 2164 2165 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2166 if (q && val) { 2167 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2168 q->subvendor, q->subdevice); 2169 val = 0; 2170 } 2171 } 2172 #endif /* CONFIG_PM */ 2173 snd_hda_set_power_save(&chip->bus, val * 1000); 2174 } 2175 2176 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2177 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2178 [AZX_DRIVER_NVIDIA] = 8, 2179 [AZX_DRIVER_TERA] = 1, 2180 }; 2181 2182 static int azx_probe_continue(struct azx *chip) 2183 { 2184 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2185 struct hdac_bus *bus = azx_bus(chip); 2186 struct pci_dev *pci = chip->pci; 2187 int dev = chip->dev_index; 2188 int err; 2189 2190 to_hda_bus(bus)->bus_probing = 1; 2191 hda->probe_continued = 1; 2192 2193 /* bind with i915 if needed */ 2194 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2195 err = snd_hdac_i915_init(bus); 2196 if (err < 0) { 2197 /* if the controller is bound only with HDMI/DP 2198 * (for HSW and BDW), we need to abort the probe; 2199 * for other chips, still continue probing as other 2200 * codecs can be on the same link. 2201 */ 2202 if (CONTROLLER_IN_GPU(pci)) { 2203 dev_err(chip->card->dev, 2204 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2205 goto out_free; 2206 } else { 2207 /* don't bother any longer */ 2208 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2209 } 2210 } 2211 2212 /* HSW/BDW controllers need this power */ 2213 if (CONTROLLER_IN_GPU(pci)) 2214 hda->need_i915_power = 1; 2215 } 2216 2217 /* Request display power well for the HDA controller or codec. For 2218 * Haswell/Broadwell, both the display HDA controller and codec need 2219 * this power. For other platforms, like Baytrail/Braswell, only the 2220 * display codec needs the power and it can be released after probe. 2221 */ 2222 display_power(chip, true); 2223 2224 err = azx_first_init(chip); 2225 if (err < 0) 2226 goto out_free; 2227 2228 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2229 chip->beep_mode = beep_mode[dev]; 2230 #endif 2231 2232 /* create codec instances */ 2233 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2234 if (err < 0) 2235 goto out_free; 2236 2237 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2238 if (chip->fw) { 2239 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2240 chip->fw->data); 2241 if (err < 0) 2242 goto out_free; 2243 #ifndef CONFIG_PM 2244 release_firmware(chip->fw); /* no longer needed */ 2245 chip->fw = NULL; 2246 #endif 2247 } 2248 #endif 2249 if ((probe_only[dev] & 1) == 0) { 2250 err = azx_codec_configure(chip); 2251 if (err < 0) 2252 goto out_free; 2253 } 2254 2255 err = snd_card_register(chip->card); 2256 if (err < 0) 2257 goto out_free; 2258 2259 setup_vga_switcheroo_runtime_pm(chip); 2260 2261 chip->running = 1; 2262 azx_add_card_list(chip); 2263 2264 set_default_power_save(chip); 2265 2266 if (azx_has_pm_runtime(chip)) 2267 pm_runtime_put_autosuspend(&pci->dev); 2268 2269 out_free: 2270 if (err < 0 || !hda->need_i915_power) 2271 display_power(chip, false); 2272 if (err < 0) 2273 hda->init_failed = 1; 2274 complete_all(&hda->probe_wait); 2275 to_hda_bus(bus)->bus_probing = 0; 2276 return err; 2277 } 2278 2279 static void azx_remove(struct pci_dev *pci) 2280 { 2281 struct snd_card *card = pci_get_drvdata(pci); 2282 struct azx *chip; 2283 struct hda_intel *hda; 2284 2285 if (card) { 2286 /* cancel the pending probing work */ 2287 chip = card->private_data; 2288 hda = container_of(chip, struct hda_intel, chip); 2289 /* FIXME: below is an ugly workaround. 2290 * Both device_release_driver() and driver_probe_device() 2291 * take *both* the device's and its parent's lock before 2292 * calling the remove() and probe() callbacks. The codec 2293 * probe takes the locks of both the codec itself and its 2294 * parent, i.e. the PCI controller dev. Meanwhile, when 2295 * the PCI controller is unbound, it takes its lock, too 2296 * ==> ouch, a deadlock! 2297 * As a workaround, we unlock temporarily here the controller 2298 * device during cancel_work_sync() call. 2299 */ 2300 device_unlock(&pci->dev); 2301 cancel_work_sync(&hda->probe_work); 2302 device_lock(&pci->dev); 2303 2304 snd_card_free(card); 2305 } 2306 } 2307 2308 static void azx_shutdown(struct pci_dev *pci) 2309 { 2310 struct snd_card *card = pci_get_drvdata(pci); 2311 struct azx *chip; 2312 2313 if (!card) 2314 return; 2315 chip = card->private_data; 2316 if (chip && chip->running) 2317 azx_stop_chip(chip); 2318 } 2319 2320 /* PCI IDs */ 2321 static const struct pci_device_id azx_ids[] = { 2322 /* CPT */ 2323 { PCI_DEVICE(0x8086, 0x1c20), 2324 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2325 /* PBG */ 2326 { PCI_DEVICE(0x8086, 0x1d20), 2327 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2328 /* Panther Point */ 2329 { PCI_DEVICE(0x8086, 0x1e20), 2330 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2331 /* Lynx Point */ 2332 { PCI_DEVICE(0x8086, 0x8c20), 2333 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2334 /* 9 Series */ 2335 { PCI_DEVICE(0x8086, 0x8ca0), 2336 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2337 /* Wellsburg */ 2338 { PCI_DEVICE(0x8086, 0x8d20), 2339 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2340 { PCI_DEVICE(0x8086, 0x8d21), 2341 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2342 /* Lewisburg */ 2343 { PCI_DEVICE(0x8086, 0xa1f0), 2344 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2345 { PCI_DEVICE(0x8086, 0xa270), 2346 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2347 /* Lynx Point-LP */ 2348 { PCI_DEVICE(0x8086, 0x9c20), 2349 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2350 /* Lynx Point-LP */ 2351 { PCI_DEVICE(0x8086, 0x9c21), 2352 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2353 /* Wildcat Point-LP */ 2354 { PCI_DEVICE(0x8086, 0x9ca0), 2355 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2356 /* Sunrise Point */ 2357 { PCI_DEVICE(0x8086, 0xa170), 2358 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2359 /* Sunrise Point-LP */ 2360 { PCI_DEVICE(0x8086, 0x9d70), 2361 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2362 /* Kabylake */ 2363 { PCI_DEVICE(0x8086, 0xa171), 2364 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2365 /* Kabylake-LP */ 2366 { PCI_DEVICE(0x8086, 0x9d71), 2367 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2368 /* Kabylake-H */ 2369 { PCI_DEVICE(0x8086, 0xa2f0), 2370 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2371 /* Coffelake */ 2372 { PCI_DEVICE(0x8086, 0xa348), 2373 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2374 /* Cannonlake */ 2375 { PCI_DEVICE(0x8086, 0x9dc8), 2376 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2377 /* CometLake-LP */ 2378 { PCI_DEVICE(0x8086, 0x02C8), 2379 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2380 /* CometLake-H */ 2381 { PCI_DEVICE(0x8086, 0x06C8), 2382 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2383 /* CometLake-S */ 2384 { PCI_DEVICE(0x8086, 0xa3f0), 2385 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2386 /* Icelake */ 2387 { PCI_DEVICE(0x8086, 0x34c8), 2388 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2389 /* Jasperlake */ 2390 { PCI_DEVICE(0x8086, 0x38c8), 2391 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2392 /* Tigerlake */ 2393 { PCI_DEVICE(0x8086, 0xa0c8), 2394 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2395 /* Elkhart Lake */ 2396 { PCI_DEVICE(0x8086, 0x4b55), 2397 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2398 /* Broxton-P(Apollolake) */ 2399 { PCI_DEVICE(0x8086, 0x5a98), 2400 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2401 /* Broxton-T */ 2402 { PCI_DEVICE(0x8086, 0x1a98), 2403 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2404 /* Gemini-Lake */ 2405 { PCI_DEVICE(0x8086, 0x3198), 2406 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2407 /* Haswell */ 2408 { PCI_DEVICE(0x8086, 0x0a0c), 2409 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2410 { PCI_DEVICE(0x8086, 0x0c0c), 2411 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2412 { PCI_DEVICE(0x8086, 0x0d0c), 2413 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2414 /* Broadwell */ 2415 { PCI_DEVICE(0x8086, 0x160c), 2416 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2417 /* 5 Series/3400 */ 2418 { PCI_DEVICE(0x8086, 0x3b56), 2419 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2420 /* Poulsbo */ 2421 { PCI_DEVICE(0x8086, 0x811b), 2422 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2423 /* Oaktrail */ 2424 { PCI_DEVICE(0x8086, 0x080a), 2425 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2426 /* BayTrail */ 2427 { PCI_DEVICE(0x8086, 0x0f04), 2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2429 /* Braswell */ 2430 { PCI_DEVICE(0x8086, 0x2284), 2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2432 /* ICH6 */ 2433 { PCI_DEVICE(0x8086, 0x2668), 2434 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2435 /* ICH7 */ 2436 { PCI_DEVICE(0x8086, 0x27d8), 2437 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2438 /* ESB2 */ 2439 { PCI_DEVICE(0x8086, 0x269a), 2440 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2441 /* ICH8 */ 2442 { PCI_DEVICE(0x8086, 0x284b), 2443 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2444 /* ICH9 */ 2445 { PCI_DEVICE(0x8086, 0x293e), 2446 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2447 /* ICH9 */ 2448 { PCI_DEVICE(0x8086, 0x293f), 2449 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2450 /* ICH10 */ 2451 { PCI_DEVICE(0x8086, 0x3a3e), 2452 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2453 /* ICH10 */ 2454 { PCI_DEVICE(0x8086, 0x3a6e), 2455 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2456 /* Generic Intel */ 2457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2458 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2459 .class_mask = 0xffffff, 2460 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2461 /* ATI SB 450/600/700/800/900 */ 2462 { PCI_DEVICE(0x1002, 0x437b), 2463 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2464 { PCI_DEVICE(0x1002, 0x4383), 2465 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2466 /* AMD Hudson */ 2467 { PCI_DEVICE(0x1022, 0x780d), 2468 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2469 /* AMD, X370 & co */ 2470 { PCI_DEVICE(0x1022, 0x1457), 2471 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2472 /* AMD, X570 & co */ 2473 { PCI_DEVICE(0x1022, 0x1487), 2474 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2475 /* AMD Stoney */ 2476 { PCI_DEVICE(0x1022, 0x157a), 2477 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2478 AZX_DCAPS_PM_RUNTIME }, 2479 /* AMD Raven */ 2480 { PCI_DEVICE(0x1022, 0x15e3), 2481 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2482 /* ATI HDMI */ 2483 { PCI_DEVICE(0x1002, 0x0002), 2484 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2485 { PCI_DEVICE(0x1002, 0x1308), 2486 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2487 { PCI_DEVICE(0x1002, 0x157a), 2488 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2489 { PCI_DEVICE(0x1002, 0x15b3), 2490 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2491 { PCI_DEVICE(0x1002, 0x793b), 2492 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2493 { PCI_DEVICE(0x1002, 0x7919), 2494 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2495 { PCI_DEVICE(0x1002, 0x960f), 2496 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2497 { PCI_DEVICE(0x1002, 0x970f), 2498 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2499 { PCI_DEVICE(0x1002, 0x9840), 2500 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2501 { PCI_DEVICE(0x1002, 0xaa00), 2502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2503 { PCI_DEVICE(0x1002, 0xaa08), 2504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2505 { PCI_DEVICE(0x1002, 0xaa10), 2506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2507 { PCI_DEVICE(0x1002, 0xaa18), 2508 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2509 { PCI_DEVICE(0x1002, 0xaa20), 2510 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2511 { PCI_DEVICE(0x1002, 0xaa28), 2512 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2513 { PCI_DEVICE(0x1002, 0xaa30), 2514 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2515 { PCI_DEVICE(0x1002, 0xaa38), 2516 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2517 { PCI_DEVICE(0x1002, 0xaa40), 2518 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2519 { PCI_DEVICE(0x1002, 0xaa48), 2520 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2521 { PCI_DEVICE(0x1002, 0xaa50), 2522 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2523 { PCI_DEVICE(0x1002, 0xaa58), 2524 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2525 { PCI_DEVICE(0x1002, 0xaa60), 2526 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2527 { PCI_DEVICE(0x1002, 0xaa68), 2528 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2529 { PCI_DEVICE(0x1002, 0xaa80), 2530 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2531 { PCI_DEVICE(0x1002, 0xaa88), 2532 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2533 { PCI_DEVICE(0x1002, 0xaa90), 2534 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2535 { PCI_DEVICE(0x1002, 0xaa98), 2536 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2537 { PCI_DEVICE(0x1002, 0x9902), 2538 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2539 { PCI_DEVICE(0x1002, 0xaaa0), 2540 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2541 { PCI_DEVICE(0x1002, 0xaaa8), 2542 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2543 { PCI_DEVICE(0x1002, 0xaab0), 2544 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2545 { PCI_DEVICE(0x1002, 0xaac0), 2546 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2547 { PCI_DEVICE(0x1002, 0xaac8), 2548 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2549 { PCI_DEVICE(0x1002, 0xaad8), 2550 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2551 { PCI_DEVICE(0x1002, 0xaae8), 2552 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2553 { PCI_DEVICE(0x1002, 0xaae0), 2554 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2555 { PCI_DEVICE(0x1002, 0xaaf0), 2556 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2557 /* VIA VT8251/VT8237A */ 2558 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2559 /* VIA GFX VT7122/VX900 */ 2560 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2561 /* VIA GFX VT6122/VX11 */ 2562 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2563 /* SIS966 */ 2564 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2565 /* ULI M5461 */ 2566 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2567 /* NVIDIA MCP */ 2568 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2569 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2570 .class_mask = 0xffffff, 2571 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2572 /* Teradici */ 2573 { PCI_DEVICE(0x6549, 0x1200), 2574 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2575 { PCI_DEVICE(0x6549, 0x2200), 2576 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2577 /* Creative X-Fi (CA0110-IBG) */ 2578 /* CTHDA chips */ 2579 { PCI_DEVICE(0x1102, 0x0010), 2580 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2581 { PCI_DEVICE(0x1102, 0x0012), 2582 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2583 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2584 /* the following entry conflicts with snd-ctxfi driver, 2585 * as ctxfi driver mutates from HD-audio to native mode with 2586 * a special command sequence. 2587 */ 2588 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2589 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2590 .class_mask = 0xffffff, 2591 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2592 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2593 #else 2594 /* this entry seems still valid -- i.e. without emu20kx chip */ 2595 { PCI_DEVICE(0x1102, 0x0009), 2596 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2597 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2598 #endif 2599 /* CM8888 */ 2600 { PCI_DEVICE(0x13f6, 0x5011), 2601 .driver_data = AZX_DRIVER_CMEDIA | 2602 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2603 /* Vortex86MX */ 2604 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2605 /* VMware HDAudio */ 2606 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2607 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2608 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2609 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2610 .class_mask = 0xffffff, 2611 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2612 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2613 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2614 .class_mask = 0xffffff, 2615 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2616 /* Zhaoxin */ 2617 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2618 { 0, } 2619 }; 2620 MODULE_DEVICE_TABLE(pci, azx_ids); 2621 2622 /* pci_driver definition */ 2623 static struct pci_driver azx_driver = { 2624 .name = KBUILD_MODNAME, 2625 .id_table = azx_ids, 2626 .probe = azx_probe, 2627 .remove = azx_remove, 2628 .shutdown = azx_shutdown, 2629 .driver = { 2630 .pm = AZX_PM_OPS, 2631 }, 2632 }; 2633 2634 module_pci_driver(azx_driver); 2635