1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40
41 #ifdef CONFIG_X86
42 /* for snoop control */
43 #include <linux/dma-map-ops.h>
44 #include <asm/set_memory.h>
45 #include <asm/cpufeature.h>
46 #endif
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include <sound/hdaudio.h>
50 #include <sound/hda_i915.h>
51 #include <sound/intel-dsp-config.h>
52 #include <linux/vgaarb.h>
53 #include <linux/vga_switcheroo.h>
54 #include <linux/apple-gmux.h>
55 #include <linux/firmware.h>
56 #include <sound/hda_codec.h>
57 #include "hda_controller.h"
58 #include "hda_intel.h"
59
60 #define CREATE_TRACE_POINTS
61 #include "hda_intel_trace.h"
62
63 /* position fix mode */
64 enum {
65 POS_FIX_AUTO,
66 POS_FIX_LPIB,
67 POS_FIX_POSBUF,
68 POS_FIX_VIACOMBO,
69 POS_FIX_COMBO,
70 POS_FIX_SKL,
71 POS_FIX_FIFO,
72 };
73
74 /* Defines for ATI HD Audio support in SB450 south bridge */
75 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
76 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
77
78 /* Defines for Nvidia HDA support */
79 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
80 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
81 #define NVIDIA_HDA_ISTRM_COH 0x4d
82 #define NVIDIA_HDA_OSTRM_COH 0x4c
83 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
84
85 /* Defines for Intel SCH HDA snoop control */
86 #define INTEL_HDA_CGCTL 0x48
87 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
88 #define INTEL_SCH_HDA_DEVC 0x78
89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91 /* max number of SDs */
92 /* ICH, ATI and VIA have 4 playback and 4 capture */
93 #define ICH6_NUM_CAPTURE 4
94 #define ICH6_NUM_PLAYBACK 4
95
96 /* ULI has 6 playback and 5 capture */
97 #define ULI_NUM_CAPTURE 5
98 #define ULI_NUM_PLAYBACK 6
99
100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
101 #define ATIHDMI_NUM_CAPTURE 0
102 #define ATIHDMI_NUM_PLAYBACK 8
103
104
105 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
106 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
107 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
108 static char *model[SNDRV_CARDS];
109 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
110 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
111 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
112 static int probe_only[SNDRV_CARDS];
113 static int jackpoll_ms[SNDRV_CARDS];
114 static int single_cmd = -1;
115 static int enable_msi = -1;
116 #ifdef CONFIG_SND_HDA_PATCH_LOADER
117 static char *patch[SNDRV_CARDS];
118 #endif
119 #ifdef CONFIG_SND_HDA_INPUT_BEEP
120 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
121 CONFIG_SND_HDA_INPUT_BEEP_MODE};
122 #endif
123 static bool dmic_detect = 1;
124 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
125
126 module_param_array(index, int, NULL, 0444);
127 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
128 module_param_array(id, charp, NULL, 0444);
129 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
130 module_param_array(enable, bool, NULL, 0444);
131 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
132 module_param_array(model, charp, NULL, 0444);
133 MODULE_PARM_DESC(model, "Use the given board model.");
134 module_param_array(position_fix, int, NULL, 0444);
135 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
136 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
137 module_param_array(bdl_pos_adj, int, NULL, 0644);
138 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
139 module_param_array(probe_mask, int, NULL, 0444);
140 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
141 module_param_array(probe_only, int, NULL, 0444);
142 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
143 module_param_array(jackpoll_ms, int, NULL, 0444);
144 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
145 module_param(single_cmd, bint, 0444);
146 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
147 "(for debugging only).");
148 module_param(enable_msi, bint, 0444);
149 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
150 #ifdef CONFIG_SND_HDA_PATCH_LOADER
151 module_param_array(patch, charp, NULL, 0444);
152 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
153 #endif
154 #ifdef CONFIG_SND_HDA_INPUT_BEEP
155 module_param_array(beep_mode, bool, NULL, 0444);
156 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
157 "(0=off, 1=on) (default=1).");
158 #endif
159 module_param(dmic_detect, bool, 0444);
160 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
161 "(0=off, 1=on) (default=1); "
162 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
163 module_param(ctl_dev_id, bool, 0444);
164 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
165
166 #ifdef CONFIG_PM
167 static int param_set_xint(const char *val, const struct kernel_param *kp);
168 static const struct kernel_param_ops param_ops_xint = {
169 .set = param_set_xint,
170 .get = param_get_int,
171 };
172 #define param_check_xint param_check_int
173
174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
175 module_param(power_save, xint, 0644);
176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
177 "(in second, 0 = disable).");
178
179 static bool pm_blacklist = true;
180 module_param(pm_blacklist, bool, 0644);
181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
182
183 /* reset the HD-audio controller in power save mode.
184 * this may give more power-saving, but will take longer time to
185 * wake up.
186 */
187 static bool power_save_controller = 1;
188 module_param(power_save_controller, bool, 0644);
189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
190 #else
191 #define power_save 0
192 #endif /* CONFIG_PM */
193
194 static int align_buffer_size = -1;
195 module_param(align_buffer_size, bint, 0644);
196 MODULE_PARM_DESC(align_buffer_size,
197 "Force buffer and period sizes to be multiple of 128 bytes.");
198
199 #ifdef CONFIG_X86
200 static int hda_snoop = -1;
201 module_param_named(snoop, hda_snoop, bint, 0444);
202 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
203 #else
204 #define hda_snoop true
205 #endif
206
207
208 MODULE_LICENSE("GPL");
209 MODULE_DESCRIPTION("Intel HDA driver");
210
211 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
212 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
213 #define SUPPORT_VGA_SWITCHEROO
214 #endif
215 #endif
216
217
218 /*
219 */
220
221 /* driver types */
222 enum {
223 AZX_DRIVER_ICH,
224 AZX_DRIVER_PCH,
225 AZX_DRIVER_SCH,
226 AZX_DRIVER_SKL,
227 AZX_DRIVER_HDMI,
228 AZX_DRIVER_ATI,
229 AZX_DRIVER_ATIHDMI,
230 AZX_DRIVER_ATIHDMI_NS,
231 AZX_DRIVER_GFHDMI,
232 AZX_DRIVER_VIA,
233 AZX_DRIVER_SIS,
234 AZX_DRIVER_ULI,
235 AZX_DRIVER_NVIDIA,
236 AZX_DRIVER_TERA,
237 AZX_DRIVER_CTX,
238 AZX_DRIVER_CTHDA,
239 AZX_DRIVER_CMEDIA,
240 AZX_DRIVER_ZHAOXIN,
241 AZX_DRIVER_LOONGSON,
242 AZX_DRIVER_GENERIC,
243 AZX_NUM_DRIVERS, /* keep this as last entry */
244 };
245
246 #define azx_get_snoop_type(chip) \
247 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
248 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
249
250 /* quirks for old Intel chipsets */
251 #define AZX_DCAPS_INTEL_ICH \
252 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
253
254 /* quirks for Intel PCH */
255 #define AZX_DCAPS_INTEL_PCH_BASE \
256 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
257 AZX_DCAPS_SNOOP_TYPE(SCH))
258
259 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
260 #define AZX_DCAPS_INTEL_PCH_NOPM \
261 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
262
263 /* PCH for HSW/BDW; with runtime PM */
264 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
265 #define AZX_DCAPS_INTEL_PCH \
266 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
267
268 /* HSW HDMI */
269 #define AZX_DCAPS_INTEL_HASWELL \
270 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
271 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
272 AZX_DCAPS_SNOOP_TYPE(SCH))
273
274 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
275 #define AZX_DCAPS_INTEL_BROADWELL \
276 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
277 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
278 AZX_DCAPS_SNOOP_TYPE(SCH))
279
280 #define AZX_DCAPS_INTEL_BAYTRAIL \
281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
282
283 #define AZX_DCAPS_INTEL_BRASWELL \
284 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
285 AZX_DCAPS_I915_COMPONENT)
286
287 #define AZX_DCAPS_INTEL_SKYLAKE \
288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
289 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
290
291 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
292
293 /* quirks for ATI SB / AMD Hudson */
294 #define AZX_DCAPS_PRESET_ATI_SB \
295 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
296 AZX_DCAPS_SNOOP_TYPE(ATI))
297
298 /* quirks for ATI/AMD HDMI */
299 #define AZX_DCAPS_PRESET_ATI_HDMI \
300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
301 AZX_DCAPS_NO_MSI64)
302
303 /* quirks for ATI HDMI with snoop off */
304 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
305 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_AMD_ALLOC_FIX)
306
307 /* quirks for AMD SB */
308 #define AZX_DCAPS_PRESET_AMD_SB \
309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
310 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
311 AZX_DCAPS_RETRY_PROBE)
312
313 /* quirks for Nvidia */
314 #define AZX_DCAPS_PRESET_NVIDIA \
315 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
316 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
317
318 #define AZX_DCAPS_PRESET_CTHDA \
319 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
320 AZX_DCAPS_NO_64BIT |\
321 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
322
323 /*
324 * vga_switcheroo support
325 */
326 #ifdef SUPPORT_VGA_SWITCHEROO
327 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
328 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
329 #else
330 #define use_vga_switcheroo(chip) 0
331 #define needs_eld_notify_link(chip) false
332 #endif
333
334 static const char * const driver_short_names[] = {
335 [AZX_DRIVER_ICH] = "HDA Intel",
336 [AZX_DRIVER_PCH] = "HDA Intel PCH",
337 [AZX_DRIVER_SCH] = "HDA Intel MID",
338 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
339 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
340 [AZX_DRIVER_ATI] = "HDA ATI SB",
341 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
342 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
343 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
344 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
345 [AZX_DRIVER_SIS] = "HDA SIS966",
346 [AZX_DRIVER_ULI] = "HDA ULI M5461",
347 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
348 [AZX_DRIVER_TERA] = "HDA Teradici",
349 [AZX_DRIVER_CTX] = "HDA Creative",
350 [AZX_DRIVER_CTHDA] = "HDA Creative",
351 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
352 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
353 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
354 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
355 };
356
357 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
358 static void set_default_power_save(struct azx *chip);
359
360 /*
361 * initialize the PCI registers
362 */
363 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)364 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
365 unsigned char mask, unsigned char val)
366 {
367 unsigned char data;
368
369 pci_read_config_byte(pci, reg, &data);
370 data &= ~mask;
371 data |= (val & mask);
372 pci_write_config_byte(pci, reg, data);
373 }
374
azx_init_pci(struct azx * chip)375 static void azx_init_pci(struct azx *chip)
376 {
377 int snoop_type = azx_get_snoop_type(chip);
378
379 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
380 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
381 * Ensuring these bits are 0 clears playback static on some HD Audio
382 * codecs.
383 * The PCI register TCSEL is defined in the Intel manuals.
384 */
385 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
386 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
387 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
388 }
389
390 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
391 * we need to enable snoop.
392 */
393 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
394 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
395 azx_snoop(chip));
396 update_pci_byte(chip->pci,
397 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
398 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
399 }
400
401 /* For NVIDIA HDA, enable snoop */
402 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
403 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
404 azx_snoop(chip));
405 update_pci_byte(chip->pci,
406 NVIDIA_HDA_TRANSREG_ADDR,
407 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
408 update_pci_byte(chip->pci,
409 NVIDIA_HDA_ISTRM_COH,
410 0x01, NVIDIA_HDA_ENABLE_COHBIT);
411 update_pci_byte(chip->pci,
412 NVIDIA_HDA_OSTRM_COH,
413 0x01, NVIDIA_HDA_ENABLE_COHBIT);
414 }
415
416 /* Enable SCH/PCH snoop if needed */
417 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
418 unsigned short snoop;
419 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
420 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
421 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
422 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
423 if (!azx_snoop(chip))
424 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
425 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
426 pci_read_config_word(chip->pci,
427 INTEL_SCH_HDA_DEVC, &snoop);
428 }
429 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
430 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
431 "Disabled" : "Enabled");
432 }
433 }
434
435 /*
436 * In BXT-P A0, HD-Audio DMA requests is later than expected,
437 * and makes an audio stream sensitive to system latencies when
438 * 24/32 bits are playing.
439 * Adjusting threshold of DMA fifo to force the DMA request
440 * sooner to improve latency tolerance at the expense of power.
441 */
bxt_reduce_dma_latency(struct azx * chip)442 static void bxt_reduce_dma_latency(struct azx *chip)
443 {
444 u32 val;
445
446 val = azx_readl(chip, VS_EM4L);
447 val &= (0x3 << 20);
448 azx_writel(chip, VS_EM4L, val);
449 }
450
451 /*
452 * ML_LCAP bits:
453 * bit 0: 6 MHz Supported
454 * bit 1: 12 MHz Supported
455 * bit 2: 24 MHz Supported
456 * bit 3: 48 MHz Supported
457 * bit 4: 96 MHz Supported
458 * bit 5: 192 MHz Supported
459 */
intel_get_lctl_scf(struct azx * chip)460 static int intel_get_lctl_scf(struct azx *chip)
461 {
462 struct hdac_bus *bus = azx_bus(chip);
463 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
464 u32 val, t;
465 int i;
466
467 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
468
469 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
470 t = preferred_bits[i];
471 if (val & (1 << t))
472 return t;
473 }
474
475 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
476 return 0;
477 }
478
intel_ml_lctl_set_power(struct azx * chip,int state)479 static int intel_ml_lctl_set_power(struct azx *chip, int state)
480 {
481 struct hdac_bus *bus = azx_bus(chip);
482 u32 val;
483 int timeout;
484
485 /*
486 * Changes to LCTL.SCF are only needed for the first multi-link dealing
487 * with external codecs
488 */
489 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
490 val &= ~AZX_ML_LCTL_SPA;
491 val |= state << AZX_ML_LCTL_SPA_SHIFT;
492 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
493 /* wait for CPA */
494 timeout = 50;
495 while (timeout) {
496 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
497 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
498 return 0;
499 timeout--;
500 udelay(10);
501 }
502
503 return -1;
504 }
505
intel_init_lctl(struct azx * chip)506 static void intel_init_lctl(struct azx *chip)
507 {
508 struct hdac_bus *bus = azx_bus(chip);
509 u32 val;
510 int ret;
511
512 /* 0. check lctl register value is correct or not */
513 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
514 /* only perform additional configurations if the SCF is initially based on 6MHz */
515 if ((val & AZX_ML_LCTL_SCF) != 0)
516 return;
517
518 /*
519 * Before operating on SPA, CPA must match SPA.
520 * Any deviation may result in undefined behavior.
521 */
522 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
523 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
524 return;
525
526 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
527 ret = intel_ml_lctl_set_power(chip, 0);
528 udelay(100);
529 if (ret)
530 goto set_spa;
531
532 /* 2. update SCF to select an audio clock different from 6MHz */
533 val &= ~AZX_ML_LCTL_SCF;
534 val |= intel_get_lctl_scf(chip);
535 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
536
537 set_spa:
538 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
539 intel_ml_lctl_set_power(chip, 1);
540 udelay(100);
541 }
542
hda_intel_init_chip(struct azx * chip,bool full_reset)543 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
544 {
545 struct hdac_bus *bus = azx_bus(chip);
546 struct pci_dev *pci = chip->pci;
547 u32 val;
548
549 snd_hdac_set_codec_wakeup(bus, true);
550 if (chip->driver_type == AZX_DRIVER_SKL) {
551 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
552 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
553 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
554 }
555 azx_init_chip(chip, full_reset);
556 if (chip->driver_type == AZX_DRIVER_SKL) {
557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
558 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
560 }
561
562 snd_hdac_set_codec_wakeup(bus, false);
563
564 /* reduce dma latency to avoid noise */
565 if (HDA_CONTROLLER_IS_APL(pci))
566 bxt_reduce_dma_latency(chip);
567
568 if (bus->mlcap != NULL)
569 intel_init_lctl(chip);
570 }
571
572 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)573 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
574 unsigned int pos)
575 {
576 struct snd_pcm_substream *substream = azx_dev->core.substream;
577 int stream = substream->stream;
578 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
579 int delay;
580
581 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
582 delay = pos - lpib_pos;
583 else
584 delay = lpib_pos - pos;
585 if (delay < 0) {
586 if (delay >= azx_dev->core.delay_negative_threshold)
587 delay = 0;
588 else
589 delay += azx_dev->core.bufsize;
590 }
591
592 if (delay >= azx_dev->core.period_bytes) {
593 dev_info(chip->card->dev,
594 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
595 delay, azx_dev->core.period_bytes);
596 delay = 0;
597 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
598 chip->get_delay[stream] = NULL;
599 }
600
601 return bytes_to_frames(substream->runtime, delay);
602 }
603
604 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
605
606 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)607 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
608 {
609 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
610 int ok;
611
612 ok = azx_position_ok(chip, azx_dev);
613 if (ok == 1) {
614 azx_dev->irq_pending = 0;
615 return ok;
616 } else if (ok == 0) {
617 /* bogus IRQ, process it later */
618 azx_dev->irq_pending = 1;
619 schedule_work(&hda->irq_pending_work);
620 }
621 return 0;
622 }
623
624 #define display_power(chip, enable) \
625 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
626
627 /*
628 * Check whether the current DMA position is acceptable for updating
629 * periods. Returns non-zero if it's OK.
630 *
631 * Many HD-audio controllers appear pretty inaccurate about
632 * the update-IRQ timing. The IRQ is issued before actually the
633 * data is processed. So, we need to process it afterwords in a
634 * workqueue.
635 *
636 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
637 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)638 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
639 {
640 struct snd_pcm_substream *substream = azx_dev->core.substream;
641 struct snd_pcm_runtime *runtime = substream->runtime;
642 int stream = substream->stream;
643 u32 wallclk;
644 unsigned int pos;
645 snd_pcm_uframes_t hwptr, target;
646
647 /*
648 * The value of the WALLCLK register is always 0
649 * on the Loongson controller, so we return directly.
650 */
651 if (chip->driver_type == AZX_DRIVER_LOONGSON)
652 return 1;
653
654 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
655 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
656 return -1; /* bogus (too early) interrupt */
657
658 if (chip->get_position[stream])
659 pos = chip->get_position[stream](chip, azx_dev);
660 else { /* use the position buffer as default */
661 pos = azx_get_pos_posbuf(chip, azx_dev);
662 if (!pos || pos == (u32)-1) {
663 dev_info(chip->card->dev,
664 "Invalid position buffer, using LPIB read method instead.\n");
665 chip->get_position[stream] = azx_get_pos_lpib;
666 if (chip->get_position[0] == azx_get_pos_lpib &&
667 chip->get_position[1] == azx_get_pos_lpib)
668 azx_bus(chip)->use_posbuf = false;
669 pos = azx_get_pos_lpib(chip, azx_dev);
670 chip->get_delay[stream] = NULL;
671 } else {
672 chip->get_position[stream] = azx_get_pos_posbuf;
673 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
674 chip->get_delay[stream] = azx_get_delay_from_lpib;
675 }
676 }
677
678 if (pos >= azx_dev->core.bufsize)
679 pos = 0;
680
681 if (WARN_ONCE(!azx_dev->core.period_bytes,
682 "hda-intel: zero azx_dev->period_bytes"))
683 return -1; /* this shouldn't happen! */
684 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
685 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
686 /* NG - it's below the first next period boundary */
687 return chip->bdl_pos_adj ? 0 : -1;
688 azx_dev->core.start_wallclk += wallclk;
689
690 if (azx_dev->core.no_period_wakeup)
691 return 1; /* OK, no need to check period boundary */
692
693 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
694 return 1; /* OK, already in hwptr updating process */
695
696 /* check whether the period gets really elapsed */
697 pos = bytes_to_frames(runtime, pos);
698 hwptr = runtime->hw_ptr_base + pos;
699 if (hwptr < runtime->status->hw_ptr)
700 hwptr += runtime->buffer_size;
701 target = runtime->hw_ptr_interrupt + runtime->period_size;
702 if (hwptr < target) {
703 /* too early wakeup, process it later */
704 return chip->bdl_pos_adj ? 0 : -1;
705 }
706
707 return 1; /* OK, it's fine */
708 }
709
710 /*
711 * The work for pending PCM period updates.
712 */
azx_irq_pending_work(struct work_struct * work)713 static void azx_irq_pending_work(struct work_struct *work)
714 {
715 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
716 struct azx *chip = &hda->chip;
717 struct hdac_bus *bus = azx_bus(chip);
718 struct hdac_stream *s;
719 int pending, ok;
720
721 if (!hda->irq_pending_warned) {
722 dev_info(chip->card->dev,
723 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
724 chip->card->number);
725 hda->irq_pending_warned = 1;
726 }
727
728 for (;;) {
729 pending = 0;
730 spin_lock_irq(&bus->reg_lock);
731 list_for_each_entry(s, &bus->stream_list, list) {
732 struct azx_dev *azx_dev = stream_to_azx_dev(s);
733 if (!azx_dev->irq_pending ||
734 !s->substream ||
735 !s->running)
736 continue;
737 ok = azx_position_ok(chip, azx_dev);
738 if (ok > 0) {
739 azx_dev->irq_pending = 0;
740 spin_unlock(&bus->reg_lock);
741 snd_pcm_period_elapsed(s->substream);
742 spin_lock(&bus->reg_lock);
743 } else if (ok < 0) {
744 pending = 0; /* too early */
745 } else
746 pending++;
747 }
748 spin_unlock_irq(&bus->reg_lock);
749 if (!pending)
750 return;
751 msleep(1);
752 }
753 }
754
755 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)756 static void azx_clear_irq_pending(struct azx *chip)
757 {
758 struct hdac_bus *bus = azx_bus(chip);
759 struct hdac_stream *s;
760
761 spin_lock_irq(&bus->reg_lock);
762 list_for_each_entry(s, &bus->stream_list, list) {
763 struct azx_dev *azx_dev = stream_to_azx_dev(s);
764 azx_dev->irq_pending = 0;
765 }
766 spin_unlock_irq(&bus->reg_lock);
767 }
768
azx_acquire_irq(struct azx * chip,int do_disconnect)769 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
770 {
771 struct hdac_bus *bus = azx_bus(chip);
772
773 if (request_irq(chip->pci->irq, azx_interrupt,
774 chip->msi ? 0 : IRQF_SHARED,
775 chip->card->irq_descr, chip)) {
776 dev_err(chip->card->dev,
777 "unable to grab IRQ %d, disabling device\n",
778 chip->pci->irq);
779 if (do_disconnect)
780 snd_card_disconnect(chip->card);
781 return -1;
782 }
783 bus->irq = chip->pci->irq;
784 chip->card->sync_irq = bus->irq;
785 pci_intx(chip->pci, !chip->msi);
786 return 0;
787 }
788
789 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)790 static unsigned int azx_via_get_position(struct azx *chip,
791 struct azx_dev *azx_dev)
792 {
793 unsigned int link_pos, mini_pos, bound_pos;
794 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
795 unsigned int fifo_size;
796
797 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
798 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
799 /* Playback, no problem using link position */
800 return link_pos;
801 }
802
803 /* Capture */
804 /* For new chipset,
805 * use mod to get the DMA position just like old chipset
806 */
807 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
808 mod_dma_pos %= azx_dev->core.period_bytes;
809
810 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
811
812 if (azx_dev->insufficient) {
813 /* Link position never gather than FIFO size */
814 if (link_pos <= fifo_size)
815 return 0;
816
817 azx_dev->insufficient = 0;
818 }
819
820 if (link_pos <= fifo_size)
821 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
822 else
823 mini_pos = link_pos - fifo_size;
824
825 /* Find nearest previous boudary */
826 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
827 mod_link_pos = link_pos % azx_dev->core.period_bytes;
828 if (mod_link_pos >= fifo_size)
829 bound_pos = link_pos - mod_link_pos;
830 else if (mod_dma_pos >= mod_mini_pos)
831 bound_pos = mini_pos - mod_mini_pos;
832 else {
833 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
834 if (bound_pos >= azx_dev->core.bufsize)
835 bound_pos = 0;
836 }
837
838 /* Calculate real DMA position we want */
839 return bound_pos + mod_dma_pos;
840 }
841
842 #define AMD_FIFO_SIZE 32
843
844 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)845 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
846 {
847 struct snd_pcm_substream *substream = azx_dev->core.substream;
848 struct snd_pcm_runtime *runtime = substream->runtime;
849 unsigned int pos, delay;
850
851 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
852 if (!runtime)
853 return pos;
854
855 runtime->delay = AMD_FIFO_SIZE;
856 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
857 if (azx_dev->insufficient) {
858 if (pos < delay) {
859 delay = pos;
860 runtime->delay = bytes_to_frames(runtime, pos);
861 } else {
862 azx_dev->insufficient = 0;
863 }
864 }
865
866 /* correct the DMA position for capture stream */
867 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
868 if (pos < delay)
869 pos += azx_dev->core.bufsize;
870 pos -= delay;
871 }
872
873 return pos;
874 }
875
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)876 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
877 unsigned int pos)
878 {
879 struct snd_pcm_substream *substream = azx_dev->core.substream;
880
881 /* just read back the calculated value in the above */
882 return substream->runtime->delay;
883 }
884
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)885 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
886 {
887 azx_stop_chip(chip);
888 if (!skip_link_reset)
889 azx_enter_link_reset(chip);
890 azx_clear_irq_pending(chip);
891 display_power(chip, false);
892 }
893
894 #ifdef CONFIG_PM
895 static DEFINE_MUTEX(card_list_lock);
896 static LIST_HEAD(card_list);
897
azx_shutdown_chip(struct azx * chip)898 static void azx_shutdown_chip(struct azx *chip)
899 {
900 __azx_shutdown_chip(chip, false);
901 }
902
azx_add_card_list(struct azx * chip)903 static void azx_add_card_list(struct azx *chip)
904 {
905 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
906 mutex_lock(&card_list_lock);
907 list_add(&hda->list, &card_list);
908 mutex_unlock(&card_list_lock);
909 }
910
azx_del_card_list(struct azx * chip)911 static void azx_del_card_list(struct azx *chip)
912 {
913 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
914 mutex_lock(&card_list_lock);
915 list_del_init(&hda->list);
916 mutex_unlock(&card_list_lock);
917 }
918
919 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)920 static int param_set_xint(const char *val, const struct kernel_param *kp)
921 {
922 struct hda_intel *hda;
923 struct azx *chip;
924 int prev = power_save;
925 int ret = param_set_int(val, kp);
926
927 if (ret || prev == power_save)
928 return ret;
929
930 mutex_lock(&card_list_lock);
931 list_for_each_entry(hda, &card_list, list) {
932 chip = &hda->chip;
933 if (!hda->probe_continued || chip->disabled)
934 continue;
935 snd_hda_set_power_save(&chip->bus, power_save * 1000);
936 }
937 mutex_unlock(&card_list_lock);
938 return 0;
939 }
940
941 /*
942 * power management
943 */
azx_is_pm_ready(struct snd_card * card)944 static bool azx_is_pm_ready(struct snd_card *card)
945 {
946 struct azx *chip;
947 struct hda_intel *hda;
948
949 if (!card)
950 return false;
951 chip = card->private_data;
952 hda = container_of(chip, struct hda_intel, chip);
953 if (chip->disabled || hda->init_failed || !chip->running)
954 return false;
955 return true;
956 }
957
__azx_runtime_resume(struct azx * chip)958 static void __azx_runtime_resume(struct azx *chip)
959 {
960 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
961 struct hdac_bus *bus = azx_bus(chip);
962 struct hda_codec *codec;
963 int status;
964
965 display_power(chip, true);
966 if (hda->need_i915_power)
967 snd_hdac_i915_set_bclk(bus);
968
969 /* Read STATESTS before controller reset */
970 status = azx_readw(chip, STATESTS);
971
972 azx_init_pci(chip);
973 hda_intel_init_chip(chip, true);
974
975 /* Avoid codec resume if runtime resume is for system suspend */
976 if (!chip->pm_prepared) {
977 list_for_each_codec(codec, &chip->bus) {
978 if (codec->relaxed_resume)
979 continue;
980
981 if (codec->forced_resume || (status & (1 << codec->addr)))
982 pm_request_resume(hda_codec_dev(codec));
983 }
984 }
985
986 /* power down again for link-controlled chips */
987 if (!hda->need_i915_power)
988 display_power(chip, false);
989 }
990
991 #ifdef CONFIG_PM_SLEEP
azx_prepare(struct device * dev)992 static int azx_prepare(struct device *dev)
993 {
994 struct snd_card *card = dev_get_drvdata(dev);
995 struct azx *chip;
996
997 if (!azx_is_pm_ready(card))
998 return 0;
999
1000 chip = card->private_data;
1001 chip->pm_prepared = 1;
1002 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1003
1004 flush_work(&azx_bus(chip)->unsol_work);
1005
1006 /* HDA controller always requires different WAKEEN for runtime suspend
1007 * and system suspend, so don't use direct-complete here.
1008 */
1009 return 0;
1010 }
1011
azx_complete(struct device * dev)1012 static void azx_complete(struct device *dev)
1013 {
1014 struct snd_card *card = dev_get_drvdata(dev);
1015 struct azx *chip;
1016
1017 if (!azx_is_pm_ready(card))
1018 return;
1019
1020 chip = card->private_data;
1021 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1022 chip->pm_prepared = 0;
1023 }
1024
azx_suspend(struct device * dev)1025 static int azx_suspend(struct device *dev)
1026 {
1027 struct snd_card *card = dev_get_drvdata(dev);
1028 struct azx *chip;
1029 struct hdac_bus *bus;
1030
1031 if (!azx_is_pm_ready(card))
1032 return 0;
1033
1034 chip = card->private_data;
1035 bus = azx_bus(chip);
1036 azx_shutdown_chip(chip);
1037 if (bus->irq >= 0) {
1038 free_irq(bus->irq, chip);
1039 bus->irq = -1;
1040 chip->card->sync_irq = -1;
1041 }
1042
1043 if (chip->msi)
1044 pci_disable_msi(chip->pci);
1045
1046 trace_azx_suspend(chip);
1047 return 0;
1048 }
1049
azx_resume(struct device * dev)1050 static int azx_resume(struct device *dev)
1051 {
1052 struct snd_card *card = dev_get_drvdata(dev);
1053 struct azx *chip;
1054
1055 if (!azx_is_pm_ready(card))
1056 return 0;
1057
1058 chip = card->private_data;
1059 if (chip->msi)
1060 if (pci_enable_msi(chip->pci) < 0)
1061 chip->msi = 0;
1062 if (azx_acquire_irq(chip, 1) < 0)
1063 return -EIO;
1064
1065 __azx_runtime_resume(chip);
1066
1067 trace_azx_resume(chip);
1068 return 0;
1069 }
1070
1071 /* put codec down to D3 at hibernation for Intel SKL+;
1072 * otherwise BIOS may still access the codec and screw up the driver
1073 */
azx_freeze_noirq(struct device * dev)1074 static int azx_freeze_noirq(struct device *dev)
1075 {
1076 struct snd_card *card = dev_get_drvdata(dev);
1077 struct azx *chip = card->private_data;
1078 struct pci_dev *pci = to_pci_dev(dev);
1079
1080 if (!azx_is_pm_ready(card))
1081 return 0;
1082 if (chip->driver_type == AZX_DRIVER_SKL)
1083 pci_set_power_state(pci, PCI_D3hot);
1084
1085 return 0;
1086 }
1087
azx_thaw_noirq(struct device * dev)1088 static int azx_thaw_noirq(struct device *dev)
1089 {
1090 struct snd_card *card = dev_get_drvdata(dev);
1091 struct azx *chip = card->private_data;
1092 struct pci_dev *pci = to_pci_dev(dev);
1093
1094 if (!azx_is_pm_ready(card))
1095 return 0;
1096 if (chip->driver_type == AZX_DRIVER_SKL)
1097 pci_set_power_state(pci, PCI_D0);
1098
1099 return 0;
1100 }
1101 #endif /* CONFIG_PM_SLEEP */
1102
azx_runtime_suspend(struct device * dev)1103 static int azx_runtime_suspend(struct device *dev)
1104 {
1105 struct snd_card *card = dev_get_drvdata(dev);
1106 struct azx *chip;
1107
1108 if (!azx_is_pm_ready(card))
1109 return 0;
1110 chip = card->private_data;
1111
1112 /* enable controller wake up event */
1113 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1114
1115 azx_shutdown_chip(chip);
1116 trace_azx_runtime_suspend(chip);
1117 return 0;
1118 }
1119
azx_runtime_resume(struct device * dev)1120 static int azx_runtime_resume(struct device *dev)
1121 {
1122 struct snd_card *card = dev_get_drvdata(dev);
1123 struct azx *chip;
1124
1125 if (!azx_is_pm_ready(card))
1126 return 0;
1127 chip = card->private_data;
1128 __azx_runtime_resume(chip);
1129
1130 /* disable controller Wake Up event*/
1131 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1132
1133 trace_azx_runtime_resume(chip);
1134 return 0;
1135 }
1136
azx_runtime_idle(struct device * dev)1137 static int azx_runtime_idle(struct device *dev)
1138 {
1139 struct snd_card *card = dev_get_drvdata(dev);
1140 struct azx *chip;
1141 struct hda_intel *hda;
1142
1143 if (!card)
1144 return 0;
1145
1146 chip = card->private_data;
1147 hda = container_of(chip, struct hda_intel, chip);
1148 if (chip->disabled || hda->init_failed)
1149 return 0;
1150
1151 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1152 azx_bus(chip)->codec_powered || !chip->running)
1153 return -EBUSY;
1154
1155 /* ELD notification gets broken when HD-audio bus is off */
1156 if (needs_eld_notify_link(chip))
1157 return -EBUSY;
1158
1159 return 0;
1160 }
1161
1162 static const struct dev_pm_ops azx_pm = {
1163 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1164 #ifdef CONFIG_PM_SLEEP
1165 .prepare = azx_prepare,
1166 .complete = azx_complete,
1167 .freeze_noirq = azx_freeze_noirq,
1168 .thaw_noirq = azx_thaw_noirq,
1169 #endif
1170 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1171 };
1172
1173 #define AZX_PM_OPS &azx_pm
1174 #else
1175 #define azx_add_card_list(chip) /* NOP */
1176 #define azx_del_card_list(chip) /* NOP */
1177 #define AZX_PM_OPS NULL
1178 #endif /* CONFIG_PM */
1179
1180
1181 static int azx_probe_continue(struct azx *chip);
1182
1183 #ifdef SUPPORT_VGA_SWITCHEROO
1184 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1185
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1186 static void azx_vs_set_state(struct pci_dev *pci,
1187 enum vga_switcheroo_state state)
1188 {
1189 struct snd_card *card = pci_get_drvdata(pci);
1190 struct azx *chip = card->private_data;
1191 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1192 struct hda_codec *codec;
1193 bool disabled;
1194
1195 wait_for_completion(&hda->probe_wait);
1196 if (hda->init_failed)
1197 return;
1198
1199 disabled = (state == VGA_SWITCHEROO_OFF);
1200 if (chip->disabled == disabled)
1201 return;
1202
1203 if (!hda->probe_continued) {
1204 chip->disabled = disabled;
1205 if (!disabled) {
1206 dev_info(chip->card->dev,
1207 "Start delayed initialization\n");
1208 if (azx_probe_continue(chip) < 0)
1209 dev_err(chip->card->dev, "initialization error\n");
1210 }
1211 } else {
1212 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1213 disabled ? "Disabling" : "Enabling");
1214 if (disabled) {
1215 list_for_each_codec(codec, &chip->bus) {
1216 pm_runtime_suspend(hda_codec_dev(codec));
1217 pm_runtime_disable(hda_codec_dev(codec));
1218 }
1219 pm_runtime_suspend(card->dev);
1220 pm_runtime_disable(card->dev);
1221 /* when we get suspended by vga_switcheroo we end up in D3cold,
1222 * however we have no ACPI handle, so pci/acpi can't put us there,
1223 * put ourselves there */
1224 pci->current_state = PCI_D3cold;
1225 chip->disabled = true;
1226 if (snd_hda_lock_devices(&chip->bus))
1227 dev_warn(chip->card->dev,
1228 "Cannot lock devices!\n");
1229 } else {
1230 snd_hda_unlock_devices(&chip->bus);
1231 chip->disabled = false;
1232 pm_runtime_enable(card->dev);
1233 list_for_each_codec(codec, &chip->bus) {
1234 pm_runtime_enable(hda_codec_dev(codec));
1235 pm_runtime_resume(hda_codec_dev(codec));
1236 }
1237 }
1238 }
1239 }
1240
azx_vs_can_switch(struct pci_dev * pci)1241 static bool azx_vs_can_switch(struct pci_dev *pci)
1242 {
1243 struct snd_card *card = pci_get_drvdata(pci);
1244 struct azx *chip = card->private_data;
1245 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1246
1247 wait_for_completion(&hda->probe_wait);
1248 if (hda->init_failed)
1249 return false;
1250 if (chip->disabled || !hda->probe_continued)
1251 return true;
1252 if (snd_hda_lock_devices(&chip->bus))
1253 return false;
1254 snd_hda_unlock_devices(&chip->bus);
1255 return true;
1256 }
1257
1258 /*
1259 * The discrete GPU cannot power down unless the HDA controller runtime
1260 * suspends, so activate runtime PM on codecs even if power_save == 0.
1261 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1262 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1263 {
1264 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1265 struct hda_codec *codec;
1266
1267 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1268 list_for_each_codec(codec, &chip->bus)
1269 codec->auto_runtime_pm = 1;
1270 /* reset the power save setup */
1271 if (chip->running)
1272 set_default_power_save(chip);
1273 }
1274 }
1275
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1276 static void azx_vs_gpu_bound(struct pci_dev *pci,
1277 enum vga_switcheroo_client_id client_id)
1278 {
1279 struct snd_card *card = pci_get_drvdata(pci);
1280 struct azx *chip = card->private_data;
1281
1282 if (client_id == VGA_SWITCHEROO_DIS)
1283 chip->bus.keep_power = 0;
1284 setup_vga_switcheroo_runtime_pm(chip);
1285 }
1286
init_vga_switcheroo(struct azx * chip)1287 static void init_vga_switcheroo(struct azx *chip)
1288 {
1289 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1290 struct pci_dev *p = get_bound_vga(chip->pci);
1291 struct pci_dev *parent;
1292 if (p) {
1293 dev_info(chip->card->dev,
1294 "Handle vga_switcheroo audio client\n");
1295 hda->use_vga_switcheroo = 1;
1296
1297 /* cleared in either gpu_bound op or codec probe, or when its
1298 * upstream port has _PR3 (i.e. dGPU).
1299 */
1300 parent = pci_upstream_bridge(p);
1301 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1302 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1303 pci_dev_put(p);
1304 }
1305 }
1306
1307 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1308 .set_gpu_state = azx_vs_set_state,
1309 .can_switch = azx_vs_can_switch,
1310 .gpu_bound = azx_vs_gpu_bound,
1311 };
1312
register_vga_switcheroo(struct azx * chip)1313 static int register_vga_switcheroo(struct azx *chip)
1314 {
1315 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1316 struct pci_dev *p;
1317 int err;
1318
1319 if (!hda->use_vga_switcheroo)
1320 return 0;
1321
1322 p = get_bound_vga(chip->pci);
1323 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1324 pci_dev_put(p);
1325
1326 if (err < 0)
1327 return err;
1328 hda->vga_switcheroo_registered = 1;
1329
1330 return 0;
1331 }
1332 #else
1333 #define init_vga_switcheroo(chip) /* NOP */
1334 #define register_vga_switcheroo(chip) 0
1335 #define check_hdmi_disabled(pci) false
1336 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1337 #endif /* SUPPORT_VGA_SWITCHER */
1338
1339 /*
1340 * destructor
1341 */
azx_free(struct azx * chip)1342 static void azx_free(struct azx *chip)
1343 {
1344 struct pci_dev *pci = chip->pci;
1345 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1346 struct hdac_bus *bus = azx_bus(chip);
1347
1348 if (hda->freed)
1349 return;
1350
1351 if (azx_has_pm_runtime(chip) && chip->running) {
1352 pm_runtime_get_noresume(&pci->dev);
1353 pm_runtime_forbid(&pci->dev);
1354 pm_runtime_dont_use_autosuspend(&pci->dev);
1355 }
1356
1357 chip->running = 0;
1358
1359 azx_del_card_list(chip);
1360
1361 hda->init_failed = 1; /* to be sure */
1362 complete_all(&hda->probe_wait);
1363
1364 if (use_vga_switcheroo(hda)) {
1365 if (chip->disabled && hda->probe_continued)
1366 snd_hda_unlock_devices(&chip->bus);
1367 if (hda->vga_switcheroo_registered)
1368 vga_switcheroo_unregister_client(chip->pci);
1369 }
1370
1371 if (bus->chip_init) {
1372 azx_clear_irq_pending(chip);
1373 azx_stop_all_streams(chip);
1374 azx_stop_chip(chip);
1375 }
1376
1377 if (bus->irq >= 0)
1378 free_irq(bus->irq, (void*)chip);
1379
1380 azx_free_stream_pages(chip);
1381 azx_free_streams(chip);
1382 snd_hdac_bus_exit(bus);
1383
1384 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1385 release_firmware(chip->fw);
1386 #endif
1387 display_power(chip, false);
1388
1389 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1390 snd_hdac_i915_exit(bus);
1391
1392 hda->freed = 1;
1393 }
1394
azx_dev_disconnect(struct snd_device * device)1395 static int azx_dev_disconnect(struct snd_device *device)
1396 {
1397 struct azx *chip = device->device_data;
1398 struct hdac_bus *bus = azx_bus(chip);
1399
1400 chip->bus.shutdown = 1;
1401 cancel_work_sync(&bus->unsol_work);
1402
1403 return 0;
1404 }
1405
azx_dev_free(struct snd_device * device)1406 static int azx_dev_free(struct snd_device *device)
1407 {
1408 azx_free(device->device_data);
1409 return 0;
1410 }
1411
1412 #ifdef SUPPORT_VGA_SWITCHEROO
1413 #ifdef CONFIG_ACPI
1414 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1415 static bool atpx_present(void)
1416 {
1417 struct pci_dev *pdev = NULL;
1418 acpi_handle dhandle, atpx_handle;
1419 acpi_status status;
1420
1421 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1422 dhandle = ACPI_HANDLE(&pdev->dev);
1423 if (dhandle) {
1424 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1425 if (ACPI_SUCCESS(status)) {
1426 pci_dev_put(pdev);
1427 return true;
1428 }
1429 }
1430 }
1431 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1432 dhandle = ACPI_HANDLE(&pdev->dev);
1433 if (dhandle) {
1434 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1435 if (ACPI_SUCCESS(status)) {
1436 pci_dev_put(pdev);
1437 return true;
1438 }
1439 }
1440 }
1441 return false;
1442 }
1443 #else
atpx_present(void)1444 static bool atpx_present(void)
1445 {
1446 return false;
1447 }
1448 #endif
1449
1450 /*
1451 * Check of disabled HDMI controller by vga_switcheroo
1452 */
get_bound_vga(struct pci_dev * pci)1453 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1454 {
1455 struct pci_dev *p;
1456
1457 /* check only discrete GPU */
1458 switch (pci->vendor) {
1459 case PCI_VENDOR_ID_ATI:
1460 case PCI_VENDOR_ID_AMD:
1461 if (pci->devfn == 1) {
1462 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1463 pci->bus->number, 0);
1464 if (p) {
1465 /* ATPX is in the integrated GPU's ACPI namespace
1466 * rather than the dGPU's namespace. However,
1467 * the dGPU is the one who is involved in
1468 * vgaswitcheroo.
1469 */
1470 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1471 (atpx_present() || apple_gmux_detect(NULL, NULL)))
1472 return p;
1473 pci_dev_put(p);
1474 }
1475 }
1476 break;
1477 case PCI_VENDOR_ID_NVIDIA:
1478 if (pci->devfn == 1) {
1479 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1480 pci->bus->number, 0);
1481 if (p) {
1482 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1483 return p;
1484 pci_dev_put(p);
1485 }
1486 }
1487 break;
1488 }
1489 return NULL;
1490 }
1491
check_hdmi_disabled(struct pci_dev * pci)1492 static bool check_hdmi_disabled(struct pci_dev *pci)
1493 {
1494 bool vga_inactive = false;
1495 struct pci_dev *p = get_bound_vga(pci);
1496
1497 if (p) {
1498 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1499 vga_inactive = true;
1500 pci_dev_put(p);
1501 }
1502 return vga_inactive;
1503 }
1504 #endif /* SUPPORT_VGA_SWITCHEROO */
1505
1506 /*
1507 * allow/deny-listing for position_fix
1508 */
1509 static const struct snd_pci_quirk position_fix_list[] = {
1510 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1520 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1521 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1522 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1523 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1524 {}
1525 };
1526
check_position_fix(struct azx * chip,int fix)1527 static int check_position_fix(struct azx *chip, int fix)
1528 {
1529 const struct snd_pci_quirk *q;
1530
1531 switch (fix) {
1532 case POS_FIX_AUTO:
1533 case POS_FIX_LPIB:
1534 case POS_FIX_POSBUF:
1535 case POS_FIX_VIACOMBO:
1536 case POS_FIX_COMBO:
1537 case POS_FIX_SKL:
1538 case POS_FIX_FIFO:
1539 return fix;
1540 }
1541
1542 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1543 if (q) {
1544 dev_info(chip->card->dev,
1545 "position_fix set to %d for device %04x:%04x\n",
1546 q->value, q->subvendor, q->subdevice);
1547 return q->value;
1548 }
1549
1550 /* Check VIA/ATI HD Audio Controller exist */
1551 if (chip->driver_type == AZX_DRIVER_VIA) {
1552 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1553 return POS_FIX_VIACOMBO;
1554 }
1555 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1556 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1557 return POS_FIX_FIFO;
1558 }
1559 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1560 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1561 return POS_FIX_LPIB;
1562 }
1563 if (chip->driver_type == AZX_DRIVER_SKL) {
1564 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1565 return POS_FIX_SKL;
1566 }
1567 return POS_FIX_AUTO;
1568 }
1569
assign_position_fix(struct azx * chip,int fix)1570 static void assign_position_fix(struct azx *chip, int fix)
1571 {
1572 static const azx_get_pos_callback_t callbacks[] = {
1573 [POS_FIX_AUTO] = NULL,
1574 [POS_FIX_LPIB] = azx_get_pos_lpib,
1575 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1576 [POS_FIX_VIACOMBO] = azx_via_get_position,
1577 [POS_FIX_COMBO] = azx_get_pos_lpib,
1578 [POS_FIX_SKL] = azx_get_pos_posbuf,
1579 [POS_FIX_FIFO] = azx_get_pos_fifo,
1580 };
1581
1582 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1583
1584 /* combo mode uses LPIB only for playback */
1585 if (fix == POS_FIX_COMBO)
1586 chip->get_position[1] = NULL;
1587
1588 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1589 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1590 chip->get_delay[0] = chip->get_delay[1] =
1591 azx_get_delay_from_lpib;
1592 }
1593
1594 if (fix == POS_FIX_FIFO)
1595 chip->get_delay[0] = chip->get_delay[1] =
1596 azx_get_delay_from_fifo;
1597 }
1598
1599 /*
1600 * deny-lists for probe_mask
1601 */
1602 static const struct snd_pci_quirk probe_mask_list[] = {
1603 /* Thinkpad often breaks the controller communication when accessing
1604 * to the non-working (or non-existing) modem codec slot.
1605 */
1606 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1607 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1608 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1609 /* broken BIOS */
1610 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1611 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1612 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1613 /* forced codec slots */
1614 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1615 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1616 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1617 /* WinFast VP200 H (Teradici) user reported broken communication */
1618 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1619 {}
1620 };
1621
1622 #define AZX_FORCE_CODEC_MASK 0x100
1623
check_probe_mask(struct azx * chip,int dev)1624 static void check_probe_mask(struct azx *chip, int dev)
1625 {
1626 const struct snd_pci_quirk *q;
1627
1628 chip->codec_probe_mask = probe_mask[dev];
1629 if (chip->codec_probe_mask == -1) {
1630 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1631 if (q) {
1632 dev_info(chip->card->dev,
1633 "probe_mask set to 0x%x for device %04x:%04x\n",
1634 q->value, q->subvendor, q->subdevice);
1635 chip->codec_probe_mask = q->value;
1636 }
1637 }
1638
1639 /* check forced option */
1640 if (chip->codec_probe_mask != -1 &&
1641 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1642 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1643 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1644 (int)azx_bus(chip)->codec_mask);
1645 }
1646 }
1647
1648 /*
1649 * allow/deny-list for enable_msi
1650 */
1651 static const struct snd_pci_quirk msi_deny_list[] = {
1652 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1653 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1654 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1655 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1656 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1657 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1658 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1659 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1660 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1661 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1662 {}
1663 };
1664
check_msi(struct azx * chip)1665 static void check_msi(struct azx *chip)
1666 {
1667 const struct snd_pci_quirk *q;
1668
1669 if (enable_msi >= 0) {
1670 chip->msi = !!enable_msi;
1671 return;
1672 }
1673 chip->msi = 1; /* enable MSI as default */
1674 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1675 if (q) {
1676 dev_info(chip->card->dev,
1677 "msi for device %04x:%04x set to %d\n",
1678 q->subvendor, q->subdevice, q->value);
1679 chip->msi = q->value;
1680 return;
1681 }
1682
1683 /* NVidia chipsets seem to cause troubles with MSI */
1684 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1685 dev_info(chip->card->dev, "Disabling MSI\n");
1686 chip->msi = 0;
1687 }
1688 }
1689
1690 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1691 static void azx_check_snoop_available(struct azx *chip)
1692 {
1693 int snoop = hda_snoop;
1694
1695 if (snoop >= 0) {
1696 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1697 snoop ? "snoop" : "non-snoop");
1698 chip->snoop = snoop;
1699 chip->uc_buffer = !snoop;
1700 return;
1701 }
1702
1703 snoop = true;
1704 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1705 chip->driver_type == AZX_DRIVER_VIA) {
1706 /* force to non-snoop mode for a new VIA controller
1707 * when BIOS is set
1708 */
1709 u8 val;
1710 pci_read_config_byte(chip->pci, 0x42, &val);
1711 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1712 chip->pci->revision == 0x20))
1713 snoop = false;
1714 }
1715
1716 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1717 snoop = false;
1718
1719 #ifdef CONFIG_X86
1720 /* check the presence of DMA ops (i.e. IOMMU), disable snoop conditionally */
1721 if ((chip->driver_caps & AZX_DCAPS_AMD_ALLOC_FIX) &&
1722 !get_dma_ops(chip->card->dev))
1723 snoop = false;
1724 #endif
1725
1726 chip->snoop = snoop;
1727 if (!snoop) {
1728 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1729 /* C-Media requires non-cached pages only for CORB/RIRB */
1730 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1731 chip->uc_buffer = true;
1732 }
1733 }
1734
azx_probe_work(struct work_struct * work)1735 static void azx_probe_work(struct work_struct *work)
1736 {
1737 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1738 azx_probe_continue(&hda->chip);
1739 }
1740
default_bdl_pos_adj(struct azx * chip)1741 static int default_bdl_pos_adj(struct azx *chip)
1742 {
1743 /* some exceptions: Atoms seem problematic with value 1 */
1744 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1745 switch (chip->pci->device) {
1746 case PCI_DEVICE_ID_INTEL_HDA_BYT:
1747 case PCI_DEVICE_ID_INTEL_HDA_BSW:
1748 return 32;
1749 case PCI_DEVICE_ID_INTEL_HDA_APL:
1750 return 64;
1751 }
1752 }
1753
1754 switch (chip->driver_type) {
1755 /*
1756 * increase the bdl size for Glenfly Gpus for hardware
1757 * limitation on hdac interrupt interval
1758 */
1759 case AZX_DRIVER_GFHDMI:
1760 return 128;
1761 case AZX_DRIVER_ICH:
1762 case AZX_DRIVER_PCH:
1763 return 1;
1764 default:
1765 return 32;
1766 }
1767 }
1768
1769 /*
1770 * constructor
1771 */
1772 static const struct hda_controller_ops pci_hda_ops;
1773
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1774 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1775 int dev, unsigned int driver_caps,
1776 struct azx **rchip)
1777 {
1778 static const struct snd_device_ops ops = {
1779 .dev_disconnect = azx_dev_disconnect,
1780 .dev_free = azx_dev_free,
1781 };
1782 struct hda_intel *hda;
1783 struct azx *chip;
1784 int err;
1785
1786 *rchip = NULL;
1787
1788 err = pcim_enable_device(pci);
1789 if (err < 0)
1790 return err;
1791
1792 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1793 if (!hda)
1794 return -ENOMEM;
1795
1796 chip = &hda->chip;
1797 mutex_init(&chip->open_mutex);
1798 chip->card = card;
1799 chip->pci = pci;
1800 chip->ops = &pci_hda_ops;
1801 chip->driver_caps = driver_caps;
1802 chip->driver_type = driver_caps & 0xff;
1803 check_msi(chip);
1804 chip->dev_index = dev;
1805 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1806 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1807 INIT_LIST_HEAD(&chip->pcm_list);
1808 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1809 INIT_LIST_HEAD(&hda->list);
1810 init_vga_switcheroo(chip);
1811 init_completion(&hda->probe_wait);
1812
1813 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1814
1815 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1816 chip->fallback_to_single_cmd = 1;
1817 else /* explicitly set to single_cmd or not */
1818 chip->single_cmd = single_cmd;
1819
1820 azx_check_snoop_available(chip);
1821
1822 if (bdl_pos_adj[dev] < 0)
1823 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1824 else
1825 chip->bdl_pos_adj = bdl_pos_adj[dev];
1826
1827 err = azx_bus_init(chip, model[dev]);
1828 if (err < 0)
1829 return err;
1830
1831 /* use the non-cached pages in non-snoop mode */
1832 if (!azx_snoop(chip))
1833 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
1834
1835 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1836 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1837 chip->bus.core.needs_damn_long_delay = 1;
1838 }
1839
1840 check_probe_mask(chip, dev);
1841
1842 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1843 if (err < 0) {
1844 dev_err(card->dev, "Error creating device [card]!\n");
1845 azx_free(chip);
1846 return err;
1847 }
1848
1849 /* continue probing in work context as may trigger request module */
1850 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1851
1852 *rchip = chip;
1853
1854 return 0;
1855 }
1856
azx_first_init(struct azx * chip)1857 static int azx_first_init(struct azx *chip)
1858 {
1859 int dev = chip->dev_index;
1860 struct pci_dev *pci = chip->pci;
1861 struct snd_card *card = chip->card;
1862 struct hdac_bus *bus = azx_bus(chip);
1863 int err;
1864 unsigned short gcap;
1865 unsigned int dma_bits = 64;
1866
1867 #if BITS_PER_LONG != 64
1868 /* Fix up base address on ULI M5461 */
1869 if (chip->driver_type == AZX_DRIVER_ULI) {
1870 u16 tmp3;
1871 pci_read_config_word(pci, 0x40, &tmp3);
1872 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1873 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1874 }
1875 #endif
1876 /*
1877 * Fix response write request not synced to memory when handle
1878 * hdac interrupt on Glenfly Gpus
1879 */
1880 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1881 bus->polling_mode = 1;
1882
1883 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1884 bus->polling_mode = 1;
1885 bus->not_use_interrupts = 1;
1886 bus->access_sdnctl_in_dword = 1;
1887 }
1888
1889 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1890 if (err < 0)
1891 return err;
1892
1893 bus->addr = pci_resource_start(pci, 0);
1894 bus->remap_addr = pcim_iomap_table(pci)[0];
1895
1896 if (chip->driver_type == AZX_DRIVER_SKL)
1897 snd_hdac_bus_parse_capabilities(bus);
1898
1899 /*
1900 * Some Intel CPUs has always running timer (ART) feature and
1901 * controller may have Global time sync reporting capability, so
1902 * check both of these before declaring synchronized time reporting
1903 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1904 */
1905 chip->gts_present = false;
1906
1907 #ifdef CONFIG_X86
1908 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1909 chip->gts_present = true;
1910 #endif
1911
1912 if (chip->msi) {
1913 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1914 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1915 pci->no_64bit_msi = true;
1916 }
1917 if (pci_enable_msi(pci) < 0)
1918 chip->msi = 0;
1919 }
1920
1921 pci_set_master(pci);
1922
1923 gcap = azx_readw(chip, GCAP);
1924 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1925
1926 /* AMD devices support 40 or 48bit DMA, take the safe one */
1927 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1928 dma_bits = 40;
1929
1930 /* disable SB600 64bit support for safety */
1931 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1932 struct pci_dev *p_smbus;
1933 dma_bits = 40;
1934 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1935 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1936 NULL);
1937 if (p_smbus) {
1938 if (p_smbus->revision < 0x30)
1939 gcap &= ~AZX_GCAP_64OK;
1940 pci_dev_put(p_smbus);
1941 }
1942 }
1943
1944 /* NVidia hardware normally only supports up to 40 bits of DMA */
1945 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1946 dma_bits = 40;
1947
1948 /* disable 64bit DMA address on some devices */
1949 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1950 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1951 gcap &= ~AZX_GCAP_64OK;
1952 }
1953
1954 /* disable buffer size rounding to 128-byte multiples if supported */
1955 if (align_buffer_size >= 0)
1956 chip->align_buffer_size = !!align_buffer_size;
1957 else {
1958 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1959 chip->align_buffer_size = 0;
1960 else
1961 chip->align_buffer_size = 1;
1962 }
1963
1964 /* allow 64bit DMA address if supported by H/W */
1965 if (!(gcap & AZX_GCAP_64OK))
1966 dma_bits = 32;
1967 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1968 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1969 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1970
1971 /* read number of streams from GCAP register instead of using
1972 * hardcoded value
1973 */
1974 chip->capture_streams = (gcap >> 8) & 0x0f;
1975 chip->playback_streams = (gcap >> 12) & 0x0f;
1976 if (!chip->playback_streams && !chip->capture_streams) {
1977 /* gcap didn't give any info, switching to old method */
1978
1979 switch (chip->driver_type) {
1980 case AZX_DRIVER_ULI:
1981 chip->playback_streams = ULI_NUM_PLAYBACK;
1982 chip->capture_streams = ULI_NUM_CAPTURE;
1983 break;
1984 case AZX_DRIVER_ATIHDMI:
1985 case AZX_DRIVER_ATIHDMI_NS:
1986 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1987 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1988 break;
1989 case AZX_DRIVER_GFHDMI:
1990 case AZX_DRIVER_GENERIC:
1991 default:
1992 chip->playback_streams = ICH6_NUM_PLAYBACK;
1993 chip->capture_streams = ICH6_NUM_CAPTURE;
1994 break;
1995 }
1996 }
1997 chip->capture_index_offset = 0;
1998 chip->playback_index_offset = chip->capture_streams;
1999 chip->num_streams = chip->playback_streams + chip->capture_streams;
2000
2001 /* sanity check for the SDxCTL.STRM field overflow */
2002 if (chip->num_streams > 15 &&
2003 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2004 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2005 "forcing separate stream tags", chip->num_streams);
2006 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2007 }
2008
2009 /* initialize streams */
2010 err = azx_init_streams(chip);
2011 if (err < 0)
2012 return err;
2013
2014 err = azx_alloc_stream_pages(chip);
2015 if (err < 0)
2016 return err;
2017
2018 /* initialize chip */
2019 azx_init_pci(chip);
2020
2021 snd_hdac_i915_set_bclk(bus);
2022
2023 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2024
2025 /* codec detection */
2026 if (!azx_bus(chip)->codec_mask) {
2027 dev_err(card->dev, "no codecs found!\n");
2028 /* keep running the rest for the runtime PM */
2029 }
2030
2031 if (azx_acquire_irq(chip, 0) < 0)
2032 return -EBUSY;
2033
2034 strcpy(card->driver, "HDA-Intel");
2035 strscpy(card->shortname, driver_short_names[chip->driver_type],
2036 sizeof(card->shortname));
2037 snprintf(card->longname, sizeof(card->longname),
2038 "%s at 0x%lx irq %i",
2039 card->shortname, bus->addr, bus->irq);
2040
2041 return 0;
2042 }
2043
2044 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2045 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2046 static void azx_firmware_cb(const struct firmware *fw, void *context)
2047 {
2048 struct snd_card *card = context;
2049 struct azx *chip = card->private_data;
2050
2051 if (fw)
2052 chip->fw = fw;
2053 else
2054 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2055 if (!chip->disabled) {
2056 /* continue probing */
2057 azx_probe_continue(chip);
2058 }
2059 }
2060 #endif
2061
disable_msi_reset_irq(struct azx * chip)2062 static int disable_msi_reset_irq(struct azx *chip)
2063 {
2064 struct hdac_bus *bus = azx_bus(chip);
2065 int err;
2066
2067 free_irq(bus->irq, chip);
2068 bus->irq = -1;
2069 chip->card->sync_irq = -1;
2070 pci_disable_msi(chip->pci);
2071 chip->msi = 0;
2072 err = azx_acquire_irq(chip, 1);
2073 if (err < 0)
2074 return err;
2075
2076 return 0;
2077 }
2078
2079 /* Denylist for skipping the whole probe:
2080 * some HD-audio PCI entries are exposed without any codecs, and such devices
2081 * should be ignored from the beginning.
2082 */
2083 static const struct pci_device_id driver_denylist[] = {
2084 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2085 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2086 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2087 {}
2088 };
2089
2090 static const struct hda_controller_ops pci_hda_ops = {
2091 .disable_msi_reset_irq = disable_msi_reset_irq,
2092 .position_check = azx_position_check,
2093 };
2094
2095 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2096
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2097 static int azx_probe(struct pci_dev *pci,
2098 const struct pci_device_id *pci_id)
2099 {
2100 struct snd_card *card;
2101 struct hda_intel *hda;
2102 struct azx *chip;
2103 bool schedule_probe;
2104 int dev;
2105 int err;
2106
2107 if (pci_match_id(driver_denylist, pci)) {
2108 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2109 return -ENODEV;
2110 }
2111
2112 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2113 if (dev >= SNDRV_CARDS)
2114 return -ENODEV;
2115 if (!enable[dev]) {
2116 set_bit(dev, probed_devs);
2117 return -ENOENT;
2118 }
2119
2120 /*
2121 * stop probe if another Intel's DSP driver should be activated
2122 */
2123 if (dmic_detect) {
2124 err = snd_intel_dsp_driver_probe(pci);
2125 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2126 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2127 return -ENODEV;
2128 }
2129 } else {
2130 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2131 }
2132
2133 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2134 0, &card);
2135 if (err < 0) {
2136 dev_err(&pci->dev, "Error creating card!\n");
2137 return err;
2138 }
2139
2140 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2141 if (err < 0)
2142 goto out_free;
2143 card->private_data = chip;
2144 hda = container_of(chip, struct hda_intel, chip);
2145
2146 pci_set_drvdata(pci, card);
2147
2148 err = register_vga_switcheroo(chip);
2149 if (err < 0) {
2150 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2151 goto out_free;
2152 }
2153
2154 if (check_hdmi_disabled(pci)) {
2155 dev_info(card->dev, "VGA controller is disabled\n");
2156 dev_info(card->dev, "Delaying initialization\n");
2157 chip->disabled = true;
2158 }
2159
2160 schedule_probe = !chip->disabled;
2161
2162 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2163 if (patch[dev] && *patch[dev]) {
2164 dev_info(card->dev, "Applying patch firmware '%s'\n",
2165 patch[dev]);
2166 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2167 &pci->dev, GFP_KERNEL, card,
2168 azx_firmware_cb);
2169 if (err < 0)
2170 goto out_free;
2171 schedule_probe = false; /* continued in azx_firmware_cb() */
2172 }
2173 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2174
2175 #ifndef CONFIG_SND_HDA_I915
2176 if (HDA_CONTROLLER_IN_GPU(pci))
2177 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2178 #endif
2179
2180 if (schedule_probe)
2181 schedule_delayed_work(&hda->probe_work, 0);
2182
2183 set_bit(dev, probed_devs);
2184 if (chip->disabled)
2185 complete_all(&hda->probe_wait);
2186 return 0;
2187
2188 out_free:
2189 snd_card_free(card);
2190 return err;
2191 }
2192
2193 #ifdef CONFIG_PM
2194 /* On some boards setting power_save to a non 0 value leads to clicking /
2195 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2196 * figure out how to avoid these sounds, but that is not always feasible.
2197 * So we keep a list of devices where we disable powersaving as its known
2198 * to causes problems on these devices.
2199 */
2200 static const struct snd_pci_quirk power_save_denylist[] = {
2201 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2202 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2203 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2204 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2205 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2206 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2207 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2208 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2209 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2210 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2211 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2212 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2213 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2214 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2215 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2216 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2217 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2218 /* https://bugs.launchpad.net/bugs/1821663 */
2219 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2220 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2221 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2222 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2223 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2224 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
2225 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2226 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2227 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2228 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2229 /* https://bugs.launchpad.net/bugs/1821663 */
2230 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2231 /* KONTRON SinglePC may cause a stall at runtime resume */
2232 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0),
2233 {}
2234 };
2235 #endif /* CONFIG_PM */
2236
set_default_power_save(struct azx * chip)2237 static void set_default_power_save(struct azx *chip)
2238 {
2239 int val = power_save;
2240
2241 #ifdef CONFIG_PM
2242 if (pm_blacklist) {
2243 const struct snd_pci_quirk *q;
2244
2245 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2246 if (q && val) {
2247 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2248 q->subvendor, q->subdevice);
2249 val = 0;
2250 }
2251 }
2252 #endif /* CONFIG_PM */
2253 snd_hda_set_power_save(&chip->bus, val * 1000);
2254 }
2255
2256 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2257 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2258 [AZX_DRIVER_NVIDIA] = 8,
2259 [AZX_DRIVER_TERA] = 1,
2260 };
2261
azx_probe_continue(struct azx * chip)2262 static int azx_probe_continue(struct azx *chip)
2263 {
2264 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2265 struct hdac_bus *bus = azx_bus(chip);
2266 struct pci_dev *pci = chip->pci;
2267 int dev = chip->dev_index;
2268 int err;
2269
2270 if (chip->disabled || hda->init_failed)
2271 return -EIO;
2272 if (hda->probe_retry)
2273 goto probe_retry;
2274
2275 to_hda_bus(bus)->bus_probing = 1;
2276 hda->probe_continued = 1;
2277
2278 /* bind with i915 if needed */
2279 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2280 err = snd_hdac_i915_init(bus);
2281 if (err < 0) {
2282 /* if the controller is bound only with HDMI/DP
2283 * (for HSW and BDW), we need to abort the probe;
2284 * for other chips, still continue probing as other
2285 * codecs can be on the same link.
2286 */
2287 if (HDA_CONTROLLER_IN_GPU(pci)) {
2288 dev_err(chip->card->dev,
2289 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2290 goto out_free;
2291 } else {
2292 /* don't bother any longer */
2293 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2294 }
2295 }
2296
2297 /* HSW/BDW controllers need this power */
2298 if (HDA_CONTROLLER_IN_GPU(pci))
2299 hda->need_i915_power = true;
2300 }
2301
2302 /* Request display power well for the HDA controller or codec. For
2303 * Haswell/Broadwell, both the display HDA controller and codec need
2304 * this power. For other platforms, like Baytrail/Braswell, only the
2305 * display codec needs the power and it can be released after probe.
2306 */
2307 display_power(chip, true);
2308
2309 err = azx_first_init(chip);
2310 if (err < 0)
2311 goto out_free;
2312
2313 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2314 chip->beep_mode = beep_mode[dev];
2315 #endif
2316
2317 chip->ctl_dev_id = ctl_dev_id;
2318
2319 /* create codec instances */
2320 if (bus->codec_mask) {
2321 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2322 if (err < 0)
2323 goto out_free;
2324 }
2325
2326 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2327 if (chip->fw) {
2328 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2329 chip->fw->data);
2330 if (err < 0)
2331 goto out_free;
2332 #ifndef CONFIG_PM
2333 release_firmware(chip->fw); /* no longer needed */
2334 chip->fw = NULL;
2335 #endif
2336 }
2337 #endif
2338
2339 probe_retry:
2340 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2341 err = azx_codec_configure(chip);
2342 if (err) {
2343 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2344 ++hda->probe_retry < 60) {
2345 schedule_delayed_work(&hda->probe_work,
2346 msecs_to_jiffies(1000));
2347 return 0; /* keep things up */
2348 }
2349 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2350 goto out_free;
2351 }
2352 }
2353
2354 err = snd_card_register(chip->card);
2355 if (err < 0)
2356 goto out_free;
2357
2358 setup_vga_switcheroo_runtime_pm(chip);
2359
2360 chip->running = 1;
2361 azx_add_card_list(chip);
2362
2363 set_default_power_save(chip);
2364
2365 if (azx_has_pm_runtime(chip)) {
2366 pm_runtime_use_autosuspend(&pci->dev);
2367 pm_runtime_allow(&pci->dev);
2368 pm_runtime_put_autosuspend(&pci->dev);
2369 }
2370
2371 out_free:
2372 if (err < 0) {
2373 pci_set_drvdata(pci, NULL);
2374 snd_card_free(chip->card);
2375 return err;
2376 }
2377
2378 if (!hda->need_i915_power)
2379 display_power(chip, false);
2380 complete_all(&hda->probe_wait);
2381 to_hda_bus(bus)->bus_probing = 0;
2382 hda->probe_retry = 0;
2383 return 0;
2384 }
2385
azx_remove(struct pci_dev * pci)2386 static void azx_remove(struct pci_dev *pci)
2387 {
2388 struct snd_card *card = pci_get_drvdata(pci);
2389 struct azx *chip;
2390 struct hda_intel *hda;
2391
2392 if (card) {
2393 /* cancel the pending probing work */
2394 chip = card->private_data;
2395 hda = container_of(chip, struct hda_intel, chip);
2396 /* FIXME: below is an ugly workaround.
2397 * Both device_release_driver() and driver_probe_device()
2398 * take *both* the device's and its parent's lock before
2399 * calling the remove() and probe() callbacks. The codec
2400 * probe takes the locks of both the codec itself and its
2401 * parent, i.e. the PCI controller dev. Meanwhile, when
2402 * the PCI controller is unbound, it takes its lock, too
2403 * ==> ouch, a deadlock!
2404 * As a workaround, we unlock temporarily here the controller
2405 * device during cancel_work_sync() call.
2406 */
2407 device_unlock(&pci->dev);
2408 cancel_delayed_work_sync(&hda->probe_work);
2409 device_lock(&pci->dev);
2410
2411 clear_bit(chip->dev_index, probed_devs);
2412 pci_set_drvdata(pci, NULL);
2413 snd_card_free(card);
2414 }
2415 }
2416
azx_shutdown(struct pci_dev * pci)2417 static void azx_shutdown(struct pci_dev *pci)
2418 {
2419 struct snd_card *card = pci_get_drvdata(pci);
2420 struct azx *chip;
2421
2422 if (!card)
2423 return;
2424 chip = card->private_data;
2425 if (chip && chip->running)
2426 __azx_shutdown_chip(chip, true);
2427 }
2428
2429 /* PCI IDs */
2430 static const struct pci_device_id azx_ids[] = {
2431 /* CPT */
2432 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2433 /* PBG */
2434 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2435 /* Panther Point */
2436 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2437 /* Lynx Point */
2438 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2439 /* 9 Series */
2440 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2441 /* Wellsburg */
2442 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2443 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2444 /* Lewisburg */
2445 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2446 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2447 /* Lynx Point-LP */
2448 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2449 /* Lynx Point-LP */
2450 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2451 /* Wildcat Point-LP */
2452 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2453 /* Skylake (Sunrise Point) */
2454 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2455 /* Skylake-LP (Sunrise Point-LP) */
2456 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2457 /* Kabylake */
2458 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2459 /* Kabylake-LP */
2460 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2461 /* Kabylake-H */
2462 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2463 /* Coffelake */
2464 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2465 /* Cannonlake */
2466 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2467 /* CometLake-LP */
2468 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2469 /* CometLake-H */
2470 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2471 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2472 /* CometLake-S */
2473 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2474 /* CometLake-R */
2475 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2476 /* Icelake */
2477 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2478 /* Icelake-H */
2479 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2480 /* Jasperlake */
2481 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2482 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2483 /* Tigerlake */
2484 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2485 /* Tigerlake-H */
2486 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2487 /* DG1 */
2488 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2489 /* DG2 */
2490 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2491 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2492 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2493 /* Alderlake-S */
2494 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2495 /* Alderlake-P */
2496 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2497 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2498 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2499 /* Alderlake-M */
2500 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2501 /* Alderlake-N */
2502 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2503 /* Elkhart Lake */
2504 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2505 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2506 /* Raptor Lake */
2507 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2508 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2509 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2510 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2511 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2512 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2513 /* Lunarlake-P */
2514 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2515 /* Arrow Lake-S */
2516 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2517 /* Arrow Lake */
2518 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2519 /* Apollolake (Broxton-P) */
2520 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2521 /* Gemini-Lake */
2522 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2523 /* Haswell */
2524 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2525 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2526 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2527 /* Broadwell */
2528 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
2529 /* 5 Series/3400 */
2530 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2531 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2532 /* Poulsbo */
2533 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2534 AZX_DCAPS_POSFIX_LPIB) },
2535 /* Oaktrail */
2536 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
2537 /* BayTrail */
2538 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
2539 /* Braswell */
2540 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
2541 /* ICH6 */
2542 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2543 /* ICH7 */
2544 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2545 /* ESB2 */
2546 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2547 /* ICH8 */
2548 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2549 /* ICH9 */
2550 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2551 /* ICH9 */
2552 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2553 /* ICH10 */
2554 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2555 /* ICH10 */
2556 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2557 /* Generic Intel */
2558 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2559 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2560 .class_mask = 0xffffff,
2561 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2562 /* ATI SB 450/600/700/800/900 */
2563 { PCI_VDEVICE(ATI, 0x437b),
2564 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2565 { PCI_VDEVICE(ATI, 0x4383),
2566 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2567 /* AMD Hudson */
2568 { PCI_VDEVICE(AMD, 0x780d),
2569 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2570 /* AMD, X370 & co */
2571 { PCI_VDEVICE(AMD, 0x1457),
2572 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2573 /* AMD, X570 & co */
2574 { PCI_VDEVICE(AMD, 0x1487),
2575 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2576 /* AMD Stoney */
2577 { PCI_VDEVICE(AMD, 0x157a),
2578 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2579 AZX_DCAPS_PM_RUNTIME },
2580 /* AMD Raven */
2581 { PCI_VDEVICE(AMD, 0x15e3),
2582 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2583 /* ATI HDMI */
2584 { PCI_VDEVICE(ATI, 0x0002),
2585 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2586 AZX_DCAPS_PM_RUNTIME },
2587 { PCI_VDEVICE(ATI, 0x1308),
2588 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2589 { PCI_VDEVICE(ATI, 0x157a),
2590 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2591 { PCI_VDEVICE(ATI, 0x15b3),
2592 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2593 { PCI_VDEVICE(ATI, 0x793b),
2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2595 { PCI_VDEVICE(ATI, 0x7919),
2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2597 { PCI_VDEVICE(ATI, 0x960f),
2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2599 { PCI_VDEVICE(ATI, 0x970f),
2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2601 { PCI_VDEVICE(ATI, 0x9840),
2602 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2603 { PCI_VDEVICE(ATI, 0xaa00),
2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2605 { PCI_VDEVICE(ATI, 0xaa08),
2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2607 { PCI_VDEVICE(ATI, 0xaa10),
2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2609 { PCI_VDEVICE(ATI, 0xaa18),
2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2611 { PCI_VDEVICE(ATI, 0xaa20),
2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613 { PCI_VDEVICE(ATI, 0xaa28),
2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2615 { PCI_VDEVICE(ATI, 0xaa30),
2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2617 { PCI_VDEVICE(ATI, 0xaa38),
2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2619 { PCI_VDEVICE(ATI, 0xaa40),
2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2621 { PCI_VDEVICE(ATI, 0xaa48),
2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2623 { PCI_VDEVICE(ATI, 0xaa50),
2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2625 { PCI_VDEVICE(ATI, 0xaa58),
2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2627 { PCI_VDEVICE(ATI, 0xaa60),
2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2629 { PCI_VDEVICE(ATI, 0xaa68),
2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2631 { PCI_VDEVICE(ATI, 0xaa80),
2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2633 { PCI_VDEVICE(ATI, 0xaa88),
2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2635 { PCI_VDEVICE(ATI, 0xaa90),
2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2637 { PCI_VDEVICE(ATI, 0xaa98),
2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2639 { PCI_VDEVICE(ATI, 0x9902),
2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2641 { PCI_VDEVICE(ATI, 0xaaa0),
2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2643 { PCI_VDEVICE(ATI, 0xaaa8),
2644 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2645 { PCI_VDEVICE(ATI, 0xaab0),
2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2647 { PCI_VDEVICE(ATI, 0xaac0),
2648 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2649 AZX_DCAPS_PM_RUNTIME },
2650 { PCI_VDEVICE(ATI, 0xaac8),
2651 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2652 AZX_DCAPS_PM_RUNTIME },
2653 { PCI_VDEVICE(ATI, 0xaad8),
2654 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2655 AZX_DCAPS_PM_RUNTIME },
2656 { PCI_VDEVICE(ATI, 0xaae0),
2657 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2658 AZX_DCAPS_PM_RUNTIME },
2659 { PCI_VDEVICE(ATI, 0xaae8),
2660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2661 AZX_DCAPS_PM_RUNTIME },
2662 { PCI_VDEVICE(ATI, 0xaaf0),
2663 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2664 AZX_DCAPS_PM_RUNTIME },
2665 { PCI_VDEVICE(ATI, 0xaaf8),
2666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2667 AZX_DCAPS_PM_RUNTIME },
2668 { PCI_VDEVICE(ATI, 0xab00),
2669 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2670 AZX_DCAPS_PM_RUNTIME },
2671 { PCI_VDEVICE(ATI, 0xab08),
2672 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2673 AZX_DCAPS_PM_RUNTIME },
2674 { PCI_VDEVICE(ATI, 0xab10),
2675 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2676 AZX_DCAPS_PM_RUNTIME },
2677 { PCI_VDEVICE(ATI, 0xab18),
2678 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2679 AZX_DCAPS_PM_RUNTIME },
2680 { PCI_VDEVICE(ATI, 0xab20),
2681 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2682 AZX_DCAPS_PM_RUNTIME },
2683 { PCI_VDEVICE(ATI, 0xab28),
2684 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2685 AZX_DCAPS_PM_RUNTIME },
2686 { PCI_VDEVICE(ATI, 0xab30),
2687 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2688 AZX_DCAPS_PM_RUNTIME },
2689 { PCI_VDEVICE(ATI, 0xab38),
2690 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2691 AZX_DCAPS_PM_RUNTIME },
2692 /* GLENFLY */
2693 { PCI_DEVICE(0x6766, PCI_ANY_ID),
2694 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2695 .class_mask = 0xffffff,
2696 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2697 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2698 /* VIA VT8251/VT8237A */
2699 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
2700 /* VIA GFX VT7122/VX900 */
2701 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2702 /* VIA GFX VT6122/VX11 */
2703 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2704 /* SIS966 */
2705 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
2706 /* ULI M5461 */
2707 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
2708 /* NVIDIA MCP */
2709 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2710 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2711 .class_mask = 0xffffff,
2712 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2713 /* Teradici */
2714 { PCI_DEVICE(0x6549, 0x1200),
2715 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2716 { PCI_DEVICE(0x6549, 0x2200),
2717 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2718 /* Creative X-Fi (CA0110-IBG) */
2719 /* CTHDA chips */
2720 { PCI_VDEVICE(CREATIVE, 0x0010),
2721 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2722 { PCI_VDEVICE(CREATIVE, 0x0012),
2723 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2724 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2725 /* the following entry conflicts with snd-ctxfi driver,
2726 * as ctxfi driver mutates from HD-audio to native mode with
2727 * a special command sequence.
2728 */
2729 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2730 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2731 .class_mask = 0xffffff,
2732 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2733 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2734 #else
2735 /* this entry seems still valid -- i.e. without emu20kx chip */
2736 { PCI_VDEVICE(CREATIVE, 0x0009),
2737 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2738 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2739 #endif
2740 /* CM8888 */
2741 { PCI_VDEVICE(CMEDIA, 0x5011),
2742 .driver_data = AZX_DRIVER_CMEDIA |
2743 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2744 /* Vortex86MX */
2745 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2746 /* VMware HDAudio */
2747 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2748 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2749 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2750 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2751 .class_mask = 0xffffff,
2752 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2753 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2754 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2755 .class_mask = 0xffffff,
2756 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2757 /* Zhaoxin */
2758 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2759 /* Loongson HDAudio*/
2760 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
2761 .driver_data = AZX_DRIVER_LOONGSON },
2762 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
2763 .driver_data = AZX_DRIVER_LOONGSON },
2764 { 0, }
2765 };
2766 MODULE_DEVICE_TABLE(pci, azx_ids);
2767
2768 /* pci_driver definition */
2769 static struct pci_driver azx_driver = {
2770 .name = KBUILD_MODNAME,
2771 .id_table = azx_ids,
2772 .probe = azx_probe,
2773 .remove = azx_remove,
2774 .shutdown = azx_shutdown,
2775 .driver = {
2776 .pm = AZX_PM_OPS,
2777 },
2778 };
2779
2780 module_pci_driver(azx_driver);
2781