1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <sound/hdaudio.h> 61 #include <sound/hda_i915.h> 62 #include <linux/vgaarb.h> 63 #include <linux/vga_switcheroo.h> 64 #include <linux/firmware.h> 65 #include "hda_codec.h" 66 #include "hda_controller.h" 67 #include "hda_intel.h" 68 69 #define CREATE_TRACE_POINTS 70 #include "hda_intel_trace.h" 71 72 /* position fix mode */ 73 enum { 74 POS_FIX_AUTO, 75 POS_FIX_LPIB, 76 POS_FIX_POSBUF, 77 POS_FIX_VIACOMBO, 78 POS_FIX_COMBO, 79 }; 80 81 /* Defines for ATI HD Audio support in SB450 south bridge */ 82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 84 85 /* Defines for Nvidia HDA support */ 86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 88 #define NVIDIA_HDA_ISTRM_COH 0x4d 89 #define NVIDIA_HDA_OSTRM_COH 0x4c 90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 91 92 /* Defines for Intel SCH HDA snoop control */ 93 #define INTEL_HDA_CGCTL 0x48 94 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 95 #define INTEL_SCH_HDA_DEVC 0x78 96 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 97 98 /* Define IN stream 0 FIFO size offset in VIA controller */ 99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 100 /* Define VIA HD Audio Device ID*/ 101 #define VIA_HDAC_DEVICE_ID 0x3288 102 103 /* max number of SDs */ 104 /* ICH, ATI and VIA have 4 playback and 4 capture */ 105 #define ICH6_NUM_CAPTURE 4 106 #define ICH6_NUM_PLAYBACK 4 107 108 /* ULI has 6 playback and 5 capture */ 109 #define ULI_NUM_CAPTURE 5 110 #define ULI_NUM_PLAYBACK 6 111 112 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 113 #define ATIHDMI_NUM_CAPTURE 0 114 #define ATIHDMI_NUM_PLAYBACK 8 115 116 /* TERA has 4 playback and 3 capture */ 117 #define TERA_NUM_CAPTURE 3 118 #define TERA_NUM_PLAYBACK 4 119 120 121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 124 static char *model[SNDRV_CARDS]; 125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 128 static int probe_only[SNDRV_CARDS]; 129 static int jackpoll_ms[SNDRV_CARDS]; 130 static bool single_cmd; 131 static int enable_msi = -1; 132 #ifdef CONFIG_SND_HDA_PATCH_LOADER 133 static char *patch[SNDRV_CARDS]; 134 #endif 135 #ifdef CONFIG_SND_HDA_INPUT_BEEP 136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 137 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 138 #endif 139 140 module_param_array(index, int, NULL, 0444); 141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 142 module_param_array(id, charp, NULL, 0444); 143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 144 module_param_array(enable, bool, NULL, 0444); 145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 146 module_param_array(model, charp, NULL, 0444); 147 MODULE_PARM_DESC(model, "Use the given board model."); 148 module_param_array(position_fix, int, NULL, 0444); 149 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 151 module_param_array(bdl_pos_adj, int, NULL, 0644); 152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 153 module_param_array(probe_mask, int, NULL, 0444); 154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 155 module_param_array(probe_only, int, NULL, 0444); 156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 157 module_param_array(jackpoll_ms, int, NULL, 0444); 158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 159 module_param(single_cmd, bool, 0444); 160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 161 "(for debugging only)."); 162 module_param(enable_msi, bint, 0444); 163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 164 #ifdef CONFIG_SND_HDA_PATCH_LOADER 165 module_param_array(patch, charp, NULL, 0444); 166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 167 #endif 168 #ifdef CONFIG_SND_HDA_INPUT_BEEP 169 module_param_array(beep_mode, bool, NULL, 0444); 170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 171 "(0=off, 1=on) (default=1)."); 172 #endif 173 174 #ifdef CONFIG_PM 175 static int param_set_xint(const char *val, const struct kernel_param *kp); 176 static const struct kernel_param_ops param_ops_xint = { 177 .set = param_set_xint, 178 .get = param_get_int, 179 }; 180 #define param_check_xint param_check_int 181 182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 183 module_param(power_save, xint, 0644); 184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 185 "(in second, 0 = disable)."); 186 187 /* reset the HD-audio controller in power save mode. 188 * this may give more power-saving, but will take longer time to 189 * wake up. 190 */ 191 static bool power_save_controller = 1; 192 module_param(power_save_controller, bool, 0644); 193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 194 #else 195 #define power_save 0 196 #endif /* CONFIG_PM */ 197 198 static int align_buffer_size = -1; 199 module_param(align_buffer_size, bint, 0644); 200 MODULE_PARM_DESC(align_buffer_size, 201 "Force buffer and period sizes to be multiple of 128 bytes."); 202 203 #ifdef CONFIG_X86 204 static int hda_snoop = -1; 205 module_param_named(snoop, hda_snoop, bint, 0444); 206 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 207 #else 208 #define hda_snoop true 209 #endif 210 211 212 MODULE_LICENSE("GPL"); 213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 214 "{Intel, ICH6M}," 215 "{Intel, ICH7}," 216 "{Intel, ESB2}," 217 "{Intel, ICH8}," 218 "{Intel, ICH9}," 219 "{Intel, ICH10}," 220 "{Intel, PCH}," 221 "{Intel, CPT}," 222 "{Intel, PPT}," 223 "{Intel, LPT}," 224 "{Intel, LPT_LP}," 225 "{Intel, WPT_LP}," 226 "{Intel, SPT}," 227 "{Intel, SPT_LP}," 228 "{Intel, HPT}," 229 "{Intel, PBG}," 230 "{Intel, SCH}," 231 "{ATI, SB450}," 232 "{ATI, SB600}," 233 "{ATI, RS600}," 234 "{ATI, RS690}," 235 "{ATI, RS780}," 236 "{ATI, R600}," 237 "{ATI, RV630}," 238 "{ATI, RV610}," 239 "{ATI, RV670}," 240 "{ATI, RV635}," 241 "{ATI, RV620}," 242 "{ATI, RV770}," 243 "{VIA, VT8251}," 244 "{VIA, VT8237A}," 245 "{SiS, SIS966}," 246 "{ULI, M5461}}"); 247 MODULE_DESCRIPTION("Intel HDA driver"); 248 249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 251 #define SUPPORT_VGA_SWITCHEROO 252 #endif 253 #endif 254 255 256 /* 257 */ 258 259 /* driver types */ 260 enum { 261 AZX_DRIVER_ICH, 262 AZX_DRIVER_PCH, 263 AZX_DRIVER_SCH, 264 AZX_DRIVER_HDMI, 265 AZX_DRIVER_ATI, 266 AZX_DRIVER_ATIHDMI, 267 AZX_DRIVER_ATIHDMI_NS, 268 AZX_DRIVER_VIA, 269 AZX_DRIVER_SIS, 270 AZX_DRIVER_ULI, 271 AZX_DRIVER_NVIDIA, 272 AZX_DRIVER_TERA, 273 AZX_DRIVER_CTX, 274 AZX_DRIVER_CTHDA, 275 AZX_DRIVER_CMEDIA, 276 AZX_DRIVER_GENERIC, 277 AZX_NUM_DRIVERS, /* keep this as last entry */ 278 }; 279 280 #define azx_get_snoop_type(chip) \ 281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 283 284 /* quirks for old Intel chipsets */ 285 #define AZX_DCAPS_INTEL_ICH \ 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 287 288 /* quirks for Intel PCH */ 289 #define AZX_DCAPS_INTEL_PCH_BASE \ 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_SNOOP_TYPE(SCH)) 292 293 /* PCH up to IVB; no runtime PM */ 294 #define AZX_DCAPS_INTEL_PCH_NOPM \ 295 (AZX_DCAPS_INTEL_PCH_BASE) 296 297 /* PCH for HSW/BDW; with runtime PM */ 298 #define AZX_DCAPS_INTEL_PCH \ 299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 300 301 /* HSW HDMI */ 302 #define AZX_DCAPS_INTEL_HASWELL \ 303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 305 AZX_DCAPS_SNOOP_TYPE(SCH)) 306 307 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 308 #define AZX_DCAPS_INTEL_BROADWELL \ 309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 311 AZX_DCAPS_SNOOP_TYPE(SCH)) 312 313 #define AZX_DCAPS_INTEL_BAYTRAIL \ 314 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL) 315 316 #define AZX_DCAPS_INTEL_BRASWELL \ 317 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL) 318 319 #define AZX_DCAPS_INTEL_SKYLAKE \ 320 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 321 AZX_DCAPS_I915_POWERWELL) 322 323 #define AZX_DCAPS_INTEL_BROXTON \ 324 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 325 AZX_DCAPS_I915_POWERWELL) 326 327 /* quirks for ATI SB / AMD Hudson */ 328 #define AZX_DCAPS_PRESET_ATI_SB \ 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 330 AZX_DCAPS_SNOOP_TYPE(ATI)) 331 332 /* quirks for ATI/AMD HDMI */ 333 #define AZX_DCAPS_PRESET_ATI_HDMI \ 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 335 AZX_DCAPS_NO_MSI64) 336 337 /* quirks for ATI HDMI with snoop off */ 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 340 341 /* quirks for Nvidia */ 342 #define AZX_DCAPS_PRESET_NVIDIA \ 343 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 344 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 345 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 346 347 #define AZX_DCAPS_PRESET_CTHDA \ 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 349 AZX_DCAPS_NO_64BIT |\ 350 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 351 352 /* 353 * vga_switcheroo support 354 */ 355 #ifdef SUPPORT_VGA_SWITCHEROO 356 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 357 #else 358 #define use_vga_switcheroo(chip) 0 359 #endif 360 361 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 362 ((pci)->device == 0x0c0c) || \ 363 ((pci)->device == 0x0d0c) || \ 364 ((pci)->device == 0x160c)) 365 366 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170) 367 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70) 368 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171) 369 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71) 370 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0) 371 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 372 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \ 373 IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci) 374 375 static char *driver_short_names[] = { 376 [AZX_DRIVER_ICH] = "HDA Intel", 377 [AZX_DRIVER_PCH] = "HDA Intel PCH", 378 [AZX_DRIVER_SCH] = "HDA Intel MID", 379 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 380 [AZX_DRIVER_ATI] = "HDA ATI SB", 381 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 382 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 383 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 384 [AZX_DRIVER_SIS] = "HDA SIS966", 385 [AZX_DRIVER_ULI] = "HDA ULI M5461", 386 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 387 [AZX_DRIVER_TERA] = "HDA Teradici", 388 [AZX_DRIVER_CTX] = "HDA Creative", 389 [AZX_DRIVER_CTHDA] = "HDA Creative", 390 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 391 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 392 }; 393 394 #ifdef CONFIG_X86 395 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 396 { 397 int pages; 398 399 if (azx_snoop(chip)) 400 return; 401 if (!dmab || !dmab->area || !dmab->bytes) 402 return; 403 404 #ifdef CONFIG_SND_DMA_SGBUF 405 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 406 struct snd_sg_buf *sgbuf = dmab->private_data; 407 if (chip->driver_type == AZX_DRIVER_CMEDIA) 408 return; /* deal with only CORB/RIRB buffers */ 409 if (on) 410 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 411 else 412 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 413 return; 414 } 415 #endif 416 417 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 418 if (on) 419 set_memory_wc((unsigned long)dmab->area, pages); 420 else 421 set_memory_wb((unsigned long)dmab->area, pages); 422 } 423 424 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 425 bool on) 426 { 427 __mark_pages_wc(chip, buf, on); 428 } 429 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 430 struct snd_pcm_substream *substream, bool on) 431 { 432 if (azx_dev->wc_marked != on) { 433 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 434 azx_dev->wc_marked = on; 435 } 436 } 437 #else 438 /* NOP for other archs */ 439 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 440 bool on) 441 { 442 } 443 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 444 struct snd_pcm_substream *substream, bool on) 445 { 446 } 447 #endif 448 449 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 450 451 /* 452 * initialize the PCI registers 453 */ 454 /* update bits in a PCI register byte */ 455 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 456 unsigned char mask, unsigned char val) 457 { 458 unsigned char data; 459 460 pci_read_config_byte(pci, reg, &data); 461 data &= ~mask; 462 data |= (val & mask); 463 pci_write_config_byte(pci, reg, data); 464 } 465 466 static void azx_init_pci(struct azx *chip) 467 { 468 int snoop_type = azx_get_snoop_type(chip); 469 470 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 471 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 472 * Ensuring these bits are 0 clears playback static on some HD Audio 473 * codecs. 474 * The PCI register TCSEL is defined in the Intel manuals. 475 */ 476 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 477 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 478 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 479 } 480 481 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 482 * we need to enable snoop. 483 */ 484 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 485 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 486 azx_snoop(chip)); 487 update_pci_byte(chip->pci, 488 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 489 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 490 } 491 492 /* For NVIDIA HDA, enable snoop */ 493 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 494 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 495 azx_snoop(chip)); 496 update_pci_byte(chip->pci, 497 NVIDIA_HDA_TRANSREG_ADDR, 498 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 499 update_pci_byte(chip->pci, 500 NVIDIA_HDA_ISTRM_COH, 501 0x01, NVIDIA_HDA_ENABLE_COHBIT); 502 update_pci_byte(chip->pci, 503 NVIDIA_HDA_OSTRM_COH, 504 0x01, NVIDIA_HDA_ENABLE_COHBIT); 505 } 506 507 /* Enable SCH/PCH snoop if needed */ 508 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 509 unsigned short snoop; 510 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 511 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 512 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 513 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 514 if (!azx_snoop(chip)) 515 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 516 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 517 pci_read_config_word(chip->pci, 518 INTEL_SCH_HDA_DEVC, &snoop); 519 } 520 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 521 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 522 "Disabled" : "Enabled"); 523 } 524 } 525 526 /* 527 * In BXT-P A0, HD-Audio DMA requests is later than expected, 528 * and makes an audio stream sensitive to system latencies when 529 * 24/32 bits are playing. 530 * Adjusting threshold of DMA fifo to force the DMA request 531 * sooner to improve latency tolerance at the expense of power. 532 */ 533 static void bxt_reduce_dma_latency(struct azx *chip) 534 { 535 u32 val; 536 537 val = azx_readl(chip, SKL_EM4L); 538 val &= (0x3 << 20); 539 azx_writel(chip, SKL_EM4L, val); 540 } 541 542 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 543 { 544 struct hdac_bus *bus = azx_bus(chip); 545 struct pci_dev *pci = chip->pci; 546 u32 val; 547 548 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 549 snd_hdac_set_codec_wakeup(bus, true); 550 if (IS_SKL_PLUS(pci)) { 551 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 552 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 553 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 554 } 555 azx_init_chip(chip, full_reset); 556 if (IS_SKL_PLUS(pci)) { 557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 558 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 560 } 561 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 562 snd_hdac_set_codec_wakeup(bus, false); 563 564 /* reduce dma latency to avoid noise */ 565 if (IS_BXT(pci)) 566 bxt_reduce_dma_latency(chip); 567 } 568 569 /* calculate runtime delay from LPIB */ 570 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 571 unsigned int pos) 572 { 573 struct snd_pcm_substream *substream = azx_dev->core.substream; 574 int stream = substream->stream; 575 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 576 int delay; 577 578 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 579 delay = pos - lpib_pos; 580 else 581 delay = lpib_pos - pos; 582 if (delay < 0) { 583 if (delay >= azx_dev->core.delay_negative_threshold) 584 delay = 0; 585 else 586 delay += azx_dev->core.bufsize; 587 } 588 589 if (delay >= azx_dev->core.period_bytes) { 590 dev_info(chip->card->dev, 591 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 592 delay, azx_dev->core.period_bytes); 593 delay = 0; 594 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 595 chip->get_delay[stream] = NULL; 596 } 597 598 return bytes_to_frames(substream->runtime, delay); 599 } 600 601 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 602 603 /* called from IRQ */ 604 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 605 { 606 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 607 int ok; 608 609 ok = azx_position_ok(chip, azx_dev); 610 if (ok == 1) { 611 azx_dev->irq_pending = 0; 612 return ok; 613 } else if (ok == 0) { 614 /* bogus IRQ, process it later */ 615 azx_dev->irq_pending = 1; 616 schedule_work(&hda->irq_pending_work); 617 } 618 return 0; 619 } 620 621 /* Enable/disable i915 display power for the link */ 622 static int azx_intel_link_power(struct azx *chip, bool enable) 623 { 624 struct hdac_bus *bus = azx_bus(chip); 625 626 return snd_hdac_display_power(bus, enable); 627 } 628 629 /* 630 * Check whether the current DMA position is acceptable for updating 631 * periods. Returns non-zero if it's OK. 632 * 633 * Many HD-audio controllers appear pretty inaccurate about 634 * the update-IRQ timing. The IRQ is issued before actually the 635 * data is processed. So, we need to process it afterwords in a 636 * workqueue. 637 */ 638 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 639 { 640 struct snd_pcm_substream *substream = azx_dev->core.substream; 641 int stream = substream->stream; 642 u32 wallclk; 643 unsigned int pos; 644 645 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 646 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 647 return -1; /* bogus (too early) interrupt */ 648 649 if (chip->get_position[stream]) 650 pos = chip->get_position[stream](chip, azx_dev); 651 else { /* use the position buffer as default */ 652 pos = azx_get_pos_posbuf(chip, azx_dev); 653 if (!pos || pos == (u32)-1) { 654 dev_info(chip->card->dev, 655 "Invalid position buffer, using LPIB read method instead.\n"); 656 chip->get_position[stream] = azx_get_pos_lpib; 657 if (chip->get_position[0] == azx_get_pos_lpib && 658 chip->get_position[1] == azx_get_pos_lpib) 659 azx_bus(chip)->use_posbuf = false; 660 pos = azx_get_pos_lpib(chip, azx_dev); 661 chip->get_delay[stream] = NULL; 662 } else { 663 chip->get_position[stream] = azx_get_pos_posbuf; 664 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 665 chip->get_delay[stream] = azx_get_delay_from_lpib; 666 } 667 } 668 669 if (pos >= azx_dev->core.bufsize) 670 pos = 0; 671 672 if (WARN_ONCE(!azx_dev->core.period_bytes, 673 "hda-intel: zero azx_dev->period_bytes")) 674 return -1; /* this shouldn't happen! */ 675 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 676 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 677 /* NG - it's below the first next period boundary */ 678 return chip->bdl_pos_adj ? 0 : -1; 679 azx_dev->core.start_wallclk += wallclk; 680 return 1; /* OK, it's fine */ 681 } 682 683 /* 684 * The work for pending PCM period updates. 685 */ 686 static void azx_irq_pending_work(struct work_struct *work) 687 { 688 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 689 struct azx *chip = &hda->chip; 690 struct hdac_bus *bus = azx_bus(chip); 691 struct hdac_stream *s; 692 int pending, ok; 693 694 if (!hda->irq_pending_warned) { 695 dev_info(chip->card->dev, 696 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 697 chip->card->number); 698 hda->irq_pending_warned = 1; 699 } 700 701 for (;;) { 702 pending = 0; 703 spin_lock_irq(&bus->reg_lock); 704 list_for_each_entry(s, &bus->stream_list, list) { 705 struct azx_dev *azx_dev = stream_to_azx_dev(s); 706 if (!azx_dev->irq_pending || 707 !s->substream || 708 !s->running) 709 continue; 710 ok = azx_position_ok(chip, azx_dev); 711 if (ok > 0) { 712 azx_dev->irq_pending = 0; 713 spin_unlock(&bus->reg_lock); 714 snd_pcm_period_elapsed(s->substream); 715 spin_lock(&bus->reg_lock); 716 } else if (ok < 0) { 717 pending = 0; /* too early */ 718 } else 719 pending++; 720 } 721 spin_unlock_irq(&bus->reg_lock); 722 if (!pending) 723 return; 724 msleep(1); 725 } 726 } 727 728 /* clear irq_pending flags and assure no on-going workq */ 729 static void azx_clear_irq_pending(struct azx *chip) 730 { 731 struct hdac_bus *bus = azx_bus(chip); 732 struct hdac_stream *s; 733 734 spin_lock_irq(&bus->reg_lock); 735 list_for_each_entry(s, &bus->stream_list, list) { 736 struct azx_dev *azx_dev = stream_to_azx_dev(s); 737 azx_dev->irq_pending = 0; 738 } 739 spin_unlock_irq(&bus->reg_lock); 740 } 741 742 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 743 { 744 struct hdac_bus *bus = azx_bus(chip); 745 746 if (request_irq(chip->pci->irq, azx_interrupt, 747 chip->msi ? 0 : IRQF_SHARED, 748 chip->card->irq_descr, chip)) { 749 dev_err(chip->card->dev, 750 "unable to grab IRQ %d, disabling device\n", 751 chip->pci->irq); 752 if (do_disconnect) 753 snd_card_disconnect(chip->card); 754 return -1; 755 } 756 bus->irq = chip->pci->irq; 757 pci_intx(chip->pci, !chip->msi); 758 return 0; 759 } 760 761 /* get the current DMA position with correction on VIA chips */ 762 static unsigned int azx_via_get_position(struct azx *chip, 763 struct azx_dev *azx_dev) 764 { 765 unsigned int link_pos, mini_pos, bound_pos; 766 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 767 unsigned int fifo_size; 768 769 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 770 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 771 /* Playback, no problem using link position */ 772 return link_pos; 773 } 774 775 /* Capture */ 776 /* For new chipset, 777 * use mod to get the DMA position just like old chipset 778 */ 779 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 780 mod_dma_pos %= azx_dev->core.period_bytes; 781 782 /* azx_dev->fifo_size can't get FIFO size of in stream. 783 * Get from base address + offset. 784 */ 785 fifo_size = readw(azx_bus(chip)->remap_addr + 786 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 787 788 if (azx_dev->insufficient) { 789 /* Link position never gather than FIFO size */ 790 if (link_pos <= fifo_size) 791 return 0; 792 793 azx_dev->insufficient = 0; 794 } 795 796 if (link_pos <= fifo_size) 797 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 798 else 799 mini_pos = link_pos - fifo_size; 800 801 /* Find nearest previous boudary */ 802 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 803 mod_link_pos = link_pos % azx_dev->core.period_bytes; 804 if (mod_link_pos >= fifo_size) 805 bound_pos = link_pos - mod_link_pos; 806 else if (mod_dma_pos >= mod_mini_pos) 807 bound_pos = mini_pos - mod_mini_pos; 808 else { 809 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 810 if (bound_pos >= azx_dev->core.bufsize) 811 bound_pos = 0; 812 } 813 814 /* Calculate real DMA position we want */ 815 return bound_pos + mod_dma_pos; 816 } 817 818 #ifdef CONFIG_PM 819 static DEFINE_MUTEX(card_list_lock); 820 static LIST_HEAD(card_list); 821 822 static void azx_add_card_list(struct azx *chip) 823 { 824 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 825 mutex_lock(&card_list_lock); 826 list_add(&hda->list, &card_list); 827 mutex_unlock(&card_list_lock); 828 } 829 830 static void azx_del_card_list(struct azx *chip) 831 { 832 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 833 mutex_lock(&card_list_lock); 834 list_del_init(&hda->list); 835 mutex_unlock(&card_list_lock); 836 } 837 838 /* trigger power-save check at writing parameter */ 839 static int param_set_xint(const char *val, const struct kernel_param *kp) 840 { 841 struct hda_intel *hda; 842 struct azx *chip; 843 int prev = power_save; 844 int ret = param_set_int(val, kp); 845 846 if (ret || prev == power_save) 847 return ret; 848 849 mutex_lock(&card_list_lock); 850 list_for_each_entry(hda, &card_list, list) { 851 chip = &hda->chip; 852 if (!hda->probe_continued || chip->disabled) 853 continue; 854 snd_hda_set_power_save(&chip->bus, power_save * 1000); 855 } 856 mutex_unlock(&card_list_lock); 857 return 0; 858 } 859 #else 860 #define azx_add_card_list(chip) /* NOP */ 861 #define azx_del_card_list(chip) /* NOP */ 862 #endif /* CONFIG_PM */ 863 864 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 865 /* 866 * power management 867 */ 868 static int azx_suspend(struct device *dev) 869 { 870 struct snd_card *card = dev_get_drvdata(dev); 871 struct azx *chip; 872 struct hda_intel *hda; 873 struct hdac_bus *bus; 874 875 if (!card) 876 return 0; 877 878 chip = card->private_data; 879 hda = container_of(chip, struct hda_intel, chip); 880 if (chip->disabled || hda->init_failed || !chip->running) 881 return 0; 882 883 bus = azx_bus(chip); 884 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 885 azx_clear_irq_pending(chip); 886 azx_stop_chip(chip); 887 azx_enter_link_reset(chip); 888 if (bus->irq >= 0) { 889 free_irq(bus->irq, chip); 890 bus->irq = -1; 891 } 892 893 if (chip->msi) 894 pci_disable_msi(chip->pci); 895 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 896 && hda->need_i915_power) 897 snd_hdac_display_power(bus, false); 898 899 trace_azx_suspend(chip); 900 return 0; 901 } 902 903 static int azx_resume(struct device *dev) 904 { 905 struct pci_dev *pci = to_pci_dev(dev); 906 struct snd_card *card = dev_get_drvdata(dev); 907 struct azx *chip; 908 struct hda_intel *hda; 909 910 if (!card) 911 return 0; 912 913 chip = card->private_data; 914 hda = container_of(chip, struct hda_intel, chip); 915 if (chip->disabled || hda->init_failed || !chip->running) 916 return 0; 917 918 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 919 && hda->need_i915_power) { 920 snd_hdac_display_power(azx_bus(chip), true); 921 snd_hdac_i915_set_bclk(azx_bus(chip)); 922 } 923 if (chip->msi) 924 if (pci_enable_msi(pci) < 0) 925 chip->msi = 0; 926 if (azx_acquire_irq(chip, 1) < 0) 927 return -EIO; 928 azx_init_pci(chip); 929 930 hda_intel_init_chip(chip, true); 931 932 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 933 934 trace_azx_resume(chip); 935 return 0; 936 } 937 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 938 939 #ifdef CONFIG_PM_SLEEP 940 /* put codec down to D3 at hibernation for Intel SKL+; 941 * otherwise BIOS may still access the codec and screw up the driver 942 */ 943 static int azx_freeze_noirq(struct device *dev) 944 { 945 struct pci_dev *pci = to_pci_dev(dev); 946 947 if (IS_SKL_PLUS(pci)) 948 pci_set_power_state(pci, PCI_D3hot); 949 950 return 0; 951 } 952 953 static int azx_thaw_noirq(struct device *dev) 954 { 955 struct pci_dev *pci = to_pci_dev(dev); 956 957 if (IS_SKL_PLUS(pci)) 958 pci_set_power_state(pci, PCI_D0); 959 960 return 0; 961 } 962 #endif /* CONFIG_PM_SLEEP */ 963 964 #ifdef CONFIG_PM 965 static int azx_runtime_suspend(struct device *dev) 966 { 967 struct snd_card *card = dev_get_drvdata(dev); 968 struct azx *chip; 969 struct hda_intel *hda; 970 971 if (!card) 972 return 0; 973 974 chip = card->private_data; 975 hda = container_of(chip, struct hda_intel, chip); 976 if (chip->disabled || hda->init_failed) 977 return 0; 978 979 if (!azx_has_pm_runtime(chip)) 980 return 0; 981 982 /* enable controller wake up event */ 983 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 984 STATESTS_INT_MASK); 985 986 azx_stop_chip(chip); 987 azx_enter_link_reset(chip); 988 azx_clear_irq_pending(chip); 989 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 990 && hda->need_i915_power) 991 snd_hdac_display_power(azx_bus(chip), false); 992 993 trace_azx_runtime_suspend(chip); 994 return 0; 995 } 996 997 static int azx_runtime_resume(struct device *dev) 998 { 999 struct snd_card *card = dev_get_drvdata(dev); 1000 struct azx *chip; 1001 struct hda_intel *hda; 1002 struct hdac_bus *bus; 1003 struct hda_codec *codec; 1004 int status; 1005 1006 if (!card) 1007 return 0; 1008 1009 chip = card->private_data; 1010 hda = container_of(chip, struct hda_intel, chip); 1011 if (chip->disabled || hda->init_failed) 1012 return 0; 1013 1014 if (!azx_has_pm_runtime(chip)) 1015 return 0; 1016 1017 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1018 bus = azx_bus(chip); 1019 if (hda->need_i915_power) { 1020 snd_hdac_display_power(bus, true); 1021 snd_hdac_i915_set_bclk(bus); 1022 } else { 1023 /* toggle codec wakeup bit for STATESTS read */ 1024 snd_hdac_set_codec_wakeup(bus, true); 1025 snd_hdac_set_codec_wakeup(bus, false); 1026 } 1027 } 1028 1029 /* Read STATESTS before controller reset */ 1030 status = azx_readw(chip, STATESTS); 1031 1032 azx_init_pci(chip); 1033 hda_intel_init_chip(chip, true); 1034 1035 if (status) { 1036 list_for_each_codec(codec, &chip->bus) 1037 if (status & (1 << codec->addr)) 1038 schedule_delayed_work(&codec->jackpoll_work, 1039 codec->jackpoll_interval); 1040 } 1041 1042 /* disable controller Wake Up event*/ 1043 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1044 ~STATESTS_INT_MASK); 1045 1046 trace_azx_runtime_resume(chip); 1047 return 0; 1048 } 1049 1050 static int azx_runtime_idle(struct device *dev) 1051 { 1052 struct snd_card *card = dev_get_drvdata(dev); 1053 struct azx *chip; 1054 struct hda_intel *hda; 1055 1056 if (!card) 1057 return 0; 1058 1059 chip = card->private_data; 1060 hda = container_of(chip, struct hda_intel, chip); 1061 if (chip->disabled || hda->init_failed) 1062 return 0; 1063 1064 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1065 azx_bus(chip)->codec_powered || !chip->running) 1066 return -EBUSY; 1067 1068 return 0; 1069 } 1070 1071 static const struct dev_pm_ops azx_pm = { 1072 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1073 #ifdef CONFIG_PM_SLEEP 1074 .freeze_noirq = azx_freeze_noirq, 1075 .thaw_noirq = azx_thaw_noirq, 1076 #endif 1077 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1078 }; 1079 1080 #define AZX_PM_OPS &azx_pm 1081 #else 1082 #define AZX_PM_OPS NULL 1083 #endif /* CONFIG_PM */ 1084 1085 1086 static int azx_probe_continue(struct azx *chip); 1087 1088 #ifdef SUPPORT_VGA_SWITCHEROO 1089 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1090 1091 static void azx_vs_set_state(struct pci_dev *pci, 1092 enum vga_switcheroo_state state) 1093 { 1094 struct snd_card *card = pci_get_drvdata(pci); 1095 struct azx *chip = card->private_data; 1096 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1097 bool disabled; 1098 1099 wait_for_completion(&hda->probe_wait); 1100 if (hda->init_failed) 1101 return; 1102 1103 disabled = (state == VGA_SWITCHEROO_OFF); 1104 if (chip->disabled == disabled) 1105 return; 1106 1107 if (!hda->probe_continued) { 1108 chip->disabled = disabled; 1109 if (!disabled) { 1110 dev_info(chip->card->dev, 1111 "Start delayed initialization\n"); 1112 if (azx_probe_continue(chip) < 0) { 1113 dev_err(chip->card->dev, "initialization error\n"); 1114 hda->init_failed = true; 1115 } 1116 } 1117 } else { 1118 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1119 disabled ? "Disabling" : "Enabling"); 1120 if (disabled) { 1121 pm_runtime_put_sync_suspend(card->dev); 1122 azx_suspend(card->dev); 1123 /* when we get suspended by vga_switcheroo we end up in D3cold, 1124 * however we have no ACPI handle, so pci/acpi can't put us there, 1125 * put ourselves there */ 1126 pci->current_state = PCI_D3cold; 1127 chip->disabled = true; 1128 if (snd_hda_lock_devices(&chip->bus)) 1129 dev_warn(chip->card->dev, 1130 "Cannot lock devices!\n"); 1131 } else { 1132 snd_hda_unlock_devices(&chip->bus); 1133 pm_runtime_get_noresume(card->dev); 1134 chip->disabled = false; 1135 azx_resume(card->dev); 1136 } 1137 } 1138 } 1139 1140 static bool azx_vs_can_switch(struct pci_dev *pci) 1141 { 1142 struct snd_card *card = pci_get_drvdata(pci); 1143 struct azx *chip = card->private_data; 1144 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1145 1146 wait_for_completion(&hda->probe_wait); 1147 if (hda->init_failed) 1148 return false; 1149 if (chip->disabled || !hda->probe_continued) 1150 return true; 1151 if (snd_hda_lock_devices(&chip->bus)) 1152 return false; 1153 snd_hda_unlock_devices(&chip->bus); 1154 return true; 1155 } 1156 1157 static void init_vga_switcheroo(struct azx *chip) 1158 { 1159 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1160 struct pci_dev *p = get_bound_vga(chip->pci); 1161 if (p) { 1162 dev_info(chip->card->dev, 1163 "Handle vga_switcheroo audio client\n"); 1164 hda->use_vga_switcheroo = 1; 1165 pci_dev_put(p); 1166 } 1167 } 1168 1169 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1170 .set_gpu_state = azx_vs_set_state, 1171 .can_switch = azx_vs_can_switch, 1172 }; 1173 1174 static int register_vga_switcheroo(struct azx *chip) 1175 { 1176 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1177 int err; 1178 1179 if (!hda->use_vga_switcheroo) 1180 return 0; 1181 /* FIXME: currently only handling DIS controller 1182 * is there any machine with two switchable HDMI audio controllers? 1183 */ 1184 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1185 VGA_SWITCHEROO_DIS); 1186 if (err < 0) 1187 return err; 1188 hda->vga_switcheroo_registered = 1; 1189 1190 /* register as an optimus hdmi audio power domain */ 1191 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1192 &hda->hdmi_pm_domain); 1193 return 0; 1194 } 1195 #else 1196 #define init_vga_switcheroo(chip) /* NOP */ 1197 #define register_vga_switcheroo(chip) 0 1198 #define check_hdmi_disabled(pci) false 1199 #endif /* SUPPORT_VGA_SWITCHER */ 1200 1201 /* 1202 * destructor 1203 */ 1204 static int azx_free(struct azx *chip) 1205 { 1206 struct pci_dev *pci = chip->pci; 1207 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1208 struct hdac_bus *bus = azx_bus(chip); 1209 1210 if (azx_has_pm_runtime(chip) && chip->running) 1211 pm_runtime_get_noresume(&pci->dev); 1212 1213 azx_del_card_list(chip); 1214 1215 hda->init_failed = 1; /* to be sure */ 1216 complete_all(&hda->probe_wait); 1217 1218 if (use_vga_switcheroo(hda)) { 1219 if (chip->disabled && hda->probe_continued) 1220 snd_hda_unlock_devices(&chip->bus); 1221 if (hda->vga_switcheroo_registered) { 1222 vga_switcheroo_unregister_client(chip->pci); 1223 vga_switcheroo_fini_domain_pm_ops(chip->card->dev); 1224 } 1225 } 1226 1227 if (bus->chip_init) { 1228 azx_clear_irq_pending(chip); 1229 azx_stop_all_streams(chip); 1230 azx_stop_chip(chip); 1231 } 1232 1233 if (bus->irq >= 0) 1234 free_irq(bus->irq, (void*)chip); 1235 if (chip->msi) 1236 pci_disable_msi(chip->pci); 1237 iounmap(bus->remap_addr); 1238 1239 azx_free_stream_pages(chip); 1240 azx_free_streams(chip); 1241 snd_hdac_bus_exit(bus); 1242 1243 if (chip->region_requested) 1244 pci_release_regions(chip->pci); 1245 1246 pci_disable_device(chip->pci); 1247 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1248 release_firmware(chip->fw); 1249 #endif 1250 1251 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1252 if (hda->need_i915_power) 1253 snd_hdac_display_power(bus, false); 1254 snd_hdac_i915_exit(bus); 1255 } 1256 kfree(hda); 1257 1258 return 0; 1259 } 1260 1261 static int azx_dev_disconnect(struct snd_device *device) 1262 { 1263 struct azx *chip = device->device_data; 1264 1265 chip->bus.shutdown = 1; 1266 return 0; 1267 } 1268 1269 static int azx_dev_free(struct snd_device *device) 1270 { 1271 return azx_free(device->device_data); 1272 } 1273 1274 #ifdef SUPPORT_VGA_SWITCHEROO 1275 /* 1276 * Check of disabled HDMI controller by vga_switcheroo 1277 */ 1278 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1279 { 1280 struct pci_dev *p; 1281 1282 /* check only discrete GPU */ 1283 switch (pci->vendor) { 1284 case PCI_VENDOR_ID_ATI: 1285 case PCI_VENDOR_ID_AMD: 1286 case PCI_VENDOR_ID_NVIDIA: 1287 if (pci->devfn == 1) { 1288 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1289 pci->bus->number, 0); 1290 if (p) { 1291 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1292 return p; 1293 pci_dev_put(p); 1294 } 1295 } 1296 break; 1297 } 1298 return NULL; 1299 } 1300 1301 static bool check_hdmi_disabled(struct pci_dev *pci) 1302 { 1303 bool vga_inactive = false; 1304 struct pci_dev *p = get_bound_vga(pci); 1305 1306 if (p) { 1307 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1308 vga_inactive = true; 1309 pci_dev_put(p); 1310 } 1311 return vga_inactive; 1312 } 1313 #endif /* SUPPORT_VGA_SWITCHEROO */ 1314 1315 /* 1316 * white/black-listing for position_fix 1317 */ 1318 static struct snd_pci_quirk position_fix_list[] = { 1319 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1320 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1321 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1322 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1323 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1324 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1325 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1326 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1327 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1328 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1329 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1330 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1331 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1332 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1333 {} 1334 }; 1335 1336 static int check_position_fix(struct azx *chip, int fix) 1337 { 1338 const struct snd_pci_quirk *q; 1339 1340 switch (fix) { 1341 case POS_FIX_AUTO: 1342 case POS_FIX_LPIB: 1343 case POS_FIX_POSBUF: 1344 case POS_FIX_VIACOMBO: 1345 case POS_FIX_COMBO: 1346 return fix; 1347 } 1348 1349 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1350 if (q) { 1351 dev_info(chip->card->dev, 1352 "position_fix set to %d for device %04x:%04x\n", 1353 q->value, q->subvendor, q->subdevice); 1354 return q->value; 1355 } 1356 1357 /* Check VIA/ATI HD Audio Controller exist */ 1358 if (chip->driver_type == AZX_DRIVER_VIA) { 1359 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1360 return POS_FIX_VIACOMBO; 1361 } 1362 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1363 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1364 return POS_FIX_LPIB; 1365 } 1366 return POS_FIX_AUTO; 1367 } 1368 1369 static void assign_position_fix(struct azx *chip, int fix) 1370 { 1371 static azx_get_pos_callback_t callbacks[] = { 1372 [POS_FIX_AUTO] = NULL, 1373 [POS_FIX_LPIB] = azx_get_pos_lpib, 1374 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1375 [POS_FIX_VIACOMBO] = azx_via_get_position, 1376 [POS_FIX_COMBO] = azx_get_pos_lpib, 1377 }; 1378 1379 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1380 1381 /* combo mode uses LPIB only for playback */ 1382 if (fix == POS_FIX_COMBO) 1383 chip->get_position[1] = NULL; 1384 1385 if (fix == POS_FIX_POSBUF && 1386 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1387 chip->get_delay[0] = chip->get_delay[1] = 1388 azx_get_delay_from_lpib; 1389 } 1390 1391 } 1392 1393 /* 1394 * black-lists for probe_mask 1395 */ 1396 static struct snd_pci_quirk probe_mask_list[] = { 1397 /* Thinkpad often breaks the controller communication when accessing 1398 * to the non-working (or non-existing) modem codec slot. 1399 */ 1400 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1401 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1402 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1403 /* broken BIOS */ 1404 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1405 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1406 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1407 /* forced codec slots */ 1408 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1409 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1410 /* WinFast VP200 H (Teradici) user reported broken communication */ 1411 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1412 {} 1413 }; 1414 1415 #define AZX_FORCE_CODEC_MASK 0x100 1416 1417 static void check_probe_mask(struct azx *chip, int dev) 1418 { 1419 const struct snd_pci_quirk *q; 1420 1421 chip->codec_probe_mask = probe_mask[dev]; 1422 if (chip->codec_probe_mask == -1) { 1423 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1424 if (q) { 1425 dev_info(chip->card->dev, 1426 "probe_mask set to 0x%x for device %04x:%04x\n", 1427 q->value, q->subvendor, q->subdevice); 1428 chip->codec_probe_mask = q->value; 1429 } 1430 } 1431 1432 /* check forced option */ 1433 if (chip->codec_probe_mask != -1 && 1434 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1435 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1436 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1437 (int)azx_bus(chip)->codec_mask); 1438 } 1439 } 1440 1441 /* 1442 * white/black-list for enable_msi 1443 */ 1444 static struct snd_pci_quirk msi_black_list[] = { 1445 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1446 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1447 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1448 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1449 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1450 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1451 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1452 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1453 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1454 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1455 {} 1456 }; 1457 1458 static void check_msi(struct azx *chip) 1459 { 1460 const struct snd_pci_quirk *q; 1461 1462 if (enable_msi >= 0) { 1463 chip->msi = !!enable_msi; 1464 return; 1465 } 1466 chip->msi = 1; /* enable MSI as default */ 1467 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1468 if (q) { 1469 dev_info(chip->card->dev, 1470 "msi for device %04x:%04x set to %d\n", 1471 q->subvendor, q->subdevice, q->value); 1472 chip->msi = q->value; 1473 return; 1474 } 1475 1476 /* NVidia chipsets seem to cause troubles with MSI */ 1477 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1478 dev_info(chip->card->dev, "Disabling MSI\n"); 1479 chip->msi = 0; 1480 } 1481 } 1482 1483 /* check the snoop mode availability */ 1484 static void azx_check_snoop_available(struct azx *chip) 1485 { 1486 int snoop = hda_snoop; 1487 1488 if (snoop >= 0) { 1489 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1490 snoop ? "snoop" : "non-snoop"); 1491 chip->snoop = snoop; 1492 return; 1493 } 1494 1495 snoop = true; 1496 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1497 chip->driver_type == AZX_DRIVER_VIA) { 1498 /* force to non-snoop mode for a new VIA controller 1499 * when BIOS is set 1500 */ 1501 u8 val; 1502 pci_read_config_byte(chip->pci, 0x42, &val); 1503 if (!(val & 0x80) && chip->pci->revision == 0x30) 1504 snoop = false; 1505 } 1506 1507 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1508 snoop = false; 1509 1510 chip->snoop = snoop; 1511 if (!snoop) 1512 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1513 } 1514 1515 static void azx_probe_work(struct work_struct *work) 1516 { 1517 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1518 azx_probe_continue(&hda->chip); 1519 } 1520 1521 static int default_bdl_pos_adj(struct azx *chip) 1522 { 1523 /* some exceptions: Atoms seem problematic with value 1 */ 1524 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1525 switch (chip->pci->device) { 1526 case 0x0f04: /* Baytrail */ 1527 case 0x2284: /* Braswell */ 1528 return 32; 1529 } 1530 } 1531 1532 switch (chip->driver_type) { 1533 case AZX_DRIVER_ICH: 1534 case AZX_DRIVER_PCH: 1535 return 1; 1536 default: 1537 return 32; 1538 } 1539 } 1540 1541 /* 1542 * constructor 1543 */ 1544 static const struct hdac_io_ops pci_hda_io_ops; 1545 static const struct hda_controller_ops pci_hda_ops; 1546 1547 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1548 int dev, unsigned int driver_caps, 1549 struct azx **rchip) 1550 { 1551 static struct snd_device_ops ops = { 1552 .dev_disconnect = azx_dev_disconnect, 1553 .dev_free = azx_dev_free, 1554 }; 1555 struct hda_intel *hda; 1556 struct azx *chip; 1557 int err; 1558 1559 *rchip = NULL; 1560 1561 err = pci_enable_device(pci); 1562 if (err < 0) 1563 return err; 1564 1565 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1566 if (!hda) { 1567 pci_disable_device(pci); 1568 return -ENOMEM; 1569 } 1570 1571 chip = &hda->chip; 1572 mutex_init(&chip->open_mutex); 1573 chip->card = card; 1574 chip->pci = pci; 1575 chip->ops = &pci_hda_ops; 1576 chip->driver_caps = driver_caps; 1577 chip->driver_type = driver_caps & 0xff; 1578 check_msi(chip); 1579 chip->dev_index = dev; 1580 chip->jackpoll_ms = jackpoll_ms; 1581 INIT_LIST_HEAD(&chip->pcm_list); 1582 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1583 INIT_LIST_HEAD(&hda->list); 1584 init_vga_switcheroo(chip); 1585 init_completion(&hda->probe_wait); 1586 1587 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1588 1589 check_probe_mask(chip, dev); 1590 1591 chip->single_cmd = single_cmd; 1592 azx_check_snoop_available(chip); 1593 1594 if (bdl_pos_adj[dev] < 0) 1595 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1596 else 1597 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1598 1599 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1600 if (err < 0) { 1601 kfree(hda); 1602 pci_disable_device(pci); 1603 return err; 1604 } 1605 1606 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1607 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1608 chip->bus.needs_damn_long_delay = 1; 1609 } 1610 1611 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1612 if (err < 0) { 1613 dev_err(card->dev, "Error creating device [card]!\n"); 1614 azx_free(chip); 1615 return err; 1616 } 1617 1618 /* continue probing in work context as may trigger request module */ 1619 INIT_WORK(&hda->probe_work, azx_probe_work); 1620 1621 *rchip = chip; 1622 1623 return 0; 1624 } 1625 1626 static int azx_first_init(struct azx *chip) 1627 { 1628 int dev = chip->dev_index; 1629 struct pci_dev *pci = chip->pci; 1630 struct snd_card *card = chip->card; 1631 struct hdac_bus *bus = azx_bus(chip); 1632 int err; 1633 unsigned short gcap; 1634 unsigned int dma_bits = 64; 1635 1636 #if BITS_PER_LONG != 64 1637 /* Fix up base address on ULI M5461 */ 1638 if (chip->driver_type == AZX_DRIVER_ULI) { 1639 u16 tmp3; 1640 pci_read_config_word(pci, 0x40, &tmp3); 1641 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1642 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1643 } 1644 #endif 1645 1646 err = pci_request_regions(pci, "ICH HD audio"); 1647 if (err < 0) 1648 return err; 1649 chip->region_requested = 1; 1650 1651 bus->addr = pci_resource_start(pci, 0); 1652 bus->remap_addr = pci_ioremap_bar(pci, 0); 1653 if (bus->remap_addr == NULL) { 1654 dev_err(card->dev, "ioremap error\n"); 1655 return -ENXIO; 1656 } 1657 1658 if (chip->msi) { 1659 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1660 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1661 pci->no_64bit_msi = true; 1662 } 1663 if (pci_enable_msi(pci) < 0) 1664 chip->msi = 0; 1665 } 1666 1667 if (azx_acquire_irq(chip, 0) < 0) 1668 return -EBUSY; 1669 1670 pci_set_master(pci); 1671 synchronize_irq(bus->irq); 1672 1673 gcap = azx_readw(chip, GCAP); 1674 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1675 1676 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1677 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1678 dma_bits = 40; 1679 1680 /* disable SB600 64bit support for safety */ 1681 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1682 struct pci_dev *p_smbus; 1683 dma_bits = 40; 1684 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1685 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1686 NULL); 1687 if (p_smbus) { 1688 if (p_smbus->revision < 0x30) 1689 gcap &= ~AZX_GCAP_64OK; 1690 pci_dev_put(p_smbus); 1691 } 1692 } 1693 1694 /* disable 64bit DMA address on some devices */ 1695 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1696 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1697 gcap &= ~AZX_GCAP_64OK; 1698 } 1699 1700 /* disable buffer size rounding to 128-byte multiples if supported */ 1701 if (align_buffer_size >= 0) 1702 chip->align_buffer_size = !!align_buffer_size; 1703 else { 1704 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1705 chip->align_buffer_size = 0; 1706 else 1707 chip->align_buffer_size = 1; 1708 } 1709 1710 /* allow 64bit DMA address if supported by H/W */ 1711 if (!(gcap & AZX_GCAP_64OK)) 1712 dma_bits = 32; 1713 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1714 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1715 } else { 1716 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1717 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1718 } 1719 1720 /* read number of streams from GCAP register instead of using 1721 * hardcoded value 1722 */ 1723 chip->capture_streams = (gcap >> 8) & 0x0f; 1724 chip->playback_streams = (gcap >> 12) & 0x0f; 1725 if (!chip->playback_streams && !chip->capture_streams) { 1726 /* gcap didn't give any info, switching to old method */ 1727 1728 switch (chip->driver_type) { 1729 case AZX_DRIVER_ULI: 1730 chip->playback_streams = ULI_NUM_PLAYBACK; 1731 chip->capture_streams = ULI_NUM_CAPTURE; 1732 break; 1733 case AZX_DRIVER_ATIHDMI: 1734 case AZX_DRIVER_ATIHDMI_NS: 1735 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1736 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1737 break; 1738 case AZX_DRIVER_GENERIC: 1739 default: 1740 chip->playback_streams = ICH6_NUM_PLAYBACK; 1741 chip->capture_streams = ICH6_NUM_CAPTURE; 1742 break; 1743 } 1744 } 1745 chip->capture_index_offset = 0; 1746 chip->playback_index_offset = chip->capture_streams; 1747 chip->num_streams = chip->playback_streams + chip->capture_streams; 1748 1749 /* initialize streams */ 1750 err = azx_init_streams(chip); 1751 if (err < 0) 1752 return err; 1753 1754 err = azx_alloc_stream_pages(chip); 1755 if (err < 0) 1756 return err; 1757 1758 /* initialize chip */ 1759 azx_init_pci(chip); 1760 1761 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1762 snd_hdac_i915_set_bclk(bus); 1763 1764 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1765 1766 /* codec detection */ 1767 if (!azx_bus(chip)->codec_mask) { 1768 dev_err(card->dev, "no codecs found!\n"); 1769 return -ENODEV; 1770 } 1771 1772 strcpy(card->driver, "HDA-Intel"); 1773 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1774 sizeof(card->shortname)); 1775 snprintf(card->longname, sizeof(card->longname), 1776 "%s at 0x%lx irq %i", 1777 card->shortname, bus->addr, bus->irq); 1778 1779 return 0; 1780 } 1781 1782 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1783 /* callback from request_firmware_nowait() */ 1784 static void azx_firmware_cb(const struct firmware *fw, void *context) 1785 { 1786 struct snd_card *card = context; 1787 struct azx *chip = card->private_data; 1788 struct pci_dev *pci = chip->pci; 1789 1790 if (!fw) { 1791 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1792 goto error; 1793 } 1794 1795 chip->fw = fw; 1796 if (!chip->disabled) { 1797 /* continue probing */ 1798 if (azx_probe_continue(chip)) 1799 goto error; 1800 } 1801 return; /* OK */ 1802 1803 error: 1804 snd_card_free(card); 1805 pci_set_drvdata(pci, NULL); 1806 } 1807 #endif 1808 1809 /* 1810 * HDA controller ops. 1811 */ 1812 1813 /* PCI register access. */ 1814 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1815 { 1816 writel(value, addr); 1817 } 1818 1819 static u32 pci_azx_readl(u32 __iomem *addr) 1820 { 1821 return readl(addr); 1822 } 1823 1824 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1825 { 1826 writew(value, addr); 1827 } 1828 1829 static u16 pci_azx_readw(u16 __iomem *addr) 1830 { 1831 return readw(addr); 1832 } 1833 1834 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1835 { 1836 writeb(value, addr); 1837 } 1838 1839 static u8 pci_azx_readb(u8 __iomem *addr) 1840 { 1841 return readb(addr); 1842 } 1843 1844 static int disable_msi_reset_irq(struct azx *chip) 1845 { 1846 struct hdac_bus *bus = azx_bus(chip); 1847 int err; 1848 1849 free_irq(bus->irq, chip); 1850 bus->irq = -1; 1851 pci_disable_msi(chip->pci); 1852 chip->msi = 0; 1853 err = azx_acquire_irq(chip, 1); 1854 if (err < 0) 1855 return err; 1856 1857 return 0; 1858 } 1859 1860 /* DMA page allocation helpers. */ 1861 static int dma_alloc_pages(struct hdac_bus *bus, 1862 int type, 1863 size_t size, 1864 struct snd_dma_buffer *buf) 1865 { 1866 struct azx *chip = bus_to_azx(bus); 1867 int err; 1868 1869 err = snd_dma_alloc_pages(type, 1870 bus->dev, 1871 size, buf); 1872 if (err < 0) 1873 return err; 1874 mark_pages_wc(chip, buf, true); 1875 return 0; 1876 } 1877 1878 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 1879 { 1880 struct azx *chip = bus_to_azx(bus); 1881 1882 mark_pages_wc(chip, buf, false); 1883 snd_dma_free_pages(buf); 1884 } 1885 1886 static int substream_alloc_pages(struct azx *chip, 1887 struct snd_pcm_substream *substream, 1888 size_t size) 1889 { 1890 struct azx_dev *azx_dev = get_azx_dev(substream); 1891 int ret; 1892 1893 mark_runtime_wc(chip, azx_dev, substream, false); 1894 ret = snd_pcm_lib_malloc_pages(substream, size); 1895 if (ret < 0) 1896 return ret; 1897 mark_runtime_wc(chip, azx_dev, substream, true); 1898 return 0; 1899 } 1900 1901 static int substream_free_pages(struct azx *chip, 1902 struct snd_pcm_substream *substream) 1903 { 1904 struct azx_dev *azx_dev = get_azx_dev(substream); 1905 mark_runtime_wc(chip, azx_dev, substream, false); 1906 return snd_pcm_lib_free_pages(substream); 1907 } 1908 1909 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1910 struct vm_area_struct *area) 1911 { 1912 #ifdef CONFIG_X86 1913 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1914 struct azx *chip = apcm->chip; 1915 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1916 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1917 #endif 1918 } 1919 1920 static const struct hdac_io_ops pci_hda_io_ops = { 1921 .reg_writel = pci_azx_writel, 1922 .reg_readl = pci_azx_readl, 1923 .reg_writew = pci_azx_writew, 1924 .reg_readw = pci_azx_readw, 1925 .reg_writeb = pci_azx_writeb, 1926 .reg_readb = pci_azx_readb, 1927 .dma_alloc_pages = dma_alloc_pages, 1928 .dma_free_pages = dma_free_pages, 1929 }; 1930 1931 static const struct hda_controller_ops pci_hda_ops = { 1932 .disable_msi_reset_irq = disable_msi_reset_irq, 1933 .substream_alloc_pages = substream_alloc_pages, 1934 .substream_free_pages = substream_free_pages, 1935 .pcm_mmap_prepare = pcm_mmap_prepare, 1936 .position_check = azx_position_check, 1937 .link_power = azx_intel_link_power, 1938 }; 1939 1940 static int azx_probe(struct pci_dev *pci, 1941 const struct pci_device_id *pci_id) 1942 { 1943 static int dev; 1944 struct snd_card *card; 1945 struct hda_intel *hda; 1946 struct azx *chip; 1947 bool schedule_probe; 1948 int err; 1949 1950 if (dev >= SNDRV_CARDS) 1951 return -ENODEV; 1952 if (!enable[dev]) { 1953 dev++; 1954 return -ENOENT; 1955 } 1956 1957 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1958 0, &card); 1959 if (err < 0) { 1960 dev_err(&pci->dev, "Error creating card!\n"); 1961 return err; 1962 } 1963 1964 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 1965 if (err < 0) 1966 goto out_free; 1967 card->private_data = chip; 1968 hda = container_of(chip, struct hda_intel, chip); 1969 1970 pci_set_drvdata(pci, card); 1971 1972 err = register_vga_switcheroo(chip); 1973 if (err < 0) { 1974 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 1975 goto out_free; 1976 } 1977 1978 if (check_hdmi_disabled(pci)) { 1979 dev_info(card->dev, "VGA controller is disabled\n"); 1980 dev_info(card->dev, "Delaying initialization\n"); 1981 chip->disabled = true; 1982 } 1983 1984 schedule_probe = !chip->disabled; 1985 1986 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1987 if (patch[dev] && *patch[dev]) { 1988 dev_info(card->dev, "Applying patch firmware '%s'\n", 1989 patch[dev]); 1990 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1991 &pci->dev, GFP_KERNEL, card, 1992 azx_firmware_cb); 1993 if (err < 0) 1994 goto out_free; 1995 schedule_probe = false; /* continued in azx_firmware_cb() */ 1996 } 1997 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1998 1999 #ifndef CONFIG_SND_HDA_I915 2000 if (CONTROLLER_IN_GPU(pci)) 2001 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2002 #endif 2003 2004 if (schedule_probe) 2005 schedule_work(&hda->probe_work); 2006 2007 dev++; 2008 if (chip->disabled) 2009 complete_all(&hda->probe_wait); 2010 return 0; 2011 2012 out_free: 2013 snd_card_free(card); 2014 return err; 2015 } 2016 2017 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2018 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2019 [AZX_DRIVER_NVIDIA] = 8, 2020 [AZX_DRIVER_TERA] = 1, 2021 }; 2022 2023 static int azx_probe_continue(struct azx *chip) 2024 { 2025 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2026 struct hdac_bus *bus = azx_bus(chip); 2027 struct pci_dev *pci = chip->pci; 2028 int dev = chip->dev_index; 2029 int err; 2030 2031 hda->probe_continued = 1; 2032 2033 /* Request display power well for the HDA controller or codec. For 2034 * Haswell/Broadwell, both the display HDA controller and codec need 2035 * this power. For other platforms, like Baytrail/Braswell, only the 2036 * display codec needs the power and it can be released after probe. 2037 */ 2038 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 2039 /* HSW/BDW controllers need this power */ 2040 if (CONTROLLER_IN_GPU(pci)) 2041 hda->need_i915_power = 1; 2042 2043 err = snd_hdac_i915_init(bus); 2044 if (err < 0) { 2045 /* if the controller is bound only with HDMI/DP 2046 * (for HSW and BDW), we need to abort the probe; 2047 * for other chips, still continue probing as other 2048 * codecs can be on the same link. 2049 */ 2050 if (CONTROLLER_IN_GPU(pci)) { 2051 dev_err(chip->card->dev, 2052 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2053 goto out_free; 2054 } else 2055 goto skip_i915; 2056 } 2057 2058 err = snd_hdac_display_power(bus, true); 2059 if (err < 0) { 2060 dev_err(chip->card->dev, 2061 "Cannot turn on display power on i915\n"); 2062 goto i915_power_fail; 2063 } 2064 } 2065 2066 skip_i915: 2067 err = azx_first_init(chip); 2068 if (err < 0) 2069 goto out_free; 2070 2071 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2072 chip->beep_mode = beep_mode[dev]; 2073 #endif 2074 2075 /* create codec instances */ 2076 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2077 if (err < 0) 2078 goto out_free; 2079 2080 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2081 if (chip->fw) { 2082 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2083 chip->fw->data); 2084 if (err < 0) 2085 goto out_free; 2086 #ifndef CONFIG_PM 2087 release_firmware(chip->fw); /* no longer needed */ 2088 chip->fw = NULL; 2089 #endif 2090 } 2091 #endif 2092 if ((probe_only[dev] & 1) == 0) { 2093 err = azx_codec_configure(chip); 2094 if (err < 0) 2095 goto out_free; 2096 } 2097 2098 err = snd_card_register(chip->card); 2099 if (err < 0) 2100 goto out_free; 2101 2102 chip->running = 1; 2103 azx_add_card_list(chip); 2104 snd_hda_set_power_save(&chip->bus, power_save * 1000); 2105 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 2106 pm_runtime_put_autosuspend(&pci->dev); 2107 2108 out_free: 2109 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 2110 && !hda->need_i915_power) 2111 snd_hdac_display_power(bus, false); 2112 2113 i915_power_fail: 2114 if (err < 0) 2115 hda->init_failed = 1; 2116 complete_all(&hda->probe_wait); 2117 return err; 2118 } 2119 2120 static void azx_remove(struct pci_dev *pci) 2121 { 2122 struct snd_card *card = pci_get_drvdata(pci); 2123 struct azx *chip; 2124 struct hda_intel *hda; 2125 2126 if (card) { 2127 /* cancel the pending probing work */ 2128 chip = card->private_data; 2129 hda = container_of(chip, struct hda_intel, chip); 2130 cancel_work_sync(&hda->probe_work); 2131 2132 snd_card_free(card); 2133 } 2134 } 2135 2136 static void azx_shutdown(struct pci_dev *pci) 2137 { 2138 struct snd_card *card = pci_get_drvdata(pci); 2139 struct azx *chip; 2140 2141 if (!card) 2142 return; 2143 chip = card->private_data; 2144 if (chip && chip->running) 2145 azx_stop_chip(chip); 2146 } 2147 2148 /* PCI IDs */ 2149 static const struct pci_device_id azx_ids[] = { 2150 /* CPT */ 2151 { PCI_DEVICE(0x8086, 0x1c20), 2152 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2153 /* PBG */ 2154 { PCI_DEVICE(0x8086, 0x1d20), 2155 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2156 /* Panther Point */ 2157 { PCI_DEVICE(0x8086, 0x1e20), 2158 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2159 /* Lynx Point */ 2160 { PCI_DEVICE(0x8086, 0x8c20), 2161 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2162 /* 9 Series */ 2163 { PCI_DEVICE(0x8086, 0x8ca0), 2164 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2165 /* Wellsburg */ 2166 { PCI_DEVICE(0x8086, 0x8d20), 2167 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2168 { PCI_DEVICE(0x8086, 0x8d21), 2169 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2170 /* Lewisburg */ 2171 { PCI_DEVICE(0x8086, 0xa1f0), 2172 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2173 { PCI_DEVICE(0x8086, 0xa270), 2174 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2175 /* Lynx Point-LP */ 2176 { PCI_DEVICE(0x8086, 0x9c20), 2177 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2178 /* Lynx Point-LP */ 2179 { PCI_DEVICE(0x8086, 0x9c21), 2180 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2181 /* Wildcat Point-LP */ 2182 { PCI_DEVICE(0x8086, 0x9ca0), 2183 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2184 /* Sunrise Point */ 2185 { PCI_DEVICE(0x8086, 0xa170), 2186 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2187 /* Sunrise Point-LP */ 2188 { PCI_DEVICE(0x8086, 0x9d70), 2189 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2190 /* Kabylake */ 2191 { PCI_DEVICE(0x8086, 0xa171), 2192 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2193 /* Kabylake-LP */ 2194 { PCI_DEVICE(0x8086, 0x9d71), 2195 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2196 /* Kabylake-H */ 2197 { PCI_DEVICE(0x8086, 0xa2f0), 2198 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2199 /* Broxton-P(Apollolake) */ 2200 { PCI_DEVICE(0x8086, 0x5a98), 2201 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON }, 2202 /* Broxton-T */ 2203 { PCI_DEVICE(0x8086, 0x1a98), 2204 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON }, 2205 /* Haswell */ 2206 { PCI_DEVICE(0x8086, 0x0a0c), 2207 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2208 { PCI_DEVICE(0x8086, 0x0c0c), 2209 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2210 { PCI_DEVICE(0x8086, 0x0d0c), 2211 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2212 /* Broadwell */ 2213 { PCI_DEVICE(0x8086, 0x160c), 2214 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2215 /* 5 Series/3400 */ 2216 { PCI_DEVICE(0x8086, 0x3b56), 2217 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2218 /* Poulsbo */ 2219 { PCI_DEVICE(0x8086, 0x811b), 2220 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2221 /* Oaktrail */ 2222 { PCI_DEVICE(0x8086, 0x080a), 2223 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2224 /* BayTrail */ 2225 { PCI_DEVICE(0x8086, 0x0f04), 2226 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2227 /* Braswell */ 2228 { PCI_DEVICE(0x8086, 0x2284), 2229 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2230 /* ICH6 */ 2231 { PCI_DEVICE(0x8086, 0x2668), 2232 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2233 /* ICH7 */ 2234 { PCI_DEVICE(0x8086, 0x27d8), 2235 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2236 /* ESB2 */ 2237 { PCI_DEVICE(0x8086, 0x269a), 2238 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2239 /* ICH8 */ 2240 { PCI_DEVICE(0x8086, 0x284b), 2241 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2242 /* ICH9 */ 2243 { PCI_DEVICE(0x8086, 0x293e), 2244 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2245 /* ICH9 */ 2246 { PCI_DEVICE(0x8086, 0x293f), 2247 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2248 /* ICH10 */ 2249 { PCI_DEVICE(0x8086, 0x3a3e), 2250 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2251 /* ICH10 */ 2252 { PCI_DEVICE(0x8086, 0x3a6e), 2253 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2254 /* Generic Intel */ 2255 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2256 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2257 .class_mask = 0xffffff, 2258 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2259 /* ATI SB 450/600/700/800/900 */ 2260 { PCI_DEVICE(0x1002, 0x437b), 2261 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2262 { PCI_DEVICE(0x1002, 0x4383), 2263 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2264 /* AMD Hudson */ 2265 { PCI_DEVICE(0x1022, 0x780d), 2266 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2267 /* ATI HDMI */ 2268 { PCI_DEVICE(0x1002, 0x1308), 2269 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2270 { PCI_DEVICE(0x1002, 0x157a), 2271 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2272 { PCI_DEVICE(0x1002, 0x15b3), 2273 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2274 { PCI_DEVICE(0x1002, 0x793b), 2275 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2276 { PCI_DEVICE(0x1002, 0x7919), 2277 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2278 { PCI_DEVICE(0x1002, 0x960f), 2279 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2280 { PCI_DEVICE(0x1002, 0x970f), 2281 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2282 { PCI_DEVICE(0x1002, 0x9840), 2283 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2284 { PCI_DEVICE(0x1002, 0xaa00), 2285 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2286 { PCI_DEVICE(0x1002, 0xaa08), 2287 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2288 { PCI_DEVICE(0x1002, 0xaa10), 2289 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2290 { PCI_DEVICE(0x1002, 0xaa18), 2291 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2292 { PCI_DEVICE(0x1002, 0xaa20), 2293 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2294 { PCI_DEVICE(0x1002, 0xaa28), 2295 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2296 { PCI_DEVICE(0x1002, 0xaa30), 2297 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2298 { PCI_DEVICE(0x1002, 0xaa38), 2299 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2300 { PCI_DEVICE(0x1002, 0xaa40), 2301 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2302 { PCI_DEVICE(0x1002, 0xaa48), 2303 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2304 { PCI_DEVICE(0x1002, 0xaa50), 2305 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2306 { PCI_DEVICE(0x1002, 0xaa58), 2307 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2308 { PCI_DEVICE(0x1002, 0xaa60), 2309 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2310 { PCI_DEVICE(0x1002, 0xaa68), 2311 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2312 { PCI_DEVICE(0x1002, 0xaa80), 2313 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2314 { PCI_DEVICE(0x1002, 0xaa88), 2315 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2316 { PCI_DEVICE(0x1002, 0xaa90), 2317 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2318 { PCI_DEVICE(0x1002, 0xaa98), 2319 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2320 { PCI_DEVICE(0x1002, 0x9902), 2321 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2322 { PCI_DEVICE(0x1002, 0xaaa0), 2323 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2324 { PCI_DEVICE(0x1002, 0xaaa8), 2325 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2326 { PCI_DEVICE(0x1002, 0xaab0), 2327 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2328 { PCI_DEVICE(0x1002, 0xaac0), 2329 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2330 { PCI_DEVICE(0x1002, 0xaac8), 2331 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2332 { PCI_DEVICE(0x1002, 0xaad8), 2333 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2334 { PCI_DEVICE(0x1002, 0xaae8), 2335 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2336 { PCI_DEVICE(0x1002, 0xaae0), 2337 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2338 { PCI_DEVICE(0x1002, 0xaaf0), 2339 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2340 /* VIA VT8251/VT8237A */ 2341 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2342 /* VIA GFX VT7122/VX900 */ 2343 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2344 /* VIA GFX VT6122/VX11 */ 2345 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2346 /* SIS966 */ 2347 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2348 /* ULI M5461 */ 2349 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2350 /* NVIDIA MCP */ 2351 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2352 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2353 .class_mask = 0xffffff, 2354 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2355 /* Teradici */ 2356 { PCI_DEVICE(0x6549, 0x1200), 2357 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2358 { PCI_DEVICE(0x6549, 0x2200), 2359 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2360 /* Creative X-Fi (CA0110-IBG) */ 2361 /* CTHDA chips */ 2362 { PCI_DEVICE(0x1102, 0x0010), 2363 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2364 { PCI_DEVICE(0x1102, 0x0012), 2365 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2366 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2367 /* the following entry conflicts with snd-ctxfi driver, 2368 * as ctxfi driver mutates from HD-audio to native mode with 2369 * a special command sequence. 2370 */ 2371 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2372 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2373 .class_mask = 0xffffff, 2374 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2375 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2376 #else 2377 /* this entry seems still valid -- i.e. without emu20kx chip */ 2378 { PCI_DEVICE(0x1102, 0x0009), 2379 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2380 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2381 #endif 2382 /* CM8888 */ 2383 { PCI_DEVICE(0x13f6, 0x5011), 2384 .driver_data = AZX_DRIVER_CMEDIA | 2385 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2386 /* Vortex86MX */ 2387 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2388 /* VMware HDAudio */ 2389 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2390 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2391 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2392 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2393 .class_mask = 0xffffff, 2394 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2395 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2396 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2397 .class_mask = 0xffffff, 2398 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2399 { 0, } 2400 }; 2401 MODULE_DEVICE_TABLE(pci, azx_ids); 2402 2403 /* pci_driver definition */ 2404 static struct pci_driver azx_driver = { 2405 .name = KBUILD_MODNAME, 2406 .id_table = azx_ids, 2407 .probe = azx_probe, 2408 .remove = azx_remove, 2409 .shutdown = azx_shutdown, 2410 .driver = { 2411 .pm = AZX_PM_OPS, 2412 }, 2413 }; 2414 2415 module_pci_driver(azx_driver); 2416