1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <sound/hdaudio.h> 61 #include <sound/hda_i915.h> 62 #include <linux/vgaarb.h> 63 #include <linux/vga_switcheroo.h> 64 #include <linux/firmware.h> 65 #include "hda_codec.h" 66 #include "hda_controller.h" 67 #include "hda_intel.h" 68 69 #define CREATE_TRACE_POINTS 70 #include "hda_intel_trace.h" 71 72 /* position fix mode */ 73 enum { 74 POS_FIX_AUTO, 75 POS_FIX_LPIB, 76 POS_FIX_POSBUF, 77 POS_FIX_VIACOMBO, 78 POS_FIX_COMBO, 79 }; 80 81 /* Defines for ATI HD Audio support in SB450 south bridge */ 82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 84 85 /* Defines for Nvidia HDA support */ 86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 88 #define NVIDIA_HDA_ISTRM_COH 0x4d 89 #define NVIDIA_HDA_OSTRM_COH 0x4c 90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 91 92 /* Defines for Intel SCH HDA snoop control */ 93 #define INTEL_SCH_HDA_DEVC 0x78 94 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 95 96 /* Define IN stream 0 FIFO size offset in VIA controller */ 97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 98 /* Define VIA HD Audio Device ID*/ 99 #define VIA_HDAC_DEVICE_ID 0x3288 100 101 /* max number of SDs */ 102 /* ICH, ATI and VIA have 4 playback and 4 capture */ 103 #define ICH6_NUM_CAPTURE 4 104 #define ICH6_NUM_PLAYBACK 4 105 106 /* ULI has 6 playback and 5 capture */ 107 #define ULI_NUM_CAPTURE 5 108 #define ULI_NUM_PLAYBACK 6 109 110 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 111 #define ATIHDMI_NUM_CAPTURE 0 112 #define ATIHDMI_NUM_PLAYBACK 8 113 114 /* TERA has 4 playback and 3 capture */ 115 #define TERA_NUM_CAPTURE 3 116 #define TERA_NUM_PLAYBACK 4 117 118 119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 122 static char *model[SNDRV_CARDS]; 123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 126 static int probe_only[SNDRV_CARDS]; 127 static int jackpoll_ms[SNDRV_CARDS]; 128 static bool single_cmd; 129 static int enable_msi = -1; 130 #ifdef CONFIG_SND_HDA_PATCH_LOADER 131 static char *patch[SNDRV_CARDS]; 132 #endif 133 #ifdef CONFIG_SND_HDA_INPUT_BEEP 134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 135 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 136 #endif 137 138 module_param_array(index, int, NULL, 0444); 139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 140 module_param_array(id, charp, NULL, 0444); 141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 142 module_param_array(enable, bool, NULL, 0444); 143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 144 module_param_array(model, charp, NULL, 0444); 145 MODULE_PARM_DESC(model, "Use the given board model."); 146 module_param_array(position_fix, int, NULL, 0444); 147 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 149 module_param_array(bdl_pos_adj, int, NULL, 0644); 150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 151 module_param_array(probe_mask, int, NULL, 0444); 152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 153 module_param_array(probe_only, int, NULL, 0444); 154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 155 module_param_array(jackpoll_ms, int, NULL, 0444); 156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 157 module_param(single_cmd, bool, 0444); 158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 159 "(for debugging only)."); 160 module_param(enable_msi, bint, 0444); 161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 162 #ifdef CONFIG_SND_HDA_PATCH_LOADER 163 module_param_array(patch, charp, NULL, 0444); 164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 165 #endif 166 #ifdef CONFIG_SND_HDA_INPUT_BEEP 167 module_param_array(beep_mode, bool, NULL, 0444); 168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 169 "(0=off, 1=on) (default=1)."); 170 #endif 171 172 #ifdef CONFIG_PM 173 static int param_set_xint(const char *val, const struct kernel_param *kp); 174 static const struct kernel_param_ops param_ops_xint = { 175 .set = param_set_xint, 176 .get = param_get_int, 177 }; 178 #define param_check_xint param_check_int 179 180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 181 module_param(power_save, xint, 0644); 182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 183 "(in second, 0 = disable)."); 184 185 /* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189 static bool power_save_controller = 1; 190 module_param(power_save_controller, bool, 0644); 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192 #else 193 #define power_save 0 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 212 "{Intel, ICH6M}," 213 "{Intel, ICH7}," 214 "{Intel, ESB2}," 215 "{Intel, ICH8}," 216 "{Intel, ICH9}," 217 "{Intel, ICH10}," 218 "{Intel, PCH}," 219 "{Intel, CPT}," 220 "{Intel, PPT}," 221 "{Intel, LPT}," 222 "{Intel, LPT_LP}," 223 "{Intel, WPT_LP}," 224 "{Intel, SPT}," 225 "{Intel, SPT_LP}," 226 "{Intel, HPT}," 227 "{Intel, PBG}," 228 "{Intel, SCH}," 229 "{ATI, SB450}," 230 "{ATI, SB600}," 231 "{ATI, RS600}," 232 "{ATI, RS690}," 233 "{ATI, RS780}," 234 "{ATI, R600}," 235 "{ATI, RV630}," 236 "{ATI, RV610}," 237 "{ATI, RV670}," 238 "{ATI, RV635}," 239 "{ATI, RV620}," 240 "{ATI, RV770}," 241 "{VIA, VT8251}," 242 "{VIA, VT8237A}," 243 "{SiS, SIS966}," 244 "{ULI, M5461}}"); 245 MODULE_DESCRIPTION("Intel HDA driver"); 246 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 249 #define SUPPORT_VGA_SWITCHEROO 250 #endif 251 #endif 252 253 254 /* 255 */ 256 257 /* driver types */ 258 enum { 259 AZX_DRIVER_ICH, 260 AZX_DRIVER_PCH, 261 AZX_DRIVER_SCH, 262 AZX_DRIVER_HDMI, 263 AZX_DRIVER_ATI, 264 AZX_DRIVER_ATIHDMI, 265 AZX_DRIVER_ATIHDMI_NS, 266 AZX_DRIVER_VIA, 267 AZX_DRIVER_SIS, 268 AZX_DRIVER_ULI, 269 AZX_DRIVER_NVIDIA, 270 AZX_DRIVER_TERA, 271 AZX_DRIVER_CTX, 272 AZX_DRIVER_CTHDA, 273 AZX_DRIVER_CMEDIA, 274 AZX_DRIVER_GENERIC, 275 AZX_NUM_DRIVERS, /* keep this as last entry */ 276 }; 277 278 #define azx_get_snoop_type(chip) \ 279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 281 282 /* quirks for old Intel chipsets */ 283 #define AZX_DCAPS_INTEL_ICH \ 284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 285 286 /* quirks for Intel PCH */ 287 #define AZX_DCAPS_INTEL_PCH_NOPM \ 288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH)) 290 291 #define AZX_DCAPS_INTEL_PCH \ 292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 293 294 #define AZX_DCAPS_INTEL_HASWELL \ 295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 297 AZX_DCAPS_SNOOP_TYPE(SCH)) 298 299 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 300 #define AZX_DCAPS_INTEL_BROADWELL \ 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 303 AZX_DCAPS_SNOOP_TYPE(SCH)) 304 305 #define AZX_DCAPS_INTEL_BAYTRAIL \ 306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL) 307 308 #define AZX_DCAPS_INTEL_BRASWELL \ 309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL) 310 311 #define AZX_DCAPS_INTEL_SKYLAKE \ 312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 313 AZX_DCAPS_I915_POWERWELL) 314 315 #define AZX_DCAPS_INTEL_BROXTON \ 316 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\ 317 AZX_DCAPS_I915_POWERWELL) 318 319 /* quirks for ATI SB / AMD Hudson */ 320 #define AZX_DCAPS_PRESET_ATI_SB \ 321 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 322 AZX_DCAPS_SNOOP_TYPE(ATI)) 323 324 /* quirks for ATI/AMD HDMI */ 325 #define AZX_DCAPS_PRESET_ATI_HDMI \ 326 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 327 AZX_DCAPS_NO_MSI64) 328 329 /* quirks for ATI HDMI with snoop off */ 330 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 331 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 332 333 /* quirks for Nvidia */ 334 #define AZX_DCAPS_PRESET_NVIDIA \ 335 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 336 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 337 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 338 339 #define AZX_DCAPS_PRESET_CTHDA \ 340 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 341 AZX_DCAPS_NO_64BIT |\ 342 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 343 344 /* 345 * vga_switcheroo support 346 */ 347 #ifdef SUPPORT_VGA_SWITCHEROO 348 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 349 #else 350 #define use_vga_switcheroo(chip) 0 351 #endif 352 353 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 354 ((pci)->device == 0x0c0c) || \ 355 ((pci)->device == 0x0d0c) || \ 356 ((pci)->device == 0x160c)) 357 358 #define IS_BROXTON(pci) ((pci)->device == 0x5a98) 359 360 static char *driver_short_names[] = { 361 [AZX_DRIVER_ICH] = "HDA Intel", 362 [AZX_DRIVER_PCH] = "HDA Intel PCH", 363 [AZX_DRIVER_SCH] = "HDA Intel MID", 364 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 365 [AZX_DRIVER_ATI] = "HDA ATI SB", 366 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 367 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 368 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 369 [AZX_DRIVER_SIS] = "HDA SIS966", 370 [AZX_DRIVER_ULI] = "HDA ULI M5461", 371 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 372 [AZX_DRIVER_TERA] = "HDA Teradici", 373 [AZX_DRIVER_CTX] = "HDA Creative", 374 [AZX_DRIVER_CTHDA] = "HDA Creative", 375 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 376 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 377 }; 378 379 #ifdef CONFIG_X86 380 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 381 { 382 int pages; 383 384 if (azx_snoop(chip)) 385 return; 386 if (!dmab || !dmab->area || !dmab->bytes) 387 return; 388 389 #ifdef CONFIG_SND_DMA_SGBUF 390 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 391 struct snd_sg_buf *sgbuf = dmab->private_data; 392 if (chip->driver_type == AZX_DRIVER_CMEDIA) 393 return; /* deal with only CORB/RIRB buffers */ 394 if (on) 395 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 396 else 397 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 398 return; 399 } 400 #endif 401 402 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 403 if (on) 404 set_memory_wc((unsigned long)dmab->area, pages); 405 else 406 set_memory_wb((unsigned long)dmab->area, pages); 407 } 408 409 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 410 bool on) 411 { 412 __mark_pages_wc(chip, buf, on); 413 } 414 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 415 struct snd_pcm_substream *substream, bool on) 416 { 417 if (azx_dev->wc_marked != on) { 418 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 419 azx_dev->wc_marked = on; 420 } 421 } 422 #else 423 /* NOP for other archs */ 424 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 425 bool on) 426 { 427 } 428 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 429 struct snd_pcm_substream *substream, bool on) 430 { 431 } 432 #endif 433 434 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 435 436 /* 437 * initialize the PCI registers 438 */ 439 /* update bits in a PCI register byte */ 440 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 441 unsigned char mask, unsigned char val) 442 { 443 unsigned char data; 444 445 pci_read_config_byte(pci, reg, &data); 446 data &= ~mask; 447 data |= (val & mask); 448 pci_write_config_byte(pci, reg, data); 449 } 450 451 static void azx_init_pci(struct azx *chip) 452 { 453 int snoop_type = azx_get_snoop_type(chip); 454 455 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 456 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 457 * Ensuring these bits are 0 clears playback static on some HD Audio 458 * codecs. 459 * The PCI register TCSEL is defined in the Intel manuals. 460 */ 461 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 462 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 463 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 464 } 465 466 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 467 * we need to enable snoop. 468 */ 469 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 470 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 471 azx_snoop(chip)); 472 update_pci_byte(chip->pci, 473 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 474 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 475 } 476 477 /* For NVIDIA HDA, enable snoop */ 478 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 479 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 480 azx_snoop(chip)); 481 update_pci_byte(chip->pci, 482 NVIDIA_HDA_TRANSREG_ADDR, 483 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 484 update_pci_byte(chip->pci, 485 NVIDIA_HDA_ISTRM_COH, 486 0x01, NVIDIA_HDA_ENABLE_COHBIT); 487 update_pci_byte(chip->pci, 488 NVIDIA_HDA_OSTRM_COH, 489 0x01, NVIDIA_HDA_ENABLE_COHBIT); 490 } 491 492 /* Enable SCH/PCH snoop if needed */ 493 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 494 unsigned short snoop; 495 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 496 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 497 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 498 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 499 if (!azx_snoop(chip)) 500 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 501 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 502 pci_read_config_word(chip->pci, 503 INTEL_SCH_HDA_DEVC, &snoop); 504 } 505 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 506 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 507 "Disabled" : "Enabled"); 508 } 509 } 510 511 /* 512 * In BXT-P A0, HD-Audio DMA requests is later than expected, 513 * and makes an audio stream sensitive to system latencies when 514 * 24/32 bits are playing. 515 * Adjusting threshold of DMA fifo to force the DMA request 516 * sooner to improve latency tolerance at the expense of power. 517 */ 518 static void bxt_reduce_dma_latency(struct azx *chip) 519 { 520 u32 val; 521 522 val = azx_readl(chip, SKL_EM4L); 523 val &= (0x3 << 20); 524 azx_writel(chip, SKL_EM4L, val); 525 } 526 527 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 528 { 529 struct hdac_bus *bus = azx_bus(chip); 530 struct pci_dev *pci = chip->pci; 531 532 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 533 snd_hdac_set_codec_wakeup(bus, true); 534 azx_init_chip(chip, full_reset); 535 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 536 snd_hdac_set_codec_wakeup(bus, false); 537 538 /* reduce dma latency to avoid noise */ 539 if (IS_BROXTON(pci)) 540 bxt_reduce_dma_latency(chip); 541 } 542 543 /* calculate runtime delay from LPIB */ 544 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 545 unsigned int pos) 546 { 547 struct snd_pcm_substream *substream = azx_dev->core.substream; 548 int stream = substream->stream; 549 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 550 int delay; 551 552 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 553 delay = pos - lpib_pos; 554 else 555 delay = lpib_pos - pos; 556 if (delay < 0) { 557 if (delay >= azx_dev->core.delay_negative_threshold) 558 delay = 0; 559 else 560 delay += azx_dev->core.bufsize; 561 } 562 563 if (delay >= azx_dev->core.period_bytes) { 564 dev_info(chip->card->dev, 565 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 566 delay, azx_dev->core.period_bytes); 567 delay = 0; 568 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 569 chip->get_delay[stream] = NULL; 570 } 571 572 return bytes_to_frames(substream->runtime, delay); 573 } 574 575 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 576 577 /* called from IRQ */ 578 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 579 { 580 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 581 int ok; 582 583 ok = azx_position_ok(chip, azx_dev); 584 if (ok == 1) { 585 azx_dev->irq_pending = 0; 586 return ok; 587 } else if (ok == 0) { 588 /* bogus IRQ, process it later */ 589 azx_dev->irq_pending = 1; 590 schedule_work(&hda->irq_pending_work); 591 } 592 return 0; 593 } 594 595 /* Enable/disable i915 display power for the link */ 596 static int azx_intel_link_power(struct azx *chip, bool enable) 597 { 598 struct hdac_bus *bus = azx_bus(chip); 599 600 return snd_hdac_display_power(bus, enable); 601 } 602 603 /* 604 * Check whether the current DMA position is acceptable for updating 605 * periods. Returns non-zero if it's OK. 606 * 607 * Many HD-audio controllers appear pretty inaccurate about 608 * the update-IRQ timing. The IRQ is issued before actually the 609 * data is processed. So, we need to process it afterwords in a 610 * workqueue. 611 */ 612 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 613 { 614 struct snd_pcm_substream *substream = azx_dev->core.substream; 615 int stream = substream->stream; 616 u32 wallclk; 617 unsigned int pos; 618 619 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 620 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 621 return -1; /* bogus (too early) interrupt */ 622 623 if (chip->get_position[stream]) 624 pos = chip->get_position[stream](chip, azx_dev); 625 else { /* use the position buffer as default */ 626 pos = azx_get_pos_posbuf(chip, azx_dev); 627 if (!pos || pos == (u32)-1) { 628 dev_info(chip->card->dev, 629 "Invalid position buffer, using LPIB read method instead.\n"); 630 chip->get_position[stream] = azx_get_pos_lpib; 631 if (chip->get_position[0] == azx_get_pos_lpib && 632 chip->get_position[1] == azx_get_pos_lpib) 633 azx_bus(chip)->use_posbuf = false; 634 pos = azx_get_pos_lpib(chip, azx_dev); 635 chip->get_delay[stream] = NULL; 636 } else { 637 chip->get_position[stream] = azx_get_pos_posbuf; 638 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 639 chip->get_delay[stream] = azx_get_delay_from_lpib; 640 } 641 } 642 643 if (pos >= azx_dev->core.bufsize) 644 pos = 0; 645 646 if (WARN_ONCE(!azx_dev->core.period_bytes, 647 "hda-intel: zero azx_dev->period_bytes")) 648 return -1; /* this shouldn't happen! */ 649 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 650 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 651 /* NG - it's below the first next period boundary */ 652 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; 653 azx_dev->core.start_wallclk += wallclk; 654 return 1; /* OK, it's fine */ 655 } 656 657 /* 658 * The work for pending PCM period updates. 659 */ 660 static void azx_irq_pending_work(struct work_struct *work) 661 { 662 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 663 struct azx *chip = &hda->chip; 664 struct hdac_bus *bus = azx_bus(chip); 665 struct hdac_stream *s; 666 int pending, ok; 667 668 if (!hda->irq_pending_warned) { 669 dev_info(chip->card->dev, 670 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 671 chip->card->number); 672 hda->irq_pending_warned = 1; 673 } 674 675 for (;;) { 676 pending = 0; 677 spin_lock_irq(&bus->reg_lock); 678 list_for_each_entry(s, &bus->stream_list, list) { 679 struct azx_dev *azx_dev = stream_to_azx_dev(s); 680 if (!azx_dev->irq_pending || 681 !s->substream || 682 !s->running) 683 continue; 684 ok = azx_position_ok(chip, azx_dev); 685 if (ok > 0) { 686 azx_dev->irq_pending = 0; 687 spin_unlock(&bus->reg_lock); 688 snd_pcm_period_elapsed(s->substream); 689 spin_lock(&bus->reg_lock); 690 } else if (ok < 0) { 691 pending = 0; /* too early */ 692 } else 693 pending++; 694 } 695 spin_unlock_irq(&bus->reg_lock); 696 if (!pending) 697 return; 698 msleep(1); 699 } 700 } 701 702 /* clear irq_pending flags and assure no on-going workq */ 703 static void azx_clear_irq_pending(struct azx *chip) 704 { 705 struct hdac_bus *bus = azx_bus(chip); 706 struct hdac_stream *s; 707 708 spin_lock_irq(&bus->reg_lock); 709 list_for_each_entry(s, &bus->stream_list, list) { 710 struct azx_dev *azx_dev = stream_to_azx_dev(s); 711 azx_dev->irq_pending = 0; 712 } 713 spin_unlock_irq(&bus->reg_lock); 714 } 715 716 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 717 { 718 struct hdac_bus *bus = azx_bus(chip); 719 720 if (request_irq(chip->pci->irq, azx_interrupt, 721 chip->msi ? 0 : IRQF_SHARED, 722 KBUILD_MODNAME, chip)) { 723 dev_err(chip->card->dev, 724 "unable to grab IRQ %d, disabling device\n", 725 chip->pci->irq); 726 if (do_disconnect) 727 snd_card_disconnect(chip->card); 728 return -1; 729 } 730 bus->irq = chip->pci->irq; 731 pci_intx(chip->pci, !chip->msi); 732 return 0; 733 } 734 735 /* get the current DMA position with correction on VIA chips */ 736 static unsigned int azx_via_get_position(struct azx *chip, 737 struct azx_dev *azx_dev) 738 { 739 unsigned int link_pos, mini_pos, bound_pos; 740 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 741 unsigned int fifo_size; 742 743 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 744 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 745 /* Playback, no problem using link position */ 746 return link_pos; 747 } 748 749 /* Capture */ 750 /* For new chipset, 751 * use mod to get the DMA position just like old chipset 752 */ 753 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 754 mod_dma_pos %= azx_dev->core.period_bytes; 755 756 /* azx_dev->fifo_size can't get FIFO size of in stream. 757 * Get from base address + offset. 758 */ 759 fifo_size = readw(azx_bus(chip)->remap_addr + 760 VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 761 762 if (azx_dev->insufficient) { 763 /* Link position never gather than FIFO size */ 764 if (link_pos <= fifo_size) 765 return 0; 766 767 azx_dev->insufficient = 0; 768 } 769 770 if (link_pos <= fifo_size) 771 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 772 else 773 mini_pos = link_pos - fifo_size; 774 775 /* Find nearest previous boudary */ 776 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 777 mod_link_pos = link_pos % azx_dev->core.period_bytes; 778 if (mod_link_pos >= fifo_size) 779 bound_pos = link_pos - mod_link_pos; 780 else if (mod_dma_pos >= mod_mini_pos) 781 bound_pos = mini_pos - mod_mini_pos; 782 else { 783 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 784 if (bound_pos >= azx_dev->core.bufsize) 785 bound_pos = 0; 786 } 787 788 /* Calculate real DMA position we want */ 789 return bound_pos + mod_dma_pos; 790 } 791 792 #ifdef CONFIG_PM 793 static DEFINE_MUTEX(card_list_lock); 794 static LIST_HEAD(card_list); 795 796 static void azx_add_card_list(struct azx *chip) 797 { 798 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 799 mutex_lock(&card_list_lock); 800 list_add(&hda->list, &card_list); 801 mutex_unlock(&card_list_lock); 802 } 803 804 static void azx_del_card_list(struct azx *chip) 805 { 806 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 807 mutex_lock(&card_list_lock); 808 list_del_init(&hda->list); 809 mutex_unlock(&card_list_lock); 810 } 811 812 /* trigger power-save check at writing parameter */ 813 static int param_set_xint(const char *val, const struct kernel_param *kp) 814 { 815 struct hda_intel *hda; 816 struct azx *chip; 817 int prev = power_save; 818 int ret = param_set_int(val, kp); 819 820 if (ret || prev == power_save) 821 return ret; 822 823 mutex_lock(&card_list_lock); 824 list_for_each_entry(hda, &card_list, list) { 825 chip = &hda->chip; 826 if (!hda->probe_continued || chip->disabled) 827 continue; 828 snd_hda_set_power_save(&chip->bus, power_save * 1000); 829 } 830 mutex_unlock(&card_list_lock); 831 return 0; 832 } 833 #else 834 #define azx_add_card_list(chip) /* NOP */ 835 #define azx_del_card_list(chip) /* NOP */ 836 #endif /* CONFIG_PM */ 837 838 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK 839 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value) 840 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK: 841 * BCLK = CDCLK * M / N 842 * The values will be lost when the display power well is disabled and need to 843 * be restored to avoid abnormal playback speed. 844 */ 845 static void haswell_set_bclk(struct hda_intel *hda) 846 { 847 struct azx *chip = &hda->chip; 848 int cdclk_freq; 849 unsigned int bclk_m, bclk_n; 850 851 if (!hda->need_i915_power) 852 return; 853 854 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip)); 855 switch (cdclk_freq) { 856 case 337500: 857 bclk_m = 16; 858 bclk_n = 225; 859 break; 860 861 case 450000: 862 default: /* default CDCLK 450MHz */ 863 bclk_m = 4; 864 bclk_n = 75; 865 break; 866 867 case 540000: 868 bclk_m = 4; 869 bclk_n = 90; 870 break; 871 872 case 675000: 873 bclk_m = 8; 874 bclk_n = 225; 875 break; 876 } 877 878 azx_writew(chip, HSW_EM4, bclk_m); 879 azx_writew(chip, HSW_EM5, bclk_n); 880 } 881 882 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 883 /* 884 * power management 885 */ 886 static int azx_suspend(struct device *dev) 887 { 888 struct snd_card *card = dev_get_drvdata(dev); 889 struct azx *chip; 890 struct hda_intel *hda; 891 struct hdac_bus *bus; 892 893 if (!card) 894 return 0; 895 896 chip = card->private_data; 897 hda = container_of(chip, struct hda_intel, chip); 898 if (chip->disabled || hda->init_failed || !chip->running) 899 return 0; 900 901 bus = azx_bus(chip); 902 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 903 azx_clear_irq_pending(chip); 904 azx_stop_chip(chip); 905 azx_enter_link_reset(chip); 906 if (bus->irq >= 0) { 907 free_irq(bus->irq, chip); 908 bus->irq = -1; 909 } 910 911 if (chip->msi) 912 pci_disable_msi(chip->pci); 913 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 914 && hda->need_i915_power) 915 snd_hdac_display_power(bus, false); 916 917 trace_azx_suspend(chip); 918 return 0; 919 } 920 921 static int azx_resume(struct device *dev) 922 { 923 struct pci_dev *pci = to_pci_dev(dev); 924 struct snd_card *card = dev_get_drvdata(dev); 925 struct azx *chip; 926 struct hda_intel *hda; 927 928 if (!card) 929 return 0; 930 931 chip = card->private_data; 932 hda = container_of(chip, struct hda_intel, chip); 933 if (chip->disabled || hda->init_failed || !chip->running) 934 return 0; 935 936 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 937 && hda->need_i915_power) { 938 snd_hdac_display_power(azx_bus(chip), true); 939 haswell_set_bclk(hda); 940 } 941 if (chip->msi) 942 if (pci_enable_msi(pci) < 0) 943 chip->msi = 0; 944 if (azx_acquire_irq(chip, 1) < 0) 945 return -EIO; 946 azx_init_pci(chip); 947 948 hda_intel_init_chip(chip, true); 949 950 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 951 952 trace_azx_resume(chip); 953 return 0; 954 } 955 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 956 957 #ifdef CONFIG_PM 958 static int azx_runtime_suspend(struct device *dev) 959 { 960 struct snd_card *card = dev_get_drvdata(dev); 961 struct azx *chip; 962 struct hda_intel *hda; 963 964 if (!card) 965 return 0; 966 967 chip = card->private_data; 968 hda = container_of(chip, struct hda_intel, chip); 969 if (chip->disabled || hda->init_failed) 970 return 0; 971 972 if (!azx_has_pm_runtime(chip)) 973 return 0; 974 975 /* enable controller wake up event */ 976 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 977 STATESTS_INT_MASK); 978 979 azx_stop_chip(chip); 980 azx_enter_link_reset(chip); 981 azx_clear_irq_pending(chip); 982 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 983 && hda->need_i915_power) 984 snd_hdac_display_power(azx_bus(chip), false); 985 986 trace_azx_runtime_suspend(chip); 987 return 0; 988 } 989 990 static int azx_runtime_resume(struct device *dev) 991 { 992 struct snd_card *card = dev_get_drvdata(dev); 993 struct azx *chip; 994 struct hda_intel *hda; 995 struct hdac_bus *bus; 996 struct hda_codec *codec; 997 int status; 998 999 if (!card) 1000 return 0; 1001 1002 chip = card->private_data; 1003 hda = container_of(chip, struct hda_intel, chip); 1004 if (chip->disabled || hda->init_failed) 1005 return 0; 1006 1007 if (!azx_has_pm_runtime(chip)) 1008 return 0; 1009 1010 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1011 bus = azx_bus(chip); 1012 if (hda->need_i915_power) { 1013 snd_hdac_display_power(bus, true); 1014 haswell_set_bclk(hda); 1015 } else { 1016 /* toggle codec wakeup bit for STATESTS read */ 1017 snd_hdac_set_codec_wakeup(bus, true); 1018 snd_hdac_set_codec_wakeup(bus, false); 1019 } 1020 } 1021 1022 /* Read STATESTS before controller reset */ 1023 status = azx_readw(chip, STATESTS); 1024 1025 azx_init_pci(chip); 1026 hda_intel_init_chip(chip, true); 1027 1028 if (status) { 1029 list_for_each_codec(codec, &chip->bus) 1030 if (status & (1 << codec->addr)) 1031 schedule_delayed_work(&codec->jackpoll_work, 1032 codec->jackpoll_interval); 1033 } 1034 1035 /* disable controller Wake Up event*/ 1036 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1037 ~STATESTS_INT_MASK); 1038 1039 trace_azx_runtime_resume(chip); 1040 return 0; 1041 } 1042 1043 static int azx_runtime_idle(struct device *dev) 1044 { 1045 struct snd_card *card = dev_get_drvdata(dev); 1046 struct azx *chip; 1047 struct hda_intel *hda; 1048 1049 if (!card) 1050 return 0; 1051 1052 chip = card->private_data; 1053 hda = container_of(chip, struct hda_intel, chip); 1054 if (chip->disabled || hda->init_failed) 1055 return 0; 1056 1057 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1058 azx_bus(chip)->codec_powered || !chip->running) 1059 return -EBUSY; 1060 1061 return 0; 1062 } 1063 1064 static const struct dev_pm_ops azx_pm = { 1065 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1066 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1067 }; 1068 1069 #define AZX_PM_OPS &azx_pm 1070 #else 1071 #define AZX_PM_OPS NULL 1072 #endif /* CONFIG_PM */ 1073 1074 1075 static int azx_probe_continue(struct azx *chip); 1076 1077 #ifdef SUPPORT_VGA_SWITCHEROO 1078 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1079 1080 static void azx_vs_set_state(struct pci_dev *pci, 1081 enum vga_switcheroo_state state) 1082 { 1083 struct snd_card *card = pci_get_drvdata(pci); 1084 struct azx *chip = card->private_data; 1085 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1086 bool disabled; 1087 1088 wait_for_completion(&hda->probe_wait); 1089 if (hda->init_failed) 1090 return; 1091 1092 disabled = (state == VGA_SWITCHEROO_OFF); 1093 if (chip->disabled == disabled) 1094 return; 1095 1096 if (!hda->probe_continued) { 1097 chip->disabled = disabled; 1098 if (!disabled) { 1099 dev_info(chip->card->dev, 1100 "Start delayed initialization\n"); 1101 if (azx_probe_continue(chip) < 0) { 1102 dev_err(chip->card->dev, "initialization error\n"); 1103 hda->init_failed = true; 1104 } 1105 } 1106 } else { 1107 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1108 disabled ? "Disabling" : "Enabling"); 1109 if (disabled) { 1110 pm_runtime_put_sync_suspend(card->dev); 1111 azx_suspend(card->dev); 1112 /* when we get suspended by vga_switcheroo we end up in D3cold, 1113 * however we have no ACPI handle, so pci/acpi can't put us there, 1114 * put ourselves there */ 1115 pci->current_state = PCI_D3cold; 1116 chip->disabled = true; 1117 if (snd_hda_lock_devices(&chip->bus)) 1118 dev_warn(chip->card->dev, 1119 "Cannot lock devices!\n"); 1120 } else { 1121 snd_hda_unlock_devices(&chip->bus); 1122 pm_runtime_get_noresume(card->dev); 1123 chip->disabled = false; 1124 azx_resume(card->dev); 1125 } 1126 } 1127 } 1128 1129 static bool azx_vs_can_switch(struct pci_dev *pci) 1130 { 1131 struct snd_card *card = pci_get_drvdata(pci); 1132 struct azx *chip = card->private_data; 1133 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1134 1135 wait_for_completion(&hda->probe_wait); 1136 if (hda->init_failed) 1137 return false; 1138 if (chip->disabled || !hda->probe_continued) 1139 return true; 1140 if (snd_hda_lock_devices(&chip->bus)) 1141 return false; 1142 snd_hda_unlock_devices(&chip->bus); 1143 return true; 1144 } 1145 1146 static void init_vga_switcheroo(struct azx *chip) 1147 { 1148 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1149 struct pci_dev *p = get_bound_vga(chip->pci); 1150 if (p) { 1151 dev_info(chip->card->dev, 1152 "Handle vga_switcheroo audio client\n"); 1153 hda->use_vga_switcheroo = 1; 1154 pci_dev_put(p); 1155 } 1156 } 1157 1158 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1159 .set_gpu_state = azx_vs_set_state, 1160 .can_switch = azx_vs_can_switch, 1161 }; 1162 1163 static int register_vga_switcheroo(struct azx *chip) 1164 { 1165 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1166 int err; 1167 1168 if (!hda->use_vga_switcheroo) 1169 return 0; 1170 /* FIXME: currently only handling DIS controller 1171 * is there any machine with two switchable HDMI audio controllers? 1172 */ 1173 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1174 VGA_SWITCHEROO_DIS); 1175 if (err < 0) 1176 return err; 1177 hda->vga_switcheroo_registered = 1; 1178 1179 /* register as an optimus hdmi audio power domain */ 1180 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1181 &hda->hdmi_pm_domain); 1182 return 0; 1183 } 1184 #else 1185 #define init_vga_switcheroo(chip) /* NOP */ 1186 #define register_vga_switcheroo(chip) 0 1187 #define check_hdmi_disabled(pci) false 1188 #endif /* SUPPORT_VGA_SWITCHER */ 1189 1190 /* 1191 * destructor 1192 */ 1193 static int azx_free(struct azx *chip) 1194 { 1195 struct pci_dev *pci = chip->pci; 1196 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1197 struct hdac_bus *bus = azx_bus(chip); 1198 1199 if (azx_has_pm_runtime(chip) && chip->running) 1200 pm_runtime_get_noresume(&pci->dev); 1201 1202 azx_del_card_list(chip); 1203 1204 hda->init_failed = 1; /* to be sure */ 1205 complete_all(&hda->probe_wait); 1206 1207 if (use_vga_switcheroo(hda)) { 1208 if (chip->disabled && hda->probe_continued) 1209 snd_hda_unlock_devices(&chip->bus); 1210 if (hda->vga_switcheroo_registered) 1211 vga_switcheroo_unregister_client(chip->pci); 1212 } 1213 1214 if (bus->chip_init) { 1215 azx_clear_irq_pending(chip); 1216 azx_stop_all_streams(chip); 1217 azx_stop_chip(chip); 1218 } 1219 1220 if (bus->irq >= 0) 1221 free_irq(bus->irq, (void*)chip); 1222 if (chip->msi) 1223 pci_disable_msi(chip->pci); 1224 iounmap(bus->remap_addr); 1225 1226 azx_free_stream_pages(chip); 1227 azx_free_streams(chip); 1228 snd_hdac_bus_exit(bus); 1229 1230 if (chip->region_requested) 1231 pci_release_regions(chip->pci); 1232 1233 pci_disable_device(chip->pci); 1234 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1235 release_firmware(chip->fw); 1236 #endif 1237 1238 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1239 if (hda->need_i915_power) 1240 snd_hdac_display_power(bus, false); 1241 snd_hdac_i915_exit(bus); 1242 } 1243 kfree(hda); 1244 1245 return 0; 1246 } 1247 1248 static int azx_dev_disconnect(struct snd_device *device) 1249 { 1250 struct azx *chip = device->device_data; 1251 1252 chip->bus.shutdown = 1; 1253 return 0; 1254 } 1255 1256 static int azx_dev_free(struct snd_device *device) 1257 { 1258 return azx_free(device->device_data); 1259 } 1260 1261 #ifdef SUPPORT_VGA_SWITCHEROO 1262 /* 1263 * Check of disabled HDMI controller by vga_switcheroo 1264 */ 1265 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1266 { 1267 struct pci_dev *p; 1268 1269 /* check only discrete GPU */ 1270 switch (pci->vendor) { 1271 case PCI_VENDOR_ID_ATI: 1272 case PCI_VENDOR_ID_AMD: 1273 case PCI_VENDOR_ID_NVIDIA: 1274 if (pci->devfn == 1) { 1275 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1276 pci->bus->number, 0); 1277 if (p) { 1278 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1279 return p; 1280 pci_dev_put(p); 1281 } 1282 } 1283 break; 1284 } 1285 return NULL; 1286 } 1287 1288 static bool check_hdmi_disabled(struct pci_dev *pci) 1289 { 1290 bool vga_inactive = false; 1291 struct pci_dev *p = get_bound_vga(pci); 1292 1293 if (p) { 1294 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1295 vga_inactive = true; 1296 pci_dev_put(p); 1297 } 1298 return vga_inactive; 1299 } 1300 #endif /* SUPPORT_VGA_SWITCHEROO */ 1301 1302 /* 1303 * white/black-listing for position_fix 1304 */ 1305 static struct snd_pci_quirk position_fix_list[] = { 1306 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1307 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1308 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1309 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1310 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1311 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1312 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1313 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1314 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1315 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1316 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1317 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1318 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1319 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1320 {} 1321 }; 1322 1323 static int check_position_fix(struct azx *chip, int fix) 1324 { 1325 const struct snd_pci_quirk *q; 1326 1327 switch (fix) { 1328 case POS_FIX_AUTO: 1329 case POS_FIX_LPIB: 1330 case POS_FIX_POSBUF: 1331 case POS_FIX_VIACOMBO: 1332 case POS_FIX_COMBO: 1333 return fix; 1334 } 1335 1336 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1337 if (q) { 1338 dev_info(chip->card->dev, 1339 "position_fix set to %d for device %04x:%04x\n", 1340 q->value, q->subvendor, q->subdevice); 1341 return q->value; 1342 } 1343 1344 /* Check VIA/ATI HD Audio Controller exist */ 1345 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 1346 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1347 return POS_FIX_VIACOMBO; 1348 } 1349 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1350 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1351 return POS_FIX_LPIB; 1352 } 1353 return POS_FIX_AUTO; 1354 } 1355 1356 static void assign_position_fix(struct azx *chip, int fix) 1357 { 1358 static azx_get_pos_callback_t callbacks[] = { 1359 [POS_FIX_AUTO] = NULL, 1360 [POS_FIX_LPIB] = azx_get_pos_lpib, 1361 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1362 [POS_FIX_VIACOMBO] = azx_via_get_position, 1363 [POS_FIX_COMBO] = azx_get_pos_lpib, 1364 }; 1365 1366 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1367 1368 /* combo mode uses LPIB only for playback */ 1369 if (fix == POS_FIX_COMBO) 1370 chip->get_position[1] = NULL; 1371 1372 if (fix == POS_FIX_POSBUF && 1373 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1374 chip->get_delay[0] = chip->get_delay[1] = 1375 azx_get_delay_from_lpib; 1376 } 1377 1378 } 1379 1380 /* 1381 * black-lists for probe_mask 1382 */ 1383 static struct snd_pci_quirk probe_mask_list[] = { 1384 /* Thinkpad often breaks the controller communication when accessing 1385 * to the non-working (or non-existing) modem codec slot. 1386 */ 1387 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1388 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1389 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1390 /* broken BIOS */ 1391 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1392 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1393 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1394 /* forced codec slots */ 1395 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1396 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1397 /* WinFast VP200 H (Teradici) user reported broken communication */ 1398 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1399 {} 1400 }; 1401 1402 #define AZX_FORCE_CODEC_MASK 0x100 1403 1404 static void check_probe_mask(struct azx *chip, int dev) 1405 { 1406 const struct snd_pci_quirk *q; 1407 1408 chip->codec_probe_mask = probe_mask[dev]; 1409 if (chip->codec_probe_mask == -1) { 1410 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1411 if (q) { 1412 dev_info(chip->card->dev, 1413 "probe_mask set to 0x%x for device %04x:%04x\n", 1414 q->value, q->subvendor, q->subdevice); 1415 chip->codec_probe_mask = q->value; 1416 } 1417 } 1418 1419 /* check forced option */ 1420 if (chip->codec_probe_mask != -1 && 1421 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1422 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1423 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1424 (int)azx_bus(chip)->codec_mask); 1425 } 1426 } 1427 1428 /* 1429 * white/black-list for enable_msi 1430 */ 1431 static struct snd_pci_quirk msi_black_list[] = { 1432 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1433 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1434 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1435 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1436 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1437 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1438 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1439 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1440 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1441 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1442 {} 1443 }; 1444 1445 static void check_msi(struct azx *chip) 1446 { 1447 const struct snd_pci_quirk *q; 1448 1449 if (enable_msi >= 0) { 1450 chip->msi = !!enable_msi; 1451 return; 1452 } 1453 chip->msi = 1; /* enable MSI as default */ 1454 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1455 if (q) { 1456 dev_info(chip->card->dev, 1457 "msi for device %04x:%04x set to %d\n", 1458 q->subvendor, q->subdevice, q->value); 1459 chip->msi = q->value; 1460 return; 1461 } 1462 1463 /* NVidia chipsets seem to cause troubles with MSI */ 1464 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1465 dev_info(chip->card->dev, "Disabling MSI\n"); 1466 chip->msi = 0; 1467 } 1468 } 1469 1470 /* check the snoop mode availability */ 1471 static void azx_check_snoop_available(struct azx *chip) 1472 { 1473 int snoop = hda_snoop; 1474 1475 if (snoop >= 0) { 1476 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1477 snoop ? "snoop" : "non-snoop"); 1478 chip->snoop = snoop; 1479 return; 1480 } 1481 1482 snoop = true; 1483 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1484 chip->driver_type == AZX_DRIVER_VIA) { 1485 /* force to non-snoop mode for a new VIA controller 1486 * when BIOS is set 1487 */ 1488 u8 val; 1489 pci_read_config_byte(chip->pci, 0x42, &val); 1490 if (!(val & 0x80) && chip->pci->revision == 0x30) 1491 snoop = false; 1492 } 1493 1494 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1495 snoop = false; 1496 1497 chip->snoop = snoop; 1498 if (!snoop) 1499 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1500 } 1501 1502 static void azx_probe_work(struct work_struct *work) 1503 { 1504 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1505 azx_probe_continue(&hda->chip); 1506 } 1507 1508 /* 1509 * constructor 1510 */ 1511 static const struct hdac_io_ops pci_hda_io_ops; 1512 static const struct hda_controller_ops pci_hda_ops; 1513 1514 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1515 int dev, unsigned int driver_caps, 1516 struct azx **rchip) 1517 { 1518 static struct snd_device_ops ops = { 1519 .dev_disconnect = azx_dev_disconnect, 1520 .dev_free = azx_dev_free, 1521 }; 1522 struct hda_intel *hda; 1523 struct azx *chip; 1524 int err; 1525 1526 *rchip = NULL; 1527 1528 err = pci_enable_device(pci); 1529 if (err < 0) 1530 return err; 1531 1532 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1533 if (!hda) { 1534 pci_disable_device(pci); 1535 return -ENOMEM; 1536 } 1537 1538 chip = &hda->chip; 1539 mutex_init(&chip->open_mutex); 1540 chip->card = card; 1541 chip->pci = pci; 1542 chip->ops = &pci_hda_ops; 1543 chip->driver_caps = driver_caps; 1544 chip->driver_type = driver_caps & 0xff; 1545 check_msi(chip); 1546 chip->dev_index = dev; 1547 chip->jackpoll_ms = jackpoll_ms; 1548 INIT_LIST_HEAD(&chip->pcm_list); 1549 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1550 INIT_LIST_HEAD(&hda->list); 1551 init_vga_switcheroo(chip); 1552 init_completion(&hda->probe_wait); 1553 1554 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1555 1556 check_probe_mask(chip, dev); 1557 1558 chip->single_cmd = single_cmd; 1559 azx_check_snoop_available(chip); 1560 1561 if (bdl_pos_adj[dev] < 0) { 1562 switch (chip->driver_type) { 1563 case AZX_DRIVER_ICH: 1564 case AZX_DRIVER_PCH: 1565 bdl_pos_adj[dev] = 1; 1566 break; 1567 default: 1568 bdl_pos_adj[dev] = 32; 1569 break; 1570 } 1571 } 1572 chip->bdl_pos_adj = bdl_pos_adj; 1573 1574 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops); 1575 if (err < 0) { 1576 kfree(hda); 1577 pci_disable_device(pci); 1578 return err; 1579 } 1580 1581 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1582 if (err < 0) { 1583 dev_err(card->dev, "Error creating device [card]!\n"); 1584 azx_free(chip); 1585 return err; 1586 } 1587 1588 /* continue probing in work context as may trigger request module */ 1589 INIT_WORK(&hda->probe_work, azx_probe_work); 1590 1591 *rchip = chip; 1592 1593 return 0; 1594 } 1595 1596 static int azx_first_init(struct azx *chip) 1597 { 1598 int dev = chip->dev_index; 1599 struct pci_dev *pci = chip->pci; 1600 struct snd_card *card = chip->card; 1601 struct hdac_bus *bus = azx_bus(chip); 1602 int err; 1603 unsigned short gcap; 1604 unsigned int dma_bits = 64; 1605 1606 #if BITS_PER_LONG != 64 1607 /* Fix up base address on ULI M5461 */ 1608 if (chip->driver_type == AZX_DRIVER_ULI) { 1609 u16 tmp3; 1610 pci_read_config_word(pci, 0x40, &tmp3); 1611 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1612 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1613 } 1614 #endif 1615 1616 err = pci_request_regions(pci, "ICH HD audio"); 1617 if (err < 0) 1618 return err; 1619 chip->region_requested = 1; 1620 1621 bus->addr = pci_resource_start(pci, 0); 1622 bus->remap_addr = pci_ioremap_bar(pci, 0); 1623 if (bus->remap_addr == NULL) { 1624 dev_err(card->dev, "ioremap error\n"); 1625 return -ENXIO; 1626 } 1627 1628 if (chip->msi) { 1629 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1630 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1631 pci->no_64bit_msi = true; 1632 } 1633 if (pci_enable_msi(pci) < 0) 1634 chip->msi = 0; 1635 } 1636 1637 if (azx_acquire_irq(chip, 0) < 0) 1638 return -EBUSY; 1639 1640 pci_set_master(pci); 1641 synchronize_irq(bus->irq); 1642 1643 gcap = azx_readw(chip, GCAP); 1644 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1645 1646 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1647 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1648 dma_bits = 40; 1649 1650 /* disable SB600 64bit support for safety */ 1651 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1652 struct pci_dev *p_smbus; 1653 dma_bits = 40; 1654 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1655 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1656 NULL); 1657 if (p_smbus) { 1658 if (p_smbus->revision < 0x30) 1659 gcap &= ~AZX_GCAP_64OK; 1660 pci_dev_put(p_smbus); 1661 } 1662 } 1663 1664 /* disable 64bit DMA address on some devices */ 1665 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1666 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1667 gcap &= ~AZX_GCAP_64OK; 1668 } 1669 1670 /* disable buffer size rounding to 128-byte multiples if supported */ 1671 if (align_buffer_size >= 0) 1672 chip->align_buffer_size = !!align_buffer_size; 1673 else { 1674 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1675 chip->align_buffer_size = 0; 1676 else 1677 chip->align_buffer_size = 1; 1678 } 1679 1680 /* allow 64bit DMA address if supported by H/W */ 1681 if (!(gcap & AZX_GCAP_64OK)) 1682 dma_bits = 32; 1683 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1684 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1685 } else { 1686 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1687 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1688 } 1689 1690 /* read number of streams from GCAP register instead of using 1691 * hardcoded value 1692 */ 1693 chip->capture_streams = (gcap >> 8) & 0x0f; 1694 chip->playback_streams = (gcap >> 12) & 0x0f; 1695 if (!chip->playback_streams && !chip->capture_streams) { 1696 /* gcap didn't give any info, switching to old method */ 1697 1698 switch (chip->driver_type) { 1699 case AZX_DRIVER_ULI: 1700 chip->playback_streams = ULI_NUM_PLAYBACK; 1701 chip->capture_streams = ULI_NUM_CAPTURE; 1702 break; 1703 case AZX_DRIVER_ATIHDMI: 1704 case AZX_DRIVER_ATIHDMI_NS: 1705 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1706 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1707 break; 1708 case AZX_DRIVER_GENERIC: 1709 default: 1710 chip->playback_streams = ICH6_NUM_PLAYBACK; 1711 chip->capture_streams = ICH6_NUM_CAPTURE; 1712 break; 1713 } 1714 } 1715 chip->capture_index_offset = 0; 1716 chip->playback_index_offset = chip->capture_streams; 1717 chip->num_streams = chip->playback_streams + chip->capture_streams; 1718 1719 /* initialize streams */ 1720 err = azx_init_streams(chip); 1721 if (err < 0) 1722 return err; 1723 1724 err = azx_alloc_stream_pages(chip); 1725 if (err < 0) 1726 return err; 1727 1728 /* initialize chip */ 1729 azx_init_pci(chip); 1730 1731 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1732 struct hda_intel *hda; 1733 1734 hda = container_of(chip, struct hda_intel, chip); 1735 haswell_set_bclk(hda); 1736 } 1737 1738 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1739 1740 /* codec detection */ 1741 if (!azx_bus(chip)->codec_mask) { 1742 dev_err(card->dev, "no codecs found!\n"); 1743 return -ENODEV; 1744 } 1745 1746 strcpy(card->driver, "HDA-Intel"); 1747 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1748 sizeof(card->shortname)); 1749 snprintf(card->longname, sizeof(card->longname), 1750 "%s at 0x%lx irq %i", 1751 card->shortname, bus->addr, bus->irq); 1752 1753 return 0; 1754 } 1755 1756 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1757 /* callback from request_firmware_nowait() */ 1758 static void azx_firmware_cb(const struct firmware *fw, void *context) 1759 { 1760 struct snd_card *card = context; 1761 struct azx *chip = card->private_data; 1762 struct pci_dev *pci = chip->pci; 1763 1764 if (!fw) { 1765 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1766 goto error; 1767 } 1768 1769 chip->fw = fw; 1770 if (!chip->disabled) { 1771 /* continue probing */ 1772 if (azx_probe_continue(chip)) 1773 goto error; 1774 } 1775 return; /* OK */ 1776 1777 error: 1778 snd_card_free(card); 1779 pci_set_drvdata(pci, NULL); 1780 } 1781 #endif 1782 1783 /* 1784 * HDA controller ops. 1785 */ 1786 1787 /* PCI register access. */ 1788 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1789 { 1790 writel(value, addr); 1791 } 1792 1793 static u32 pci_azx_readl(u32 __iomem *addr) 1794 { 1795 return readl(addr); 1796 } 1797 1798 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1799 { 1800 writew(value, addr); 1801 } 1802 1803 static u16 pci_azx_readw(u16 __iomem *addr) 1804 { 1805 return readw(addr); 1806 } 1807 1808 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1809 { 1810 writeb(value, addr); 1811 } 1812 1813 static u8 pci_azx_readb(u8 __iomem *addr) 1814 { 1815 return readb(addr); 1816 } 1817 1818 static int disable_msi_reset_irq(struct azx *chip) 1819 { 1820 struct hdac_bus *bus = azx_bus(chip); 1821 int err; 1822 1823 free_irq(bus->irq, chip); 1824 bus->irq = -1; 1825 pci_disable_msi(chip->pci); 1826 chip->msi = 0; 1827 err = azx_acquire_irq(chip, 1); 1828 if (err < 0) 1829 return err; 1830 1831 return 0; 1832 } 1833 1834 /* DMA page allocation helpers. */ 1835 static int dma_alloc_pages(struct hdac_bus *bus, 1836 int type, 1837 size_t size, 1838 struct snd_dma_buffer *buf) 1839 { 1840 struct azx *chip = bus_to_azx(bus); 1841 int err; 1842 1843 err = snd_dma_alloc_pages(type, 1844 bus->dev, 1845 size, buf); 1846 if (err < 0) 1847 return err; 1848 mark_pages_wc(chip, buf, true); 1849 return 0; 1850 } 1851 1852 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 1853 { 1854 struct azx *chip = bus_to_azx(bus); 1855 1856 mark_pages_wc(chip, buf, false); 1857 snd_dma_free_pages(buf); 1858 } 1859 1860 static int substream_alloc_pages(struct azx *chip, 1861 struct snd_pcm_substream *substream, 1862 size_t size) 1863 { 1864 struct azx_dev *azx_dev = get_azx_dev(substream); 1865 int ret; 1866 1867 mark_runtime_wc(chip, azx_dev, substream, false); 1868 ret = snd_pcm_lib_malloc_pages(substream, size); 1869 if (ret < 0) 1870 return ret; 1871 mark_runtime_wc(chip, azx_dev, substream, true); 1872 return 0; 1873 } 1874 1875 static int substream_free_pages(struct azx *chip, 1876 struct snd_pcm_substream *substream) 1877 { 1878 struct azx_dev *azx_dev = get_azx_dev(substream); 1879 mark_runtime_wc(chip, azx_dev, substream, false); 1880 return snd_pcm_lib_free_pages(substream); 1881 } 1882 1883 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1884 struct vm_area_struct *area) 1885 { 1886 #ifdef CONFIG_X86 1887 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1888 struct azx *chip = apcm->chip; 1889 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1890 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1891 #endif 1892 } 1893 1894 static const struct hdac_io_ops pci_hda_io_ops = { 1895 .reg_writel = pci_azx_writel, 1896 .reg_readl = pci_azx_readl, 1897 .reg_writew = pci_azx_writew, 1898 .reg_readw = pci_azx_readw, 1899 .reg_writeb = pci_azx_writeb, 1900 .reg_readb = pci_azx_readb, 1901 .dma_alloc_pages = dma_alloc_pages, 1902 .dma_free_pages = dma_free_pages, 1903 }; 1904 1905 static const struct hda_controller_ops pci_hda_ops = { 1906 .disable_msi_reset_irq = disable_msi_reset_irq, 1907 .substream_alloc_pages = substream_alloc_pages, 1908 .substream_free_pages = substream_free_pages, 1909 .pcm_mmap_prepare = pcm_mmap_prepare, 1910 .position_check = azx_position_check, 1911 .link_power = azx_intel_link_power, 1912 }; 1913 1914 static int azx_probe(struct pci_dev *pci, 1915 const struct pci_device_id *pci_id) 1916 { 1917 static int dev; 1918 struct snd_card *card; 1919 struct hda_intel *hda; 1920 struct azx *chip; 1921 bool schedule_probe; 1922 int err; 1923 1924 if (dev >= SNDRV_CARDS) 1925 return -ENODEV; 1926 if (!enable[dev]) { 1927 dev++; 1928 return -ENOENT; 1929 } 1930 1931 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1932 0, &card); 1933 if (err < 0) { 1934 dev_err(&pci->dev, "Error creating card!\n"); 1935 return err; 1936 } 1937 1938 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 1939 if (err < 0) 1940 goto out_free; 1941 card->private_data = chip; 1942 hda = container_of(chip, struct hda_intel, chip); 1943 1944 pci_set_drvdata(pci, card); 1945 1946 err = register_vga_switcheroo(chip); 1947 if (err < 0) { 1948 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 1949 goto out_free; 1950 } 1951 1952 if (check_hdmi_disabled(pci)) { 1953 dev_info(card->dev, "VGA controller is disabled\n"); 1954 dev_info(card->dev, "Delaying initialization\n"); 1955 chip->disabled = true; 1956 } 1957 1958 schedule_probe = !chip->disabled; 1959 1960 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1961 if (patch[dev] && *patch[dev]) { 1962 dev_info(card->dev, "Applying patch firmware '%s'\n", 1963 patch[dev]); 1964 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1965 &pci->dev, GFP_KERNEL, card, 1966 azx_firmware_cb); 1967 if (err < 0) 1968 goto out_free; 1969 schedule_probe = false; /* continued in azx_firmware_cb() */ 1970 } 1971 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1972 1973 #ifndef CONFIG_SND_HDA_I915 1974 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1975 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); 1976 #endif 1977 1978 if (schedule_probe) 1979 schedule_work(&hda->probe_work); 1980 1981 dev++; 1982 if (chip->disabled) 1983 complete_all(&hda->probe_wait); 1984 return 0; 1985 1986 out_free: 1987 snd_card_free(card); 1988 return err; 1989 } 1990 1991 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1992 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1993 [AZX_DRIVER_NVIDIA] = 8, 1994 [AZX_DRIVER_TERA] = 1, 1995 }; 1996 1997 static int azx_probe_continue(struct azx *chip) 1998 { 1999 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2000 struct hdac_bus *bus = azx_bus(chip); 2001 struct pci_dev *pci = chip->pci; 2002 int dev = chip->dev_index; 2003 int err; 2004 2005 hda->probe_continued = 1; 2006 2007 /* Request display power well for the HDA controller or codec. For 2008 * Haswell/Broadwell, both the display HDA controller and codec need 2009 * this power. For other platforms, like Baytrail/Braswell, only the 2010 * display codec needs the power and it can be released after probe. 2011 */ 2012 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 2013 /* HSW/BDW controllers need this power */ 2014 if (CONTROLLER_IN_GPU(pci)) 2015 hda->need_i915_power = 1; 2016 2017 err = snd_hdac_i915_init(bus); 2018 if (err < 0) { 2019 /* if the controller is bound only with HDMI/DP 2020 * (for HSW and BDW), we need to abort the probe; 2021 * for other chips, still continue probing as other 2022 * codecs can be on the same link. 2023 */ 2024 if (CONTROLLER_IN_GPU(pci)) 2025 goto out_free; 2026 else 2027 goto skip_i915; 2028 } 2029 2030 err = snd_hdac_display_power(bus, true); 2031 if (err < 0) { 2032 dev_err(chip->card->dev, 2033 "Cannot turn on display power on i915\n"); 2034 goto i915_power_fail; 2035 } 2036 } 2037 2038 skip_i915: 2039 err = azx_first_init(chip); 2040 if (err < 0) 2041 goto out_free; 2042 2043 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2044 chip->beep_mode = beep_mode[dev]; 2045 #endif 2046 2047 /* create codec instances */ 2048 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2049 if (err < 0) 2050 goto out_free; 2051 2052 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2053 if (chip->fw) { 2054 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2055 chip->fw->data); 2056 if (err < 0) 2057 goto out_free; 2058 #ifndef CONFIG_PM 2059 release_firmware(chip->fw); /* no longer needed */ 2060 chip->fw = NULL; 2061 #endif 2062 } 2063 #endif 2064 if ((probe_only[dev] & 1) == 0) { 2065 err = azx_codec_configure(chip); 2066 if (err < 0) 2067 goto out_free; 2068 } 2069 2070 err = snd_card_register(chip->card); 2071 if (err < 0) 2072 goto out_free; 2073 2074 chip->running = 1; 2075 azx_add_card_list(chip); 2076 snd_hda_set_power_save(&chip->bus, power_save * 1000); 2077 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 2078 pm_runtime_put_noidle(&pci->dev); 2079 2080 out_free: 2081 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL 2082 && !hda->need_i915_power) 2083 snd_hdac_display_power(bus, false); 2084 2085 i915_power_fail: 2086 if (err < 0) 2087 hda->init_failed = 1; 2088 complete_all(&hda->probe_wait); 2089 return err; 2090 } 2091 2092 static void azx_remove(struct pci_dev *pci) 2093 { 2094 struct snd_card *card = pci_get_drvdata(pci); 2095 2096 if (card) 2097 snd_card_free(card); 2098 } 2099 2100 static void azx_shutdown(struct pci_dev *pci) 2101 { 2102 struct snd_card *card = pci_get_drvdata(pci); 2103 struct azx *chip; 2104 2105 if (!card) 2106 return; 2107 chip = card->private_data; 2108 if (chip && chip->running) 2109 azx_stop_chip(chip); 2110 } 2111 2112 /* PCI IDs */ 2113 static const struct pci_device_id azx_ids[] = { 2114 /* CPT */ 2115 { PCI_DEVICE(0x8086, 0x1c20), 2116 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2117 /* PBG */ 2118 { PCI_DEVICE(0x8086, 0x1d20), 2119 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2120 /* Panther Point */ 2121 { PCI_DEVICE(0x8086, 0x1e20), 2122 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2123 /* Lynx Point */ 2124 { PCI_DEVICE(0x8086, 0x8c20), 2125 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2126 /* 9 Series */ 2127 { PCI_DEVICE(0x8086, 0x8ca0), 2128 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2129 /* Wellsburg */ 2130 { PCI_DEVICE(0x8086, 0x8d20), 2131 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2132 { PCI_DEVICE(0x8086, 0x8d21), 2133 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2134 /* Lewisburg */ 2135 { PCI_DEVICE(0x8086, 0xa1f0), 2136 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2137 { PCI_DEVICE(0x8086, 0xa270), 2138 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2139 /* Lynx Point-LP */ 2140 { PCI_DEVICE(0x8086, 0x9c20), 2141 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2142 /* Lynx Point-LP */ 2143 { PCI_DEVICE(0x8086, 0x9c21), 2144 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2145 /* Wildcat Point-LP */ 2146 { PCI_DEVICE(0x8086, 0x9ca0), 2147 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2148 /* Sunrise Point */ 2149 { PCI_DEVICE(0x8086, 0xa170), 2150 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2151 /* Sunrise Point-LP */ 2152 { PCI_DEVICE(0x8086, 0x9d70), 2153 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2154 /* Broxton-P(Apollolake) */ 2155 { PCI_DEVICE(0x8086, 0x5a98), 2156 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON }, 2157 /* Haswell */ 2158 { PCI_DEVICE(0x8086, 0x0a0c), 2159 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2160 { PCI_DEVICE(0x8086, 0x0c0c), 2161 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2162 { PCI_DEVICE(0x8086, 0x0d0c), 2163 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2164 /* Broadwell */ 2165 { PCI_DEVICE(0x8086, 0x160c), 2166 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2167 /* 5 Series/3400 */ 2168 { PCI_DEVICE(0x8086, 0x3b56), 2169 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2170 /* Poulsbo */ 2171 { PCI_DEVICE(0x8086, 0x811b), 2172 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2173 /* Oaktrail */ 2174 { PCI_DEVICE(0x8086, 0x080a), 2175 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2176 /* BayTrail */ 2177 { PCI_DEVICE(0x8086, 0x0f04), 2178 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2179 /* Braswell */ 2180 { PCI_DEVICE(0x8086, 0x2284), 2181 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2182 /* ICH6 */ 2183 { PCI_DEVICE(0x8086, 0x2668), 2184 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2185 /* ICH7 */ 2186 { PCI_DEVICE(0x8086, 0x27d8), 2187 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2188 /* ESB2 */ 2189 { PCI_DEVICE(0x8086, 0x269a), 2190 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2191 /* ICH8 */ 2192 { PCI_DEVICE(0x8086, 0x284b), 2193 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2194 /* ICH9 */ 2195 { PCI_DEVICE(0x8086, 0x293e), 2196 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2197 /* ICH9 */ 2198 { PCI_DEVICE(0x8086, 0x293f), 2199 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2200 /* ICH10 */ 2201 { PCI_DEVICE(0x8086, 0x3a3e), 2202 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2203 /* ICH10 */ 2204 { PCI_DEVICE(0x8086, 0x3a6e), 2205 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2206 /* Generic Intel */ 2207 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2208 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2209 .class_mask = 0xffffff, 2210 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2211 /* ATI SB 450/600/700/800/900 */ 2212 { PCI_DEVICE(0x1002, 0x437b), 2213 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2214 { PCI_DEVICE(0x1002, 0x4383), 2215 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2216 /* AMD Hudson */ 2217 { PCI_DEVICE(0x1022, 0x780d), 2218 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2219 /* ATI HDMI */ 2220 { PCI_DEVICE(0x1002, 0x1308), 2221 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2222 { PCI_DEVICE(0x1002, 0x157a), 2223 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2224 { PCI_DEVICE(0x1002, 0x793b), 2225 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2226 { PCI_DEVICE(0x1002, 0x7919), 2227 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2228 { PCI_DEVICE(0x1002, 0x960f), 2229 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2230 { PCI_DEVICE(0x1002, 0x970f), 2231 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2232 { PCI_DEVICE(0x1002, 0x9840), 2233 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2234 { PCI_DEVICE(0x1002, 0xaa00), 2235 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2236 { PCI_DEVICE(0x1002, 0xaa08), 2237 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2238 { PCI_DEVICE(0x1002, 0xaa10), 2239 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2240 { PCI_DEVICE(0x1002, 0xaa18), 2241 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2242 { PCI_DEVICE(0x1002, 0xaa20), 2243 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2244 { PCI_DEVICE(0x1002, 0xaa28), 2245 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2246 { PCI_DEVICE(0x1002, 0xaa30), 2247 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2248 { PCI_DEVICE(0x1002, 0xaa38), 2249 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2250 { PCI_DEVICE(0x1002, 0xaa40), 2251 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2252 { PCI_DEVICE(0x1002, 0xaa48), 2253 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2254 { PCI_DEVICE(0x1002, 0xaa50), 2255 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2256 { PCI_DEVICE(0x1002, 0xaa58), 2257 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2258 { PCI_DEVICE(0x1002, 0xaa60), 2259 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2260 { PCI_DEVICE(0x1002, 0xaa68), 2261 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2262 { PCI_DEVICE(0x1002, 0xaa80), 2263 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2264 { PCI_DEVICE(0x1002, 0xaa88), 2265 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2266 { PCI_DEVICE(0x1002, 0xaa90), 2267 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2268 { PCI_DEVICE(0x1002, 0xaa98), 2269 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2270 { PCI_DEVICE(0x1002, 0x9902), 2271 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2272 { PCI_DEVICE(0x1002, 0xaaa0), 2273 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2274 { PCI_DEVICE(0x1002, 0xaaa8), 2275 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2276 { PCI_DEVICE(0x1002, 0xaab0), 2277 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2278 { PCI_DEVICE(0x1002, 0xaac0), 2279 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2280 { PCI_DEVICE(0x1002, 0xaac8), 2281 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2282 { PCI_DEVICE(0x1002, 0xaad8), 2283 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2284 { PCI_DEVICE(0x1002, 0xaae8), 2285 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2286 /* VIA VT8251/VT8237A */ 2287 { PCI_DEVICE(0x1106, 0x3288), 2288 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 2289 /* VIA GFX VT7122/VX900 */ 2290 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2291 /* VIA GFX VT6122/VX11 */ 2292 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2293 /* SIS966 */ 2294 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2295 /* ULI M5461 */ 2296 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2297 /* NVIDIA MCP */ 2298 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2299 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2300 .class_mask = 0xffffff, 2301 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2302 /* Teradici */ 2303 { PCI_DEVICE(0x6549, 0x1200), 2304 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2305 { PCI_DEVICE(0x6549, 0x2200), 2306 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2307 /* Creative X-Fi (CA0110-IBG) */ 2308 /* CTHDA chips */ 2309 { PCI_DEVICE(0x1102, 0x0010), 2310 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2311 { PCI_DEVICE(0x1102, 0x0012), 2312 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2313 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2314 /* the following entry conflicts with snd-ctxfi driver, 2315 * as ctxfi driver mutates from HD-audio to native mode with 2316 * a special command sequence. 2317 */ 2318 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2319 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2320 .class_mask = 0xffffff, 2321 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2322 AZX_DCAPS_NO_64BIT | 2323 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2324 #else 2325 /* this entry seems still valid -- i.e. without emu20kx chip */ 2326 { PCI_DEVICE(0x1102, 0x0009), 2327 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2328 AZX_DCAPS_NO_64BIT | 2329 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2330 #endif 2331 /* CM8888 */ 2332 { PCI_DEVICE(0x13f6, 0x5011), 2333 .driver_data = AZX_DRIVER_CMEDIA | 2334 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2335 /* Vortex86MX */ 2336 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2337 /* VMware HDAudio */ 2338 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2339 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2340 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2341 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2342 .class_mask = 0xffffff, 2343 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2344 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2345 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2346 .class_mask = 0xffffff, 2347 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2348 { 0, } 2349 }; 2350 MODULE_DEVICE_TABLE(pci, azx_ids); 2351 2352 /* pci_driver definition */ 2353 static struct pci_driver azx_driver = { 2354 .name = KBUILD_MODNAME, 2355 .id_table = azx_ids, 2356 .probe = azx_probe, 2357 .remove = azx_remove, 2358 .shutdown = azx_shutdown, 2359 .driver = { 2360 .pm = AZX_PM_OPS, 2361 }, 2362 }; 2363 2364 module_pci_driver(azx_driver); 2365