1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <linux/vgaarb.h> 61 #include <linux/vga_switcheroo.h> 62 #include <linux/firmware.h> 63 #include "hda_codec.h" 64 #include "hda_controller.h" 65 #include "hda_intel.h" 66 67 /* position fix mode */ 68 enum { 69 POS_FIX_AUTO, 70 POS_FIX_LPIB, 71 POS_FIX_POSBUF, 72 POS_FIX_VIACOMBO, 73 POS_FIX_COMBO, 74 }; 75 76 /* Defines for ATI HD Audio support in SB450 south bridge */ 77 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 78 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 79 80 /* Defines for Nvidia HDA support */ 81 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 82 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 83 #define NVIDIA_HDA_ISTRM_COH 0x4d 84 #define NVIDIA_HDA_OSTRM_COH 0x4c 85 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 86 87 /* Defines for Intel SCH HDA snoop control */ 88 #define INTEL_SCH_HDA_DEVC 0x78 89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 90 91 /* Define IN stream 0 FIFO size offset in VIA controller */ 92 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 93 /* Define VIA HD Audio Device ID*/ 94 #define VIA_HDAC_DEVICE_ID 0x3288 95 96 /* max number of SDs */ 97 /* ICH, ATI and VIA have 4 playback and 4 capture */ 98 #define ICH6_NUM_CAPTURE 4 99 #define ICH6_NUM_PLAYBACK 4 100 101 /* ULI has 6 playback and 5 capture */ 102 #define ULI_NUM_CAPTURE 5 103 #define ULI_NUM_PLAYBACK 6 104 105 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 106 #define ATIHDMI_NUM_CAPTURE 0 107 #define ATIHDMI_NUM_PLAYBACK 8 108 109 /* TERA has 4 playback and 3 capture */ 110 #define TERA_NUM_CAPTURE 3 111 #define TERA_NUM_PLAYBACK 4 112 113 114 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 115 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 116 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 117 static char *model[SNDRV_CARDS]; 118 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 119 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 120 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 121 static int probe_only[SNDRV_CARDS]; 122 static int jackpoll_ms[SNDRV_CARDS]; 123 static bool single_cmd; 124 static int enable_msi = -1; 125 #ifdef CONFIG_SND_HDA_PATCH_LOADER 126 static char *patch[SNDRV_CARDS]; 127 #endif 128 #ifdef CONFIG_SND_HDA_INPUT_BEEP 129 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 130 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 131 #endif 132 133 module_param_array(index, int, NULL, 0444); 134 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 135 module_param_array(id, charp, NULL, 0444); 136 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 137 module_param_array(enable, bool, NULL, 0444); 138 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 139 module_param_array(model, charp, NULL, 0444); 140 MODULE_PARM_DESC(model, "Use the given board model."); 141 module_param_array(position_fix, int, NULL, 0444); 142 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 144 module_param_array(bdl_pos_adj, int, NULL, 0644); 145 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 146 module_param_array(probe_mask, int, NULL, 0444); 147 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 148 module_param_array(probe_only, int, NULL, 0444); 149 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 150 module_param_array(jackpoll_ms, int, NULL, 0444); 151 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 152 module_param(single_cmd, bool, 0444); 153 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 154 "(for debugging only)."); 155 module_param(enable_msi, bint, 0444); 156 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 157 #ifdef CONFIG_SND_HDA_PATCH_LOADER 158 module_param_array(patch, charp, NULL, 0444); 159 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 160 #endif 161 #ifdef CONFIG_SND_HDA_INPUT_BEEP 162 module_param_array(beep_mode, bool, NULL, 0444); 163 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 164 "(0=off, 1=on) (default=1)."); 165 #endif 166 167 #ifdef CONFIG_PM 168 static int param_set_xint(const char *val, const struct kernel_param *kp); 169 static struct kernel_param_ops param_ops_xint = { 170 .set = param_set_xint, 171 .get = param_get_int, 172 }; 173 #define param_check_xint param_check_int 174 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 176 module_param(power_save, xint, 0644); 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 178 "(in second, 0 = disable)."); 179 180 /* reset the HD-audio controller in power save mode. 181 * this may give more power-saving, but will take longer time to 182 * wake up. 183 */ 184 static bool power_save_controller = 1; 185 module_param(power_save_controller, bool, 0644); 186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 187 #else 188 #define power_save 0 189 #endif /* CONFIG_PM */ 190 191 static int align_buffer_size = -1; 192 module_param(align_buffer_size, bint, 0644); 193 MODULE_PARM_DESC(align_buffer_size, 194 "Force buffer and period sizes to be multiple of 128 bytes."); 195 196 #ifdef CONFIG_X86 197 static int hda_snoop = -1; 198 module_param_named(snoop, hda_snoop, bint, 0444); 199 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 200 #else 201 #define hda_snoop true 202 #endif 203 204 205 MODULE_LICENSE("GPL"); 206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 207 "{Intel, ICH6M}," 208 "{Intel, ICH7}," 209 "{Intel, ESB2}," 210 "{Intel, ICH8}," 211 "{Intel, ICH9}," 212 "{Intel, ICH10}," 213 "{Intel, PCH}," 214 "{Intel, CPT}," 215 "{Intel, PPT}," 216 "{Intel, LPT}," 217 "{Intel, LPT_LP}," 218 "{Intel, WPT_LP}," 219 "{Intel, SPT}," 220 "{Intel, SPT_LP}," 221 "{Intel, HPT}," 222 "{Intel, PBG}," 223 "{Intel, SCH}," 224 "{ATI, SB450}," 225 "{ATI, SB600}," 226 "{ATI, RS600}," 227 "{ATI, RS690}," 228 "{ATI, RS780}," 229 "{ATI, R600}," 230 "{ATI, RV630}," 231 "{ATI, RV610}," 232 "{ATI, RV670}," 233 "{ATI, RV635}," 234 "{ATI, RV620}," 235 "{ATI, RV770}," 236 "{VIA, VT8251}," 237 "{VIA, VT8237A}," 238 "{SiS, SIS966}," 239 "{ULI, M5461}}"); 240 MODULE_DESCRIPTION("Intel HDA driver"); 241 242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 244 #define SUPPORT_VGA_SWITCHEROO 245 #endif 246 #endif 247 248 249 /* 250 */ 251 252 /* driver types */ 253 enum { 254 AZX_DRIVER_ICH, 255 AZX_DRIVER_PCH, 256 AZX_DRIVER_SCH, 257 AZX_DRIVER_HDMI, 258 AZX_DRIVER_ATI, 259 AZX_DRIVER_ATIHDMI, 260 AZX_DRIVER_ATIHDMI_NS, 261 AZX_DRIVER_VIA, 262 AZX_DRIVER_SIS, 263 AZX_DRIVER_ULI, 264 AZX_DRIVER_NVIDIA, 265 AZX_DRIVER_TERA, 266 AZX_DRIVER_CTX, 267 AZX_DRIVER_CTHDA, 268 AZX_DRIVER_CMEDIA, 269 AZX_DRIVER_GENERIC, 270 AZX_NUM_DRIVERS, /* keep this as last entry */ 271 }; 272 273 #define azx_get_snoop_type(chip) \ 274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 276 277 /* quirks for old Intel chipsets */ 278 #define AZX_DCAPS_INTEL_ICH \ 279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 280 281 /* quirks for Intel PCH */ 282 #define AZX_DCAPS_INTEL_PCH_NOPM \ 283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH)) 285 286 #define AZX_DCAPS_INTEL_PCH \ 287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 288 289 #define AZX_DCAPS_INTEL_HASWELL \ 290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 292 AZX_DCAPS_SNOOP_TYPE(SCH)) 293 294 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 295 #define AZX_DCAPS_INTEL_BROADWELL \ 296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\ 298 AZX_DCAPS_SNOOP_TYPE(SCH)) 299 300 #define AZX_DCAPS_INTEL_SKYLAKE \ 301 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG) 302 303 /* quirks for ATI SB / AMD Hudson */ 304 #define AZX_DCAPS_PRESET_ATI_SB \ 305 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 306 AZX_DCAPS_SNOOP_TYPE(ATI)) 307 308 /* quirks for ATI/AMD HDMI */ 309 #define AZX_DCAPS_PRESET_ATI_HDMI \ 310 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 311 AZX_DCAPS_NO_MSI64) 312 313 /* quirks for ATI HDMI with snoop off */ 314 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 315 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 316 317 /* quirks for Nvidia */ 318 #define AZX_DCAPS_PRESET_NVIDIA \ 319 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \ 320 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 321 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 322 323 #define AZX_DCAPS_PRESET_CTHDA \ 324 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 325 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 326 327 /* 328 * VGA-switcher support 329 */ 330 #ifdef SUPPORT_VGA_SWITCHEROO 331 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 332 #else 333 #define use_vga_switcheroo(chip) 0 334 #endif 335 336 static char *driver_short_names[] = { 337 [AZX_DRIVER_ICH] = "HDA Intel", 338 [AZX_DRIVER_PCH] = "HDA Intel PCH", 339 [AZX_DRIVER_SCH] = "HDA Intel MID", 340 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 341 [AZX_DRIVER_ATI] = "HDA ATI SB", 342 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 343 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 344 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 345 [AZX_DRIVER_SIS] = "HDA SIS966", 346 [AZX_DRIVER_ULI] = "HDA ULI M5461", 347 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 348 [AZX_DRIVER_TERA] = "HDA Teradici", 349 [AZX_DRIVER_CTX] = "HDA Creative", 350 [AZX_DRIVER_CTHDA] = "HDA Creative", 351 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 352 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 353 }; 354 355 #ifdef CONFIG_X86 356 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 357 { 358 int pages; 359 360 if (azx_snoop(chip)) 361 return; 362 if (!dmab || !dmab->area || !dmab->bytes) 363 return; 364 365 #ifdef CONFIG_SND_DMA_SGBUF 366 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 367 struct snd_sg_buf *sgbuf = dmab->private_data; 368 if (chip->driver_type == AZX_DRIVER_CMEDIA) 369 return; /* deal with only CORB/RIRB buffers */ 370 if (on) 371 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 372 else 373 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 374 return; 375 } 376 #endif 377 378 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 379 if (on) 380 set_memory_wc((unsigned long)dmab->area, pages); 381 else 382 set_memory_wb((unsigned long)dmab->area, pages); 383 } 384 385 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 386 bool on) 387 { 388 __mark_pages_wc(chip, buf, on); 389 } 390 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 391 struct snd_pcm_substream *substream, bool on) 392 { 393 if (azx_dev->wc_marked != on) { 394 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 395 azx_dev->wc_marked = on; 396 } 397 } 398 #else 399 /* NOP for other archs */ 400 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 401 bool on) 402 { 403 } 404 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 405 struct snd_pcm_substream *substream, bool on) 406 { 407 } 408 #endif 409 410 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 411 412 /* 413 * initialize the PCI registers 414 */ 415 /* update bits in a PCI register byte */ 416 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 417 unsigned char mask, unsigned char val) 418 { 419 unsigned char data; 420 421 pci_read_config_byte(pci, reg, &data); 422 data &= ~mask; 423 data |= (val & mask); 424 pci_write_config_byte(pci, reg, data); 425 } 426 427 static void azx_init_pci(struct azx *chip) 428 { 429 int snoop_type = azx_get_snoop_type(chip); 430 431 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 432 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 433 * Ensuring these bits are 0 clears playback static on some HD Audio 434 * codecs. 435 * The PCI register TCSEL is defined in the Intel manuals. 436 */ 437 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 438 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 439 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 440 } 441 442 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 443 * we need to enable snoop. 444 */ 445 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 446 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 447 azx_snoop(chip)); 448 update_pci_byte(chip->pci, 449 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 450 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 451 } 452 453 /* For NVIDIA HDA, enable snoop */ 454 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 455 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 456 azx_snoop(chip)); 457 update_pci_byte(chip->pci, 458 NVIDIA_HDA_TRANSREG_ADDR, 459 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 460 update_pci_byte(chip->pci, 461 NVIDIA_HDA_ISTRM_COH, 462 0x01, NVIDIA_HDA_ENABLE_COHBIT); 463 update_pci_byte(chip->pci, 464 NVIDIA_HDA_OSTRM_COH, 465 0x01, NVIDIA_HDA_ENABLE_COHBIT); 466 } 467 468 /* Enable SCH/PCH snoop if needed */ 469 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 470 unsigned short snoop; 471 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 472 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 473 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 474 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 475 if (!azx_snoop(chip)) 476 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 477 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 478 pci_read_config_word(chip->pci, 479 INTEL_SCH_HDA_DEVC, &snoop); 480 } 481 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 482 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 483 "Disabled" : "Enabled"); 484 } 485 } 486 487 /* calculate runtime delay from LPIB */ 488 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 489 unsigned int pos) 490 { 491 struct snd_pcm_substream *substream = azx_dev->substream; 492 int stream = substream->stream; 493 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 494 int delay; 495 496 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 497 delay = pos - lpib_pos; 498 else 499 delay = lpib_pos - pos; 500 if (delay < 0) { 501 if (delay >= azx_dev->delay_negative_threshold) 502 delay = 0; 503 else 504 delay += azx_dev->bufsize; 505 } 506 507 if (delay >= azx_dev->period_bytes) { 508 dev_info(chip->card->dev, 509 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 510 delay, azx_dev->period_bytes); 511 delay = 0; 512 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 513 chip->get_delay[stream] = NULL; 514 } 515 516 return bytes_to_frames(substream->runtime, delay); 517 } 518 519 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 520 521 /* called from IRQ */ 522 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 523 { 524 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 525 int ok; 526 527 ok = azx_position_ok(chip, azx_dev); 528 if (ok == 1) { 529 azx_dev->irq_pending = 0; 530 return ok; 531 } else if (ok == 0) { 532 /* bogus IRQ, process it later */ 533 azx_dev->irq_pending = 1; 534 schedule_work(&hda->irq_pending_work); 535 } 536 return 0; 537 } 538 539 /* 540 * Check whether the current DMA position is acceptable for updating 541 * periods. Returns non-zero if it's OK. 542 * 543 * Many HD-audio controllers appear pretty inaccurate about 544 * the update-IRQ timing. The IRQ is issued before actually the 545 * data is processed. So, we need to process it afterwords in a 546 * workqueue. 547 */ 548 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 549 { 550 struct snd_pcm_substream *substream = azx_dev->substream; 551 int stream = substream->stream; 552 u32 wallclk; 553 unsigned int pos; 554 555 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 556 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 557 return -1; /* bogus (too early) interrupt */ 558 559 if (chip->get_position[stream]) 560 pos = chip->get_position[stream](chip, azx_dev); 561 else { /* use the position buffer as default */ 562 pos = azx_get_pos_posbuf(chip, azx_dev); 563 if (!pos || pos == (u32)-1) { 564 dev_info(chip->card->dev, 565 "Invalid position buffer, using LPIB read method instead.\n"); 566 chip->get_position[stream] = azx_get_pos_lpib; 567 pos = azx_get_pos_lpib(chip, azx_dev); 568 chip->get_delay[stream] = NULL; 569 } else { 570 chip->get_position[stream] = azx_get_pos_posbuf; 571 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 572 chip->get_delay[stream] = azx_get_delay_from_lpib; 573 } 574 } 575 576 if (pos >= azx_dev->bufsize) 577 pos = 0; 578 579 if (WARN_ONCE(!azx_dev->period_bytes, 580 "hda-intel: zero azx_dev->period_bytes")) 581 return -1; /* this shouldn't happen! */ 582 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 583 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 584 /* NG - it's below the first next period boundary */ 585 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; 586 azx_dev->start_wallclk += wallclk; 587 return 1; /* OK, it's fine */ 588 } 589 590 /* 591 * The work for pending PCM period updates. 592 */ 593 static void azx_irq_pending_work(struct work_struct *work) 594 { 595 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 596 struct azx *chip = &hda->chip; 597 int i, pending, ok; 598 599 if (!hda->irq_pending_warned) { 600 dev_info(chip->card->dev, 601 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 602 chip->card->number); 603 hda->irq_pending_warned = 1; 604 } 605 606 for (;;) { 607 pending = 0; 608 spin_lock_irq(&chip->reg_lock); 609 for (i = 0; i < chip->num_streams; i++) { 610 struct azx_dev *azx_dev = &chip->azx_dev[i]; 611 if (!azx_dev->irq_pending || 612 !azx_dev->substream || 613 !azx_dev->running) 614 continue; 615 ok = azx_position_ok(chip, azx_dev); 616 if (ok > 0) { 617 azx_dev->irq_pending = 0; 618 spin_unlock(&chip->reg_lock); 619 snd_pcm_period_elapsed(azx_dev->substream); 620 spin_lock(&chip->reg_lock); 621 } else if (ok < 0) { 622 pending = 0; /* too early */ 623 } else 624 pending++; 625 } 626 spin_unlock_irq(&chip->reg_lock); 627 if (!pending) 628 return; 629 msleep(1); 630 } 631 } 632 633 /* clear irq_pending flags and assure no on-going workq */ 634 static void azx_clear_irq_pending(struct azx *chip) 635 { 636 int i; 637 638 spin_lock_irq(&chip->reg_lock); 639 for (i = 0; i < chip->num_streams; i++) 640 chip->azx_dev[i].irq_pending = 0; 641 spin_unlock_irq(&chip->reg_lock); 642 } 643 644 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 645 { 646 if (request_irq(chip->pci->irq, azx_interrupt, 647 chip->msi ? 0 : IRQF_SHARED, 648 KBUILD_MODNAME, chip)) { 649 dev_err(chip->card->dev, 650 "unable to grab IRQ %d, disabling device\n", 651 chip->pci->irq); 652 if (do_disconnect) 653 snd_card_disconnect(chip->card); 654 return -1; 655 } 656 chip->irq = chip->pci->irq; 657 pci_intx(chip->pci, !chip->msi); 658 return 0; 659 } 660 661 /* get the current DMA position with correction on VIA chips */ 662 static unsigned int azx_via_get_position(struct azx *chip, 663 struct azx_dev *azx_dev) 664 { 665 unsigned int link_pos, mini_pos, bound_pos; 666 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 667 unsigned int fifo_size; 668 669 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); 670 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 671 /* Playback, no problem using link position */ 672 return link_pos; 673 } 674 675 /* Capture */ 676 /* For new chipset, 677 * use mod to get the DMA position just like old chipset 678 */ 679 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 680 mod_dma_pos %= azx_dev->period_bytes; 681 682 /* azx_dev->fifo_size can't get FIFO size of in stream. 683 * Get from base address + offset. 684 */ 685 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 686 687 if (azx_dev->insufficient) { 688 /* Link position never gather than FIFO size */ 689 if (link_pos <= fifo_size) 690 return 0; 691 692 azx_dev->insufficient = 0; 693 } 694 695 if (link_pos <= fifo_size) 696 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 697 else 698 mini_pos = link_pos - fifo_size; 699 700 /* Find nearest previous boudary */ 701 mod_mini_pos = mini_pos % azx_dev->period_bytes; 702 mod_link_pos = link_pos % azx_dev->period_bytes; 703 if (mod_link_pos >= fifo_size) 704 bound_pos = link_pos - mod_link_pos; 705 else if (mod_dma_pos >= mod_mini_pos) 706 bound_pos = mini_pos - mod_mini_pos; 707 else { 708 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 709 if (bound_pos >= azx_dev->bufsize) 710 bound_pos = 0; 711 } 712 713 /* Calculate real DMA position we want */ 714 return bound_pos + mod_dma_pos; 715 } 716 717 #ifdef CONFIG_PM 718 static DEFINE_MUTEX(card_list_lock); 719 static LIST_HEAD(card_list); 720 721 static void azx_add_card_list(struct azx *chip) 722 { 723 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 724 mutex_lock(&card_list_lock); 725 list_add(&hda->list, &card_list); 726 mutex_unlock(&card_list_lock); 727 } 728 729 static void azx_del_card_list(struct azx *chip) 730 { 731 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 732 mutex_lock(&card_list_lock); 733 list_del_init(&hda->list); 734 mutex_unlock(&card_list_lock); 735 } 736 737 /* trigger power-save check at writing parameter */ 738 static int param_set_xint(const char *val, const struct kernel_param *kp) 739 { 740 struct hda_intel *hda; 741 struct azx *chip; 742 int prev = power_save; 743 int ret = param_set_int(val, kp); 744 745 if (ret || prev == power_save) 746 return ret; 747 748 mutex_lock(&card_list_lock); 749 list_for_each_entry(hda, &card_list, list) { 750 chip = &hda->chip; 751 if (!chip->bus || chip->disabled) 752 continue; 753 snd_hda_set_power_save(chip->bus, power_save * 1000); 754 } 755 mutex_unlock(&card_list_lock); 756 return 0; 757 } 758 #else 759 #define azx_add_card_list(chip) /* NOP */ 760 #define azx_del_card_list(chip) /* NOP */ 761 #endif /* CONFIG_PM */ 762 763 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 764 /* 765 * power management 766 */ 767 static int azx_suspend(struct device *dev) 768 { 769 struct snd_card *card = dev_get_drvdata(dev); 770 struct azx *chip; 771 struct hda_intel *hda; 772 773 if (!card) 774 return 0; 775 776 chip = card->private_data; 777 hda = container_of(chip, struct hda_intel, chip); 778 if (chip->disabled || hda->init_failed) 779 return 0; 780 781 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 782 azx_clear_irq_pending(chip); 783 azx_stop_chip(chip); 784 azx_enter_link_reset(chip); 785 if (chip->irq >= 0) { 786 free_irq(chip->irq, chip); 787 chip->irq = -1; 788 } 789 790 if (chip->msi) 791 pci_disable_msi(chip->pci); 792 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 793 hda_display_power(hda, false); 794 return 0; 795 } 796 797 static int azx_resume(struct device *dev) 798 { 799 struct pci_dev *pci = to_pci_dev(dev); 800 struct snd_card *card = dev_get_drvdata(dev); 801 struct azx *chip; 802 struct hda_intel *hda; 803 804 if (!card) 805 return 0; 806 807 chip = card->private_data; 808 hda = container_of(chip, struct hda_intel, chip); 809 if (chip->disabled || hda->init_failed) 810 return 0; 811 812 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 813 hda_display_power(hda, true); 814 haswell_set_bclk(hda); 815 } 816 if (chip->msi) 817 if (pci_enable_msi(pci) < 0) 818 chip->msi = 0; 819 if (azx_acquire_irq(chip, 1) < 0) 820 return -EIO; 821 azx_init_pci(chip); 822 823 azx_init_chip(chip, true); 824 825 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 826 return 0; 827 } 828 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 829 830 #ifdef CONFIG_PM 831 static int azx_runtime_suspend(struct device *dev) 832 { 833 struct snd_card *card = dev_get_drvdata(dev); 834 struct azx *chip; 835 struct hda_intel *hda; 836 837 if (!card) 838 return 0; 839 840 chip = card->private_data; 841 hda = container_of(chip, struct hda_intel, chip); 842 if (chip->disabled || hda->init_failed) 843 return 0; 844 845 if (!azx_has_pm_runtime(chip)) 846 return 0; 847 848 /* enable controller wake up event */ 849 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 850 STATESTS_INT_MASK); 851 852 azx_stop_chip(chip); 853 azx_enter_link_reset(chip); 854 azx_clear_irq_pending(chip); 855 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 856 hda_display_power(hda, false); 857 858 return 0; 859 } 860 861 static int azx_runtime_resume(struct device *dev) 862 { 863 struct snd_card *card = dev_get_drvdata(dev); 864 struct azx *chip; 865 struct hda_intel *hda; 866 struct hda_bus *bus; 867 struct hda_codec *codec; 868 int status; 869 870 if (!card) 871 return 0; 872 873 chip = card->private_data; 874 hda = container_of(chip, struct hda_intel, chip); 875 if (chip->disabled || hda->init_failed) 876 return 0; 877 878 if (!azx_has_pm_runtime(chip)) 879 return 0; 880 881 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 882 hda_display_power(hda, true); 883 haswell_set_bclk(hda); 884 } 885 886 /* Read STATESTS before controller reset */ 887 status = azx_readw(chip, STATESTS); 888 889 azx_init_pci(chip); 890 azx_init_chip(chip, true); 891 892 bus = chip->bus; 893 if (status && bus) { 894 list_for_each_codec(codec, bus) 895 if (status & (1 << codec->addr)) 896 schedule_delayed_work(&codec->jackpoll_work, 897 codec->jackpoll_interval); 898 } 899 900 /* disable controller Wake Up event*/ 901 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 902 ~STATESTS_INT_MASK); 903 904 return 0; 905 } 906 907 static int azx_runtime_idle(struct device *dev) 908 { 909 struct snd_card *card = dev_get_drvdata(dev); 910 struct azx *chip; 911 struct hda_intel *hda; 912 913 if (!card) 914 return 0; 915 916 chip = card->private_data; 917 hda = container_of(chip, struct hda_intel, chip); 918 if (chip->disabled || hda->init_failed) 919 return 0; 920 921 if (!power_save_controller || !azx_has_pm_runtime(chip) || 922 chip->bus->core.codec_powered) 923 return -EBUSY; 924 925 return 0; 926 } 927 928 static const struct dev_pm_ops azx_pm = { 929 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 930 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 931 }; 932 933 #define AZX_PM_OPS &azx_pm 934 #else 935 #define AZX_PM_OPS NULL 936 #endif /* CONFIG_PM */ 937 938 939 static int azx_probe_continue(struct azx *chip); 940 941 #ifdef SUPPORT_VGA_SWITCHEROO 942 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 943 944 static void azx_vs_set_state(struct pci_dev *pci, 945 enum vga_switcheroo_state state) 946 { 947 struct snd_card *card = pci_get_drvdata(pci); 948 struct azx *chip = card->private_data; 949 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 950 bool disabled; 951 952 wait_for_completion(&hda->probe_wait); 953 if (hda->init_failed) 954 return; 955 956 disabled = (state == VGA_SWITCHEROO_OFF); 957 if (chip->disabled == disabled) 958 return; 959 960 if (!chip->bus) { 961 chip->disabled = disabled; 962 if (!disabled) { 963 dev_info(chip->card->dev, 964 "Start delayed initialization\n"); 965 if (azx_probe_continue(chip) < 0) { 966 dev_err(chip->card->dev, "initialization error\n"); 967 hda->init_failed = true; 968 } 969 } 970 } else { 971 dev_info(chip->card->dev, "%s via VGA-switcheroo\n", 972 disabled ? "Disabling" : "Enabling"); 973 if (disabled) { 974 pm_runtime_put_sync_suspend(card->dev); 975 azx_suspend(card->dev); 976 /* when we get suspended by vga switcheroo we end up in D3cold, 977 * however we have no ACPI handle, so pci/acpi can't put us there, 978 * put ourselves there */ 979 pci->current_state = PCI_D3cold; 980 chip->disabled = true; 981 if (snd_hda_lock_devices(chip->bus)) 982 dev_warn(chip->card->dev, 983 "Cannot lock devices!\n"); 984 } else { 985 snd_hda_unlock_devices(chip->bus); 986 pm_runtime_get_noresume(card->dev); 987 chip->disabled = false; 988 azx_resume(card->dev); 989 } 990 } 991 } 992 993 static bool azx_vs_can_switch(struct pci_dev *pci) 994 { 995 struct snd_card *card = pci_get_drvdata(pci); 996 struct azx *chip = card->private_data; 997 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 998 999 wait_for_completion(&hda->probe_wait); 1000 if (hda->init_failed) 1001 return false; 1002 if (chip->disabled || !chip->bus) 1003 return true; 1004 if (snd_hda_lock_devices(chip->bus)) 1005 return false; 1006 snd_hda_unlock_devices(chip->bus); 1007 return true; 1008 } 1009 1010 static void init_vga_switcheroo(struct azx *chip) 1011 { 1012 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1013 struct pci_dev *p = get_bound_vga(chip->pci); 1014 if (p) { 1015 dev_info(chip->card->dev, 1016 "Handle VGA-switcheroo audio client\n"); 1017 hda->use_vga_switcheroo = 1; 1018 pci_dev_put(p); 1019 } 1020 } 1021 1022 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1023 .set_gpu_state = azx_vs_set_state, 1024 .can_switch = azx_vs_can_switch, 1025 }; 1026 1027 static int register_vga_switcheroo(struct azx *chip) 1028 { 1029 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1030 int err; 1031 1032 if (!hda->use_vga_switcheroo) 1033 return 0; 1034 /* FIXME: currently only handling DIS controller 1035 * is there any machine with two switchable HDMI audio controllers? 1036 */ 1037 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1038 VGA_SWITCHEROO_DIS, 1039 chip->bus != NULL); 1040 if (err < 0) 1041 return err; 1042 hda->vga_switcheroo_registered = 1; 1043 1044 /* register as an optimus hdmi audio power domain */ 1045 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1046 &hda->hdmi_pm_domain); 1047 return 0; 1048 } 1049 #else 1050 #define init_vga_switcheroo(chip) /* NOP */ 1051 #define register_vga_switcheroo(chip) 0 1052 #define check_hdmi_disabled(pci) false 1053 #endif /* SUPPORT_VGA_SWITCHER */ 1054 1055 /* 1056 * destructor 1057 */ 1058 static int azx_free(struct azx *chip) 1059 { 1060 struct pci_dev *pci = chip->pci; 1061 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1062 int i; 1063 1064 if (azx_has_pm_runtime(chip) && chip->running) 1065 pm_runtime_get_noresume(&pci->dev); 1066 1067 azx_del_card_list(chip); 1068 1069 hda->init_failed = 1; /* to be sure */ 1070 complete_all(&hda->probe_wait); 1071 1072 if (use_vga_switcheroo(hda)) { 1073 if (chip->disabled && chip->bus) 1074 snd_hda_unlock_devices(chip->bus); 1075 if (hda->vga_switcheroo_registered) 1076 vga_switcheroo_unregister_client(chip->pci); 1077 } 1078 1079 if (chip->initialized) { 1080 azx_clear_irq_pending(chip); 1081 for (i = 0; i < chip->num_streams; i++) 1082 azx_stream_stop(chip, &chip->azx_dev[i]); 1083 azx_stop_chip(chip); 1084 } 1085 1086 if (chip->irq >= 0) 1087 free_irq(chip->irq, (void*)chip); 1088 if (chip->msi) 1089 pci_disable_msi(chip->pci); 1090 iounmap(chip->remap_addr); 1091 1092 azx_free_stream_pages(chip); 1093 if (chip->region_requested) 1094 pci_release_regions(chip->pci); 1095 pci_disable_device(chip->pci); 1096 kfree(chip->azx_dev); 1097 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1098 release_firmware(chip->fw); 1099 #endif 1100 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1101 hda_display_power(hda, false); 1102 hda_i915_exit(hda); 1103 } 1104 kfree(hda); 1105 1106 return 0; 1107 } 1108 1109 static int azx_dev_free(struct snd_device *device) 1110 { 1111 return azx_free(device->device_data); 1112 } 1113 1114 #ifdef SUPPORT_VGA_SWITCHEROO 1115 /* 1116 * Check of disabled HDMI controller by vga-switcheroo 1117 */ 1118 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1119 { 1120 struct pci_dev *p; 1121 1122 /* check only discrete GPU */ 1123 switch (pci->vendor) { 1124 case PCI_VENDOR_ID_ATI: 1125 case PCI_VENDOR_ID_AMD: 1126 case PCI_VENDOR_ID_NVIDIA: 1127 if (pci->devfn == 1) { 1128 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1129 pci->bus->number, 0); 1130 if (p) { 1131 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1132 return p; 1133 pci_dev_put(p); 1134 } 1135 } 1136 break; 1137 } 1138 return NULL; 1139 } 1140 1141 static bool check_hdmi_disabled(struct pci_dev *pci) 1142 { 1143 bool vga_inactive = false; 1144 struct pci_dev *p = get_bound_vga(pci); 1145 1146 if (p) { 1147 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1148 vga_inactive = true; 1149 pci_dev_put(p); 1150 } 1151 return vga_inactive; 1152 } 1153 #endif /* SUPPORT_VGA_SWITCHEROO */ 1154 1155 /* 1156 * white/black-listing for position_fix 1157 */ 1158 static struct snd_pci_quirk position_fix_list[] = { 1159 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1160 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1161 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1162 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1163 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1164 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1165 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1166 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1167 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1168 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1169 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1170 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1171 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1172 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1173 {} 1174 }; 1175 1176 static int check_position_fix(struct azx *chip, int fix) 1177 { 1178 const struct snd_pci_quirk *q; 1179 1180 switch (fix) { 1181 case POS_FIX_AUTO: 1182 case POS_FIX_LPIB: 1183 case POS_FIX_POSBUF: 1184 case POS_FIX_VIACOMBO: 1185 case POS_FIX_COMBO: 1186 return fix; 1187 } 1188 1189 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1190 if (q) { 1191 dev_info(chip->card->dev, 1192 "position_fix set to %d for device %04x:%04x\n", 1193 q->value, q->subvendor, q->subdevice); 1194 return q->value; 1195 } 1196 1197 /* Check VIA/ATI HD Audio Controller exist */ 1198 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 1199 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1200 return POS_FIX_VIACOMBO; 1201 } 1202 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1203 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1204 return POS_FIX_LPIB; 1205 } 1206 return POS_FIX_AUTO; 1207 } 1208 1209 static void assign_position_fix(struct azx *chip, int fix) 1210 { 1211 static azx_get_pos_callback_t callbacks[] = { 1212 [POS_FIX_AUTO] = NULL, 1213 [POS_FIX_LPIB] = azx_get_pos_lpib, 1214 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1215 [POS_FIX_VIACOMBO] = azx_via_get_position, 1216 [POS_FIX_COMBO] = azx_get_pos_lpib, 1217 }; 1218 1219 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1220 1221 /* combo mode uses LPIB only for playback */ 1222 if (fix == POS_FIX_COMBO) 1223 chip->get_position[1] = NULL; 1224 1225 if (fix == POS_FIX_POSBUF && 1226 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1227 chip->get_delay[0] = chip->get_delay[1] = 1228 azx_get_delay_from_lpib; 1229 } 1230 1231 } 1232 1233 /* 1234 * black-lists for probe_mask 1235 */ 1236 static struct snd_pci_quirk probe_mask_list[] = { 1237 /* Thinkpad often breaks the controller communication when accessing 1238 * to the non-working (or non-existing) modem codec slot. 1239 */ 1240 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1241 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1242 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1243 /* broken BIOS */ 1244 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1245 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1246 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1247 /* forced codec slots */ 1248 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1249 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1250 /* WinFast VP200 H (Teradici) user reported broken communication */ 1251 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1252 {} 1253 }; 1254 1255 #define AZX_FORCE_CODEC_MASK 0x100 1256 1257 static void check_probe_mask(struct azx *chip, int dev) 1258 { 1259 const struct snd_pci_quirk *q; 1260 1261 chip->codec_probe_mask = probe_mask[dev]; 1262 if (chip->codec_probe_mask == -1) { 1263 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1264 if (q) { 1265 dev_info(chip->card->dev, 1266 "probe_mask set to 0x%x for device %04x:%04x\n", 1267 q->value, q->subvendor, q->subdevice); 1268 chip->codec_probe_mask = q->value; 1269 } 1270 } 1271 1272 /* check forced option */ 1273 if (chip->codec_probe_mask != -1 && 1274 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1275 chip->codec_mask = chip->codec_probe_mask & 0xff; 1276 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1277 chip->codec_mask); 1278 } 1279 } 1280 1281 /* 1282 * white/black-list for enable_msi 1283 */ 1284 static struct snd_pci_quirk msi_black_list[] = { 1285 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1286 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1287 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1288 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1289 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1290 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1291 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1292 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1293 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1294 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1295 {} 1296 }; 1297 1298 static void check_msi(struct azx *chip) 1299 { 1300 const struct snd_pci_quirk *q; 1301 1302 if (enable_msi >= 0) { 1303 chip->msi = !!enable_msi; 1304 return; 1305 } 1306 chip->msi = 1; /* enable MSI as default */ 1307 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1308 if (q) { 1309 dev_info(chip->card->dev, 1310 "msi for device %04x:%04x set to %d\n", 1311 q->subvendor, q->subdevice, q->value); 1312 chip->msi = q->value; 1313 return; 1314 } 1315 1316 /* NVidia chipsets seem to cause troubles with MSI */ 1317 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1318 dev_info(chip->card->dev, "Disabling MSI\n"); 1319 chip->msi = 0; 1320 } 1321 } 1322 1323 /* check the snoop mode availability */ 1324 static void azx_check_snoop_available(struct azx *chip) 1325 { 1326 int snoop = hda_snoop; 1327 1328 if (snoop >= 0) { 1329 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1330 snoop ? "snoop" : "non-snoop"); 1331 chip->snoop = snoop; 1332 return; 1333 } 1334 1335 snoop = true; 1336 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1337 chip->driver_type == AZX_DRIVER_VIA) { 1338 /* force to non-snoop mode for a new VIA controller 1339 * when BIOS is set 1340 */ 1341 u8 val; 1342 pci_read_config_byte(chip->pci, 0x42, &val); 1343 if (!(val & 0x80) && chip->pci->revision == 0x30) 1344 snoop = false; 1345 } 1346 1347 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1348 snoop = false; 1349 1350 chip->snoop = snoop; 1351 if (!snoop) 1352 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1353 } 1354 1355 static void azx_probe_work(struct work_struct *work) 1356 { 1357 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1358 azx_probe_continue(&hda->chip); 1359 } 1360 1361 /* 1362 * constructor 1363 */ 1364 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1365 int dev, unsigned int driver_caps, 1366 const struct hda_controller_ops *hda_ops, 1367 struct azx **rchip) 1368 { 1369 static struct snd_device_ops ops = { 1370 .dev_free = azx_dev_free, 1371 }; 1372 struct hda_intel *hda; 1373 struct azx *chip; 1374 int err; 1375 1376 *rchip = NULL; 1377 1378 err = pci_enable_device(pci); 1379 if (err < 0) 1380 return err; 1381 1382 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1383 if (!hda) { 1384 pci_disable_device(pci); 1385 return -ENOMEM; 1386 } 1387 1388 chip = &hda->chip; 1389 spin_lock_init(&chip->reg_lock); 1390 mutex_init(&chip->open_mutex); 1391 chip->card = card; 1392 chip->pci = pci; 1393 chip->ops = hda_ops; 1394 chip->irq = -1; 1395 chip->driver_caps = driver_caps; 1396 chip->driver_type = driver_caps & 0xff; 1397 check_msi(chip); 1398 chip->dev_index = dev; 1399 chip->jackpoll_ms = jackpoll_ms; 1400 INIT_LIST_HEAD(&chip->pcm_list); 1401 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1402 INIT_LIST_HEAD(&hda->list); 1403 init_vga_switcheroo(chip); 1404 init_completion(&hda->probe_wait); 1405 1406 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1407 1408 check_probe_mask(chip, dev); 1409 1410 chip->single_cmd = single_cmd; 1411 azx_check_snoop_available(chip); 1412 1413 if (bdl_pos_adj[dev] < 0) { 1414 switch (chip->driver_type) { 1415 case AZX_DRIVER_ICH: 1416 case AZX_DRIVER_PCH: 1417 bdl_pos_adj[dev] = 1; 1418 break; 1419 default: 1420 bdl_pos_adj[dev] = 32; 1421 break; 1422 } 1423 } 1424 chip->bdl_pos_adj = bdl_pos_adj; 1425 1426 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1427 if (err < 0) { 1428 dev_err(card->dev, "Error creating device [card]!\n"); 1429 azx_free(chip); 1430 return err; 1431 } 1432 1433 /* continue probing in work context as may trigger request module */ 1434 INIT_WORK(&hda->probe_work, azx_probe_work); 1435 1436 *rchip = chip; 1437 1438 return 0; 1439 } 1440 1441 static int azx_first_init(struct azx *chip) 1442 { 1443 int dev = chip->dev_index; 1444 struct pci_dev *pci = chip->pci; 1445 struct snd_card *card = chip->card; 1446 int err; 1447 unsigned short gcap; 1448 unsigned int dma_bits = 64; 1449 1450 #if BITS_PER_LONG != 64 1451 /* Fix up base address on ULI M5461 */ 1452 if (chip->driver_type == AZX_DRIVER_ULI) { 1453 u16 tmp3; 1454 pci_read_config_word(pci, 0x40, &tmp3); 1455 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1456 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1457 } 1458 #endif 1459 1460 err = pci_request_regions(pci, "ICH HD audio"); 1461 if (err < 0) 1462 return err; 1463 chip->region_requested = 1; 1464 1465 chip->addr = pci_resource_start(pci, 0); 1466 chip->remap_addr = pci_ioremap_bar(pci, 0); 1467 if (chip->remap_addr == NULL) { 1468 dev_err(card->dev, "ioremap error\n"); 1469 return -ENXIO; 1470 } 1471 1472 if (chip->msi) { 1473 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1474 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1475 pci->no_64bit_msi = true; 1476 } 1477 if (pci_enable_msi(pci) < 0) 1478 chip->msi = 0; 1479 } 1480 1481 if (azx_acquire_irq(chip, 0) < 0) 1482 return -EBUSY; 1483 1484 pci_set_master(pci); 1485 synchronize_irq(chip->irq); 1486 1487 gcap = azx_readw(chip, GCAP); 1488 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1489 1490 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1491 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1492 dma_bits = 40; 1493 1494 /* disable SB600 64bit support for safety */ 1495 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1496 struct pci_dev *p_smbus; 1497 dma_bits = 40; 1498 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1499 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1500 NULL); 1501 if (p_smbus) { 1502 if (p_smbus->revision < 0x30) 1503 gcap &= ~AZX_GCAP_64OK; 1504 pci_dev_put(p_smbus); 1505 } 1506 } 1507 1508 /* disable 64bit DMA address on some devices */ 1509 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1510 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1511 gcap &= ~AZX_GCAP_64OK; 1512 } 1513 1514 /* disable buffer size rounding to 128-byte multiples if supported */ 1515 if (align_buffer_size >= 0) 1516 chip->align_buffer_size = !!align_buffer_size; 1517 else { 1518 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1519 chip->align_buffer_size = 0; 1520 else 1521 chip->align_buffer_size = 1; 1522 } 1523 1524 /* allow 64bit DMA address if supported by H/W */ 1525 if (!(gcap & AZX_GCAP_64OK)) 1526 dma_bits = 32; 1527 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) { 1528 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits)); 1529 } else { 1530 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 1531 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 1532 } 1533 1534 /* read number of streams from GCAP register instead of using 1535 * hardcoded value 1536 */ 1537 chip->capture_streams = (gcap >> 8) & 0x0f; 1538 chip->playback_streams = (gcap >> 12) & 0x0f; 1539 if (!chip->playback_streams && !chip->capture_streams) { 1540 /* gcap didn't give any info, switching to old method */ 1541 1542 switch (chip->driver_type) { 1543 case AZX_DRIVER_ULI: 1544 chip->playback_streams = ULI_NUM_PLAYBACK; 1545 chip->capture_streams = ULI_NUM_CAPTURE; 1546 break; 1547 case AZX_DRIVER_ATIHDMI: 1548 case AZX_DRIVER_ATIHDMI_NS: 1549 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1550 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1551 break; 1552 case AZX_DRIVER_GENERIC: 1553 default: 1554 chip->playback_streams = ICH6_NUM_PLAYBACK; 1555 chip->capture_streams = ICH6_NUM_CAPTURE; 1556 break; 1557 } 1558 } 1559 chip->capture_index_offset = 0; 1560 chip->playback_index_offset = chip->capture_streams; 1561 chip->num_streams = chip->playback_streams + chip->capture_streams; 1562 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 1563 GFP_KERNEL); 1564 if (!chip->azx_dev) 1565 return -ENOMEM; 1566 1567 err = azx_alloc_stream_pages(chip); 1568 if (err < 0) 1569 return err; 1570 1571 /* initialize streams */ 1572 azx_init_stream(chip); 1573 1574 /* initialize chip */ 1575 azx_init_pci(chip); 1576 1577 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1578 struct hda_intel *hda; 1579 1580 hda = container_of(chip, struct hda_intel, chip); 1581 haswell_set_bclk(hda); 1582 } 1583 1584 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 1585 1586 /* codec detection */ 1587 if (!chip->codec_mask) { 1588 dev_err(card->dev, "no codecs found!\n"); 1589 return -ENODEV; 1590 } 1591 1592 strcpy(card->driver, "HDA-Intel"); 1593 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1594 sizeof(card->shortname)); 1595 snprintf(card->longname, sizeof(card->longname), 1596 "%s at 0x%lx irq %i", 1597 card->shortname, chip->addr, chip->irq); 1598 1599 return 0; 1600 } 1601 1602 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1603 /* callback from request_firmware_nowait() */ 1604 static void azx_firmware_cb(const struct firmware *fw, void *context) 1605 { 1606 struct snd_card *card = context; 1607 struct azx *chip = card->private_data; 1608 struct pci_dev *pci = chip->pci; 1609 1610 if (!fw) { 1611 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1612 goto error; 1613 } 1614 1615 chip->fw = fw; 1616 if (!chip->disabled) { 1617 /* continue probing */ 1618 if (azx_probe_continue(chip)) 1619 goto error; 1620 } 1621 return; /* OK */ 1622 1623 error: 1624 snd_card_free(card); 1625 pci_set_drvdata(pci, NULL); 1626 } 1627 #endif 1628 1629 /* 1630 * HDA controller ops. 1631 */ 1632 1633 /* PCI register access. */ 1634 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1635 { 1636 writel(value, addr); 1637 } 1638 1639 static u32 pci_azx_readl(u32 __iomem *addr) 1640 { 1641 return readl(addr); 1642 } 1643 1644 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1645 { 1646 writew(value, addr); 1647 } 1648 1649 static u16 pci_azx_readw(u16 __iomem *addr) 1650 { 1651 return readw(addr); 1652 } 1653 1654 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1655 { 1656 writeb(value, addr); 1657 } 1658 1659 static u8 pci_azx_readb(u8 __iomem *addr) 1660 { 1661 return readb(addr); 1662 } 1663 1664 static int disable_msi_reset_irq(struct azx *chip) 1665 { 1666 int err; 1667 1668 free_irq(chip->irq, chip); 1669 chip->irq = -1; 1670 pci_disable_msi(chip->pci); 1671 chip->msi = 0; 1672 err = azx_acquire_irq(chip, 1); 1673 if (err < 0) 1674 return err; 1675 1676 return 0; 1677 } 1678 1679 /* DMA page allocation helpers. */ 1680 static int dma_alloc_pages(struct azx *chip, 1681 int type, 1682 size_t size, 1683 struct snd_dma_buffer *buf) 1684 { 1685 int err; 1686 1687 err = snd_dma_alloc_pages(type, 1688 chip->card->dev, 1689 size, buf); 1690 if (err < 0) 1691 return err; 1692 mark_pages_wc(chip, buf, true); 1693 return 0; 1694 } 1695 1696 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) 1697 { 1698 mark_pages_wc(chip, buf, false); 1699 snd_dma_free_pages(buf); 1700 } 1701 1702 static int substream_alloc_pages(struct azx *chip, 1703 struct snd_pcm_substream *substream, 1704 size_t size) 1705 { 1706 struct azx_dev *azx_dev = get_azx_dev(substream); 1707 int ret; 1708 1709 mark_runtime_wc(chip, azx_dev, substream, false); 1710 azx_dev->bufsize = 0; 1711 azx_dev->period_bytes = 0; 1712 azx_dev->format_val = 0; 1713 ret = snd_pcm_lib_malloc_pages(substream, size); 1714 if (ret < 0) 1715 return ret; 1716 mark_runtime_wc(chip, azx_dev, substream, true); 1717 return 0; 1718 } 1719 1720 static int substream_free_pages(struct azx *chip, 1721 struct snd_pcm_substream *substream) 1722 { 1723 struct azx_dev *azx_dev = get_azx_dev(substream); 1724 mark_runtime_wc(chip, azx_dev, substream, false); 1725 return snd_pcm_lib_free_pages(substream); 1726 } 1727 1728 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1729 struct vm_area_struct *area) 1730 { 1731 #ifdef CONFIG_X86 1732 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1733 struct azx *chip = apcm->chip; 1734 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA) 1735 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1736 #endif 1737 } 1738 1739 static const struct hda_controller_ops pci_hda_ops = { 1740 .reg_writel = pci_azx_writel, 1741 .reg_readl = pci_azx_readl, 1742 .reg_writew = pci_azx_writew, 1743 .reg_readw = pci_azx_readw, 1744 .reg_writeb = pci_azx_writeb, 1745 .reg_readb = pci_azx_readb, 1746 .disable_msi_reset_irq = disable_msi_reset_irq, 1747 .dma_alloc_pages = dma_alloc_pages, 1748 .dma_free_pages = dma_free_pages, 1749 .substream_alloc_pages = substream_alloc_pages, 1750 .substream_free_pages = substream_free_pages, 1751 .pcm_mmap_prepare = pcm_mmap_prepare, 1752 .position_check = azx_position_check, 1753 }; 1754 1755 static int azx_probe(struct pci_dev *pci, 1756 const struct pci_device_id *pci_id) 1757 { 1758 static int dev; 1759 struct snd_card *card; 1760 struct hda_intel *hda; 1761 struct azx *chip; 1762 bool schedule_probe; 1763 int err; 1764 1765 if (dev >= SNDRV_CARDS) 1766 return -ENODEV; 1767 if (!enable[dev]) { 1768 dev++; 1769 return -ENOENT; 1770 } 1771 1772 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1773 0, &card); 1774 if (err < 0) { 1775 dev_err(&pci->dev, "Error creating card!\n"); 1776 return err; 1777 } 1778 1779 err = azx_create(card, pci, dev, pci_id->driver_data, 1780 &pci_hda_ops, &chip); 1781 if (err < 0) 1782 goto out_free; 1783 card->private_data = chip; 1784 hda = container_of(chip, struct hda_intel, chip); 1785 1786 pci_set_drvdata(pci, card); 1787 1788 err = register_vga_switcheroo(chip); 1789 if (err < 0) { 1790 dev_err(card->dev, "Error registering VGA-switcheroo client\n"); 1791 goto out_free; 1792 } 1793 1794 if (check_hdmi_disabled(pci)) { 1795 dev_info(card->dev, "VGA controller is disabled\n"); 1796 dev_info(card->dev, "Delaying initialization\n"); 1797 chip->disabled = true; 1798 } 1799 1800 schedule_probe = !chip->disabled; 1801 1802 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1803 if (patch[dev] && *patch[dev]) { 1804 dev_info(card->dev, "Applying patch firmware '%s'\n", 1805 patch[dev]); 1806 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1807 &pci->dev, GFP_KERNEL, card, 1808 azx_firmware_cb); 1809 if (err < 0) 1810 goto out_free; 1811 schedule_probe = false; /* continued in azx_firmware_cb() */ 1812 } 1813 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1814 1815 #ifndef CONFIG_SND_HDA_I915 1816 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1817 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); 1818 #endif 1819 1820 if (schedule_probe) 1821 schedule_work(&hda->probe_work); 1822 1823 dev++; 1824 if (chip->disabled) 1825 complete_all(&hda->probe_wait); 1826 return 0; 1827 1828 out_free: 1829 snd_card_free(card); 1830 return err; 1831 } 1832 1833 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1834 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1835 [AZX_DRIVER_NVIDIA] = 8, 1836 [AZX_DRIVER_TERA] = 1, 1837 }; 1838 1839 static int azx_probe_continue(struct azx *chip) 1840 { 1841 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1842 struct pci_dev *pci = chip->pci; 1843 int dev = chip->dev_index; 1844 int err; 1845 1846 /* Request power well for Haswell HDA controller and codec */ 1847 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1848 #ifdef CONFIG_SND_HDA_I915 1849 err = hda_i915_init(hda); 1850 if (err < 0) 1851 goto out_free; 1852 err = hda_display_power(hda, true); 1853 if (err < 0) { 1854 dev_err(chip->card->dev, 1855 "Cannot turn on display power on i915\n"); 1856 goto out_free; 1857 } 1858 #endif 1859 } 1860 1861 err = azx_first_init(chip); 1862 if (err < 0) 1863 goto out_free; 1864 1865 #ifdef CONFIG_SND_HDA_INPUT_BEEP 1866 chip->beep_mode = beep_mode[dev]; 1867 #endif 1868 1869 /* create codec instances */ 1870 err = azx_bus_create(chip, model[dev]); 1871 if (err < 0) 1872 goto out_free; 1873 1874 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 1875 if (err < 0) 1876 goto out_free; 1877 1878 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1879 if (chip->fw) { 1880 err = snd_hda_load_patch(chip->bus, chip->fw->size, 1881 chip->fw->data); 1882 if (err < 0) 1883 goto out_free; 1884 #ifndef CONFIG_PM 1885 release_firmware(chip->fw); /* no longer needed */ 1886 chip->fw = NULL; 1887 #endif 1888 } 1889 #endif 1890 if ((probe_only[dev] & 1) == 0) { 1891 err = azx_codec_configure(chip); 1892 if (err < 0) 1893 goto out_free; 1894 } 1895 1896 err = snd_card_register(chip->card); 1897 if (err < 0) 1898 goto out_free; 1899 1900 chip->running = 1; 1901 azx_add_card_list(chip); 1902 snd_hda_set_power_save(chip->bus, power_save * 1000); 1903 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo) 1904 pm_runtime_put_noidle(&pci->dev); 1905 1906 out_free: 1907 if (err < 0) 1908 hda->init_failed = 1; 1909 complete_all(&hda->probe_wait); 1910 return err; 1911 } 1912 1913 static void azx_remove(struct pci_dev *pci) 1914 { 1915 struct snd_card *card = pci_get_drvdata(pci); 1916 1917 if (card) 1918 snd_card_free(card); 1919 } 1920 1921 static void azx_shutdown(struct pci_dev *pci) 1922 { 1923 struct snd_card *card = pci_get_drvdata(pci); 1924 struct azx *chip; 1925 1926 if (!card) 1927 return; 1928 chip = card->private_data; 1929 if (chip && chip->running) 1930 azx_stop_chip(chip); 1931 } 1932 1933 /* PCI IDs */ 1934 static const struct pci_device_id azx_ids[] = { 1935 /* CPT */ 1936 { PCI_DEVICE(0x8086, 0x1c20), 1937 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1938 /* PBG */ 1939 { PCI_DEVICE(0x8086, 0x1d20), 1940 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1941 /* Panther Point */ 1942 { PCI_DEVICE(0x8086, 0x1e20), 1943 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1944 /* Lynx Point */ 1945 { PCI_DEVICE(0x8086, 0x8c20), 1946 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1947 /* 9 Series */ 1948 { PCI_DEVICE(0x8086, 0x8ca0), 1949 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1950 /* Wellsburg */ 1951 { PCI_DEVICE(0x8086, 0x8d20), 1952 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1953 { PCI_DEVICE(0x8086, 0x8d21), 1954 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1955 /* Lynx Point-LP */ 1956 { PCI_DEVICE(0x8086, 0x9c20), 1957 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1958 /* Lynx Point-LP */ 1959 { PCI_DEVICE(0x8086, 0x9c21), 1960 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1961 /* Wildcat Point-LP */ 1962 { PCI_DEVICE(0x8086, 0x9ca0), 1963 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1964 /* Sunrise Point */ 1965 { PCI_DEVICE(0x8086, 0xa170), 1966 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1967 /* Sunrise Point-LP */ 1968 { PCI_DEVICE(0x8086, 0x9d70), 1969 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 1970 /* Haswell */ 1971 { PCI_DEVICE(0x8086, 0x0a0c), 1972 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 1973 { PCI_DEVICE(0x8086, 0x0c0c), 1974 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 1975 { PCI_DEVICE(0x8086, 0x0d0c), 1976 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 1977 /* Broadwell */ 1978 { PCI_DEVICE(0x8086, 0x160c), 1979 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 1980 /* 5 Series/3400 */ 1981 { PCI_DEVICE(0x8086, 0x3b56), 1982 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1983 /* Poulsbo */ 1984 { PCI_DEVICE(0x8086, 0x811b), 1985 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1986 /* Oaktrail */ 1987 { PCI_DEVICE(0x8086, 0x080a), 1988 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1989 /* BayTrail */ 1990 { PCI_DEVICE(0x8086, 0x0f04), 1991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1992 /* Braswell */ 1993 { PCI_DEVICE(0x8086, 0x2284), 1994 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1995 /* ICH6 */ 1996 { PCI_DEVICE(0x8086, 0x2668), 1997 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 1998 /* ICH7 */ 1999 { PCI_DEVICE(0x8086, 0x27d8), 2000 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2001 /* ESB2 */ 2002 { PCI_DEVICE(0x8086, 0x269a), 2003 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2004 /* ICH8 */ 2005 { PCI_DEVICE(0x8086, 0x284b), 2006 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2007 /* ICH9 */ 2008 { PCI_DEVICE(0x8086, 0x293e), 2009 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2010 /* ICH9 */ 2011 { PCI_DEVICE(0x8086, 0x293f), 2012 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2013 /* ICH10 */ 2014 { PCI_DEVICE(0x8086, 0x3a3e), 2015 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2016 /* ICH10 */ 2017 { PCI_DEVICE(0x8086, 0x3a6e), 2018 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2019 /* Generic Intel */ 2020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2021 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2022 .class_mask = 0xffffff, 2023 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2024 /* ATI SB 450/600/700/800/900 */ 2025 { PCI_DEVICE(0x1002, 0x437b), 2026 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2027 { PCI_DEVICE(0x1002, 0x4383), 2028 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2029 /* AMD Hudson */ 2030 { PCI_DEVICE(0x1022, 0x780d), 2031 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2032 /* ATI HDMI */ 2033 { PCI_DEVICE(0x1002, 0x793b), 2034 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2035 { PCI_DEVICE(0x1002, 0x7919), 2036 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2037 { PCI_DEVICE(0x1002, 0x960f), 2038 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2039 { PCI_DEVICE(0x1002, 0x970f), 2040 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2041 { PCI_DEVICE(0x1002, 0xaa00), 2042 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2043 { PCI_DEVICE(0x1002, 0xaa08), 2044 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2045 { PCI_DEVICE(0x1002, 0xaa10), 2046 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2047 { PCI_DEVICE(0x1002, 0xaa18), 2048 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2049 { PCI_DEVICE(0x1002, 0xaa20), 2050 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2051 { PCI_DEVICE(0x1002, 0xaa28), 2052 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2053 { PCI_DEVICE(0x1002, 0xaa30), 2054 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2055 { PCI_DEVICE(0x1002, 0xaa38), 2056 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2057 { PCI_DEVICE(0x1002, 0xaa40), 2058 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2059 { PCI_DEVICE(0x1002, 0xaa48), 2060 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2061 { PCI_DEVICE(0x1002, 0xaa50), 2062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2063 { PCI_DEVICE(0x1002, 0xaa58), 2064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2065 { PCI_DEVICE(0x1002, 0xaa60), 2066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2067 { PCI_DEVICE(0x1002, 0xaa68), 2068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2069 { PCI_DEVICE(0x1002, 0xaa80), 2070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2071 { PCI_DEVICE(0x1002, 0xaa88), 2072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2073 { PCI_DEVICE(0x1002, 0xaa90), 2074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2075 { PCI_DEVICE(0x1002, 0xaa98), 2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2077 { PCI_DEVICE(0x1002, 0x9902), 2078 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2079 { PCI_DEVICE(0x1002, 0xaaa0), 2080 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2081 { PCI_DEVICE(0x1002, 0xaaa8), 2082 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2083 { PCI_DEVICE(0x1002, 0xaab0), 2084 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2085 /* VIA VT8251/VT8237A */ 2086 { PCI_DEVICE(0x1106, 0x3288), 2087 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 2088 /* VIA GFX VT7122/VX900 */ 2089 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2090 /* VIA GFX VT6122/VX11 */ 2091 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2092 /* SIS966 */ 2093 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2094 /* ULI M5461 */ 2095 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2096 /* NVIDIA MCP */ 2097 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2098 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2099 .class_mask = 0xffffff, 2100 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2101 /* Teradici */ 2102 { PCI_DEVICE(0x6549, 0x1200), 2103 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2104 { PCI_DEVICE(0x6549, 0x2200), 2105 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2106 /* Creative X-Fi (CA0110-IBG) */ 2107 /* CTHDA chips */ 2108 { PCI_DEVICE(0x1102, 0x0010), 2109 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2110 { PCI_DEVICE(0x1102, 0x0012), 2111 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2112 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2113 /* the following entry conflicts with snd-ctxfi driver, 2114 * as ctxfi driver mutates from HD-audio to native mode with 2115 * a special command sequence. 2116 */ 2117 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2118 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2119 .class_mask = 0xffffff, 2120 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2121 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2122 #else 2123 /* this entry seems still valid -- i.e. without emu20kx chip */ 2124 { PCI_DEVICE(0x1102, 0x0009), 2125 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2126 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2127 #endif 2128 /* CM8888 */ 2129 { PCI_DEVICE(0x13f6, 0x5011), 2130 .driver_data = AZX_DRIVER_CMEDIA | 2131 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2132 /* Vortex86MX */ 2133 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2134 /* VMware HDAudio */ 2135 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2136 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2137 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2138 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2139 .class_mask = 0xffffff, 2140 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2141 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2142 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2143 .class_mask = 0xffffff, 2144 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2145 { 0, } 2146 }; 2147 MODULE_DEVICE_TABLE(pci, azx_ids); 2148 2149 /* pci_driver definition */ 2150 static struct pci_driver azx_driver = { 2151 .name = KBUILD_MODNAME, 2152 .id_table = azx_ids, 2153 .probe = azx_probe, 2154 .remove = azx_remove, 2155 .shutdown = azx_shutdown, 2156 .driver = { 2157 .pm = AZX_PM_OPS, 2158 }, 2159 }; 2160 2161 module_pci_driver(azx_driver); 2162