1 /* 2 * Common functionality for the alsa driver code base for HD Audio. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef __SOUND_HDA_CONTROLLER_H 16 #define __SOUND_HDA_CONTROLLER_H 17 18 #include <linux/timecounter.h> 19 #include <linux/interrupt.h> 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/initval.h> 23 #include "hda_codec.h" 24 25 /* 26 * registers 27 */ 28 #define AZX_REG_GCAP 0x00 29 #define AZX_GCAP_64OK (1 << 0) /* 64bit address support */ 30 #define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 31 #define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 32 #define AZX_GCAP_ISS (15 << 8) /* # of input streams */ 33 #define AZX_GCAP_OSS (15 << 12) /* # of output streams */ 34 #define AZX_REG_VMIN 0x02 35 #define AZX_REG_VMAJ 0x03 36 #define AZX_REG_OUTPAY 0x04 37 #define AZX_REG_INPAY 0x06 38 #define AZX_REG_GCTL 0x08 39 #define AZX_GCTL_RESET (1 << 0) /* controller reset */ 40 #define AZX_GCTL_FCNTRL (1 << 1) /* flush control */ 41 #define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 42 #define AZX_REG_WAKEEN 0x0c 43 #define AZX_REG_STATESTS 0x0e 44 #define AZX_REG_GSTS 0x10 45 #define AZX_GSTS_FSTS (1 << 1) /* flush status */ 46 #define AZX_REG_INTCTL 0x20 47 #define AZX_REG_INTSTS 0x24 48 #define AZX_REG_WALLCLK 0x30 /* 24Mhz source */ 49 #define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ 50 #define AZX_REG_SSYNC 0x38 51 #define AZX_REG_CORBLBASE 0x40 52 #define AZX_REG_CORBUBASE 0x44 53 #define AZX_REG_CORBWP 0x48 54 #define AZX_REG_CORBRP 0x4a 55 #define AZX_CORBRP_RST (1 << 15) /* read pointer reset */ 56 #define AZX_REG_CORBCTL 0x4c 57 #define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */ 58 #define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 59 #define AZX_REG_CORBSTS 0x4d 60 #define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */ 61 #define AZX_REG_CORBSIZE 0x4e 62 63 #define AZX_REG_RIRBLBASE 0x50 64 #define AZX_REG_RIRBUBASE 0x54 65 #define AZX_REG_RIRBWP 0x58 66 #define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */ 67 #define AZX_REG_RINTCNT 0x5a 68 #define AZX_REG_RIRBCTL 0x5c 69 #define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 70 #define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 71 #define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 72 #define AZX_REG_RIRBSTS 0x5d 73 #define AZX_RBSTS_IRQ (1 << 0) /* response irq */ 74 #define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 75 #define AZX_REG_RIRBSIZE 0x5e 76 77 #define AZX_REG_IC 0x60 78 #define AZX_REG_IR 0x64 79 #define AZX_REG_IRS 0x68 80 #define AZX_IRS_VALID (1<<1) 81 #define AZX_IRS_BUSY (1<<0) 82 83 #define AZX_REG_DPLBASE 0x70 84 #define AZX_REG_DPUBASE 0x74 85 #define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 86 87 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 88 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 89 90 /* stream register offsets from stream base */ 91 #define AZX_REG_SD_CTL 0x00 92 #define AZX_REG_SD_STS 0x03 93 #define AZX_REG_SD_LPIB 0x04 94 #define AZX_REG_SD_CBL 0x08 95 #define AZX_REG_SD_LVI 0x0c 96 #define AZX_REG_SD_FIFOW 0x0e 97 #define AZX_REG_SD_FIFOSIZE 0x10 98 #define AZX_REG_SD_FORMAT 0x12 99 #define AZX_REG_SD_BDLPL 0x18 100 #define AZX_REG_SD_BDLPU 0x1c 101 102 /* PCI space */ 103 #define AZX_PCIREG_TCSEL 0x44 104 105 /* 106 * other constants 107 */ 108 109 /* max number of fragments - we may use more if allocating more pages for BDL */ 110 #define BDL_SIZE 4096 111 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 112 #define AZX_MAX_FRAG 32 113 /* max buffer size - no h/w limit, you can increase as you like */ 114 #define AZX_MAX_BUF_SIZE (1024*1024*1024) 115 116 /* RIRB int mask: overrun[2], response[0] */ 117 #define RIRB_INT_RESPONSE 0x01 118 #define RIRB_INT_OVERRUN 0x04 119 #define RIRB_INT_MASK 0x05 120 121 /* STATESTS int mask: S3,SD2,SD1,SD0 */ 122 #define AZX_MAX_CODECS 8 123 #define AZX_DEFAULT_CODECS 4 124 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) 125 126 /* SD_CTL bits */ 127 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 128 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 129 #define SD_CTL_STRIPE (3 << 16) /* stripe control */ 130 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 131 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 132 #define SD_CTL_STREAM_TAG_MASK (0xf << 20) 133 #define SD_CTL_STREAM_TAG_SHIFT 20 134 135 /* SD_CTL and SD_STS */ 136 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 137 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 138 #define SD_INT_COMPLETE 0x04 /* completion interrupt */ 139 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 140 SD_INT_COMPLETE) 141 142 /* SD_STS */ 143 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 144 145 /* INTCTL and INTSTS */ 146 #define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */ 147 #define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 148 #define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 149 150 /* below are so far hardcoded - should read registers in future */ 151 #define AZX_MAX_CORB_ENTRIES 256 152 #define AZX_MAX_RIRB_ENTRIES 256 153 154 /* driver quirks (capabilities) */ 155 /* bits 0-7 are used for indicating driver type */ 156 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */ 157 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */ 158 #define AZX_DCAPS_SNOOP_MASK (3 << 10) /* snoop type mask */ 159 #define AZX_DCAPS_SNOOP_OFF (1 << 12) /* snoop default off */ 160 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */ 161 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */ 162 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */ 163 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */ 164 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */ 165 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */ 166 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */ 167 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */ 168 #define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21) /* no buffer size alignment */ 169 /* 22 unused */ 170 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ 171 #define AZX_DCAPS_REVERSE_ASSIGN (1 << 24) /* Assign devices in reverse order */ 172 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ 173 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ 174 #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */ 175 #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */ 176 #define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */ 177 #define AZX_DCAPS_SEPARATE_STREAM_TAG (1 << 30) /* capture and playback use separate stream tag */ 178 179 enum { 180 AZX_SNOOP_TYPE_NONE, 181 AZX_SNOOP_TYPE_SCH, 182 AZX_SNOOP_TYPE_ATI, 183 AZX_SNOOP_TYPE_NVIDIA, 184 }; 185 186 /* HD Audio class code */ 187 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 188 189 struct azx_dev { 190 struct snd_dma_buffer bdl; /* BDL buffer */ 191 u32 *posbuf; /* position buffer pointer */ 192 193 unsigned int bufsize; /* size of the play buffer in bytes */ 194 unsigned int period_bytes; /* size of the period in bytes */ 195 unsigned int frags; /* number for period in the play buffer */ 196 unsigned int fifo_size; /* FIFO size */ 197 unsigned long start_wallclk; /* start + minimum wallclk */ 198 unsigned long period_wallclk; /* wallclk for period */ 199 200 void __iomem *sd_addr; /* stream descriptor pointer */ 201 202 u32 sd_int_sta_mask; /* stream int status mask */ 203 204 /* pcm support */ 205 struct snd_pcm_substream *substream; /* assigned substream, 206 * set in PCM open 207 */ 208 unsigned int format_val; /* format value to be set in the 209 * controller and the codec 210 */ 211 unsigned char stream_tag; /* assigned stream */ 212 unsigned char index; /* stream index */ 213 int assigned_key; /* last device# key assigned to */ 214 215 unsigned int opened:1; 216 unsigned int running:1; 217 unsigned int irq_pending:1; 218 unsigned int prepared:1; 219 unsigned int locked:1; 220 /* 221 * For VIA: 222 * A flag to ensure DMA position is 0 223 * when link position is not greater than FIFO size 224 */ 225 unsigned int insufficient:1; 226 unsigned int wc_marked:1; 227 unsigned int no_period_wakeup:1; 228 229 struct timecounter azx_tc; 230 struct cyclecounter azx_cc; 231 232 int delay_negative_threshold; 233 234 #ifdef CONFIG_SND_HDA_DSP_LOADER 235 /* Allows dsp load to have sole access to the playback stream. */ 236 struct mutex dsp_mutex; 237 #endif 238 }; 239 240 /* CORB/RIRB */ 241 struct azx_rb { 242 u32 *buf; /* CORB/RIRB buffer 243 * Each CORB entry is 4byte, RIRB is 8byte 244 */ 245 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 246 /* for RIRB */ 247 unsigned short rp, wp; /* read/write pointers */ 248 int cmds[AZX_MAX_CODECS]; /* number of pending requests */ 249 u32 res[AZX_MAX_CODECS]; /* last read value */ 250 }; 251 252 struct azx; 253 254 /* Functions to read/write to hda registers. */ 255 struct hda_controller_ops { 256 /* Register Access */ 257 void (*reg_writel)(u32 value, u32 __iomem *addr); 258 u32 (*reg_readl)(u32 __iomem *addr); 259 void (*reg_writew)(u16 value, u16 __iomem *addr); 260 u16 (*reg_readw)(u16 __iomem *addr); 261 void (*reg_writeb)(u8 value, u8 __iomem *addr); 262 u8 (*reg_readb)(u8 __iomem *addr); 263 /* Disable msi if supported, PCI only */ 264 int (*disable_msi_reset_irq)(struct azx *); 265 /* Allocation ops */ 266 int (*dma_alloc_pages)(struct azx *chip, 267 int type, 268 size_t size, 269 struct snd_dma_buffer *buf); 270 void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf); 271 int (*substream_alloc_pages)(struct azx *chip, 272 struct snd_pcm_substream *substream, 273 size_t size); 274 int (*substream_free_pages)(struct azx *chip, 275 struct snd_pcm_substream *substream); 276 void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream, 277 struct vm_area_struct *area); 278 /* Check if current position is acceptable */ 279 int (*position_check)(struct azx *chip, struct azx_dev *azx_dev); 280 }; 281 282 struct azx_pcm { 283 struct azx *chip; 284 struct snd_pcm *pcm; 285 struct hda_codec *codec; 286 struct hda_pcm *info; 287 struct list_head list; 288 }; 289 290 typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *); 291 typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos); 292 293 struct azx { 294 struct snd_card *card; 295 struct pci_dev *pci; 296 int dev_index; 297 298 /* chip type specific */ 299 int driver_type; 300 unsigned int driver_caps; 301 int playback_streams; 302 int playback_index_offset; 303 int capture_streams; 304 int capture_index_offset; 305 int num_streams; 306 const int *jackpoll_ms; /* per-card jack poll interval */ 307 308 /* Register interaction. */ 309 const struct hda_controller_ops *ops; 310 311 /* position adjustment callbacks */ 312 azx_get_pos_callback_t get_position[2]; 313 azx_get_delay_callback_t get_delay[2]; 314 315 /* pci resources */ 316 unsigned long addr; 317 void __iomem *remap_addr; 318 int irq; 319 320 /* locks */ 321 spinlock_t reg_lock; 322 struct mutex open_mutex; /* Prevents concurrent open/close operations */ 323 324 /* streams (x num_streams) */ 325 struct azx_dev *azx_dev; 326 327 /* PCM */ 328 struct list_head pcm_list; /* azx_pcm list */ 329 330 /* HD codec */ 331 unsigned short codec_mask; 332 int codec_probe_mask; /* copied from probe_mask option */ 333 struct hda_bus *bus; 334 unsigned int beep_mode; 335 336 /* CORB/RIRB */ 337 struct azx_rb corb; 338 struct azx_rb rirb; 339 340 /* CORB/RIRB and position buffers */ 341 struct snd_dma_buffer rb; 342 struct snd_dma_buffer posbuf; 343 344 #ifdef CONFIG_SND_HDA_PATCH_LOADER 345 const struct firmware *fw; 346 #endif 347 348 /* flags */ 349 const int *bdl_pos_adj; 350 int poll_count; 351 unsigned int running:1; 352 unsigned int initialized:1; 353 unsigned int single_cmd:1; 354 unsigned int polling_mode:1; 355 unsigned int msi:1; 356 unsigned int probing:1; /* codec probing phase */ 357 unsigned int snoop:1; 358 unsigned int align_buffer_size:1; 359 unsigned int region_requested:1; 360 unsigned int disabled:1; /* disabled by VGA-switcher */ 361 362 /* for debugging */ 363 unsigned int last_cmd[AZX_MAX_CODECS]; 364 365 #ifdef CONFIG_SND_HDA_DSP_LOADER 366 struct azx_dev saved_azx_dev; 367 #endif 368 }; 369 370 #ifdef CONFIG_X86 371 #define azx_snoop(chip) ((chip)->snoop) 372 #else 373 #define azx_snoop(chip) true 374 #endif 375 376 /* 377 * macros for easy use 378 */ 379 380 #define azx_writel(chip, reg, value) \ 381 ((chip)->ops->reg_writel(value, (chip)->remap_addr + AZX_REG_##reg)) 382 #define azx_readl(chip, reg) \ 383 ((chip)->ops->reg_readl((chip)->remap_addr + AZX_REG_##reg)) 384 #define azx_writew(chip, reg, value) \ 385 ((chip)->ops->reg_writew(value, (chip)->remap_addr + AZX_REG_##reg)) 386 #define azx_readw(chip, reg) \ 387 ((chip)->ops->reg_readw((chip)->remap_addr + AZX_REG_##reg)) 388 #define azx_writeb(chip, reg, value) \ 389 ((chip)->ops->reg_writeb(value, (chip)->remap_addr + AZX_REG_##reg)) 390 #define azx_readb(chip, reg) \ 391 ((chip)->ops->reg_readb((chip)->remap_addr + AZX_REG_##reg)) 392 393 #define azx_sd_writel(chip, dev, reg, value) \ 394 ((chip)->ops->reg_writel(value, (dev)->sd_addr + AZX_REG_##reg)) 395 #define azx_sd_readl(chip, dev, reg) \ 396 ((chip)->ops->reg_readl((dev)->sd_addr + AZX_REG_##reg)) 397 #define azx_sd_writew(chip, dev, reg, value) \ 398 ((chip)->ops->reg_writew(value, (dev)->sd_addr + AZX_REG_##reg)) 399 #define azx_sd_readw(chip, dev, reg) \ 400 ((chip)->ops->reg_readw((dev)->sd_addr + AZX_REG_##reg)) 401 #define azx_sd_writeb(chip, dev, reg, value) \ 402 ((chip)->ops->reg_writeb(value, (dev)->sd_addr + AZX_REG_##reg)) 403 #define azx_sd_readb(chip, dev, reg) \ 404 ((chip)->ops->reg_readb((dev)->sd_addr + AZX_REG_##reg)) 405 406 #define azx_has_pm_runtime(chip) \ 407 ((chip)->driver_caps & AZX_DCAPS_PM_RUNTIME) 408 409 /* PCM setup */ 410 static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream) 411 { 412 return substream->runtime->private_data; 413 } 414 unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev); 415 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev); 416 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev); 417 418 /* Stream control. */ 419 void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev); 420 421 /* Allocation functions. */ 422 int azx_alloc_stream_pages(struct azx *chip); 423 void azx_free_stream_pages(struct azx *chip); 424 425 /* Low level azx interface */ 426 void azx_init_chip(struct azx *chip, bool full_reset); 427 void azx_stop_chip(struct azx *chip); 428 void azx_enter_link_reset(struct azx *chip); 429 irqreturn_t azx_interrupt(int irq, void *dev_id); 430 431 /* Codec interface */ 432 int azx_bus_create(struct azx *chip, const char *model); 433 int azx_probe_codecs(struct azx *chip, unsigned int max_slots); 434 int azx_codec_configure(struct azx *chip); 435 int azx_init_stream(struct azx *chip); 436 437 #endif /* __SOUND_HDA_CONTROLLER_H */ 438