1 /* 2 * Common functionality for the alsa driver code base for HD Audio. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef __SOUND_HDA_CONTROLLER_H 16 #define __SOUND_HDA_CONTROLLER_H 17 18 #include <linux/timecounter.h> 19 #include <linux/interrupt.h> 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/initval.h> 23 #include <sound/hda_codec.h> 24 #include <sound/hda_register.h> 25 26 #define AZX_MAX_CODECS HDA_MAX_CODECS 27 #define AZX_DEFAULT_CODECS 4 28 29 /* driver quirks (capabilities) */ 30 /* bits 0-7 are used for indicating driver type */ 31 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */ 32 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */ 33 #define AZX_DCAPS_SNOOP_MASK (3 << 10) /* snoop type mask */ 34 #define AZX_DCAPS_SNOOP_OFF (1 << 12) /* snoop default off */ 35 #ifdef CONFIG_SND_HDA_I915 36 #define AZX_DCAPS_I915_COMPONENT (1 << 13) /* bind with i915 gfx */ 37 #else 38 #define AZX_DCAPS_I915_COMPONENT 0 /* NOP */ 39 #endif 40 /* 14 unused */ 41 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */ 42 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */ 43 /* 17 unused */ 44 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */ 45 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */ 46 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */ 47 #define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21) /* no buffer size alignment */ 48 /* 22 unused */ 49 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ 50 /* 24 unused */ 51 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ 52 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ 53 /* 27 unused */ 54 #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */ 55 #define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */ 56 #define AZX_DCAPS_SEPARATE_STREAM_TAG (1 << 30) /* capture and playback use separate stream tag */ 57 58 enum { 59 AZX_SNOOP_TYPE_NONE, 60 AZX_SNOOP_TYPE_SCH, 61 AZX_SNOOP_TYPE_ATI, 62 AZX_SNOOP_TYPE_NVIDIA, 63 }; 64 65 struct azx_dev { 66 struct hdac_stream core; 67 68 unsigned int irq_pending:1; 69 /* 70 * For VIA: 71 * A flag to ensure DMA position is 0 72 * when link position is not greater than FIFO size 73 */ 74 unsigned int insufficient:1; 75 }; 76 77 #define azx_stream(dev) (&(dev)->core) 78 #define stream_to_azx_dev(s) container_of(s, struct azx_dev, core) 79 80 struct azx; 81 82 /* Functions to read/write to hda registers. */ 83 struct hda_controller_ops { 84 /* Disable msi if supported, PCI only */ 85 int (*disable_msi_reset_irq)(struct azx *); 86 void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream, 87 struct vm_area_struct *area); 88 /* Check if current position is acceptable */ 89 int (*position_check)(struct azx *chip, struct azx_dev *azx_dev); 90 /* enable/disable the link power */ 91 int (*link_power)(struct azx *chip, bool enable); 92 }; 93 94 struct azx_pcm { 95 struct azx *chip; 96 struct snd_pcm *pcm; 97 struct hda_codec *codec; 98 struct hda_pcm *info; 99 struct list_head list; 100 }; 101 102 typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *); 103 typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos); 104 105 struct azx { 106 struct hda_bus bus; 107 108 struct snd_card *card; 109 struct pci_dev *pci; 110 int dev_index; 111 112 /* chip type specific */ 113 int driver_type; 114 unsigned int driver_caps; 115 int playback_streams; 116 int playback_index_offset; 117 int capture_streams; 118 int capture_index_offset; 119 int num_streams; 120 int jackpoll_interval; /* jack poll interval in jiffies */ 121 122 /* Register interaction. */ 123 const struct hda_controller_ops *ops; 124 125 /* position adjustment callbacks */ 126 azx_get_pos_callback_t get_position[2]; 127 azx_get_delay_callback_t get_delay[2]; 128 129 /* locks */ 130 struct mutex open_mutex; /* Prevents concurrent open/close operations */ 131 132 /* PCM */ 133 struct list_head pcm_list; /* azx_pcm list */ 134 135 /* HD codec */ 136 int codec_probe_mask; /* copied from probe_mask option */ 137 unsigned int beep_mode; 138 139 #ifdef CONFIG_SND_HDA_PATCH_LOADER 140 const struct firmware *fw; 141 #endif 142 143 /* flags */ 144 int bdl_pos_adj; 145 int poll_count; 146 unsigned int running:1; 147 unsigned int fallback_to_single_cmd:1; 148 unsigned int single_cmd:1; 149 unsigned int polling_mode:1; 150 unsigned int msi:1; 151 unsigned int probing:1; /* codec probing phase */ 152 unsigned int snoop:1; 153 unsigned int uc_buffer:1; /* non-cached pages for stream buffers */ 154 unsigned int align_buffer_size:1; 155 unsigned int region_requested:1; 156 unsigned int disabled:1; /* disabled by vga_switcheroo */ 157 158 /* GTS present */ 159 unsigned int gts_present:1; 160 161 #ifdef CONFIG_SND_HDA_DSP_LOADER 162 struct azx_dev saved_azx_dev; 163 #endif 164 }; 165 166 #define azx_bus(chip) (&(chip)->bus.core) 167 #define bus_to_azx(_bus) container_of(_bus, struct azx, bus.core) 168 169 static inline bool azx_snoop(struct azx *chip) 170 { 171 return !IS_ENABLED(CONFIG_X86) || chip->snoop; 172 } 173 174 /* 175 * macros for easy use 176 */ 177 178 #define azx_writel(chip, reg, value) \ 179 snd_hdac_chip_writel(azx_bus(chip), reg, value) 180 #define azx_readl(chip, reg) \ 181 snd_hdac_chip_readl(azx_bus(chip), reg) 182 #define azx_writew(chip, reg, value) \ 183 snd_hdac_chip_writew(azx_bus(chip), reg, value) 184 #define azx_readw(chip, reg) \ 185 snd_hdac_chip_readw(azx_bus(chip), reg) 186 #define azx_writeb(chip, reg, value) \ 187 snd_hdac_chip_writeb(azx_bus(chip), reg, value) 188 #define azx_readb(chip, reg) \ 189 snd_hdac_chip_readb(azx_bus(chip), reg) 190 191 #define azx_has_pm_runtime(chip) \ 192 ((chip)->driver_caps & AZX_DCAPS_PM_RUNTIME) 193 194 /* PCM setup */ 195 static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream) 196 { 197 return substream->runtime->private_data; 198 } 199 unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev); 200 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev); 201 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev); 202 203 /* Stream control. */ 204 void azx_stop_all_streams(struct azx *chip); 205 206 /* Allocation functions. */ 207 #define azx_alloc_stream_pages(chip) \ 208 snd_hdac_bus_alloc_stream_pages(azx_bus(chip)) 209 #define azx_free_stream_pages(chip) \ 210 snd_hdac_bus_free_stream_pages(azx_bus(chip)) 211 212 /* Low level azx interface */ 213 void azx_init_chip(struct azx *chip, bool full_reset); 214 void azx_stop_chip(struct azx *chip); 215 #define azx_enter_link_reset(chip) \ 216 snd_hdac_bus_enter_link_reset(azx_bus(chip)) 217 irqreturn_t azx_interrupt(int irq, void *dev_id); 218 219 /* Codec interface */ 220 int azx_bus_init(struct azx *chip, const char *model, 221 const struct hdac_io_ops *io_ops); 222 int azx_probe_codecs(struct azx *chip, unsigned int max_slots); 223 int azx_codec_configure(struct azx *chip); 224 int azx_init_streams(struct azx *chip); 225 void azx_free_streams(struct azx *chip); 226 227 #endif /* __SOUND_HDA_CONTROLLER_H */ 228