1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41.c -- CS35l41 ALSA HDA audio driver 4 // 5 // Copyright 2021 Cirrus Logic, Inc. 6 // 7 // Author: Lucas Tanure <tanureal@opensource.cirrus.com> 8 9 #include <linux/acpi.h> 10 #include <linux/module.h> 11 #include <sound/hda_codec.h> 12 #include "hda_local.h" 13 #include "hda_auto_parser.h" 14 #include "hda_jack.h" 15 #include "hda_generic.h" 16 #include "hda_component.h" 17 #include "cs35l41_hda.h" 18 19 static const struct reg_sequence cs35l41_hda_config[] = { 20 { CS35L41_PLL_CLK_CTRL, 0x00000430 }, //3200000Hz, BCLK Input, PLL_REFCLK_EN = 1 21 { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, //GLOBAL_FS = 48 kHz 22 { CS35L41_SP_ENABLES, 0x00010000 }, //ASP_RX1_EN = 1 23 { CS35L41_SP_RATE_CTRL, 0x00000021 }, //ASP_BCLK_FREQ = 3.072 MHz 24 { CS35L41_SP_FORMAT, 0x20200200 }, //24 bits, I2S, BCLK Slave, FSYNC Slave 25 { CS35L41_DAC_PCM1_SRC, 0x00000008 }, //DACPCM1_SRC = ASPRX1 26 { CS35L41_AMP_DIG_VOL_CTRL, 0x00000000 }, //AMP_VOL_PCM 0.0 dB 27 { CS35L41_AMP_GAIN_CTRL, 0x00000084 }, //AMP_GAIN_PCM 4.5 dB 28 { CS35L41_PWR_CTRL2, 0x00000001 }, //AMP_EN = 1 29 }; 30 31 static const struct reg_sequence cs35l41_hda_start_bst[] = { 32 { CS35L41_PWR_CTRL2, 0x00000021 }, //BST_EN = 10, AMP_EN = 1 33 { CS35L41_PWR_CTRL1, 0x00000001, 3000}, // set GLOBAL_EN = 1 34 }; 35 36 static const struct reg_sequence cs35l41_hda_stop_bst[] = { 37 { CS35L41_PWR_CTRL1, 0x00000000, 3000}, // set GLOBAL_EN = 0 38 }; 39 40 // only on amps where GPIO1 is used to control ext. VSPK switch 41 static const struct reg_sequence cs35l41_start_ext_vspk[] = { 42 { 0x00000040, 0x00000055 }, 43 { 0x00000040, 0x000000AA }, 44 { 0x00007438, 0x00585941 }, 45 { 0x00007414, 0x08C82222 }, 46 { 0x0000742C, 0x00000009 }, 47 { 0x00011008, 0x00008001 }, 48 { 0x0000742C, 0x0000000F }, 49 { 0x0000742C, 0x00000079 }, 50 { 0x00007438, 0x00585941 }, 51 { CS35L41_PWR_CTRL1, 0x00000001, 3000}, // set GLOBAL_EN = 1 52 { 0x0000742C, 0x000000F9 }, 53 { 0x00007438, 0x00580941 }, 54 { 0x00000040, 0x000000CC }, 55 { 0x00000040, 0x00000033 }, 56 }; 57 58 //only on amps where GPIO1 is used to control ext. VSPK switch 59 static const struct reg_sequence cs35l41_stop_ext_vspk[] = { 60 { 0x00000040, 0x00000055 }, 61 { 0x00000040, 0x000000AA }, 62 { 0x00007438, 0x00585941 }, 63 { 0x00002014, 0x00000000, 3000}, //set GLOBAL_EN = 0 64 { 0x0000742C, 0x00000009 }, 65 { 0x00007438, 0x00580941 }, 66 { 0x00011008, 0x00000001 }, 67 { 0x0000393C, 0x000000C0, 6000}, 68 { 0x0000393C, 0x00000000 }, 69 { 0x00007414, 0x00C82222 }, 70 { 0x0000742C, 0x00000000 }, 71 { 0x00000040, 0x000000CC }, 72 { 0x00000040, 0x00000033 }, 73 }; 74 75 static const struct reg_sequence cs35l41_safe_to_active[] = { 76 { 0x00000040, 0x00000055 }, 77 { 0x00000040, 0x000000AA }, 78 { 0x0000742C, 0x0000000F }, 79 { 0x0000742C, 0x00000079 }, 80 { 0x00007438, 0x00585941 }, 81 { CS35L41_PWR_CTRL1, 0x00000001, 2000 }, //GLOBAL_EN = 1 82 { 0x0000742C, 0x000000F9 }, 83 { 0x00007438, 0x00580941 }, 84 { 0x00000040, 0x000000CC }, 85 { 0x00000040, 0x00000033 }, 86 }; 87 88 static const struct reg_sequence cs35l41_active_to_safe[] = { 89 { 0x00000040, 0x00000055 }, 90 { 0x00000040, 0x000000AA }, 91 { 0x00007438, 0x00585941 }, 92 { CS35L41_AMP_DIG_VOL_CTRL, 0x0000A678 }, //AMP_VOL_PCM Mute 93 { CS35L41_PWR_CTRL2, 0x00000000 }, //AMP_EN = 0 94 { CS35L41_PWR_CTRL1, 0x00000000 }, 95 { 0x0000742C, 0x00000009, 2000 }, 96 { 0x00007438, 0x00580941 }, 97 { 0x00000040, 0x000000CC }, 98 { 0x00000040, 0x00000033 }, 99 }; 100 101 static const struct reg_sequence cs35l41_reset_to_safe[] = { 102 { 0x00000040, 0x00000055 }, 103 { 0x00000040, 0x000000AA }, 104 { 0x00007438, 0x00585941 }, 105 { 0x00007414, 0x08C82222 }, 106 { 0x0000742C, 0x00000009 }, 107 { 0x00000040, 0x000000CC }, 108 { 0x00000040, 0x00000033 }, 109 }; 110 111 static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_no_bst = { 112 .probe = cs35l41_reset_to_safe, 113 .num_probe = ARRAY_SIZE(cs35l41_reset_to_safe), 114 .open = cs35l41_hda_config, 115 .num_open = ARRAY_SIZE(cs35l41_hda_config), 116 .prepare = cs35l41_safe_to_active, 117 .num_prepare = ARRAY_SIZE(cs35l41_safe_to_active), 118 .cleanup = cs35l41_active_to_safe, 119 .num_cleanup = ARRAY_SIZE(cs35l41_active_to_safe), 120 }; 121 122 static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_ext_bst = { 123 .open = cs35l41_hda_config, 124 .num_open = ARRAY_SIZE(cs35l41_hda_config), 125 .prepare = cs35l41_start_ext_vspk, 126 .num_prepare = ARRAY_SIZE(cs35l41_start_ext_vspk), 127 .cleanup = cs35l41_stop_ext_vspk, 128 .num_cleanup = ARRAY_SIZE(cs35l41_stop_ext_vspk), 129 }; 130 131 static const struct cs35l41_hda_reg_sequence cs35l41_hda_reg_seq_int_bst = { 132 .open = cs35l41_hda_config, 133 .num_open = ARRAY_SIZE(cs35l41_hda_config), 134 .prepare = cs35l41_hda_start_bst, 135 .num_prepare = ARRAY_SIZE(cs35l41_hda_start_bst), 136 .cleanup = cs35l41_hda_stop_bst, 137 .num_cleanup = ARRAY_SIZE(cs35l41_hda_stop_bst), 138 }; 139 140 static void cs35l41_hda_playback_hook(struct device *dev, int action) 141 { 142 struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev); 143 const struct cs35l41_hda_reg_sequence *reg_seq = cs35l41->reg_seq; 144 struct regmap *reg = cs35l41->regmap; 145 int ret = 0; 146 147 switch (action) { 148 case HDA_GEN_PCM_ACT_OPEN: 149 if (reg_seq->open) 150 ret = regmap_multi_reg_write(reg, reg_seq->open, reg_seq->num_open); 151 break; 152 case HDA_GEN_PCM_ACT_PREPARE: 153 if (reg_seq->prepare) 154 ret = regmap_multi_reg_write(reg, reg_seq->prepare, reg_seq->num_prepare); 155 break; 156 case HDA_GEN_PCM_ACT_CLEANUP: 157 if (reg_seq->cleanup) 158 ret = regmap_multi_reg_write(reg, reg_seq->cleanup, reg_seq->num_cleanup); 159 break; 160 case HDA_GEN_PCM_ACT_CLOSE: 161 if (reg_seq->close) 162 ret = regmap_multi_reg_write(reg, reg_seq->close, reg_seq->num_close); 163 break; 164 } 165 166 if (ret) 167 dev_warn(cs35l41->dev, "Failed to apply multi reg write: %d\n", ret); 168 169 } 170 171 static int cs35l41_hda_channel_map(struct device *dev, unsigned int tx_num, unsigned int *tx_slot, 172 unsigned int rx_num, unsigned int *rx_slot) 173 { 174 struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev); 175 176 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_num, tx_slot, rx_num, 177 rx_slot); 178 } 179 180 static int cs35l41_hda_bind(struct device *dev, struct device *master, void *master_data) 181 { 182 struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev); 183 struct hda_component *comps = master_data; 184 185 if (comps && cs35l41->index >= 0 && cs35l41->index < HDA_MAX_COMPONENTS) 186 comps = &comps[cs35l41->index]; 187 else 188 return -EINVAL; 189 190 if (!comps->dev) { 191 comps->dev = dev; 192 strscpy(comps->name, dev_name(dev), sizeof(comps->name)); 193 comps->playback_hook = cs35l41_hda_playback_hook; 194 comps->set_channel_map = cs35l41_hda_channel_map; 195 return 0; 196 } 197 198 return -EBUSY; 199 } 200 201 static void cs35l41_hda_unbind(struct device *dev, struct device *master, void *master_data) 202 { 203 struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev); 204 struct hda_component *comps = master_data; 205 206 if (comps[cs35l41->index].dev == dev) 207 memset(&comps[cs35l41->index], 0, sizeof(*comps)); 208 } 209 210 static const struct component_ops cs35l41_hda_comp_ops = { 211 .bind = cs35l41_hda_bind, 212 .unbind = cs35l41_hda_unbind, 213 }; 214 215 static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41, 216 const struct cs35l41_hda_hw_config *hw_cfg) 217 { 218 bool internal_boost = false; 219 int ret; 220 221 if (!hw_cfg) { 222 cs35l41->reg_seq = &cs35l41_hda_reg_seq_no_bst; 223 return 0; 224 } 225 226 if (hw_cfg->bst_ind || hw_cfg->bst_cap || hw_cfg->bst_ipk) 227 internal_boost = true; 228 229 switch (hw_cfg->gpio1_func) { 230 case CS35l41_VSPK_SWITCH: 231 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, 232 CS35L41_GPIO1_CTRL_MASK, 1 << CS35L41_GPIO1_CTRL_SHIFT); 233 break; 234 case CS35l41_SYNC: 235 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, 236 CS35L41_GPIO1_CTRL_MASK, 2 << CS35L41_GPIO1_CTRL_SHIFT); 237 break; 238 } 239 240 switch (hw_cfg->gpio2_func) { 241 case CS35L41_INTERRUPT: 242 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, 243 CS35L41_GPIO2_CTRL_MASK, 2 << CS35L41_GPIO2_CTRL_SHIFT); 244 break; 245 } 246 247 if (internal_boost) { 248 cs35l41->reg_seq = &cs35l41_hda_reg_seq_int_bst; 249 if (!(hw_cfg->bst_ind && hw_cfg->bst_cap && hw_cfg->bst_ipk)) 250 return -EINVAL; 251 ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, 252 hw_cfg->bst_ind, hw_cfg->bst_cap, hw_cfg->bst_ipk); 253 if (ret) 254 return ret; 255 } else { 256 cs35l41->reg_seq = &cs35l41_hda_reg_seq_ext_bst; 257 } 258 259 ret = cs35l41_hda_channel_map(cs35l41->dev, 0, NULL, 1, (unsigned int *)&hw_cfg->spk_pos); 260 if (ret) 261 return ret; 262 263 return 0; 264 } 265 266 static struct cs35l41_hda_hw_config *cs35l41_hda_read_acpi(struct cs35l41_hda *cs35l41, 267 const char *hid, int id) 268 { 269 struct cs35l41_hda_hw_config *hw_cfg; 270 u32 values[HDA_MAX_COMPONENTS]; 271 struct acpi_device *adev; 272 struct device *acpi_dev; 273 char *property; 274 size_t nval; 275 int i, ret; 276 277 adev = acpi_dev_get_first_match_dev(hid, NULL, -1); 278 if (!adev) { 279 dev_err(cs35l41->dev, "Failed to find an ACPI device for %s\n", hid); 280 return ERR_PTR(-ENODEV); 281 } 282 283 acpi_dev = get_device(acpi_get_first_physical_node(adev)); 284 acpi_dev_put(adev); 285 286 property = "cirrus,dev-index"; 287 ret = device_property_count_u32(acpi_dev, property); 288 if (ret <= 0) 289 goto no_acpi_dsd; 290 291 if (ret > ARRAY_SIZE(values)) { 292 ret = -EINVAL; 293 goto err; 294 } 295 nval = ret; 296 297 ret = device_property_read_u32_array(acpi_dev, property, values, nval); 298 if (ret) 299 goto err; 300 301 cs35l41->index = -1; 302 for (i = 0; i < nval; i++) { 303 if (values[i] == id) { 304 cs35l41->index = i; 305 break; 306 } 307 } 308 if (cs35l41->index == -1) { 309 dev_err(cs35l41->dev, "No index found in %s\n", property); 310 ret = -ENODEV; 311 goto err; 312 } 313 314 /* No devm_ version as CLSA0100, in no_acpi_dsd case, can't use devm version */ 315 cs35l41->reset_gpio = fwnode_gpiod_get_index(&adev->fwnode, "reset", cs35l41->index, 316 GPIOD_OUT_LOW, "cs35l41-reset"); 317 318 hw_cfg = kzalloc(sizeof(*hw_cfg), GFP_KERNEL); 319 if (!hw_cfg) { 320 ret = -ENOMEM; 321 goto err; 322 } 323 324 property = "cirrus,speaker-position"; 325 ret = device_property_read_u32_array(acpi_dev, property, values, nval); 326 if (ret) 327 goto err_free; 328 hw_cfg->spk_pos = values[cs35l41->index]; 329 330 property = "cirrus,gpio1-func"; 331 ret = device_property_read_u32_array(acpi_dev, property, values, nval); 332 if (ret) 333 goto err_free; 334 hw_cfg->gpio1_func = values[cs35l41->index]; 335 336 property = "cirrus,gpio2-func"; 337 ret = device_property_read_u32_array(acpi_dev, property, values, nval); 338 if (ret) 339 goto err_free; 340 hw_cfg->gpio2_func = values[cs35l41->index]; 341 342 property = "cirrus,boost-peak-milliamp"; 343 ret = device_property_read_u32_array(acpi_dev, property, values, nval); 344 if (ret == 0) 345 hw_cfg->bst_ipk = values[cs35l41->index]; 346 347 property = "cirrus,boost-ind-nanohenry"; 348 ret = device_property_read_u32_array(acpi_dev, property, values, nval); 349 if (ret == 0) 350 hw_cfg->bst_ind = values[cs35l41->index]; 351 352 property = "cirrus,boost-cap-microfarad"; 353 ret = device_property_read_u32_array(acpi_dev, property, values, nval); 354 if (ret == 0) 355 hw_cfg->bst_cap = values[cs35l41->index]; 356 357 put_device(acpi_dev); 358 359 return hw_cfg; 360 361 err_free: 362 kfree(hw_cfg); 363 err: 364 put_device(acpi_dev); 365 dev_err(cs35l41->dev, "Failed property %s: %d\n", property, ret); 366 367 return ERR_PTR(ret); 368 369 no_acpi_dsd: 370 /* 371 * Device CLSA0100 doesn't have _DSD so a gpiod_get by the label reset won't work. 372 * And devices created by i2c-multi-instantiate don't have their device struct pointing to 373 * the correct fwnode, so acpi_dev must be used here 374 * And devm functions expect that the device requesting the resource has the correct 375 * fwnode 376 */ 377 if (strncmp(hid, "CLSA0100", 8) != 0) 378 return ERR_PTR(-EINVAL); 379 380 /* check I2C address to assign the index */ 381 cs35l41->index = id == 0x40 ? 0 : 1; 382 cs35l41->reset_gpio = gpiod_get_index(acpi_dev, NULL, 0, GPIOD_OUT_HIGH); 383 cs35l41->vspk_always_on = true; 384 put_device(acpi_dev); 385 386 return NULL; 387 } 388 389 int cs35l41_hda_probe(struct device *dev, const char *device_name, int id, int irq, 390 struct regmap *regmap) 391 { 392 unsigned int int_sts, regid, reg_revid, mtl_revid, chipid, int_status; 393 struct cs35l41_hda_hw_config *acpi_hw_cfg; 394 struct cs35l41_hda *cs35l41; 395 int ret; 396 397 if (IS_ERR(regmap)) 398 return PTR_ERR(regmap); 399 400 cs35l41 = devm_kzalloc(dev, sizeof(*cs35l41), GFP_KERNEL); 401 if (!cs35l41) 402 return -ENOMEM; 403 404 cs35l41->dev = dev; 405 cs35l41->irq = irq; 406 cs35l41->regmap = regmap; 407 dev_set_drvdata(dev, cs35l41); 408 409 acpi_hw_cfg = cs35l41_hda_read_acpi(cs35l41, device_name, id); 410 if (IS_ERR(acpi_hw_cfg)) 411 return PTR_ERR(acpi_hw_cfg); 412 413 if (IS_ERR(cs35l41->reset_gpio)) { 414 ret = PTR_ERR(cs35l41->reset_gpio); 415 cs35l41->reset_gpio = NULL; 416 if (ret == -EBUSY) { 417 dev_info(cs35l41->dev, "Reset line busy, assuming shared reset\n"); 418 } else { 419 if (ret != -EPROBE_DEFER) 420 dev_err(cs35l41->dev, "Failed to get reset GPIO: %d\n", ret); 421 goto err; 422 } 423 } 424 if (cs35l41->reset_gpio) { 425 usleep_range(2000, 2100); 426 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 427 } 428 429 usleep_range(2000, 2100); 430 431 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, int_status, 432 int_status & CS35L41_OTP_BOOT_DONE, 1000, 100000); 433 if (ret) { 434 dev_err(cs35l41->dev, "Failed waiting for OTP_BOOT_DONE: %d\n", ret); 435 goto err; 436 } 437 438 ret = regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_sts); 439 if (ret || (int_sts & CS35L41_OTP_BOOT_ERR)) { 440 dev_err(cs35l41->dev, "OTP Boot error\n"); 441 ret = -EIO; 442 goto err; 443 } 444 445 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 446 if (ret) { 447 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret); 448 goto err; 449 } 450 451 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 452 if (ret) { 453 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret); 454 goto err; 455 } 456 457 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 458 459 chipid = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 460 if (regid != chipid) { 461 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", regid, chipid); 462 ret = -ENODEV; 463 goto err; 464 } 465 466 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid); 467 if (ret) 468 goto err; 469 470 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap); 471 if (ret) { 472 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret); 473 goto err; 474 } 475 476 ret = cs35l41_hda_apply_properties(cs35l41, acpi_hw_cfg); 477 if (ret) 478 goto err; 479 kfree(acpi_hw_cfg); 480 481 if (cs35l41->reg_seq->probe) { 482 ret = regmap_register_patch(cs35l41->regmap, cs35l41->reg_seq->probe, 483 cs35l41->reg_seq->num_probe); 484 if (ret) { 485 dev_err(cs35l41->dev, "Fail to apply probe reg patch: %d\n", ret); 486 goto err; 487 } 488 } 489 490 ret = component_add(cs35l41->dev, &cs35l41_hda_comp_ops); 491 if (ret) { 492 dev_err(cs35l41->dev, "Register component failed: %d\n", ret); 493 goto err; 494 } 495 496 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", regid, reg_revid); 497 498 return 0; 499 500 err: 501 kfree(acpi_hw_cfg); 502 if (!cs35l41->vspk_always_on) 503 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 504 gpiod_put(cs35l41->reset_gpio); 505 506 return ret; 507 } 508 EXPORT_SYMBOL_GPL(cs35l41_hda_probe); 509 510 int cs35l41_hda_remove(struct device *dev) 511 { 512 struct cs35l41_hda *cs35l41 = dev_get_drvdata(dev); 513 514 component_del(cs35l41->dev, &cs35l41_hda_comp_ops); 515 516 if (!cs35l41->vspk_always_on) 517 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 518 gpiod_put(cs35l41->reset_gpio); 519 520 return 0; 521 } 522 EXPORT_SYMBOL_GPL(cs35l41_hda_remove); 523 524 525 MODULE_DESCRIPTION("CS35L41 HDA Driver"); 526 MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, <tanureal@opensource.cirrus.com>"); 527 MODULE_LICENSE("GPL"); 528