1 /* 2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99) 3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>. 4 * Takashi Iwai <tiwai@suse.de> 5 * 6 * Most of the driver code comes from Zach Brown(zab@redhat.com) 7 * Alan Cox OSS Driver 8 * Rewritted from card-es1938.c source. 9 * 10 * TODO: 11 * Perhaps Synth 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 * 27 * 28 * Notes from Zach Brown about the driver code 29 * 30 * Hardware Description 31 * 32 * A working Maestro setup contains the Maestro chip wired to a 33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the 34 * Wavecache. The APUs can be though of as virtual audio routing 35 * channels. They can take data from a number of sources and perform 36 * basic encodings of the data. The wavecache is a storehouse for 37 * PCM data. Typically it deals with PCI and interracts with the 38 * APUs. The ASSP is a wacky DSP like device that ESS is loth 39 * to release docs on. Thankfully it isn't required on the Maestro 40 * until you start doing insane things like FM emulation and surround 41 * encoding. The codecs are almost always AC-97 compliant codecs, 42 * but it appears that early Maestros may have had PT101 (an ESS 43 * part?) wired to them. The only real difference in the Maestro 44 * families is external goop like docking capability, memory for 45 * the ASSP, and initialization differences. 46 * 47 * Driver Operation 48 * 49 * We only drive the APU/Wavecache as typical DACs and drive the 50 * mixers in the codecs. There are 64 APUs. We assign 6 to each 51 * /dev/dsp? device. 2 channels for output, and 4 channels for 52 * input. 53 * 54 * Each APU can do a number of things, but we only really use 55 * 3 basic functions. For playback we use them to convert PCM 56 * data fetched over PCI by the wavecahche into analog data that 57 * is handed to the codec. One APU for mono, and a pair for stereo. 58 * When in stereo, the combination of smarts in the APU and Wavecache 59 * decide which wavecache gets the left or right channel. 60 * 61 * For record we still use the old overly mono system. For each in 62 * coming channel the data comes in from the codec, through a 'input' 63 * APU, through another rate converter APU, and then into memory via 64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in 65 * software. The pass between the 2 APUs is supposedly what requires us 66 * to have a 512 byte buffer sitting around in wavecache/memory. 67 * 68 * The wavecache makes our life even more fun. First off, it can 69 * only address the first 28 bits of PCI address space, making it 70 * useless on quite a few architectures. Secondly, its insane. 71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length. 72 * But that doesn't really work. You can only use 1 region. So all our 73 * allocations have to be in 4meg of each other. Booo. Hiss. 74 * So we have a module parameter, dsps_order, that is the order of 75 * the number of dsps to provide. All their buffer space is allocated 76 * on open time. The sonicvibes OSS routines we inherited really want 77 * power of 2 buffers, so we have all those next to each other, then 78 * 512 byte regions for the recording wavecaches. This ends up 79 * wasting quite a bit of memory. The only fixes I can see would be 80 * getting a kernel allocator that could work in zones, or figuring out 81 * just how to coerce the WP into doing what we want. 82 * 83 * The indirection of the various registers means we have to spinlock 84 * nearly all register accesses. We have the main register indirection 85 * like the wave cache, maestro registers, etc. Then we have beasts 86 * like the APU interface that is indirect registers gotten at through 87 * the main maestro indirection. Ouch. We spinlock around the actual 88 * ports on a per card basis. This means spinlock activity at each IO 89 * operation, but the only IO operation clusters are in non critical 90 * paths and it makes the code far easier to follow. Interrupts are 91 * blocked while holding the locks because the int handler has to 92 * get at some of them :(. The mixer interface doesn't, however. 93 * We also have an OSS state lock that is thrown around in a few 94 * places. 95 */ 96 97 #include <sound/driver.h> 98 #include <asm/io.h> 99 #include <linux/delay.h> 100 #include <linux/interrupt.h> 101 #include <linux/init.h> 102 #include <linux/pci.h> 103 #include <linux/dma-mapping.h> 104 #include <linux/slab.h> 105 #include <linux/gameport.h> 106 #include <linux/moduleparam.h> 107 #include <linux/mutex.h> 108 109 #include <sound/core.h> 110 #include <sound/pcm.h> 111 #include <sound/mpu401.h> 112 #include <sound/ac97_codec.h> 113 #include <sound/initval.h> 114 115 #define CARD_NAME "ESS Maestro1/2" 116 #define DRIVER_NAME "ES1968" 117 118 MODULE_DESCRIPTION("ESS Maestro"); 119 MODULE_LICENSE("GPL"); 120 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e}," 121 "{ESS,Maestro 2}," 122 "{ESS,Maestro 1}," 123 "{TerraTec,DMX}}"); 124 125 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 126 #define SUPPORT_JOYSTICK 1 127 #endif 128 129 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */ 130 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 131 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 132 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 }; 133 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 }; 134 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 }; 135 static int clock[SNDRV_CARDS]; 136 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 137 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 138 #ifdef SUPPORT_JOYSTICK 139 static int joystick[SNDRV_CARDS]; 140 #endif 141 142 module_param_array(index, int, NULL, 0444); 143 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 144 module_param_array(id, charp, NULL, 0444); 145 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 146 module_param_array(enable, bool, NULL, 0444); 147 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard."); 148 module_param_array(total_bufsize, int, NULL, 0444); 149 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB."); 150 module_param_array(pcm_substreams_p, int, NULL, 0444); 151 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard."); 152 module_param_array(pcm_substreams_c, int, NULL, 0444); 153 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard."); 154 module_param_array(clock, int, NULL, 0444); 155 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)"); 156 module_param_array(use_pm, int, NULL, 0444); 157 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)"); 158 module_param_array(enable_mpu, int, NULL, 0444); 159 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)"); 160 #ifdef SUPPORT_JOYSTICK 161 module_param_array(joystick, bool, NULL, 0444); 162 MODULE_PARM_DESC(joystick, "Enable joystick."); 163 #endif 164 165 166 #define NR_APUS 64 167 #define NR_APU_REGS 16 168 169 /* NEC Versas ? */ 170 #define NEC_VERSA_SUBID1 0x80581033 171 #define NEC_VERSA_SUBID2 0x803c1033 172 173 /* Mode Flags */ 174 #define ESS_FMT_STEREO 0x01 175 #define ESS_FMT_16BIT 0x02 176 177 #define DAC_RUNNING 1 178 #define ADC_RUNNING 2 179 180 /* Values for the ESM_LEGACY_AUDIO_CONTROL */ 181 182 #define ESS_DISABLE_AUDIO 0x8000 183 #define ESS_ENABLE_SERIAL_IRQ 0x4000 184 #define IO_ADRESS_ALIAS 0x0020 185 #define MPU401_IRQ_ENABLE 0x0010 186 #define MPU401_IO_ENABLE 0x0008 187 #define GAME_IO_ENABLE 0x0004 188 #define FM_IO_ENABLE 0x0002 189 #define SB_IO_ENABLE 0x0001 190 191 /* Values for the ESM_CONFIG_A */ 192 193 #define PIC_SNOOP1 0x4000 194 #define PIC_SNOOP2 0x2000 195 #define SAFEGUARD 0x0800 196 #define DMA_CLEAR 0x0700 197 #define DMA_DDMA 0x0000 198 #define DMA_TDMA 0x0100 199 #define DMA_PCPCI 0x0200 200 #define POST_WRITE 0x0080 201 #define PCI_TIMING 0x0040 202 #define SWAP_LR 0x0020 203 #define SUBTR_DECODE 0x0002 204 205 /* Values for the ESM_CONFIG_B */ 206 207 #define SPDIF_CONFB 0x0100 208 #define HWV_CONFB 0x0080 209 #define DEBOUNCE 0x0040 210 #define GPIO_CONFB 0x0020 211 #define CHI_CONFB 0x0010 212 #define IDMA_CONFB 0x0008 /*undoc */ 213 #define MIDI_FIX 0x0004 /*undoc */ 214 #define IRQ_TO_ISA 0x0001 /*undoc */ 215 216 /* Values for Ring Bus Control B */ 217 #define RINGB_2CODEC_ID_MASK 0x0003 218 #define RINGB_DIS_VALIDATION 0x0008 219 #define RINGB_EN_SPDIF 0x0010 220 #define RINGB_EN_2CODEC 0x0020 221 #define RINGB_SING_BIT_DUAL 0x0040 222 223 /* ****Port Adresses**** */ 224 225 /* Write & Read */ 226 #define ESM_INDEX 0x02 227 #define ESM_DATA 0x00 228 229 /* AC97 + RingBus */ 230 #define ESM_AC97_INDEX 0x30 231 #define ESM_AC97_DATA 0x32 232 #define ESM_RING_BUS_DEST 0x34 233 #define ESM_RING_BUS_CONTR_A 0x36 234 #define ESM_RING_BUS_CONTR_B 0x38 235 #define ESM_RING_BUS_SDO 0x3A 236 237 /* WaveCache*/ 238 #define WC_INDEX 0x10 239 #define WC_DATA 0x12 240 #define WC_CONTROL 0x14 241 242 /* ASSP*/ 243 #define ASSP_INDEX 0x80 244 #define ASSP_MEMORY 0x82 245 #define ASSP_DATA 0x84 246 #define ASSP_CONTROL_A 0xA2 247 #define ASSP_CONTROL_B 0xA4 248 #define ASSP_CONTROL_C 0xA6 249 #define ASSP_HOSTW_INDEX 0xA8 250 #define ASSP_HOSTW_DATA 0xAA 251 #define ASSP_HOSTW_IRQ 0xAC 252 /* Midi */ 253 #define ESM_MPU401_PORT 0x98 254 /* Others */ 255 #define ESM_PORT_HOST_IRQ 0x18 256 257 #define IDR0_DATA_PORT 0x00 258 #define IDR1_CRAM_POINTER 0x01 259 #define IDR2_CRAM_DATA 0x02 260 #define IDR3_WAVE_DATA 0x03 261 #define IDR4_WAVE_PTR_LOW 0x04 262 #define IDR5_WAVE_PTR_HI 0x05 263 #define IDR6_TIMER_CTRL 0x06 264 #define IDR7_WAVE_ROMRAM 0x07 265 266 #define WRITEABLE_MAP 0xEFFFFF 267 #define READABLE_MAP 0x64003F 268 269 /* PCI Register */ 270 271 #define ESM_LEGACY_AUDIO_CONTROL 0x40 272 #define ESM_ACPI_COMMAND 0x54 273 #define ESM_CONFIG_A 0x50 274 #define ESM_CONFIG_B 0x52 275 #define ESM_DDMA 0x60 276 277 /* Bob Bits */ 278 #define ESM_BOB_ENABLE 0x0001 279 #define ESM_BOB_START 0x0001 280 281 /* Host IRQ Control Bits */ 282 #define ESM_RESET_MAESTRO 0x8000 283 #define ESM_RESET_DIRECTSOUND 0x4000 284 #define ESM_HIRQ_ClkRun 0x0100 285 #define ESM_HIRQ_HW_VOLUME 0x0040 286 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */ 287 #define ESM_HIRQ_ASSP 0x0010 288 #define ESM_HIRQ_DSIE 0x0004 289 #define ESM_HIRQ_MPU401 0x0002 290 #define ESM_HIRQ_SB 0x0001 291 292 /* Host IRQ Status Bits */ 293 #define ESM_MPU401_IRQ 0x02 294 #define ESM_SB_IRQ 0x01 295 #define ESM_SOUND_IRQ 0x04 296 #define ESM_ASSP_IRQ 0x10 297 #define ESM_HWVOL_IRQ 0x40 298 299 #define ESS_SYSCLK 50000000 300 #define ESM_BOB_FREQ 200 301 #define ESM_BOB_FREQ_MAX 800 302 303 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */ 304 #define ESM_FREQ_ESM2 (50000000L / 1024L) 305 306 /* APU Modes: reg 0x00, bit 4-7 */ 307 #define ESM_APU_MODE_SHIFT 4 308 #define ESM_APU_MODE_MASK (0xf << 4) 309 #define ESM_APU_OFF 0x00 310 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */ 311 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */ 312 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */ 313 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */ 314 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */ 315 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */ 316 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */ 317 #define ESM_APU_CORRELATOR 0x08 /* Correlator */ 318 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */ 319 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */ 320 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */ 321 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */ 322 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */ 323 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */ 324 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */ 325 326 /* reg 0x00 */ 327 #define ESM_APU_FILTER_Q_SHIFT 0 328 #define ESM_APU_FILTER_Q_MASK (3 << 0) 329 /* APU Filtey Q Control */ 330 #define ESM_APU_FILTER_LESSQ 0x00 331 #define ESM_APU_FILTER_MOREQ 0x03 332 333 #define ESM_APU_FILTER_TYPE_SHIFT 2 334 #define ESM_APU_FILTER_TYPE_MASK (3 << 2) 335 #define ESM_APU_ENV_TYPE_SHIFT 8 336 #define ESM_APU_ENV_TYPE_MASK (3 << 8) 337 #define ESM_APU_ENV_STATE_SHIFT 10 338 #define ESM_APU_ENV_STATE_MASK (3 << 10) 339 #define ESM_APU_END_CURVE (1 << 12) 340 #define ESM_APU_INT_ON_LOOP (1 << 13) 341 #define ESM_APU_DMA_ENABLE (1 << 14) 342 343 /* reg 0x02 */ 344 #define ESM_APU_SUBMIX_GROUP_SHIRT 0 345 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0) 346 #define ESM_APU_SUBMIX_MODE (1 << 3) 347 #define ESM_APU_6dB (1 << 4) 348 #define ESM_APU_DUAL_EFFECT (1 << 5) 349 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6 350 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6) 351 352 /* reg 0x03 */ 353 #define ESM_APU_STEP_SIZE_MASK 0x0fff 354 355 /* reg 0x04 */ 356 #define ESM_APU_PHASE_SHIFT 0 357 #define ESM_APU_PHASE_MASK (0xff << 0) 358 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */ 359 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8) 360 361 /* reg 0x05 - wave start offset */ 362 /* reg 0x06 - wave end offset */ 363 /* reg 0x07 - wave loop length */ 364 365 /* reg 0x08 */ 366 #define ESM_APU_EFFECT_GAIN_SHIFT 0 367 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0) 368 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8 369 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8) 370 #define ESM_APU_TREMOLO_RATE_SHIFT 12 371 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12) 372 373 /* reg 0x09 */ 374 /* bit 0-7 amplitude dest? */ 375 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8 376 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8) 377 378 /* reg 0x0a */ 379 #define ESM_APU_POLAR_PAN_SHIFT 0 380 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0) 381 /* Polar Pan Control */ 382 #define ESM_APU_PAN_CENTER_CIRCLE 0x00 383 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01 384 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02 385 386 #define ESM_APU_FILTER_TUNING_SHIFT 8 387 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8) 388 389 /* reg 0x0b */ 390 #define ESM_APU_DATA_SRC_A_SHIFT 0 391 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0) 392 #define ESM_APU_INV_POL_A (1 << 7) 393 #define ESM_APU_DATA_SRC_B_SHIFT 8 394 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8) 395 #define ESM_APU_INV_POL_B (1 << 15) 396 397 #define ESM_APU_VIBRATO_RATE_SHIFT 0 398 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0) 399 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4 400 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4) 401 #define ESM_APU_VIBRATO_PHASE_SHIFT 8 402 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8) 403 404 /* reg 0x0c */ 405 #define ESM_APU_RADIUS_SELECT (1 << 6) 406 407 /* APU Filter Control */ 408 #define ESM_APU_FILTER_2POLE_LOPASS 0x00 409 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01 410 #define ESM_APU_FILTER_2POLE_HIPASS 0x02 411 #define ESM_APU_FILTER_1POLE_LOPASS 0x03 412 #define ESM_APU_FILTER_1POLE_HIPASS 0x04 413 #define ESM_APU_FILTER_OFF 0x05 414 415 /* APU ATFP Type */ 416 #define ESM_APU_ATFP_AMPLITUDE 0x00 417 #define ESM_APU_ATFP_TREMELO 0x01 418 #define ESM_APU_ATFP_FILTER 0x02 419 #define ESM_APU_ATFP_PAN 0x03 420 421 /* APU ATFP Flags */ 422 #define ESM_APU_ATFP_FLG_OFF 0x00 423 #define ESM_APU_ATFP_FLG_WAIT 0x01 424 #define ESM_APU_ATFP_FLG_DONE 0x02 425 #define ESM_APU_ATFP_FLG_INPROCESS 0x03 426 427 428 /* capture mixing buffer size */ 429 #define ESM_MEM_ALIGN 0x1000 430 #define ESM_MIXBUF_SIZE 0x400 431 432 #define ESM_MODE_PLAY 0 433 #define ESM_MODE_CAPTURE 1 434 435 /* acpi states */ 436 enum { 437 ACPI_D0=0, 438 ACPI_D1, 439 ACPI_D2, 440 ACPI_D3 441 }; 442 443 /* bits in the acpi masks */ 444 #define ACPI_12MHZ ( 1 << 15) 445 #define ACPI_24MHZ ( 1 << 14) 446 #define ACPI_978 ( 1 << 13) 447 #define ACPI_SPDIF ( 1 << 12) 448 #define ACPI_GLUE ( 1 << 11) 449 #define ACPI__10 ( 1 << 10) /* reserved */ 450 #define ACPI_PCIINT ( 1 << 9) 451 #define ACPI_HV ( 1 << 8) /* hardware volume */ 452 #define ACPI_GPIO ( 1 << 7) 453 #define ACPI_ASSP ( 1 << 6) 454 #define ACPI_SB ( 1 << 5) /* sb emul */ 455 #define ACPI_FM ( 1 << 4) /* fm emul */ 456 #define ACPI_RB ( 1 << 3) /* ringbus / aclink */ 457 #define ACPI_MIDI ( 1 << 2) 458 #define ACPI_GP ( 1 << 1) /* game port */ 459 #define ACPI_WP ( 1 << 0) /* wave processor */ 460 461 #define ACPI_ALL (0xffff) 462 #define ACPI_SLEEP (~(ACPI_SPDIF|ACPI_ASSP|ACPI_SB|ACPI_FM| \ 463 ACPI_MIDI|ACPI_GP|ACPI_WP)) 464 #define ACPI_NONE (ACPI__10) 465 466 /* these masks indicate which units we care about at 467 which states */ 468 static u16 acpi_state_mask[] = { 469 [ACPI_D0] = ACPI_ALL, 470 [ACPI_D1] = ACPI_SLEEP, 471 [ACPI_D2] = ACPI_SLEEP, 472 [ACPI_D3] = ACPI_NONE 473 }; 474 475 476 /* APU use in the driver */ 477 enum snd_enum_apu_type { 478 ESM_APU_PCM_PLAY, 479 ESM_APU_PCM_CAPTURE, 480 ESM_APU_PCM_RATECONV, 481 ESM_APU_FREE 482 }; 483 484 /* chip type */ 485 enum { 486 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E 487 }; 488 489 /* DMA Hack! */ 490 struct esm_memory { 491 struct snd_dma_buffer buf; 492 int empty; /* status */ 493 struct list_head list; 494 }; 495 496 /* Playback Channel */ 497 struct esschan { 498 int running; 499 500 u8 apu[4]; 501 u8 apu_mode[4]; 502 503 /* playback/capture pcm buffer */ 504 struct esm_memory *memory; 505 /* capture mixer buffer */ 506 struct esm_memory *mixbuf; 507 508 unsigned int hwptr; /* current hw pointer in bytes */ 509 unsigned int count; /* sample counter in bytes */ 510 unsigned int dma_size; /* total buffer size in bytes */ 511 unsigned int frag_size; /* period size in bytes */ 512 unsigned int wav_shift; 513 u16 base[4]; /* offset for ptr */ 514 515 /* stereo/16bit flag */ 516 unsigned char fmt; 517 int mode; /* playback / capture */ 518 519 int bob_freq; /* required timer frequency */ 520 521 struct snd_pcm_substream *substream; 522 523 /* linked list */ 524 struct list_head list; 525 526 #ifdef CONFIG_PM 527 u16 wc_map[4]; 528 #endif 529 }; 530 531 struct es1968 { 532 /* Module Config */ 533 int total_bufsize; /* in bytes */ 534 535 int playback_streams, capture_streams; 536 537 unsigned int clock; /* clock */ 538 /* for clock measurement */ 539 unsigned int in_measurement: 1; 540 unsigned int measure_apu; 541 unsigned int measure_lastpos; 542 unsigned int measure_count; 543 544 /* buffer */ 545 struct snd_dma_buffer dma; 546 547 /* Resources... */ 548 int irq; 549 unsigned long io_port; 550 int type; 551 struct pci_dev *pci; 552 struct snd_card *card; 553 struct snd_pcm *pcm; 554 int do_pm; /* power-management enabled */ 555 556 /* DMA memory block */ 557 struct list_head buf_list; 558 559 /* ALSA Stuff */ 560 struct snd_ac97 *ac97; 561 struct snd_kcontrol *master_switch; /* for h/w volume control */ 562 struct snd_kcontrol *master_volume; 563 564 struct snd_rawmidi *rmidi; 565 566 spinlock_t reg_lock; 567 spinlock_t ac97_lock; 568 struct tasklet_struct hwvol_tq; 569 unsigned int in_suspend; 570 571 /* Maestro Stuff */ 572 u16 maestro_map[32]; 573 int bobclient; /* active timer instancs */ 574 int bob_freq; /* timer frequency */ 575 struct mutex memory_mutex; /* memory lock */ 576 577 /* APU states */ 578 unsigned char apu[NR_APUS]; 579 580 /* active substreams */ 581 struct list_head substream_list; 582 spinlock_t substream_lock; 583 584 #ifdef CONFIG_PM 585 u16 apu_map[NR_APUS][NR_APU_REGS]; 586 #endif 587 588 #ifdef SUPPORT_JOYSTICK 589 struct gameport *gameport; 590 #endif 591 }; 592 593 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs); 594 595 static struct pci_device_id snd_es1968_ids[] = { 596 /* Maestro 1 */ 597 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO }, 598 /* Maestro 2 */ 599 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 }, 600 /* Maestro 2E */ 601 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E }, 602 { 0, } 603 }; 604 605 MODULE_DEVICE_TABLE(pci, snd_es1968_ids); 606 607 /* ********************* 608 * Low Level Funcs! * 609 *********************/ 610 611 /* no spinlock */ 612 static void __maestro_write(struct es1968 *chip, u16 reg, u16 data) 613 { 614 outw(reg, chip->io_port + ESM_INDEX); 615 outw(data, chip->io_port + ESM_DATA); 616 chip->maestro_map[reg] = data; 617 } 618 619 static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data) 620 { 621 unsigned long flags; 622 spin_lock_irqsave(&chip->reg_lock, flags); 623 __maestro_write(chip, reg, data); 624 spin_unlock_irqrestore(&chip->reg_lock, flags); 625 } 626 627 /* no spinlock */ 628 static u16 __maestro_read(struct es1968 *chip, u16 reg) 629 { 630 if (READABLE_MAP & (1 << reg)) { 631 outw(reg, chip->io_port + ESM_INDEX); 632 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA); 633 } 634 return chip->maestro_map[reg]; 635 } 636 637 static inline u16 maestro_read(struct es1968 *chip, u16 reg) 638 { 639 unsigned long flags; 640 u16 result; 641 spin_lock_irqsave(&chip->reg_lock, flags); 642 result = __maestro_read(chip, reg); 643 spin_unlock_irqrestore(&chip->reg_lock, flags); 644 return result; 645 } 646 647 /* Wait for the codec bus to be free */ 648 static int snd_es1968_ac97_wait(struct es1968 *chip) 649 { 650 int timeout = 100000; 651 652 while (timeout-- > 0) { 653 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) 654 return 0; 655 cond_resched(); 656 } 657 snd_printd("es1968: ac97 timeout\n"); 658 return 1; /* timeout */ 659 } 660 661 static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) 662 { 663 struct es1968 *chip = ac97->private_data; 664 unsigned long flags; 665 666 snd_es1968_ac97_wait(chip); 667 668 /* Write the bus */ 669 spin_lock_irqsave(&chip->ac97_lock, flags); 670 outw(val, chip->io_port + ESM_AC97_DATA); 671 /*msleep(1);*/ 672 outb(reg, chip->io_port + ESM_AC97_INDEX); 673 /*msleep(1);*/ 674 spin_unlock_irqrestore(&chip->ac97_lock, flags); 675 } 676 677 static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 678 { 679 u16 data = 0; 680 struct es1968 *chip = ac97->private_data; 681 unsigned long flags; 682 683 snd_es1968_ac97_wait(chip); 684 685 spin_lock_irqsave(&chip->ac97_lock, flags); 686 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX); 687 /*msleep(1);*/ 688 689 if (! snd_es1968_ac97_wait(chip)) { 690 data = inw(chip->io_port + ESM_AC97_DATA); 691 /*msleep(1);*/ 692 } 693 spin_unlock_irqrestore(&chip->ac97_lock, flags); 694 695 return data; 696 } 697 698 /* no spinlock */ 699 static void apu_index_set(struct es1968 *chip, u16 index) 700 { 701 int i; 702 __maestro_write(chip, IDR1_CRAM_POINTER, index); 703 for (i = 0; i < 1000; i++) 704 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index) 705 return; 706 snd_printd("es1968: APU register select failed. (Timeout)\n"); 707 } 708 709 /* no spinlock */ 710 static void apu_data_set(struct es1968 *chip, u16 data) 711 { 712 int i; 713 for (i = 0; i < 1000; i++) { 714 if (__maestro_read(chip, IDR0_DATA_PORT) == data) 715 return; 716 __maestro_write(chip, IDR0_DATA_PORT, data); 717 } 718 snd_printd("es1968: APU register set probably failed (Timeout)!\n"); 719 } 720 721 /* no spinlock */ 722 static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) 723 { 724 snd_assert(channel < NR_APUS, return); 725 #ifdef CONFIG_PM 726 chip->apu_map[channel][reg] = data; 727 #endif 728 reg |= (channel << 4); 729 apu_index_set(chip, reg); 730 apu_data_set(chip, data); 731 } 732 733 static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) 734 { 735 unsigned long flags; 736 spin_lock_irqsave(&chip->reg_lock, flags); 737 __apu_set_register(chip, channel, reg, data); 738 spin_unlock_irqrestore(&chip->reg_lock, flags); 739 } 740 741 static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg) 742 { 743 snd_assert(channel < NR_APUS, return 0); 744 reg |= (channel << 4); 745 apu_index_set(chip, reg); 746 return __maestro_read(chip, IDR0_DATA_PORT); 747 } 748 749 static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg) 750 { 751 unsigned long flags; 752 u16 v; 753 spin_lock_irqsave(&chip->reg_lock, flags); 754 v = __apu_get_register(chip, channel, reg); 755 spin_unlock_irqrestore(&chip->reg_lock, flags); 756 return v; 757 } 758 759 #if 0 /* ASSP is not supported */ 760 761 static void assp_set_register(struct es1968 *chip, u32 reg, u32 value) 762 { 763 unsigned long flags; 764 765 spin_lock_irqsave(&chip->reg_lock, flags); 766 outl(reg, chip->io_port + ASSP_INDEX); 767 outl(value, chip->io_port + ASSP_DATA); 768 spin_unlock_irqrestore(&chip->reg_lock, flags); 769 } 770 771 static u32 assp_get_register(struct es1968 *chip, u32 reg) 772 { 773 unsigned long flags; 774 u32 value; 775 776 spin_lock_irqsave(&chip->reg_lock, flags); 777 outl(reg, chip->io_port + ASSP_INDEX); 778 value = inl(chip->io_port + ASSP_DATA); 779 spin_unlock_irqrestore(&chip->reg_lock, flags); 780 781 return value; 782 } 783 784 #endif 785 786 static void wave_set_register(struct es1968 *chip, u16 reg, u16 value) 787 { 788 unsigned long flags; 789 790 spin_lock_irqsave(&chip->reg_lock, flags); 791 outw(reg, chip->io_port + WC_INDEX); 792 outw(value, chip->io_port + WC_DATA); 793 spin_unlock_irqrestore(&chip->reg_lock, flags); 794 } 795 796 static u16 wave_get_register(struct es1968 *chip, u16 reg) 797 { 798 unsigned long flags; 799 u16 value; 800 801 spin_lock_irqsave(&chip->reg_lock, flags); 802 outw(reg, chip->io_port + WC_INDEX); 803 value = inw(chip->io_port + WC_DATA); 804 spin_unlock_irqrestore(&chip->reg_lock, flags); 805 806 return value; 807 } 808 809 /* ******************* 810 * Bob the Timer! * 811 *******************/ 812 813 static void snd_es1968_bob_stop(struct es1968 *chip) 814 { 815 u16 reg; 816 817 reg = __maestro_read(chip, 0x11); 818 reg &= ~ESM_BOB_ENABLE; 819 __maestro_write(chip, 0x11, reg); 820 reg = __maestro_read(chip, 0x17); 821 reg &= ~ESM_BOB_START; 822 __maestro_write(chip, 0x17, reg); 823 } 824 825 static void snd_es1968_bob_start(struct es1968 *chip) 826 { 827 int prescale; 828 int divide; 829 830 /* compute ideal interrupt frequency for buffer size & play rate */ 831 /* first, find best prescaler value to match freq */ 832 for (prescale = 5; prescale < 12; prescale++) 833 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9))) 834 break; 835 836 /* next, back off prescaler whilst getting divider into optimum range */ 837 divide = 1; 838 while ((prescale > 5) && (divide < 32)) { 839 prescale--; 840 divide <<= 1; 841 } 842 divide >>= 1; 843 844 /* now fine-tune the divider for best match */ 845 for (; divide < 31; divide++) 846 if (chip->bob_freq > 847 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break; 848 849 /* divide = 0 is illegal, but don't let prescale = 4! */ 850 if (divide == 0) { 851 divide++; 852 if (prescale > 5) 853 prescale--; 854 } else if (divide > 1) 855 divide--; 856 857 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */ 858 859 /* Now set IDR 11/17 */ 860 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1); 861 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1); 862 } 863 864 /* call with substream spinlock */ 865 static void snd_es1968_bob_inc(struct es1968 *chip, int freq) 866 { 867 chip->bobclient++; 868 if (chip->bobclient == 1) { 869 chip->bob_freq = freq; 870 snd_es1968_bob_start(chip); 871 } else if (chip->bob_freq < freq) { 872 snd_es1968_bob_stop(chip); 873 chip->bob_freq = freq; 874 snd_es1968_bob_start(chip); 875 } 876 } 877 878 /* call with substream spinlock */ 879 static void snd_es1968_bob_dec(struct es1968 *chip) 880 { 881 chip->bobclient--; 882 if (chip->bobclient <= 0) 883 snd_es1968_bob_stop(chip); 884 else if (chip->bob_freq > ESM_BOB_FREQ) { 885 /* check reduction of timer frequency */ 886 struct list_head *p; 887 int max_freq = ESM_BOB_FREQ; 888 list_for_each(p, &chip->substream_list) { 889 struct esschan *es = list_entry(p, struct esschan, list); 890 if (max_freq < es->bob_freq) 891 max_freq = es->bob_freq; 892 } 893 if (max_freq != chip->bob_freq) { 894 snd_es1968_bob_stop(chip); 895 chip->bob_freq = max_freq; 896 snd_es1968_bob_start(chip); 897 } 898 } 899 } 900 901 static int 902 snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es, 903 struct snd_pcm_runtime *runtime) 904 { 905 /* we acquire 4 interrupts per period for precise control.. */ 906 int freq = runtime->rate * 4; 907 if (es->fmt & ESS_FMT_STEREO) 908 freq <<= 1; 909 if (es->fmt & ESS_FMT_16BIT) 910 freq <<= 1; 911 freq /= es->frag_size; 912 if (freq < ESM_BOB_FREQ) 913 freq = ESM_BOB_FREQ; 914 else if (freq > ESM_BOB_FREQ_MAX) 915 freq = ESM_BOB_FREQ_MAX; 916 return freq; 917 } 918 919 920 /************* 921 * PCM Part * 922 *************/ 923 924 static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq) 925 { 926 u32 rate = (freq << 16) / chip->clock; 927 #if 0 /* XXX: do we need this? */ 928 if (rate > 0x10000) 929 rate = 0x10000; 930 #endif 931 return rate; 932 } 933 934 /* get current pointer */ 935 static inline unsigned int 936 snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es) 937 { 938 unsigned int offset; 939 940 offset = apu_get_register(chip, es->apu[0], 5); 941 942 offset -= es->base[0]; 943 944 return (offset & 0xFFFE); /* hardware is in words */ 945 } 946 947 static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq) 948 { 949 apu_set_register(chip, apu, 2, 950 (apu_get_register(chip, apu, 2) & 0x00FF) | 951 ((freq & 0xff) << 8) | 0x10); 952 apu_set_register(chip, apu, 3, freq >> 8); 953 } 954 955 /* spin lock held */ 956 static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode) 957 { 958 /* set the APU mode */ 959 __apu_set_register(esm, apu, 0, 960 (__apu_get_register(esm, apu, 0) & 0xff0f) | 961 (mode << 4)); 962 } 963 964 static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es) 965 { 966 spin_lock(&chip->reg_lock); 967 __apu_set_register(chip, es->apu[0], 5, es->base[0]); 968 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]); 969 if (es->mode == ESM_MODE_CAPTURE) { 970 __apu_set_register(chip, es->apu[2], 5, es->base[2]); 971 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]); 972 } 973 if (es->fmt & ESS_FMT_STEREO) { 974 __apu_set_register(chip, es->apu[1], 5, es->base[1]); 975 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]); 976 if (es->mode == ESM_MODE_CAPTURE) { 977 __apu_set_register(chip, es->apu[3], 5, es->base[3]); 978 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]); 979 } 980 } 981 spin_unlock(&chip->reg_lock); 982 } 983 984 static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es) 985 { 986 spin_lock(&chip->reg_lock); 987 snd_es1968_trigger_apu(chip, es->apu[0], 0); 988 snd_es1968_trigger_apu(chip, es->apu[1], 0); 989 if (es->mode == ESM_MODE_CAPTURE) { 990 snd_es1968_trigger_apu(chip, es->apu[2], 0); 991 snd_es1968_trigger_apu(chip, es->apu[3], 0); 992 } 993 spin_unlock(&chip->reg_lock); 994 } 995 996 /* set the wavecache control reg */ 997 static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es, 998 int channel, u32 addr, int capture) 999 { 1000 u32 tmpval = (addr - 0x10) & 0xFFF8; 1001 1002 if (! capture) { 1003 if (!(es->fmt & ESS_FMT_16BIT)) 1004 tmpval |= 4; /* 8bit */ 1005 if (es->fmt & ESS_FMT_STEREO) 1006 tmpval |= 2; /* stereo */ 1007 } 1008 1009 /* set the wavecache control reg */ 1010 wave_set_register(chip, es->apu[channel] << 3, tmpval); 1011 1012 #ifdef CONFIG_PM 1013 es->wc_map[channel] = tmpval; 1014 #endif 1015 } 1016 1017 1018 static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es, 1019 struct snd_pcm_runtime *runtime) 1020 { 1021 u32 pa; 1022 int high_apu = 0; 1023 int channel, apu; 1024 int i, size; 1025 unsigned long flags; 1026 u32 freq; 1027 1028 size = es->dma_size >> es->wav_shift; 1029 1030 if (es->fmt & ESS_FMT_STEREO) 1031 high_apu++; 1032 1033 for (channel = 0; channel <= high_apu; channel++) { 1034 apu = es->apu[channel]; 1035 1036 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0); 1037 1038 /* Offset to PCMBAR */ 1039 pa = es->memory->buf.addr; 1040 pa -= chip->dma.addr; 1041 pa >>= 1; /* words */ 1042 1043 pa |= 0x00400000; /* System RAM (Bit 22) */ 1044 1045 if (es->fmt & ESS_FMT_STEREO) { 1046 /* Enable stereo */ 1047 if (channel) 1048 pa |= 0x00800000; /* (Bit 23) */ 1049 if (es->fmt & ESS_FMT_16BIT) 1050 pa >>= 1; 1051 } 1052 1053 /* base offset of dma calcs when reading the pointer 1054 on this left one */ 1055 es->base[channel] = pa & 0xFFFF; 1056 1057 for (i = 0; i < 16; i++) 1058 apu_set_register(chip, apu, i, 0x0000); 1059 1060 /* Load the buffer into the wave engine */ 1061 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1062 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1063 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF); 1064 /* setting loop == sample len */ 1065 apu_set_register(chip, apu, 7, size); 1066 1067 /* clear effects/env.. */ 1068 apu_set_register(chip, apu, 8, 0x0000); 1069 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */ 1070 apu_set_register(chip, apu, 9, 0xD000); 1071 1072 /* clear routing stuff */ 1073 apu_set_register(chip, apu, 11, 0x0000); 1074 /* dma on, no envelopes, filter to all 1s) */ 1075 apu_set_register(chip, apu, 0, 0x400F); 1076 1077 if (es->fmt & ESS_FMT_16BIT) 1078 es->apu_mode[channel] = ESM_APU_16BITLINEAR; 1079 else 1080 es->apu_mode[channel] = ESM_APU_8BITLINEAR; 1081 1082 if (es->fmt & ESS_FMT_STEREO) { 1083 /* set panning: left or right */ 1084 /* Check: different panning. On my Canyon 3D Chipset the 1085 Channels are swapped. I don't know, about the output 1086 to the SPDif Link. Perhaps you have to change this 1087 and not the APU Regs 4-5. */ 1088 apu_set_register(chip, apu, 10, 1089 0x8F00 | (channel ? 0 : 0x10)); 1090 es->apu_mode[channel] += 1; /* stereo */ 1091 } else 1092 apu_set_register(chip, apu, 10, 0x8F08); 1093 } 1094 1095 spin_lock_irqsave(&chip->reg_lock, flags); 1096 /* clear WP interrupts */ 1097 outw(1, chip->io_port + 0x04); 1098 /* enable WP ints */ 1099 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1100 spin_unlock_irqrestore(&chip->reg_lock, flags); 1101 1102 freq = runtime->rate; 1103 /* set frequency */ 1104 if (freq > 48000) 1105 freq = 48000; 1106 if (freq < 4000) 1107 freq = 4000; 1108 1109 /* hmmm.. */ 1110 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO)) 1111 freq >>= 1; 1112 1113 freq = snd_es1968_compute_rate(chip, freq); 1114 1115 /* Load the frequency, turn on 6dB */ 1116 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1117 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1118 } 1119 1120 1121 static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel, 1122 unsigned int pa, unsigned int bsize, 1123 int mode, int route) 1124 { 1125 int i, apu = es->apu[channel]; 1126 1127 es->apu_mode[channel] = mode; 1128 1129 /* set the wavecache control reg */ 1130 snd_es1968_program_wavecache(chip, es, channel, pa, 1); 1131 1132 /* Offset to PCMBAR */ 1133 pa -= chip->dma.addr; 1134 pa >>= 1; /* words */ 1135 1136 /* base offset of dma calcs when reading the pointer 1137 on this left one */ 1138 es->base[channel] = pa & 0xFFFF; 1139 pa |= 0x00400000; /* bit 22 -> System RAM */ 1140 1141 /* Begin loading the APU */ 1142 for (i = 0; i < 16; i++) 1143 apu_set_register(chip, apu, i, 0x0000); 1144 1145 /* need to enable subgroups.. and we should probably 1146 have different groups for different /dev/dsps.. */ 1147 apu_set_register(chip, apu, 2, 0x8); 1148 1149 /* Load the buffer into the wave engine */ 1150 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1151 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1152 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF); 1153 apu_set_register(chip, apu, 7, bsize); 1154 /* clear effects/env.. */ 1155 apu_set_register(chip, apu, 8, 0x00F0); 1156 /* amplitude now? sure. why not. */ 1157 apu_set_register(chip, apu, 9, 0x0000); 1158 /* set filter tune, radius, polar pan */ 1159 apu_set_register(chip, apu, 10, 0x8F08); 1160 /* route input */ 1161 apu_set_register(chip, apu, 11, route); 1162 /* dma on, no envelopes, filter to all 1s) */ 1163 apu_set_register(chip, apu, 0, 0x400F); 1164 } 1165 1166 static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es, 1167 struct snd_pcm_runtime *runtime) 1168 { 1169 int size; 1170 u32 freq; 1171 unsigned long flags; 1172 1173 size = es->dma_size >> es->wav_shift; 1174 1175 /* APU assignments: 1176 0 = mono/left SRC 1177 1 = right SRC 1178 2 = mono/left Input Mixer 1179 3 = right Input Mixer 1180 */ 1181 /* data seems to flow from the codec, through an apu into 1182 the 'mixbuf' bit of page, then through the SRC apu 1183 and out to the real 'buffer'. ok. sure. */ 1184 1185 /* input mixer (left/mono) */ 1186 /* parallel in crap, see maestro reg 0xC [8-11] */ 1187 init_capture_apu(chip, es, 2, 1188 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */ 1189 ESM_APU_INPUTMIXER, 0x14); 1190 /* SRC (left/mono); get input from inputing apu */ 1191 init_capture_apu(chip, es, 0, es->memory->buf.addr, size, 1192 ESM_APU_SRCONVERTOR, es->apu[2]); 1193 if (es->fmt & ESS_FMT_STEREO) { 1194 /* input mixer (right) */ 1195 init_capture_apu(chip, es, 3, 1196 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2, 1197 ESM_MIXBUF_SIZE/4, /* in words */ 1198 ESM_APU_INPUTMIXER, 0x15); 1199 /* SRC (right) */ 1200 init_capture_apu(chip, es, 1, 1201 es->memory->buf.addr + size*2, size, 1202 ESM_APU_SRCONVERTOR, es->apu[3]); 1203 } 1204 1205 freq = runtime->rate; 1206 /* Sample Rate conversion APUs don't like 0x10000 for their rate */ 1207 if (freq > 47999) 1208 freq = 47999; 1209 if (freq < 4000) 1210 freq = 4000; 1211 1212 freq = snd_es1968_compute_rate(chip, freq); 1213 1214 /* Load the frequency, turn on 6dB */ 1215 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1216 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1217 1218 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */ 1219 freq = 0x10000; 1220 snd_es1968_apu_set_freq(chip, es->apu[2], freq); 1221 snd_es1968_apu_set_freq(chip, es->apu[3], freq); 1222 1223 spin_lock_irqsave(&chip->reg_lock, flags); 1224 /* clear WP interrupts */ 1225 outw(1, chip->io_port + 0x04); 1226 /* enable WP ints */ 1227 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1228 spin_unlock_irqrestore(&chip->reg_lock, flags); 1229 } 1230 1231 /******************* 1232 * ALSA Interface * 1233 *******************/ 1234 1235 static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream) 1236 { 1237 struct es1968 *chip = snd_pcm_substream_chip(substream); 1238 struct snd_pcm_runtime *runtime = substream->runtime; 1239 struct esschan *es = runtime->private_data; 1240 1241 es->dma_size = snd_pcm_lib_buffer_bytes(substream); 1242 es->frag_size = snd_pcm_lib_period_bytes(substream); 1243 1244 es->wav_shift = 1; /* maestro handles always 16bit */ 1245 es->fmt = 0; 1246 if (snd_pcm_format_width(runtime->format) == 16) 1247 es->fmt |= ESS_FMT_16BIT; 1248 if (runtime->channels > 1) { 1249 es->fmt |= ESS_FMT_STEREO; 1250 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */ 1251 es->wav_shift++; 1252 } 1253 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime); 1254 1255 switch (es->mode) { 1256 case ESM_MODE_PLAY: 1257 snd_es1968_playback_setup(chip, es, runtime); 1258 break; 1259 case ESM_MODE_CAPTURE: 1260 snd_es1968_capture_setup(chip, es, runtime); 1261 break; 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1268 { 1269 struct es1968 *chip = snd_pcm_substream_chip(substream); 1270 struct esschan *es = substream->runtime->private_data; 1271 1272 spin_lock(&chip->substream_lock); 1273 switch (cmd) { 1274 case SNDRV_PCM_TRIGGER_START: 1275 case SNDRV_PCM_TRIGGER_RESUME: 1276 if (es->running) 1277 break; 1278 snd_es1968_bob_inc(chip, es->bob_freq); 1279 es->count = 0; 1280 es->hwptr = 0; 1281 snd_es1968_pcm_start(chip, es); 1282 es->running = 1; 1283 break; 1284 case SNDRV_PCM_TRIGGER_STOP: 1285 case SNDRV_PCM_TRIGGER_SUSPEND: 1286 if (! es->running) 1287 break; 1288 snd_es1968_pcm_stop(chip, es); 1289 es->running = 0; 1290 snd_es1968_bob_dec(chip); 1291 break; 1292 } 1293 spin_unlock(&chip->substream_lock); 1294 return 0; 1295 } 1296 1297 static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream) 1298 { 1299 struct es1968 *chip = snd_pcm_substream_chip(substream); 1300 struct esschan *es = substream->runtime->private_data; 1301 unsigned int ptr; 1302 1303 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1304 1305 return bytes_to_frames(substream->runtime, ptr % es->dma_size); 1306 } 1307 1308 static struct snd_pcm_hardware snd_es1968_playback = { 1309 .info = (SNDRV_PCM_INFO_MMAP | 1310 SNDRV_PCM_INFO_MMAP_VALID | 1311 SNDRV_PCM_INFO_INTERLEAVED | 1312 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1313 /*SNDRV_PCM_INFO_PAUSE |*/ 1314 SNDRV_PCM_INFO_RESUME), 1315 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1316 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1317 .rate_min = 4000, 1318 .rate_max = 48000, 1319 .channels_min = 1, 1320 .channels_max = 2, 1321 .buffer_bytes_max = 65536, 1322 .period_bytes_min = 256, 1323 .period_bytes_max = 65536, 1324 .periods_min = 1, 1325 .periods_max = 1024, 1326 .fifo_size = 0, 1327 }; 1328 1329 static struct snd_pcm_hardware snd_es1968_capture = { 1330 .info = (SNDRV_PCM_INFO_NONINTERLEAVED | 1331 SNDRV_PCM_INFO_MMAP | 1332 SNDRV_PCM_INFO_MMAP_VALID | 1333 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1334 /*SNDRV_PCM_INFO_PAUSE |*/ 1335 SNDRV_PCM_INFO_RESUME), 1336 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE, 1337 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1338 .rate_min = 4000, 1339 .rate_max = 48000, 1340 .channels_min = 1, 1341 .channels_max = 2, 1342 .buffer_bytes_max = 65536, 1343 .period_bytes_min = 256, 1344 .period_bytes_max = 65536, 1345 .periods_min = 1, 1346 .periods_max = 1024, 1347 .fifo_size = 0, 1348 }; 1349 1350 /* ************************* 1351 * DMA memory management * 1352 *************************/ 1353 1354 /* Because the Maestro can only take addresses relative to the PCM base address 1355 register :( */ 1356 1357 static int calc_available_memory_size(struct es1968 *chip) 1358 { 1359 struct list_head *p; 1360 int max_size = 0; 1361 1362 mutex_lock(&chip->memory_mutex); 1363 list_for_each(p, &chip->buf_list) { 1364 struct esm_memory *buf = list_entry(p, struct esm_memory, list); 1365 if (buf->empty && buf->buf.bytes > max_size) 1366 max_size = buf->buf.bytes; 1367 } 1368 mutex_unlock(&chip->memory_mutex); 1369 if (max_size >= 128*1024) 1370 max_size = 127*1024; 1371 return max_size; 1372 } 1373 1374 /* allocate a new memory chunk with the specified size */ 1375 static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size) 1376 { 1377 struct esm_memory *buf; 1378 struct list_head *p; 1379 1380 size = ((size + ESM_MEM_ALIGN - 1) / ESM_MEM_ALIGN) * ESM_MEM_ALIGN; 1381 mutex_lock(&chip->memory_mutex); 1382 list_for_each(p, &chip->buf_list) { 1383 buf = list_entry(p, struct esm_memory, list); 1384 if (buf->empty && buf->buf.bytes >= size) 1385 goto __found; 1386 } 1387 mutex_unlock(&chip->memory_mutex); 1388 return NULL; 1389 1390 __found: 1391 if (buf->buf.bytes > size) { 1392 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1393 if (chunk == NULL) { 1394 mutex_unlock(&chip->memory_mutex); 1395 return NULL; 1396 } 1397 chunk->buf = buf->buf; 1398 chunk->buf.bytes -= size; 1399 chunk->buf.area += size; 1400 chunk->buf.addr += size; 1401 chunk->empty = 1; 1402 buf->buf.bytes = size; 1403 list_add(&chunk->list, &buf->list); 1404 } 1405 buf->empty = 0; 1406 mutex_unlock(&chip->memory_mutex); 1407 return buf; 1408 } 1409 1410 /* free a memory chunk */ 1411 static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf) 1412 { 1413 struct esm_memory *chunk; 1414 1415 mutex_lock(&chip->memory_mutex); 1416 buf->empty = 1; 1417 if (buf->list.prev != &chip->buf_list) { 1418 chunk = list_entry(buf->list.prev, struct esm_memory, list); 1419 if (chunk->empty) { 1420 chunk->buf.bytes += buf->buf.bytes; 1421 list_del(&buf->list); 1422 kfree(buf); 1423 buf = chunk; 1424 } 1425 } 1426 if (buf->list.next != &chip->buf_list) { 1427 chunk = list_entry(buf->list.next, struct esm_memory, list); 1428 if (chunk->empty) { 1429 buf->buf.bytes += chunk->buf.bytes; 1430 list_del(&chunk->list); 1431 kfree(chunk); 1432 } 1433 } 1434 mutex_unlock(&chip->memory_mutex); 1435 } 1436 1437 static void snd_es1968_free_dmabuf(struct es1968 *chip) 1438 { 1439 struct list_head *p; 1440 1441 if (! chip->dma.area) 1442 return; 1443 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci)); 1444 while ((p = chip->buf_list.next) != &chip->buf_list) { 1445 struct esm_memory *chunk = list_entry(p, struct esm_memory, list); 1446 list_del(p); 1447 kfree(chunk); 1448 } 1449 } 1450 1451 static int __devinit 1452 snd_es1968_init_dmabuf(struct es1968 *chip) 1453 { 1454 int err; 1455 struct esm_memory *chunk; 1456 1457 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV; 1458 chip->dma.dev.dev = snd_dma_pci_data(chip->pci); 1459 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) { 1460 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV, 1461 snd_dma_pci_data(chip->pci), 1462 chip->total_bufsize, &chip->dma); 1463 if (err < 0 || ! chip->dma.area) { 1464 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n", 1465 chip->total_bufsize); 1466 return -ENOMEM; 1467 } 1468 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) { 1469 snd_dma_free_pages(&chip->dma); 1470 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n"); 1471 return -ENOMEM; 1472 } 1473 } 1474 1475 INIT_LIST_HEAD(&chip->buf_list); 1476 /* allocate an empty chunk */ 1477 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1478 if (chunk == NULL) { 1479 snd_es1968_free_dmabuf(chip); 1480 return -ENOMEM; 1481 } 1482 memset(chip->dma.area, 0, ESM_MEM_ALIGN); 1483 chunk->buf = chip->dma; 1484 chunk->buf.area += ESM_MEM_ALIGN; 1485 chunk->buf.addr += ESM_MEM_ALIGN; 1486 chunk->buf.bytes -= ESM_MEM_ALIGN; 1487 chunk->empty = 1; 1488 list_add(&chunk->list, &chip->buf_list); 1489 1490 return 0; 1491 } 1492 1493 /* setup the dma_areas */ 1494 /* buffer is extracted from the pre-allocated memory chunk */ 1495 static int snd_es1968_hw_params(struct snd_pcm_substream *substream, 1496 struct snd_pcm_hw_params *hw_params) 1497 { 1498 struct es1968 *chip = snd_pcm_substream_chip(substream); 1499 struct snd_pcm_runtime *runtime = substream->runtime; 1500 struct esschan *chan = runtime->private_data; 1501 int size = params_buffer_bytes(hw_params); 1502 1503 if (chan->memory) { 1504 if (chan->memory->buf.bytes >= size) { 1505 runtime->dma_bytes = size; 1506 return 0; 1507 } 1508 snd_es1968_free_memory(chip, chan->memory); 1509 } 1510 chan->memory = snd_es1968_new_memory(chip, size); 1511 if (chan->memory == NULL) { 1512 // snd_printd("cannot allocate dma buffer: size = %d\n", size); 1513 return -ENOMEM; 1514 } 1515 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf); 1516 return 1; /* area was changed */ 1517 } 1518 1519 /* remove dma areas if allocated */ 1520 static int snd_es1968_hw_free(struct snd_pcm_substream *substream) 1521 { 1522 struct es1968 *chip = snd_pcm_substream_chip(substream); 1523 struct snd_pcm_runtime *runtime = substream->runtime; 1524 struct esschan *chan; 1525 1526 if (runtime->private_data == NULL) 1527 return 0; 1528 chan = runtime->private_data; 1529 if (chan->memory) { 1530 snd_es1968_free_memory(chip, chan->memory); 1531 chan->memory = NULL; 1532 } 1533 return 0; 1534 } 1535 1536 1537 /* 1538 * allocate APU pair 1539 */ 1540 static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type) 1541 { 1542 int apu; 1543 1544 for (apu = 0; apu < NR_APUS; apu += 2) { 1545 if (chip->apu[apu] == ESM_APU_FREE && 1546 chip->apu[apu + 1] == ESM_APU_FREE) { 1547 chip->apu[apu] = chip->apu[apu + 1] = type; 1548 return apu; 1549 } 1550 } 1551 return -EBUSY; 1552 } 1553 1554 /* 1555 * release APU pair 1556 */ 1557 static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu) 1558 { 1559 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE; 1560 } 1561 1562 1563 /****************** 1564 * PCM open/close * 1565 ******************/ 1566 1567 static int snd_es1968_playback_open(struct snd_pcm_substream *substream) 1568 { 1569 struct es1968 *chip = snd_pcm_substream_chip(substream); 1570 struct snd_pcm_runtime *runtime = substream->runtime; 1571 struct esschan *es; 1572 int apu1; 1573 1574 /* search 2 APUs */ 1575 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY); 1576 if (apu1 < 0) 1577 return apu1; 1578 1579 es = kzalloc(sizeof(*es), GFP_KERNEL); 1580 if (!es) { 1581 snd_es1968_free_apu_pair(chip, apu1); 1582 return -ENOMEM; 1583 } 1584 1585 es->apu[0] = apu1; 1586 es->apu[1] = apu1 + 1; 1587 es->apu_mode[0] = 0; 1588 es->apu_mode[1] = 0; 1589 es->running = 0; 1590 es->substream = substream; 1591 es->mode = ESM_MODE_PLAY; 1592 1593 runtime->private_data = es; 1594 runtime->hw = snd_es1968_playback; 1595 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1596 calc_available_memory_size(chip); 1597 #if 0 1598 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1599 1024); 1600 #endif 1601 spin_lock_irq(&chip->substream_lock); 1602 list_add(&es->list, &chip->substream_list); 1603 spin_unlock_irq(&chip->substream_lock); 1604 1605 return 0; 1606 } 1607 1608 static int snd_es1968_capture_open(struct snd_pcm_substream *substream) 1609 { 1610 struct snd_pcm_runtime *runtime = substream->runtime; 1611 struct es1968 *chip = snd_pcm_substream_chip(substream); 1612 struct esschan *es; 1613 int apu1, apu2; 1614 1615 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE); 1616 if (apu1 < 0) 1617 return apu1; 1618 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV); 1619 if (apu2 < 0) { 1620 snd_es1968_free_apu_pair(chip, apu1); 1621 return apu2; 1622 } 1623 1624 es = kzalloc(sizeof(*es), GFP_KERNEL); 1625 if (!es) { 1626 snd_es1968_free_apu_pair(chip, apu1); 1627 snd_es1968_free_apu_pair(chip, apu2); 1628 return -ENOMEM; 1629 } 1630 1631 es->apu[0] = apu1; 1632 es->apu[1] = apu1 + 1; 1633 es->apu[2] = apu2; 1634 es->apu[3] = apu2 + 1; 1635 es->apu_mode[0] = 0; 1636 es->apu_mode[1] = 0; 1637 es->apu_mode[2] = 0; 1638 es->apu_mode[3] = 0; 1639 es->running = 0; 1640 es->substream = substream; 1641 es->mode = ESM_MODE_CAPTURE; 1642 1643 /* get mixbuffer */ 1644 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) { 1645 snd_es1968_free_apu_pair(chip, apu1); 1646 snd_es1968_free_apu_pair(chip, apu2); 1647 kfree(es); 1648 return -ENOMEM; 1649 } 1650 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE); 1651 1652 runtime->private_data = es; 1653 runtime->hw = snd_es1968_capture; 1654 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1655 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */ 1656 #if 0 1657 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1658 1024); 1659 #endif 1660 spin_lock_irq(&chip->substream_lock); 1661 list_add(&es->list, &chip->substream_list); 1662 spin_unlock_irq(&chip->substream_lock); 1663 1664 return 0; 1665 } 1666 1667 static int snd_es1968_playback_close(struct snd_pcm_substream *substream) 1668 { 1669 struct es1968 *chip = snd_pcm_substream_chip(substream); 1670 struct esschan *es; 1671 1672 if (substream->runtime->private_data == NULL) 1673 return 0; 1674 es = substream->runtime->private_data; 1675 spin_lock_irq(&chip->substream_lock); 1676 list_del(&es->list); 1677 spin_unlock_irq(&chip->substream_lock); 1678 snd_es1968_free_apu_pair(chip, es->apu[0]); 1679 kfree(es); 1680 1681 return 0; 1682 } 1683 1684 static int snd_es1968_capture_close(struct snd_pcm_substream *substream) 1685 { 1686 struct es1968 *chip = snd_pcm_substream_chip(substream); 1687 struct esschan *es; 1688 1689 if (substream->runtime->private_data == NULL) 1690 return 0; 1691 es = substream->runtime->private_data; 1692 spin_lock_irq(&chip->substream_lock); 1693 list_del(&es->list); 1694 spin_unlock_irq(&chip->substream_lock); 1695 snd_es1968_free_memory(chip, es->mixbuf); 1696 snd_es1968_free_apu_pair(chip, es->apu[0]); 1697 snd_es1968_free_apu_pair(chip, es->apu[2]); 1698 kfree(es); 1699 1700 return 0; 1701 } 1702 1703 static struct snd_pcm_ops snd_es1968_playback_ops = { 1704 .open = snd_es1968_playback_open, 1705 .close = snd_es1968_playback_close, 1706 .ioctl = snd_pcm_lib_ioctl, 1707 .hw_params = snd_es1968_hw_params, 1708 .hw_free = snd_es1968_hw_free, 1709 .prepare = snd_es1968_pcm_prepare, 1710 .trigger = snd_es1968_pcm_trigger, 1711 .pointer = snd_es1968_pcm_pointer, 1712 }; 1713 1714 static struct snd_pcm_ops snd_es1968_capture_ops = { 1715 .open = snd_es1968_capture_open, 1716 .close = snd_es1968_capture_close, 1717 .ioctl = snd_pcm_lib_ioctl, 1718 .hw_params = snd_es1968_hw_params, 1719 .hw_free = snd_es1968_hw_free, 1720 .prepare = snd_es1968_pcm_prepare, 1721 .trigger = snd_es1968_pcm_trigger, 1722 .pointer = snd_es1968_pcm_pointer, 1723 }; 1724 1725 1726 /* 1727 * measure clock 1728 */ 1729 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */ 1730 1731 static void __devinit es1968_measure_clock(struct es1968 *chip) 1732 { 1733 int i, apu; 1734 unsigned int pa, offset, t; 1735 struct esm_memory *memory; 1736 struct timeval start_time, stop_time; 1737 1738 if (chip->clock == 0) 1739 chip->clock = 48000; /* default clock value */ 1740 1741 /* search 2 APUs (although one apu is enough) */ 1742 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) { 1743 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n"); 1744 return; 1745 } 1746 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) { 1747 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock); 1748 snd_es1968_free_apu_pair(chip, apu); 1749 return; 1750 } 1751 1752 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE); 1753 1754 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8); 1755 1756 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1); 1757 pa |= 0x00400000; /* System RAM (Bit 22) */ 1758 1759 /* initialize apu */ 1760 for (i = 0; i < 16; i++) 1761 apu_set_register(chip, apu, i, 0x0000); 1762 1763 apu_set_register(chip, apu, 0, 0x400f); 1764 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8); 1765 apu_set_register(chip, apu, 5, pa & 0xffff); 1766 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff); 1767 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2); 1768 apu_set_register(chip, apu, 8, 0x0000); 1769 apu_set_register(chip, apu, 9, 0xD000); 1770 apu_set_register(chip, apu, 10, 0x8F08); 1771 apu_set_register(chip, apu, 11, 0x0000); 1772 spin_lock_irq(&chip->reg_lock); 1773 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 1774 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */ 1775 spin_unlock_irq(&chip->reg_lock); 1776 1777 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */ 1778 1779 chip->in_measurement = 1; 1780 chip->measure_apu = apu; 1781 spin_lock_irq(&chip->reg_lock); 1782 snd_es1968_bob_inc(chip, ESM_BOB_FREQ); 1783 __apu_set_register(chip, apu, 5, pa & 0xffff); 1784 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR); 1785 do_gettimeofday(&start_time); 1786 spin_unlock_irq(&chip->reg_lock); 1787 msleep(50); 1788 spin_lock_irq(&chip->reg_lock); 1789 offset = __apu_get_register(chip, apu, 5); 1790 do_gettimeofday(&stop_time); 1791 snd_es1968_trigger_apu(chip, apu, 0); /* stop */ 1792 snd_es1968_bob_dec(chip); 1793 chip->in_measurement = 0; 1794 spin_unlock_irq(&chip->reg_lock); 1795 1796 /* check the current position */ 1797 offset -= (pa & 0xffff); 1798 offset &= 0xfffe; 1799 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2); 1800 1801 t = stop_time.tv_sec - start_time.tv_sec; 1802 t *= 1000000; 1803 if (stop_time.tv_usec < start_time.tv_usec) 1804 t -= start_time.tv_usec - stop_time.tv_usec; 1805 else 1806 t += stop_time.tv_usec - start_time.tv_usec; 1807 if (t == 0) { 1808 snd_printk(KERN_ERR "?? calculation error..\n"); 1809 } else { 1810 offset *= 1000; 1811 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t; 1812 if (offset < 47500 || offset > 48500) { 1813 if (offset >= 40000 && offset <= 50000) 1814 chip->clock = (chip->clock * offset) / 48000; 1815 } 1816 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock); 1817 } 1818 snd_es1968_free_memory(chip, memory); 1819 snd_es1968_free_apu_pair(chip, apu); 1820 } 1821 1822 1823 /* 1824 */ 1825 1826 static void snd_es1968_pcm_free(struct snd_pcm *pcm) 1827 { 1828 struct es1968 *esm = pcm->private_data; 1829 snd_es1968_free_dmabuf(esm); 1830 esm->pcm = NULL; 1831 } 1832 1833 static int __devinit 1834 snd_es1968_pcm(struct es1968 *chip, int device) 1835 { 1836 struct snd_pcm *pcm; 1837 int err; 1838 1839 /* get DMA buffer */ 1840 if ((err = snd_es1968_init_dmabuf(chip)) < 0) 1841 return err; 1842 1843 /* set PCMBAR */ 1844 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 1845 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12); 1846 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12); 1847 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12); 1848 1849 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device, 1850 chip->playback_streams, 1851 chip->capture_streams, &pcm)) < 0) 1852 return err; 1853 1854 pcm->private_data = chip; 1855 pcm->private_free = snd_es1968_pcm_free; 1856 1857 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops); 1858 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops); 1859 1860 pcm->info_flags = 0; 1861 1862 strcpy(pcm->name, "ESS Maestro"); 1863 1864 chip->pcm = pcm; 1865 1866 return 0; 1867 } 1868 1869 /* 1870 * update pointer 1871 */ 1872 static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es) 1873 { 1874 unsigned int hwptr; 1875 unsigned int diff; 1876 struct snd_pcm_substream *subs = es->substream; 1877 1878 if (subs == NULL || !es->running) 1879 return; 1880 1881 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1882 hwptr %= es->dma_size; 1883 1884 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size; 1885 1886 es->hwptr = hwptr; 1887 es->count += diff; 1888 1889 if (es->count > es->frag_size) { 1890 spin_unlock(&chip->substream_lock); 1891 snd_pcm_period_elapsed(subs); 1892 spin_lock(&chip->substream_lock); 1893 es->count %= es->frag_size; 1894 } 1895 } 1896 1897 /* 1898 */ 1899 static void es1968_update_hw_volume(unsigned long private_data) 1900 { 1901 struct es1968 *chip = (struct es1968 *) private_data; 1902 int x, val; 1903 unsigned long flags; 1904 1905 /* Figure out which volume control button was pushed, 1906 based on differences from the default register 1907 values. */ 1908 x = inb(chip->io_port + 0x1c) & 0xee; 1909 /* Reset the volume control registers. */ 1910 outb(0x88, chip->io_port + 0x1c); 1911 outb(0x88, chip->io_port + 0x1d); 1912 outb(0x88, chip->io_port + 0x1e); 1913 outb(0x88, chip->io_port + 0x1f); 1914 1915 if (chip->in_suspend) 1916 return; 1917 1918 if (! chip->master_switch || ! chip->master_volume) 1919 return; 1920 1921 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */ 1922 spin_lock_irqsave(&chip->ac97_lock, flags); 1923 val = chip->ac97->regs[AC97_MASTER]; 1924 switch (x) { 1925 case 0x88: 1926 /* mute */ 1927 val ^= 0x8000; 1928 chip->ac97->regs[AC97_MASTER] = val; 1929 outw(val, chip->io_port + ESM_AC97_DATA); 1930 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1931 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1932 &chip->master_switch->id); 1933 break; 1934 case 0xaa: 1935 /* volume up */ 1936 if ((val & 0x7f) > 0) 1937 val--; 1938 if ((val & 0x7f00) > 0) 1939 val -= 0x0100; 1940 chip->ac97->regs[AC97_MASTER] = val; 1941 outw(val, chip->io_port + ESM_AC97_DATA); 1942 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1943 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1944 &chip->master_volume->id); 1945 break; 1946 case 0x66: 1947 /* volume down */ 1948 if ((val & 0x7f) < 0x1f) 1949 val++; 1950 if ((val & 0x7f00) < 0x1f00) 1951 val += 0x0100; 1952 chip->ac97->regs[AC97_MASTER] = val; 1953 outw(val, chip->io_port + ESM_AC97_DATA); 1954 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1955 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1956 &chip->master_volume->id); 1957 break; 1958 } 1959 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1960 } 1961 1962 /* 1963 * interrupt handler 1964 */ 1965 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1966 { 1967 struct es1968 *chip = dev_id; 1968 u32 event; 1969 1970 if (!(event = inb(chip->io_port + 0x1A))) 1971 return IRQ_NONE; 1972 1973 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4); 1974 1975 if (event & ESM_HWVOL_IRQ) 1976 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */ 1977 1978 /* else ack 'em all, i imagine */ 1979 outb(0xFF, chip->io_port + 0x1A); 1980 1981 if ((event & ESM_MPU401_IRQ) && chip->rmidi) { 1982 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs); 1983 } 1984 1985 if (event & ESM_SOUND_IRQ) { 1986 struct list_head *p; 1987 spin_lock(&chip->substream_lock); 1988 list_for_each(p, &chip->substream_list) { 1989 struct esschan *es = list_entry(p, struct esschan, list); 1990 if (es->running) 1991 snd_es1968_update_pcm(chip, es); 1992 } 1993 spin_unlock(&chip->substream_lock); 1994 if (chip->in_measurement) { 1995 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5); 1996 if (curp < chip->measure_lastpos) 1997 chip->measure_count++; 1998 chip->measure_lastpos = curp; 1999 } 2000 } 2001 2002 return IRQ_HANDLED; 2003 } 2004 2005 /* 2006 * Mixer stuff 2007 */ 2008 2009 static int __devinit 2010 snd_es1968_mixer(struct es1968 *chip) 2011 { 2012 struct snd_ac97_bus *pbus; 2013 struct snd_ac97_template ac97; 2014 struct snd_ctl_elem_id id; 2015 int err; 2016 static struct snd_ac97_bus_ops ops = { 2017 .write = snd_es1968_ac97_write, 2018 .read = snd_es1968_ac97_read, 2019 }; 2020 2021 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) 2022 return err; 2023 pbus->no_vra = 1; /* ES1968 doesn't need VRA */ 2024 2025 memset(&ac97, 0, sizeof(ac97)); 2026 ac97.private_data = chip; 2027 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0) 2028 return err; 2029 2030 /* attach master switch / volumes for h/w volume control */ 2031 memset(&id, 0, sizeof(id)); 2032 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2033 strcpy(id.name, "Master Playback Switch"); 2034 chip->master_switch = snd_ctl_find_id(chip->card, &id); 2035 memset(&id, 0, sizeof(id)); 2036 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2037 strcpy(id.name, "Master Playback Volume"); 2038 chip->master_volume = snd_ctl_find_id(chip->card, &id); 2039 2040 return 0; 2041 } 2042 2043 /* 2044 * reset ac97 codec 2045 */ 2046 2047 static void snd_es1968_ac97_reset(struct es1968 *chip) 2048 { 2049 unsigned long ioaddr = chip->io_port; 2050 2051 unsigned short save_ringbus_a; 2052 unsigned short save_68; 2053 unsigned short w; 2054 unsigned int vend; 2055 2056 /* save configuration */ 2057 save_ringbus_a = inw(ioaddr + 0x36); 2058 2059 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */ 2060 /* set command/status address i/o to 1st codec */ 2061 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2062 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2063 2064 /* disable ac link */ 2065 outw(0x0000, ioaddr + 0x36); 2066 save_68 = inw(ioaddr + 0x68); 2067 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */ 2068 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2069 if (w & 1) 2070 save_68 |= 0x10; 2071 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */ 2072 outw(0x0001, ioaddr + 0x68); /* gpio write */ 2073 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */ 2074 udelay(20); 2075 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */ 2076 msleep(20); 2077 2078 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */ 2079 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38); 2080 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a); 2081 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c); 2082 2083 /* now the second codec */ 2084 /* disable ac link */ 2085 outw(0x0000, ioaddr + 0x36); 2086 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */ 2087 save_68 = inw(ioaddr + 0x68); 2088 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */ 2089 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */ 2090 udelay(20); 2091 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */ 2092 msleep(500); 2093 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); 2094 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2095 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2096 2097 #if 0 /* the loop here needs to be much better if we want it.. */ 2098 snd_printk(KERN_INFO "trying software reset\n"); 2099 /* try and do a software reset */ 2100 outb(0x80 | 0x7c, ioaddr + 0x30); 2101 for (w = 0;; w++) { 2102 if ((inw(ioaddr + 0x30) & 1) == 0) { 2103 if (inb(ioaddr + 0x32) != 0) 2104 break; 2105 2106 outb(0x80 | 0x7d, ioaddr + 0x30); 2107 if (((inw(ioaddr + 0x30) & 1) == 0) 2108 && (inb(ioaddr + 0x32) != 0)) 2109 break; 2110 outb(0x80 | 0x7f, ioaddr + 0x30); 2111 if (((inw(ioaddr + 0x30) & 1) == 0) 2112 && (inb(ioaddr + 0x32) != 0)) 2113 break; 2114 } 2115 2116 if (w > 10000) { 2117 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */ 2118 msleep(500); /* oh my.. */ 2119 outb(inb(ioaddr + 0x37) & ~0x08, 2120 ioaddr + 0x37); 2121 udelay(1); 2122 outw(0x80, ioaddr + 0x30); 2123 for (w = 0; w < 10000; w++) { 2124 if ((inw(ioaddr + 0x30) & 1) == 0) 2125 break; 2126 } 2127 } 2128 } 2129 #endif 2130 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) { 2131 /* turn on external amp? */ 2132 outw(0xf9ff, ioaddr + 0x64); 2133 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68); 2134 outw(0x0209, ioaddr + 0x60); 2135 } 2136 2137 /* restore.. */ 2138 outw(save_ringbus_a, ioaddr + 0x36); 2139 2140 /* Turn on the 978 docking chip. 2141 First frob the "master output enable" bit, 2142 then set most of the playback volume control registers to max. */ 2143 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0); 2144 outb(0xff, ioaddr+0xc3); 2145 outb(0xff, ioaddr+0xc4); 2146 outb(0xff, ioaddr+0xc6); 2147 outb(0xff, ioaddr+0xc8); 2148 outb(0x3f, ioaddr+0xcf); 2149 outb(0x3f, ioaddr+0xd0); 2150 } 2151 2152 static void snd_es1968_reset(struct es1968 *chip) 2153 { 2154 /* Reset */ 2155 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND, 2156 chip->io_port + ESM_PORT_HOST_IRQ); 2157 udelay(10); 2158 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ); 2159 udelay(10); 2160 } 2161 2162 /* 2163 * power management 2164 */ 2165 static void snd_es1968_set_acpi(struct es1968 *chip, int state) 2166 { 2167 u16 active_mask = acpi_state_mask[state]; 2168 2169 pci_set_power_state(chip->pci, state); 2170 /* make sure the units we care about are on 2171 XXX we might want to do this before state flipping? */ 2172 pci_write_config_word(chip->pci, 0x54, ~ active_mask); 2173 pci_write_config_word(chip->pci, 0x56, ~ active_mask); 2174 } 2175 2176 2177 /* 2178 * initialize maestro chip 2179 */ 2180 static void snd_es1968_chip_init(struct es1968 *chip) 2181 { 2182 struct pci_dev *pci = chip->pci; 2183 int i; 2184 unsigned long iobase = chip->io_port; 2185 u16 w; 2186 u32 n; 2187 2188 /* We used to muck around with pci config space that 2189 * we had no business messing with. We don't know enough 2190 * about the machine to know which DMA mode is appropriate, 2191 * etc. We were guessing wrong on some machines and making 2192 * them unhappy. We now trust in the BIOS to do things right, 2193 * which almost certainly means a new host of problems will 2194 * arise with broken BIOS implementations. screw 'em. 2195 * We're already intolerant of machines that don't assign 2196 * IRQs. 2197 */ 2198 2199 /* do config work at full power */ 2200 snd_es1968_set_acpi(chip, ACPI_D0); 2201 2202 /* Config Reg A */ 2203 pci_read_config_word(pci, ESM_CONFIG_A, &w); 2204 2205 w &= ~DMA_CLEAR; /* Clear DMA bits */ 2206 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */ 2207 w &= ~SAFEGUARD; /* Safeguard off */ 2208 w |= POST_WRITE; /* Posted write */ 2209 w |= PCI_TIMING; /* PCI timing on */ 2210 /* XXX huh? claims to be reserved.. */ 2211 w &= ~SWAP_LR; /* swap left/right 2212 seems to only have effect on SB 2213 Emulation */ 2214 w &= ~SUBTR_DECODE; /* Subtractive decode off */ 2215 2216 pci_write_config_word(pci, ESM_CONFIG_A, w); 2217 2218 /* Config Reg B */ 2219 2220 pci_read_config_word(pci, ESM_CONFIG_B, &w); 2221 2222 w &= ~(1 << 15); /* Turn off internal clock multiplier */ 2223 /* XXX how do we know which to use? */ 2224 w &= ~(1 << 14); /* External clock */ 2225 2226 w &= ~SPDIF_CONFB; /* disable S/PDIF output */ 2227 w |= HWV_CONFB; /* HWV on */ 2228 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */ 2229 w &= ~GPIO_CONFB; /* GPIO 4:5 */ 2230 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */ 2231 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */ 2232 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */ 2233 w &= ~(1 << 1); /* reserved, always write 0 */ 2234 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */ 2235 2236 pci_write_config_word(pci, ESM_CONFIG_B, w); 2237 2238 /* DDMA off */ 2239 2240 pci_read_config_word(pci, ESM_DDMA, &w); 2241 w &= ~(1 << 0); 2242 pci_write_config_word(pci, ESM_DDMA, w); 2243 2244 /* 2245 * Legacy mode 2246 */ 2247 2248 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w); 2249 2250 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */ 2251 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */ 2252 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */ 2253 2254 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w); 2255 2256 /* Set up 978 docking control chip. */ 2257 pci_read_config_word(pci, 0x58, &w); 2258 w|=1<<2; /* Enable 978. */ 2259 w|=1<<3; /* Turn on 978 hardware volume control. */ 2260 w&=~(1<<11); /* Turn on 978 mixer volume control. */ 2261 pci_write_config_word(pci, 0x58, w); 2262 2263 /* Sound Reset */ 2264 2265 snd_es1968_reset(chip); 2266 2267 /* 2268 * Ring Bus Setup 2269 */ 2270 2271 /* setup usual 0x34 stuff.. 0x36 may be chip specific */ 2272 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */ 2273 udelay(20); 2274 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */ 2275 udelay(20); 2276 2277 /* 2278 * Reset the CODEC 2279 */ 2280 2281 snd_es1968_ac97_reset(chip); 2282 2283 /* Ring Bus Control B */ 2284 2285 n = inl(iobase + ESM_RING_BUS_CONTR_B); 2286 n &= ~RINGB_EN_SPDIF; /* SPDIF off */ 2287 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */ 2288 outl(n, iobase + ESM_RING_BUS_CONTR_B); 2289 2290 /* Set hardware volume control registers to midpoints. 2291 We can tell which button was pushed based on how they change. */ 2292 outb(0x88, iobase+0x1c); 2293 outb(0x88, iobase+0x1d); 2294 outb(0x88, iobase+0x1e); 2295 outb(0x88, iobase+0x1f); 2296 2297 /* it appears some maestros (dell 7500) only work if these are set, 2298 regardless of wether we use the assp or not. */ 2299 2300 outb(0, iobase + ASSP_CONTROL_B); 2301 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */ 2302 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */ 2303 2304 /* 2305 * set up wavecache 2306 */ 2307 for (i = 0; i < 16; i++) { 2308 /* Write 0 into the buffer area 0x1E0->1EF */ 2309 outw(0x01E0 + i, iobase + WC_INDEX); 2310 outw(0x0000, iobase + WC_DATA); 2311 2312 /* The 1.10 test program seem to write 0 into the buffer area 2313 * 0x1D0-0x1DF too.*/ 2314 outw(0x01D0 + i, iobase + WC_INDEX); 2315 outw(0x0000, iobase + WC_DATA); 2316 } 2317 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2318 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00)); 2319 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2320 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100); 2321 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2322 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200); 2323 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2324 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400); 2325 2326 2327 maestro_write(chip, IDR2_CRAM_DATA, 0x0000); 2328 /* Now back to the DirectSound stuff */ 2329 /* audio serial configuration.. ? */ 2330 maestro_write(chip, 0x08, 0xB004); 2331 maestro_write(chip, 0x09, 0x001B); 2332 maestro_write(chip, 0x0A, 0x8000); 2333 maestro_write(chip, 0x0B, 0x3F37); 2334 maestro_write(chip, 0x0C, 0x0098); 2335 2336 /* parallel in, has something to do with recording :) */ 2337 maestro_write(chip, 0x0C, 2338 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000); 2339 /* parallel out */ 2340 maestro_write(chip, 0x0C, 2341 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500); 2342 2343 maestro_write(chip, 0x0D, 0x7632); 2344 2345 /* Wave cache control on - test off, sg off, 2346 enable, enable extra chans 1Mb */ 2347 2348 w = inw(iobase + WC_CONTROL); 2349 2350 w &= ~0xFA00; /* Seems to be reserved? I don't know */ 2351 w |= 0xA000; /* reserved... I don't know */ 2352 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable 2353 Seems to crash the Computer if enabled... */ 2354 w |= 0x0100; /* Wave Cache Operation Enabled */ 2355 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */ 2356 w &= ~0x0060; /* Clear Wavtable Size */ 2357 w |= 0x0020; /* Wavetable Size : 1MB */ 2358 /* Bit 4 is reserved */ 2359 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */ 2360 /* Bit 1 is reserved */ 2361 w &= ~0x0001; /* Test Mode off */ 2362 2363 outw(w, iobase + WC_CONTROL); 2364 2365 /* Now clear the APU control ram */ 2366 for (i = 0; i < NR_APUS; i++) { 2367 for (w = 0; w < NR_APU_REGS; w++) 2368 apu_set_register(chip, i, w, 0); 2369 2370 } 2371 } 2372 2373 /* Enable IRQ's */ 2374 static void snd_es1968_start_irq(struct es1968 *chip) 2375 { 2376 unsigned short w; 2377 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME; 2378 if (chip->rmidi) 2379 w |= ESM_HIRQ_MPU401; 2380 outw(w, chip->io_port + ESM_PORT_HOST_IRQ); 2381 } 2382 2383 #ifdef CONFIG_PM 2384 /* 2385 * PM support 2386 */ 2387 static int es1968_suspend(struct pci_dev *pci, pm_message_t state) 2388 { 2389 struct snd_card *card = pci_get_drvdata(pci); 2390 struct es1968 *chip = card->private_data; 2391 2392 if (! chip->do_pm) 2393 return 0; 2394 2395 chip->in_suspend = 1; 2396 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2397 snd_pcm_suspend_all(chip->pcm); 2398 snd_ac97_suspend(chip->ac97); 2399 snd_es1968_bob_stop(chip); 2400 snd_es1968_set_acpi(chip, ACPI_D3); 2401 pci_disable_device(pci); 2402 pci_save_state(pci); 2403 return 0; 2404 } 2405 2406 static int es1968_resume(struct pci_dev *pci) 2407 { 2408 struct snd_card *card = pci_get_drvdata(pci); 2409 struct es1968 *chip = card->private_data; 2410 struct list_head *p; 2411 2412 if (! chip->do_pm) 2413 return 0; 2414 2415 /* restore all our config */ 2416 pci_restore_state(pci); 2417 pci_enable_device(pci); 2418 pci_set_master(pci); 2419 snd_es1968_chip_init(chip); 2420 2421 /* need to restore the base pointers.. */ 2422 if (chip->dma.addr) { 2423 /* set PCMBAR */ 2424 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 2425 } 2426 2427 snd_es1968_start_irq(chip); 2428 2429 /* restore ac97 state */ 2430 snd_ac97_resume(chip->ac97); 2431 2432 list_for_each(p, &chip->substream_list) { 2433 struct esschan *es = list_entry(p, struct esschan, list); 2434 switch (es->mode) { 2435 case ESM_MODE_PLAY: 2436 snd_es1968_playback_setup(chip, es, es->substream->runtime); 2437 break; 2438 case ESM_MODE_CAPTURE: 2439 snd_es1968_capture_setup(chip, es, es->substream->runtime); 2440 break; 2441 } 2442 } 2443 2444 /* start timer again */ 2445 if (chip->bobclient) 2446 snd_es1968_bob_start(chip); 2447 2448 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2449 chip->in_suspend = 0; 2450 return 0; 2451 } 2452 #endif /* CONFIG_PM */ 2453 2454 #ifdef SUPPORT_JOYSTICK 2455 #define JOYSTICK_ADDR 0x200 2456 static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev) 2457 { 2458 struct gameport *gp; 2459 struct resource *r; 2460 u16 val; 2461 2462 if (!joystick[dev]) 2463 return -ENODEV; 2464 2465 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport"); 2466 if (!r) 2467 return -EBUSY; 2468 2469 chip->gameport = gp = gameport_allocate_port(); 2470 if (!gp) { 2471 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n"); 2472 release_and_free_resource(r); 2473 return -ENOMEM; 2474 } 2475 2476 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val); 2477 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04); 2478 2479 gameport_set_name(gp, "ES1968 Gameport"); 2480 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2481 gameport_set_dev_parent(gp, &chip->pci->dev); 2482 gp->io = JOYSTICK_ADDR; 2483 gameport_set_port_data(gp, r); 2484 2485 gameport_register_port(gp); 2486 2487 return 0; 2488 } 2489 2490 static void snd_es1968_free_gameport(struct es1968 *chip) 2491 { 2492 if (chip->gameport) { 2493 struct resource *r = gameport_get_port_data(chip->gameport); 2494 2495 gameport_unregister_port(chip->gameport); 2496 chip->gameport = NULL; 2497 2498 release_and_free_resource(r); 2499 } 2500 } 2501 #else 2502 static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; } 2503 static inline void snd_es1968_free_gameport(struct es1968 *chip) { } 2504 #endif 2505 2506 static int snd_es1968_free(struct es1968 *chip) 2507 { 2508 if (chip->io_port) { 2509 synchronize_irq(chip->irq); 2510 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 2511 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */ 2512 } 2513 2514 if (chip->irq >= 0) 2515 free_irq(chip->irq, (void *)chip); 2516 snd_es1968_free_gameport(chip); 2517 snd_es1968_set_acpi(chip, ACPI_D3); 2518 chip->master_switch = NULL; 2519 chip->master_volume = NULL; 2520 pci_release_regions(chip->pci); 2521 pci_disable_device(chip->pci); 2522 kfree(chip); 2523 return 0; 2524 } 2525 2526 static int snd_es1968_dev_free(struct snd_device *device) 2527 { 2528 struct es1968 *chip = device->device_data; 2529 return snd_es1968_free(chip); 2530 } 2531 2532 struct ess_device_list { 2533 unsigned short type; /* chip type */ 2534 unsigned short vendor; /* subsystem vendor id */ 2535 }; 2536 2537 static struct ess_device_list pm_whitelist[] __devinitdata = { 2538 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */ 2539 { TYPE_MAESTRO2E, 0x1028 }, 2540 { TYPE_MAESTRO2E, 0x103c }, 2541 { TYPE_MAESTRO2E, 0x1179 }, 2542 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */ 2543 { TYPE_MAESTRO2E, 0x1558 }, 2544 }; 2545 2546 static struct ess_device_list mpu_blacklist[] __devinitdata = { 2547 { TYPE_MAESTRO2, 0x125d }, 2548 }; 2549 2550 static int __devinit snd_es1968_create(struct snd_card *card, 2551 struct pci_dev *pci, 2552 int total_bufsize, 2553 int play_streams, 2554 int capt_streams, 2555 int chip_type, 2556 int do_pm, 2557 struct es1968 **chip_ret) 2558 { 2559 static struct snd_device_ops ops = { 2560 .dev_free = snd_es1968_dev_free, 2561 }; 2562 struct es1968 *chip; 2563 int i, err; 2564 2565 *chip_ret = NULL; 2566 2567 /* enable PCI device */ 2568 if ((err = pci_enable_device(pci)) < 0) 2569 return err; 2570 /* check, if we can restrict PCI DMA transfers to 28 bits */ 2571 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 || 2572 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) { 2573 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n"); 2574 pci_disable_device(pci); 2575 return -ENXIO; 2576 } 2577 2578 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2579 if (! chip) { 2580 pci_disable_device(pci); 2581 return -ENOMEM; 2582 } 2583 2584 /* Set Vars */ 2585 chip->type = chip_type; 2586 spin_lock_init(&chip->reg_lock); 2587 spin_lock_init(&chip->substream_lock); 2588 INIT_LIST_HEAD(&chip->buf_list); 2589 INIT_LIST_HEAD(&chip->substream_list); 2590 spin_lock_init(&chip->ac97_lock); 2591 mutex_init(&chip->memory_mutex); 2592 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip); 2593 chip->card = card; 2594 chip->pci = pci; 2595 chip->irq = -1; 2596 chip->total_bufsize = total_bufsize; /* in bytes */ 2597 chip->playback_streams = play_streams; 2598 chip->capture_streams = capt_streams; 2599 2600 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) { 2601 kfree(chip); 2602 pci_disable_device(pci); 2603 return err; 2604 } 2605 chip->io_port = pci_resource_start(pci, 0); 2606 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_DISABLED|IRQF_SHARED, 2607 "ESS Maestro", (void*)chip)) { 2608 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2609 snd_es1968_free(chip); 2610 return -EBUSY; 2611 } 2612 chip->irq = pci->irq; 2613 2614 /* Clear Maestro_map */ 2615 for (i = 0; i < 32; i++) 2616 chip->maestro_map[i] = 0; 2617 2618 /* Clear Apu Map */ 2619 for (i = 0; i < NR_APUS; i++) 2620 chip->apu[i] = ESM_APU_FREE; 2621 2622 /* just to be sure */ 2623 pci_set_master(pci); 2624 2625 if (do_pm > 1) { 2626 /* disable power-management if not on the whitelist */ 2627 unsigned short vend; 2628 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2629 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) { 2630 if (chip->type == pm_whitelist[i].type && 2631 vend == pm_whitelist[i].vendor) { 2632 do_pm = 1; 2633 break; 2634 } 2635 } 2636 if (do_pm > 1) { 2637 /* not matched; disabling pm */ 2638 printk(KERN_INFO "es1968: not attempting power management.\n"); 2639 do_pm = 0; 2640 } 2641 } 2642 chip->do_pm = do_pm; 2643 2644 snd_es1968_chip_init(chip); 2645 2646 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2647 snd_es1968_free(chip); 2648 return err; 2649 } 2650 2651 snd_card_set_dev(card, &pci->dev); 2652 2653 *chip_ret = chip; 2654 2655 return 0; 2656 } 2657 2658 2659 /* 2660 */ 2661 static int __devinit snd_es1968_probe(struct pci_dev *pci, 2662 const struct pci_device_id *pci_id) 2663 { 2664 static int dev; 2665 struct snd_card *card; 2666 struct es1968 *chip; 2667 unsigned int i; 2668 int err; 2669 2670 if (dev >= SNDRV_CARDS) 2671 return -ENODEV; 2672 if (!enable[dev]) { 2673 dev++; 2674 return -ENOENT; 2675 } 2676 2677 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2678 if (!card) 2679 return -ENOMEM; 2680 2681 if (total_bufsize[dev] < 128) 2682 total_bufsize[dev] = 128; 2683 if (total_bufsize[dev] > 4096) 2684 total_bufsize[dev] = 4096; 2685 if ((err = snd_es1968_create(card, pci, 2686 total_bufsize[dev] * 1024, /* in bytes */ 2687 pcm_substreams_p[dev], 2688 pcm_substreams_c[dev], 2689 pci_id->driver_data, 2690 use_pm[dev], 2691 &chip)) < 0) { 2692 snd_card_free(card); 2693 return err; 2694 } 2695 card->private_data = chip; 2696 2697 switch (chip->type) { 2698 case TYPE_MAESTRO2E: 2699 strcpy(card->driver, "ES1978"); 2700 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)"); 2701 break; 2702 case TYPE_MAESTRO2: 2703 strcpy(card->driver, "ES1968"); 2704 strcpy(card->shortname, "ESS ES1968 (Maestro 2)"); 2705 break; 2706 case TYPE_MAESTRO: 2707 strcpy(card->driver, "ESM1"); 2708 strcpy(card->shortname, "ESS Maestro 1"); 2709 break; 2710 } 2711 2712 if ((err = snd_es1968_pcm(chip, 0)) < 0) { 2713 snd_card_free(card); 2714 return err; 2715 } 2716 2717 if ((err = snd_es1968_mixer(chip)) < 0) { 2718 snd_card_free(card); 2719 return err; 2720 } 2721 2722 if (enable_mpu[dev] == 2) { 2723 /* check the black list */ 2724 unsigned short vend; 2725 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2726 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) { 2727 if (chip->type == mpu_blacklist[i].type && 2728 vend == mpu_blacklist[i].vendor) { 2729 enable_mpu[dev] = 0; 2730 break; 2731 } 2732 } 2733 } 2734 if (enable_mpu[dev]) { 2735 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401, 2736 chip->io_port + ESM_MPU401_PORT, 2737 MPU401_INFO_INTEGRATED, 2738 chip->irq, 0, &chip->rmidi)) < 0) { 2739 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n"); 2740 } 2741 } 2742 2743 snd_es1968_create_gameport(chip, dev); 2744 2745 snd_es1968_start_irq(chip); 2746 2747 chip->clock = clock[dev]; 2748 if (! chip->clock) 2749 es1968_measure_clock(chip); 2750 2751 sprintf(card->longname, "%s at 0x%lx, irq %i", 2752 card->shortname, chip->io_port, chip->irq); 2753 2754 if ((err = snd_card_register(card)) < 0) { 2755 snd_card_free(card); 2756 return err; 2757 } 2758 pci_set_drvdata(pci, card); 2759 dev++; 2760 return 0; 2761 } 2762 2763 static void __devexit snd_es1968_remove(struct pci_dev *pci) 2764 { 2765 snd_card_free(pci_get_drvdata(pci)); 2766 pci_set_drvdata(pci, NULL); 2767 } 2768 2769 static struct pci_driver driver = { 2770 .name = "ES1968 (ESS Maestro)", 2771 .id_table = snd_es1968_ids, 2772 .probe = snd_es1968_probe, 2773 .remove = __devexit_p(snd_es1968_remove), 2774 #ifdef CONFIG_PM 2775 .suspend = es1968_suspend, 2776 .resume = es1968_resume, 2777 #endif 2778 }; 2779 2780 static int __init alsa_card_es1968_init(void) 2781 { 2782 return pci_register_driver(&driver); 2783 } 2784 2785 static void __exit alsa_card_es1968_exit(void) 2786 { 2787 pci_unregister_driver(&driver); 2788 } 2789 2790 module_init(alsa_card_es1968_init) 2791 module_exit(alsa_card_es1968_exit) 2792