1 /* 2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99) 3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>. 4 * Takashi Iwai <tiwai@suse.de> 5 * 6 * Most of the driver code comes from Zach Brown(zab@redhat.com) 7 * Alan Cox OSS Driver 8 * Rewritted from card-es1938.c source. 9 * 10 * TODO: 11 * Perhaps Synth 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 * 27 * 28 * Notes from Zach Brown about the driver code 29 * 30 * Hardware Description 31 * 32 * A working Maestro setup contains the Maestro chip wired to a 33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the 34 * Wavecache. The APUs can be though of as virtual audio routing 35 * channels. They can take data from a number of sources and perform 36 * basic encodings of the data. The wavecache is a storehouse for 37 * PCM data. Typically it deals with PCI and interracts with the 38 * APUs. The ASSP is a wacky DSP like device that ESS is loth 39 * to release docs on. Thankfully it isn't required on the Maestro 40 * until you start doing insane things like FM emulation and surround 41 * encoding. The codecs are almost always AC-97 compliant codecs, 42 * but it appears that early Maestros may have had PT101 (an ESS 43 * part?) wired to them. The only real difference in the Maestro 44 * families is external goop like docking capability, memory for 45 * the ASSP, and initialization differences. 46 * 47 * Driver Operation 48 * 49 * We only drive the APU/Wavecache as typical DACs and drive the 50 * mixers in the codecs. There are 64 APUs. We assign 6 to each 51 * /dev/dsp? device. 2 channels for output, and 4 channels for 52 * input. 53 * 54 * Each APU can do a number of things, but we only really use 55 * 3 basic functions. For playback we use them to convert PCM 56 * data fetched over PCI by the wavecahche into analog data that 57 * is handed to the codec. One APU for mono, and a pair for stereo. 58 * When in stereo, the combination of smarts in the APU and Wavecache 59 * decide which wavecache gets the left or right channel. 60 * 61 * For record we still use the old overly mono system. For each in 62 * coming channel the data comes in from the codec, through a 'input' 63 * APU, through another rate converter APU, and then into memory via 64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in 65 * software. The pass between the 2 APUs is supposedly what requires us 66 * to have a 512 byte buffer sitting around in wavecache/memory. 67 * 68 * The wavecache makes our life even more fun. First off, it can 69 * only address the first 28 bits of PCI address space, making it 70 * useless on quite a few architectures. Secondly, its insane. 71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length. 72 * But that doesn't really work. You can only use 1 region. So all our 73 * allocations have to be in 4meg of each other. Booo. Hiss. 74 * So we have a module parameter, dsps_order, that is the order of 75 * the number of dsps to provide. All their buffer space is allocated 76 * on open time. The sonicvibes OSS routines we inherited really want 77 * power of 2 buffers, so we have all those next to each other, then 78 * 512 byte regions for the recording wavecaches. This ends up 79 * wasting quite a bit of memory. The only fixes I can see would be 80 * getting a kernel allocator that could work in zones, or figuring out 81 * just how to coerce the WP into doing what we want. 82 * 83 * The indirection of the various registers means we have to spinlock 84 * nearly all register accesses. We have the main register indirection 85 * like the wave cache, maestro registers, etc. Then we have beasts 86 * like the APU interface that is indirect registers gotten at through 87 * the main maestro indirection. Ouch. We spinlock around the actual 88 * ports on a per card basis. This means spinlock activity at each IO 89 * operation, but the only IO operation clusters are in non critical 90 * paths and it makes the code far easier to follow. Interrupts are 91 * blocked while holding the locks because the int handler has to 92 * get at some of them :(. The mixer interface doesn't, however. 93 * We also have an OSS state lock that is thrown around in a few 94 * places. 95 */ 96 97 #include <asm/io.h> 98 #include <linux/delay.h> 99 #include <linux/interrupt.h> 100 #include <linux/init.h> 101 #include <linux/pci.h> 102 #include <linux/dma-mapping.h> 103 #include <linux/slab.h> 104 #include <linux/gameport.h> 105 #include <linux/module.h> 106 #include <linux/mutex.h> 107 #include <linux/input.h> 108 109 #include <sound/core.h> 110 #include <sound/pcm.h> 111 #include <sound/mpu401.h> 112 #include <sound/ac97_codec.h> 113 #include <sound/initval.h> 114 115 #ifdef CONFIG_SND_ES1968_RADIO 116 #include <sound/tea575x-tuner.h> 117 #endif 118 119 #define CARD_NAME "ESS Maestro1/2" 120 #define DRIVER_NAME "ES1968" 121 122 MODULE_DESCRIPTION("ESS Maestro"); 123 MODULE_LICENSE("GPL"); 124 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e}," 125 "{ESS,Maestro 2}," 126 "{ESS,Maestro 1}," 127 "{TerraTec,DMX}}"); 128 129 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 130 #define SUPPORT_JOYSTICK 1 131 #endif 132 133 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */ 134 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 135 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 136 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 }; 137 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 }; 138 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 }; 139 static int clock[SNDRV_CARDS]; 140 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 141 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 142 #ifdef SUPPORT_JOYSTICK 143 static bool joystick[SNDRV_CARDS]; 144 #endif 145 static int radio_nr[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; 146 147 module_param_array(index, int, NULL, 0444); 148 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 149 module_param_array(id, charp, NULL, 0444); 150 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 151 module_param_array(enable, bool, NULL, 0444); 152 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard."); 153 module_param_array(total_bufsize, int, NULL, 0444); 154 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB."); 155 module_param_array(pcm_substreams_p, int, NULL, 0444); 156 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard."); 157 module_param_array(pcm_substreams_c, int, NULL, 0444); 158 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard."); 159 module_param_array(clock, int, NULL, 0444); 160 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)"); 161 module_param_array(use_pm, int, NULL, 0444); 162 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)"); 163 module_param_array(enable_mpu, int, NULL, 0444); 164 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)"); 165 #ifdef SUPPORT_JOYSTICK 166 module_param_array(joystick, bool, NULL, 0444); 167 MODULE_PARM_DESC(joystick, "Enable joystick."); 168 #endif 169 module_param_array(radio_nr, int, NULL, 0444); 170 MODULE_PARM_DESC(radio_nr, "Radio device numbers"); 171 172 173 174 #define NR_APUS 64 175 #define NR_APU_REGS 16 176 177 /* NEC Versas ? */ 178 #define NEC_VERSA_SUBID1 0x80581033 179 #define NEC_VERSA_SUBID2 0x803c1033 180 181 /* Mode Flags */ 182 #define ESS_FMT_STEREO 0x01 183 #define ESS_FMT_16BIT 0x02 184 185 #define DAC_RUNNING 1 186 #define ADC_RUNNING 2 187 188 /* Values for the ESM_LEGACY_AUDIO_CONTROL */ 189 190 #define ESS_DISABLE_AUDIO 0x8000 191 #define ESS_ENABLE_SERIAL_IRQ 0x4000 192 #define IO_ADRESS_ALIAS 0x0020 193 #define MPU401_IRQ_ENABLE 0x0010 194 #define MPU401_IO_ENABLE 0x0008 195 #define GAME_IO_ENABLE 0x0004 196 #define FM_IO_ENABLE 0x0002 197 #define SB_IO_ENABLE 0x0001 198 199 /* Values for the ESM_CONFIG_A */ 200 201 #define PIC_SNOOP1 0x4000 202 #define PIC_SNOOP2 0x2000 203 #define SAFEGUARD 0x0800 204 #define DMA_CLEAR 0x0700 205 #define DMA_DDMA 0x0000 206 #define DMA_TDMA 0x0100 207 #define DMA_PCPCI 0x0200 208 #define POST_WRITE 0x0080 209 #define PCI_TIMING 0x0040 210 #define SWAP_LR 0x0020 211 #define SUBTR_DECODE 0x0002 212 213 /* Values for the ESM_CONFIG_B */ 214 215 #define SPDIF_CONFB 0x0100 216 #define HWV_CONFB 0x0080 217 #define DEBOUNCE 0x0040 218 #define GPIO_CONFB 0x0020 219 #define CHI_CONFB 0x0010 220 #define IDMA_CONFB 0x0008 /*undoc */ 221 #define MIDI_FIX 0x0004 /*undoc */ 222 #define IRQ_TO_ISA 0x0001 /*undoc */ 223 224 /* Values for Ring Bus Control B */ 225 #define RINGB_2CODEC_ID_MASK 0x0003 226 #define RINGB_DIS_VALIDATION 0x0008 227 #define RINGB_EN_SPDIF 0x0010 228 #define RINGB_EN_2CODEC 0x0020 229 #define RINGB_SING_BIT_DUAL 0x0040 230 231 /* ****Port Addresses**** */ 232 233 /* Write & Read */ 234 #define ESM_INDEX 0x02 235 #define ESM_DATA 0x00 236 237 /* AC97 + RingBus */ 238 #define ESM_AC97_INDEX 0x30 239 #define ESM_AC97_DATA 0x32 240 #define ESM_RING_BUS_DEST 0x34 241 #define ESM_RING_BUS_CONTR_A 0x36 242 #define ESM_RING_BUS_CONTR_B 0x38 243 #define ESM_RING_BUS_SDO 0x3A 244 245 /* WaveCache*/ 246 #define WC_INDEX 0x10 247 #define WC_DATA 0x12 248 #define WC_CONTROL 0x14 249 250 /* ASSP*/ 251 #define ASSP_INDEX 0x80 252 #define ASSP_MEMORY 0x82 253 #define ASSP_DATA 0x84 254 #define ASSP_CONTROL_A 0xA2 255 #define ASSP_CONTROL_B 0xA4 256 #define ASSP_CONTROL_C 0xA6 257 #define ASSP_HOSTW_INDEX 0xA8 258 #define ASSP_HOSTW_DATA 0xAA 259 #define ASSP_HOSTW_IRQ 0xAC 260 /* Midi */ 261 #define ESM_MPU401_PORT 0x98 262 /* Others */ 263 #define ESM_PORT_HOST_IRQ 0x18 264 265 #define IDR0_DATA_PORT 0x00 266 #define IDR1_CRAM_POINTER 0x01 267 #define IDR2_CRAM_DATA 0x02 268 #define IDR3_WAVE_DATA 0x03 269 #define IDR4_WAVE_PTR_LOW 0x04 270 #define IDR5_WAVE_PTR_HI 0x05 271 #define IDR6_TIMER_CTRL 0x06 272 #define IDR7_WAVE_ROMRAM 0x07 273 274 #define WRITEABLE_MAP 0xEFFFFF 275 #define READABLE_MAP 0x64003F 276 277 /* PCI Register */ 278 279 #define ESM_LEGACY_AUDIO_CONTROL 0x40 280 #define ESM_ACPI_COMMAND 0x54 281 #define ESM_CONFIG_A 0x50 282 #define ESM_CONFIG_B 0x52 283 #define ESM_DDMA 0x60 284 285 /* Bob Bits */ 286 #define ESM_BOB_ENABLE 0x0001 287 #define ESM_BOB_START 0x0001 288 289 /* Host IRQ Control Bits */ 290 #define ESM_RESET_MAESTRO 0x8000 291 #define ESM_RESET_DIRECTSOUND 0x4000 292 #define ESM_HIRQ_ClkRun 0x0100 293 #define ESM_HIRQ_HW_VOLUME 0x0040 294 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */ 295 #define ESM_HIRQ_ASSP 0x0010 296 #define ESM_HIRQ_DSIE 0x0004 297 #define ESM_HIRQ_MPU401 0x0002 298 #define ESM_HIRQ_SB 0x0001 299 300 /* Host IRQ Status Bits */ 301 #define ESM_MPU401_IRQ 0x02 302 #define ESM_SB_IRQ 0x01 303 #define ESM_SOUND_IRQ 0x04 304 #define ESM_ASSP_IRQ 0x10 305 #define ESM_HWVOL_IRQ 0x40 306 307 #define ESS_SYSCLK 50000000 308 #define ESM_BOB_FREQ 200 309 #define ESM_BOB_FREQ_MAX 800 310 311 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */ 312 #define ESM_FREQ_ESM2 (50000000L / 1024L) 313 314 /* APU Modes: reg 0x00, bit 4-7 */ 315 #define ESM_APU_MODE_SHIFT 4 316 #define ESM_APU_MODE_MASK (0xf << 4) 317 #define ESM_APU_OFF 0x00 318 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */ 319 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */ 320 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */ 321 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */ 322 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */ 323 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */ 324 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */ 325 #define ESM_APU_CORRELATOR 0x08 /* Correlator */ 326 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */ 327 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */ 328 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */ 329 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */ 330 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */ 331 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */ 332 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */ 333 334 /* reg 0x00 */ 335 #define ESM_APU_FILTER_Q_SHIFT 0 336 #define ESM_APU_FILTER_Q_MASK (3 << 0) 337 /* APU Filtey Q Control */ 338 #define ESM_APU_FILTER_LESSQ 0x00 339 #define ESM_APU_FILTER_MOREQ 0x03 340 341 #define ESM_APU_FILTER_TYPE_SHIFT 2 342 #define ESM_APU_FILTER_TYPE_MASK (3 << 2) 343 #define ESM_APU_ENV_TYPE_SHIFT 8 344 #define ESM_APU_ENV_TYPE_MASK (3 << 8) 345 #define ESM_APU_ENV_STATE_SHIFT 10 346 #define ESM_APU_ENV_STATE_MASK (3 << 10) 347 #define ESM_APU_END_CURVE (1 << 12) 348 #define ESM_APU_INT_ON_LOOP (1 << 13) 349 #define ESM_APU_DMA_ENABLE (1 << 14) 350 351 /* reg 0x02 */ 352 #define ESM_APU_SUBMIX_GROUP_SHIRT 0 353 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0) 354 #define ESM_APU_SUBMIX_MODE (1 << 3) 355 #define ESM_APU_6dB (1 << 4) 356 #define ESM_APU_DUAL_EFFECT (1 << 5) 357 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6 358 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6) 359 360 /* reg 0x03 */ 361 #define ESM_APU_STEP_SIZE_MASK 0x0fff 362 363 /* reg 0x04 */ 364 #define ESM_APU_PHASE_SHIFT 0 365 #define ESM_APU_PHASE_MASK (0xff << 0) 366 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */ 367 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8) 368 369 /* reg 0x05 - wave start offset */ 370 /* reg 0x06 - wave end offset */ 371 /* reg 0x07 - wave loop length */ 372 373 /* reg 0x08 */ 374 #define ESM_APU_EFFECT_GAIN_SHIFT 0 375 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0) 376 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8 377 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8) 378 #define ESM_APU_TREMOLO_RATE_SHIFT 12 379 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12) 380 381 /* reg 0x09 */ 382 /* bit 0-7 amplitude dest? */ 383 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8 384 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8) 385 386 /* reg 0x0a */ 387 #define ESM_APU_POLAR_PAN_SHIFT 0 388 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0) 389 /* Polar Pan Control */ 390 #define ESM_APU_PAN_CENTER_CIRCLE 0x00 391 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01 392 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02 393 394 #define ESM_APU_FILTER_TUNING_SHIFT 8 395 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8) 396 397 /* reg 0x0b */ 398 #define ESM_APU_DATA_SRC_A_SHIFT 0 399 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0) 400 #define ESM_APU_INV_POL_A (1 << 7) 401 #define ESM_APU_DATA_SRC_B_SHIFT 8 402 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8) 403 #define ESM_APU_INV_POL_B (1 << 15) 404 405 #define ESM_APU_VIBRATO_RATE_SHIFT 0 406 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0) 407 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4 408 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4) 409 #define ESM_APU_VIBRATO_PHASE_SHIFT 8 410 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8) 411 412 /* reg 0x0c */ 413 #define ESM_APU_RADIUS_SELECT (1 << 6) 414 415 /* APU Filter Control */ 416 #define ESM_APU_FILTER_2POLE_LOPASS 0x00 417 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01 418 #define ESM_APU_FILTER_2POLE_HIPASS 0x02 419 #define ESM_APU_FILTER_1POLE_LOPASS 0x03 420 #define ESM_APU_FILTER_1POLE_HIPASS 0x04 421 #define ESM_APU_FILTER_OFF 0x05 422 423 /* APU ATFP Type */ 424 #define ESM_APU_ATFP_AMPLITUDE 0x00 425 #define ESM_APU_ATFP_TREMELO 0x01 426 #define ESM_APU_ATFP_FILTER 0x02 427 #define ESM_APU_ATFP_PAN 0x03 428 429 /* APU ATFP Flags */ 430 #define ESM_APU_ATFP_FLG_OFF 0x00 431 #define ESM_APU_ATFP_FLG_WAIT 0x01 432 #define ESM_APU_ATFP_FLG_DONE 0x02 433 #define ESM_APU_ATFP_FLG_INPROCESS 0x03 434 435 436 /* capture mixing buffer size */ 437 #define ESM_MEM_ALIGN 0x1000 438 #define ESM_MIXBUF_SIZE 0x400 439 440 #define ESM_MODE_PLAY 0 441 #define ESM_MODE_CAPTURE 1 442 443 444 /* APU use in the driver */ 445 enum snd_enum_apu_type { 446 ESM_APU_PCM_PLAY, 447 ESM_APU_PCM_CAPTURE, 448 ESM_APU_PCM_RATECONV, 449 ESM_APU_FREE 450 }; 451 452 /* chip type */ 453 enum { 454 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E 455 }; 456 457 /* DMA Hack! */ 458 struct esm_memory { 459 struct snd_dma_buffer buf; 460 int empty; /* status */ 461 struct list_head list; 462 }; 463 464 /* Playback Channel */ 465 struct esschan { 466 int running; 467 468 u8 apu[4]; 469 u8 apu_mode[4]; 470 471 /* playback/capture pcm buffer */ 472 struct esm_memory *memory; 473 /* capture mixer buffer */ 474 struct esm_memory *mixbuf; 475 476 unsigned int hwptr; /* current hw pointer in bytes */ 477 unsigned int count; /* sample counter in bytes */ 478 unsigned int dma_size; /* total buffer size in bytes */ 479 unsigned int frag_size; /* period size in bytes */ 480 unsigned int wav_shift; 481 u16 base[4]; /* offset for ptr */ 482 483 /* stereo/16bit flag */ 484 unsigned char fmt; 485 int mode; /* playback / capture */ 486 487 int bob_freq; /* required timer frequency */ 488 489 struct snd_pcm_substream *substream; 490 491 /* linked list */ 492 struct list_head list; 493 494 #ifdef CONFIG_PM 495 u16 wc_map[4]; 496 #endif 497 }; 498 499 struct es1968 { 500 /* Module Config */ 501 int total_bufsize; /* in bytes */ 502 503 int playback_streams, capture_streams; 504 505 unsigned int clock; /* clock */ 506 /* for clock measurement */ 507 unsigned int in_measurement: 1; 508 unsigned int measure_apu; 509 unsigned int measure_lastpos; 510 unsigned int measure_count; 511 512 /* buffer */ 513 struct snd_dma_buffer dma; 514 515 /* Resources... */ 516 int irq; 517 unsigned long io_port; 518 int type; 519 struct pci_dev *pci; 520 struct snd_card *card; 521 struct snd_pcm *pcm; 522 int do_pm; /* power-management enabled */ 523 524 /* DMA memory block */ 525 struct list_head buf_list; 526 527 /* ALSA Stuff */ 528 struct snd_ac97 *ac97; 529 struct snd_rawmidi *rmidi; 530 531 spinlock_t reg_lock; 532 unsigned int in_suspend; 533 534 /* Maestro Stuff */ 535 u16 maestro_map[32]; 536 int bobclient; /* active timer instancs */ 537 int bob_freq; /* timer frequency */ 538 struct mutex memory_mutex; /* memory lock */ 539 540 /* APU states */ 541 unsigned char apu[NR_APUS]; 542 543 /* active substreams */ 544 struct list_head substream_list; 545 spinlock_t substream_lock; 546 547 #ifdef CONFIG_PM 548 u16 apu_map[NR_APUS][NR_APU_REGS]; 549 #endif 550 551 #ifdef SUPPORT_JOYSTICK 552 struct gameport *gameport; 553 #endif 554 555 #ifdef CONFIG_SND_ES1968_INPUT 556 struct input_dev *input_dev; 557 char phys[64]; /* physical device path */ 558 #else 559 struct snd_kcontrol *master_switch; /* for h/w volume control */ 560 struct snd_kcontrol *master_volume; 561 #endif 562 struct work_struct hwvol_work; 563 564 #ifdef CONFIG_SND_ES1968_RADIO 565 struct v4l2_device v4l2_dev; 566 struct snd_tea575x tea; 567 #endif 568 }; 569 570 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id); 571 572 static DEFINE_PCI_DEVICE_TABLE(snd_es1968_ids) = { 573 /* Maestro 1 */ 574 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO }, 575 /* Maestro 2 */ 576 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 }, 577 /* Maestro 2E */ 578 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E }, 579 { 0, } 580 }; 581 582 MODULE_DEVICE_TABLE(pci, snd_es1968_ids); 583 584 /* ********************* 585 * Low Level Funcs! * 586 *********************/ 587 588 /* no spinlock */ 589 static void __maestro_write(struct es1968 *chip, u16 reg, u16 data) 590 { 591 outw(reg, chip->io_port + ESM_INDEX); 592 outw(data, chip->io_port + ESM_DATA); 593 chip->maestro_map[reg] = data; 594 } 595 596 static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data) 597 { 598 unsigned long flags; 599 spin_lock_irqsave(&chip->reg_lock, flags); 600 __maestro_write(chip, reg, data); 601 spin_unlock_irqrestore(&chip->reg_lock, flags); 602 } 603 604 /* no spinlock */ 605 static u16 __maestro_read(struct es1968 *chip, u16 reg) 606 { 607 if (READABLE_MAP & (1 << reg)) { 608 outw(reg, chip->io_port + ESM_INDEX); 609 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA); 610 } 611 return chip->maestro_map[reg]; 612 } 613 614 static inline u16 maestro_read(struct es1968 *chip, u16 reg) 615 { 616 unsigned long flags; 617 u16 result; 618 spin_lock_irqsave(&chip->reg_lock, flags); 619 result = __maestro_read(chip, reg); 620 spin_unlock_irqrestore(&chip->reg_lock, flags); 621 return result; 622 } 623 624 /* Wait for the codec bus to be free */ 625 static int snd_es1968_ac97_wait(struct es1968 *chip) 626 { 627 int timeout = 100000; 628 629 while (timeout-- > 0) { 630 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) 631 return 0; 632 cond_resched(); 633 } 634 snd_printd("es1968: ac97 timeout\n"); 635 return 1; /* timeout */ 636 } 637 638 static int snd_es1968_ac97_wait_poll(struct es1968 *chip) 639 { 640 int timeout = 100000; 641 642 while (timeout-- > 0) { 643 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) 644 return 0; 645 } 646 snd_printd("es1968: ac97 timeout\n"); 647 return 1; /* timeout */ 648 } 649 650 static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) 651 { 652 struct es1968 *chip = ac97->private_data; 653 654 snd_es1968_ac97_wait(chip); 655 656 /* Write the bus */ 657 outw(val, chip->io_port + ESM_AC97_DATA); 658 /*msleep(1);*/ 659 outb(reg, chip->io_port + ESM_AC97_INDEX); 660 /*msleep(1);*/ 661 } 662 663 static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 664 { 665 u16 data = 0; 666 struct es1968 *chip = ac97->private_data; 667 668 snd_es1968_ac97_wait(chip); 669 670 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX); 671 /*msleep(1);*/ 672 673 if (!snd_es1968_ac97_wait_poll(chip)) { 674 data = inw(chip->io_port + ESM_AC97_DATA); 675 /*msleep(1);*/ 676 } 677 678 return data; 679 } 680 681 /* no spinlock */ 682 static void apu_index_set(struct es1968 *chip, u16 index) 683 { 684 int i; 685 __maestro_write(chip, IDR1_CRAM_POINTER, index); 686 for (i = 0; i < 1000; i++) 687 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index) 688 return; 689 snd_printd("es1968: APU register select failed. (Timeout)\n"); 690 } 691 692 /* no spinlock */ 693 static void apu_data_set(struct es1968 *chip, u16 data) 694 { 695 int i; 696 for (i = 0; i < 1000; i++) { 697 if (__maestro_read(chip, IDR0_DATA_PORT) == data) 698 return; 699 __maestro_write(chip, IDR0_DATA_PORT, data); 700 } 701 snd_printd("es1968: APU register set probably failed (Timeout)!\n"); 702 } 703 704 /* no spinlock */ 705 static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) 706 { 707 if (snd_BUG_ON(channel >= NR_APUS)) 708 return; 709 #ifdef CONFIG_PM 710 chip->apu_map[channel][reg] = data; 711 #endif 712 reg |= (channel << 4); 713 apu_index_set(chip, reg); 714 apu_data_set(chip, data); 715 } 716 717 static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) 718 { 719 unsigned long flags; 720 spin_lock_irqsave(&chip->reg_lock, flags); 721 __apu_set_register(chip, channel, reg, data); 722 spin_unlock_irqrestore(&chip->reg_lock, flags); 723 } 724 725 static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg) 726 { 727 if (snd_BUG_ON(channel >= NR_APUS)) 728 return 0; 729 reg |= (channel << 4); 730 apu_index_set(chip, reg); 731 return __maestro_read(chip, IDR0_DATA_PORT); 732 } 733 734 static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg) 735 { 736 unsigned long flags; 737 u16 v; 738 spin_lock_irqsave(&chip->reg_lock, flags); 739 v = __apu_get_register(chip, channel, reg); 740 spin_unlock_irqrestore(&chip->reg_lock, flags); 741 return v; 742 } 743 744 #if 0 /* ASSP is not supported */ 745 746 static void assp_set_register(struct es1968 *chip, u32 reg, u32 value) 747 { 748 unsigned long flags; 749 750 spin_lock_irqsave(&chip->reg_lock, flags); 751 outl(reg, chip->io_port + ASSP_INDEX); 752 outl(value, chip->io_port + ASSP_DATA); 753 spin_unlock_irqrestore(&chip->reg_lock, flags); 754 } 755 756 static u32 assp_get_register(struct es1968 *chip, u32 reg) 757 { 758 unsigned long flags; 759 u32 value; 760 761 spin_lock_irqsave(&chip->reg_lock, flags); 762 outl(reg, chip->io_port + ASSP_INDEX); 763 value = inl(chip->io_port + ASSP_DATA); 764 spin_unlock_irqrestore(&chip->reg_lock, flags); 765 766 return value; 767 } 768 769 #endif 770 771 static void wave_set_register(struct es1968 *chip, u16 reg, u16 value) 772 { 773 unsigned long flags; 774 775 spin_lock_irqsave(&chip->reg_lock, flags); 776 outw(reg, chip->io_port + WC_INDEX); 777 outw(value, chip->io_port + WC_DATA); 778 spin_unlock_irqrestore(&chip->reg_lock, flags); 779 } 780 781 static u16 wave_get_register(struct es1968 *chip, u16 reg) 782 { 783 unsigned long flags; 784 u16 value; 785 786 spin_lock_irqsave(&chip->reg_lock, flags); 787 outw(reg, chip->io_port + WC_INDEX); 788 value = inw(chip->io_port + WC_DATA); 789 spin_unlock_irqrestore(&chip->reg_lock, flags); 790 791 return value; 792 } 793 794 /* ******************* 795 * Bob the Timer! * 796 *******************/ 797 798 static void snd_es1968_bob_stop(struct es1968 *chip) 799 { 800 u16 reg; 801 802 reg = __maestro_read(chip, 0x11); 803 reg &= ~ESM_BOB_ENABLE; 804 __maestro_write(chip, 0x11, reg); 805 reg = __maestro_read(chip, 0x17); 806 reg &= ~ESM_BOB_START; 807 __maestro_write(chip, 0x17, reg); 808 } 809 810 static void snd_es1968_bob_start(struct es1968 *chip) 811 { 812 int prescale; 813 int divide; 814 815 /* compute ideal interrupt frequency for buffer size & play rate */ 816 /* first, find best prescaler value to match freq */ 817 for (prescale = 5; prescale < 12; prescale++) 818 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9))) 819 break; 820 821 /* next, back off prescaler whilst getting divider into optimum range */ 822 divide = 1; 823 while ((prescale > 5) && (divide < 32)) { 824 prescale--; 825 divide <<= 1; 826 } 827 divide >>= 1; 828 829 /* now fine-tune the divider for best match */ 830 for (; divide < 31; divide++) 831 if (chip->bob_freq > 832 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break; 833 834 /* divide = 0 is illegal, but don't let prescale = 4! */ 835 if (divide == 0) { 836 divide++; 837 if (prescale > 5) 838 prescale--; 839 } else if (divide > 1) 840 divide--; 841 842 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */ 843 844 /* Now set IDR 11/17 */ 845 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1); 846 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1); 847 } 848 849 /* call with substream spinlock */ 850 static void snd_es1968_bob_inc(struct es1968 *chip, int freq) 851 { 852 chip->bobclient++; 853 if (chip->bobclient == 1) { 854 chip->bob_freq = freq; 855 snd_es1968_bob_start(chip); 856 } else if (chip->bob_freq < freq) { 857 snd_es1968_bob_stop(chip); 858 chip->bob_freq = freq; 859 snd_es1968_bob_start(chip); 860 } 861 } 862 863 /* call with substream spinlock */ 864 static void snd_es1968_bob_dec(struct es1968 *chip) 865 { 866 chip->bobclient--; 867 if (chip->bobclient <= 0) 868 snd_es1968_bob_stop(chip); 869 else if (chip->bob_freq > ESM_BOB_FREQ) { 870 /* check reduction of timer frequency */ 871 int max_freq = ESM_BOB_FREQ; 872 struct esschan *es; 873 list_for_each_entry(es, &chip->substream_list, list) { 874 if (max_freq < es->bob_freq) 875 max_freq = es->bob_freq; 876 } 877 if (max_freq != chip->bob_freq) { 878 snd_es1968_bob_stop(chip); 879 chip->bob_freq = max_freq; 880 snd_es1968_bob_start(chip); 881 } 882 } 883 } 884 885 static int 886 snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es, 887 struct snd_pcm_runtime *runtime) 888 { 889 /* we acquire 4 interrupts per period for precise control.. */ 890 int freq = runtime->rate * 4; 891 if (es->fmt & ESS_FMT_STEREO) 892 freq <<= 1; 893 if (es->fmt & ESS_FMT_16BIT) 894 freq <<= 1; 895 freq /= es->frag_size; 896 if (freq < ESM_BOB_FREQ) 897 freq = ESM_BOB_FREQ; 898 else if (freq > ESM_BOB_FREQ_MAX) 899 freq = ESM_BOB_FREQ_MAX; 900 return freq; 901 } 902 903 904 /************* 905 * PCM Part * 906 *************/ 907 908 static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq) 909 { 910 u32 rate = (freq << 16) / chip->clock; 911 #if 0 /* XXX: do we need this? */ 912 if (rate > 0x10000) 913 rate = 0x10000; 914 #endif 915 return rate; 916 } 917 918 /* get current pointer */ 919 static inline unsigned int 920 snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es) 921 { 922 unsigned int offset; 923 924 offset = apu_get_register(chip, es->apu[0], 5); 925 926 offset -= es->base[0]; 927 928 return (offset & 0xFFFE); /* hardware is in words */ 929 } 930 931 static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq) 932 { 933 apu_set_register(chip, apu, 2, 934 (apu_get_register(chip, apu, 2) & 0x00FF) | 935 ((freq & 0xff) << 8) | 0x10); 936 apu_set_register(chip, apu, 3, freq >> 8); 937 } 938 939 /* spin lock held */ 940 static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode) 941 { 942 /* set the APU mode */ 943 __apu_set_register(esm, apu, 0, 944 (__apu_get_register(esm, apu, 0) & 0xff0f) | 945 (mode << 4)); 946 } 947 948 static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es) 949 { 950 spin_lock(&chip->reg_lock); 951 __apu_set_register(chip, es->apu[0], 5, es->base[0]); 952 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]); 953 if (es->mode == ESM_MODE_CAPTURE) { 954 __apu_set_register(chip, es->apu[2], 5, es->base[2]); 955 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]); 956 } 957 if (es->fmt & ESS_FMT_STEREO) { 958 __apu_set_register(chip, es->apu[1], 5, es->base[1]); 959 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]); 960 if (es->mode == ESM_MODE_CAPTURE) { 961 __apu_set_register(chip, es->apu[3], 5, es->base[3]); 962 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]); 963 } 964 } 965 spin_unlock(&chip->reg_lock); 966 } 967 968 static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es) 969 { 970 spin_lock(&chip->reg_lock); 971 snd_es1968_trigger_apu(chip, es->apu[0], 0); 972 snd_es1968_trigger_apu(chip, es->apu[1], 0); 973 if (es->mode == ESM_MODE_CAPTURE) { 974 snd_es1968_trigger_apu(chip, es->apu[2], 0); 975 snd_es1968_trigger_apu(chip, es->apu[3], 0); 976 } 977 spin_unlock(&chip->reg_lock); 978 } 979 980 /* set the wavecache control reg */ 981 static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es, 982 int channel, u32 addr, int capture) 983 { 984 u32 tmpval = (addr - 0x10) & 0xFFF8; 985 986 if (! capture) { 987 if (!(es->fmt & ESS_FMT_16BIT)) 988 tmpval |= 4; /* 8bit */ 989 if (es->fmt & ESS_FMT_STEREO) 990 tmpval |= 2; /* stereo */ 991 } 992 993 /* set the wavecache control reg */ 994 wave_set_register(chip, es->apu[channel] << 3, tmpval); 995 996 #ifdef CONFIG_PM 997 es->wc_map[channel] = tmpval; 998 #endif 999 } 1000 1001 1002 static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es, 1003 struct snd_pcm_runtime *runtime) 1004 { 1005 u32 pa; 1006 int high_apu = 0; 1007 int channel, apu; 1008 int i, size; 1009 unsigned long flags; 1010 u32 freq; 1011 1012 size = es->dma_size >> es->wav_shift; 1013 1014 if (es->fmt & ESS_FMT_STEREO) 1015 high_apu++; 1016 1017 for (channel = 0; channel <= high_apu; channel++) { 1018 apu = es->apu[channel]; 1019 1020 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0); 1021 1022 /* Offset to PCMBAR */ 1023 pa = es->memory->buf.addr; 1024 pa -= chip->dma.addr; 1025 pa >>= 1; /* words */ 1026 1027 pa |= 0x00400000; /* System RAM (Bit 22) */ 1028 1029 if (es->fmt & ESS_FMT_STEREO) { 1030 /* Enable stereo */ 1031 if (channel) 1032 pa |= 0x00800000; /* (Bit 23) */ 1033 if (es->fmt & ESS_FMT_16BIT) 1034 pa >>= 1; 1035 } 1036 1037 /* base offset of dma calcs when reading the pointer 1038 on this left one */ 1039 es->base[channel] = pa & 0xFFFF; 1040 1041 for (i = 0; i < 16; i++) 1042 apu_set_register(chip, apu, i, 0x0000); 1043 1044 /* Load the buffer into the wave engine */ 1045 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1046 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1047 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF); 1048 /* setting loop == sample len */ 1049 apu_set_register(chip, apu, 7, size); 1050 1051 /* clear effects/env.. */ 1052 apu_set_register(chip, apu, 8, 0x0000); 1053 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */ 1054 apu_set_register(chip, apu, 9, 0xD000); 1055 1056 /* clear routing stuff */ 1057 apu_set_register(chip, apu, 11, 0x0000); 1058 /* dma on, no envelopes, filter to all 1s) */ 1059 apu_set_register(chip, apu, 0, 0x400F); 1060 1061 if (es->fmt & ESS_FMT_16BIT) 1062 es->apu_mode[channel] = ESM_APU_16BITLINEAR; 1063 else 1064 es->apu_mode[channel] = ESM_APU_8BITLINEAR; 1065 1066 if (es->fmt & ESS_FMT_STEREO) { 1067 /* set panning: left or right */ 1068 /* Check: different panning. On my Canyon 3D Chipset the 1069 Channels are swapped. I don't know, about the output 1070 to the SPDif Link. Perhaps you have to change this 1071 and not the APU Regs 4-5. */ 1072 apu_set_register(chip, apu, 10, 1073 0x8F00 | (channel ? 0 : 0x10)); 1074 es->apu_mode[channel] += 1; /* stereo */ 1075 } else 1076 apu_set_register(chip, apu, 10, 0x8F08); 1077 } 1078 1079 spin_lock_irqsave(&chip->reg_lock, flags); 1080 /* clear WP interrupts */ 1081 outw(1, chip->io_port + 0x04); 1082 /* enable WP ints */ 1083 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1084 spin_unlock_irqrestore(&chip->reg_lock, flags); 1085 1086 freq = runtime->rate; 1087 /* set frequency */ 1088 if (freq > 48000) 1089 freq = 48000; 1090 if (freq < 4000) 1091 freq = 4000; 1092 1093 /* hmmm.. */ 1094 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO)) 1095 freq >>= 1; 1096 1097 freq = snd_es1968_compute_rate(chip, freq); 1098 1099 /* Load the frequency, turn on 6dB */ 1100 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1101 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1102 } 1103 1104 1105 static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel, 1106 unsigned int pa, unsigned int bsize, 1107 int mode, int route) 1108 { 1109 int i, apu = es->apu[channel]; 1110 1111 es->apu_mode[channel] = mode; 1112 1113 /* set the wavecache control reg */ 1114 snd_es1968_program_wavecache(chip, es, channel, pa, 1); 1115 1116 /* Offset to PCMBAR */ 1117 pa -= chip->dma.addr; 1118 pa >>= 1; /* words */ 1119 1120 /* base offset of dma calcs when reading the pointer 1121 on this left one */ 1122 es->base[channel] = pa & 0xFFFF; 1123 pa |= 0x00400000; /* bit 22 -> System RAM */ 1124 1125 /* Begin loading the APU */ 1126 for (i = 0; i < 16; i++) 1127 apu_set_register(chip, apu, i, 0x0000); 1128 1129 /* need to enable subgroups.. and we should probably 1130 have different groups for different /dev/dsps.. */ 1131 apu_set_register(chip, apu, 2, 0x8); 1132 1133 /* Load the buffer into the wave engine */ 1134 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1135 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1136 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF); 1137 apu_set_register(chip, apu, 7, bsize); 1138 /* clear effects/env.. */ 1139 apu_set_register(chip, apu, 8, 0x00F0); 1140 /* amplitude now? sure. why not. */ 1141 apu_set_register(chip, apu, 9, 0x0000); 1142 /* set filter tune, radius, polar pan */ 1143 apu_set_register(chip, apu, 10, 0x8F08); 1144 /* route input */ 1145 apu_set_register(chip, apu, 11, route); 1146 /* dma on, no envelopes, filter to all 1s) */ 1147 apu_set_register(chip, apu, 0, 0x400F); 1148 } 1149 1150 static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es, 1151 struct snd_pcm_runtime *runtime) 1152 { 1153 int size; 1154 u32 freq; 1155 unsigned long flags; 1156 1157 size = es->dma_size >> es->wav_shift; 1158 1159 /* APU assignments: 1160 0 = mono/left SRC 1161 1 = right SRC 1162 2 = mono/left Input Mixer 1163 3 = right Input Mixer 1164 */ 1165 /* data seems to flow from the codec, through an apu into 1166 the 'mixbuf' bit of page, then through the SRC apu 1167 and out to the real 'buffer'. ok. sure. */ 1168 1169 /* input mixer (left/mono) */ 1170 /* parallel in crap, see maestro reg 0xC [8-11] */ 1171 init_capture_apu(chip, es, 2, 1172 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */ 1173 ESM_APU_INPUTMIXER, 0x14); 1174 /* SRC (left/mono); get input from inputing apu */ 1175 init_capture_apu(chip, es, 0, es->memory->buf.addr, size, 1176 ESM_APU_SRCONVERTOR, es->apu[2]); 1177 if (es->fmt & ESS_FMT_STEREO) { 1178 /* input mixer (right) */ 1179 init_capture_apu(chip, es, 3, 1180 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2, 1181 ESM_MIXBUF_SIZE/4, /* in words */ 1182 ESM_APU_INPUTMIXER, 0x15); 1183 /* SRC (right) */ 1184 init_capture_apu(chip, es, 1, 1185 es->memory->buf.addr + size*2, size, 1186 ESM_APU_SRCONVERTOR, es->apu[3]); 1187 } 1188 1189 freq = runtime->rate; 1190 /* Sample Rate conversion APUs don't like 0x10000 for their rate */ 1191 if (freq > 47999) 1192 freq = 47999; 1193 if (freq < 4000) 1194 freq = 4000; 1195 1196 freq = snd_es1968_compute_rate(chip, freq); 1197 1198 /* Load the frequency, turn on 6dB */ 1199 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1200 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1201 1202 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */ 1203 freq = 0x10000; 1204 snd_es1968_apu_set_freq(chip, es->apu[2], freq); 1205 snd_es1968_apu_set_freq(chip, es->apu[3], freq); 1206 1207 spin_lock_irqsave(&chip->reg_lock, flags); 1208 /* clear WP interrupts */ 1209 outw(1, chip->io_port + 0x04); 1210 /* enable WP ints */ 1211 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1212 spin_unlock_irqrestore(&chip->reg_lock, flags); 1213 } 1214 1215 /******************* 1216 * ALSA Interface * 1217 *******************/ 1218 1219 static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream) 1220 { 1221 struct es1968 *chip = snd_pcm_substream_chip(substream); 1222 struct snd_pcm_runtime *runtime = substream->runtime; 1223 struct esschan *es = runtime->private_data; 1224 1225 es->dma_size = snd_pcm_lib_buffer_bytes(substream); 1226 es->frag_size = snd_pcm_lib_period_bytes(substream); 1227 1228 es->wav_shift = 1; /* maestro handles always 16bit */ 1229 es->fmt = 0; 1230 if (snd_pcm_format_width(runtime->format) == 16) 1231 es->fmt |= ESS_FMT_16BIT; 1232 if (runtime->channels > 1) { 1233 es->fmt |= ESS_FMT_STEREO; 1234 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */ 1235 es->wav_shift++; 1236 } 1237 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime); 1238 1239 switch (es->mode) { 1240 case ESM_MODE_PLAY: 1241 snd_es1968_playback_setup(chip, es, runtime); 1242 break; 1243 case ESM_MODE_CAPTURE: 1244 snd_es1968_capture_setup(chip, es, runtime); 1245 break; 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1252 { 1253 struct es1968 *chip = snd_pcm_substream_chip(substream); 1254 struct esschan *es = substream->runtime->private_data; 1255 1256 spin_lock(&chip->substream_lock); 1257 switch (cmd) { 1258 case SNDRV_PCM_TRIGGER_START: 1259 case SNDRV_PCM_TRIGGER_RESUME: 1260 if (es->running) 1261 break; 1262 snd_es1968_bob_inc(chip, es->bob_freq); 1263 es->count = 0; 1264 es->hwptr = 0; 1265 snd_es1968_pcm_start(chip, es); 1266 es->running = 1; 1267 break; 1268 case SNDRV_PCM_TRIGGER_STOP: 1269 case SNDRV_PCM_TRIGGER_SUSPEND: 1270 if (! es->running) 1271 break; 1272 snd_es1968_pcm_stop(chip, es); 1273 es->running = 0; 1274 snd_es1968_bob_dec(chip); 1275 break; 1276 } 1277 spin_unlock(&chip->substream_lock); 1278 return 0; 1279 } 1280 1281 static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream) 1282 { 1283 struct es1968 *chip = snd_pcm_substream_chip(substream); 1284 struct esschan *es = substream->runtime->private_data; 1285 unsigned int ptr; 1286 1287 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1288 1289 return bytes_to_frames(substream->runtime, ptr % es->dma_size); 1290 } 1291 1292 static struct snd_pcm_hardware snd_es1968_playback = { 1293 .info = (SNDRV_PCM_INFO_MMAP | 1294 SNDRV_PCM_INFO_MMAP_VALID | 1295 SNDRV_PCM_INFO_INTERLEAVED | 1296 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1297 /*SNDRV_PCM_INFO_PAUSE |*/ 1298 SNDRV_PCM_INFO_RESUME), 1299 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1300 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1301 .rate_min = 4000, 1302 .rate_max = 48000, 1303 .channels_min = 1, 1304 .channels_max = 2, 1305 .buffer_bytes_max = 65536, 1306 .period_bytes_min = 256, 1307 .period_bytes_max = 65536, 1308 .periods_min = 1, 1309 .periods_max = 1024, 1310 .fifo_size = 0, 1311 }; 1312 1313 static struct snd_pcm_hardware snd_es1968_capture = { 1314 .info = (SNDRV_PCM_INFO_NONINTERLEAVED | 1315 SNDRV_PCM_INFO_MMAP | 1316 SNDRV_PCM_INFO_MMAP_VALID | 1317 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1318 /*SNDRV_PCM_INFO_PAUSE |*/ 1319 SNDRV_PCM_INFO_RESUME), 1320 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE, 1321 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1322 .rate_min = 4000, 1323 .rate_max = 48000, 1324 .channels_min = 1, 1325 .channels_max = 2, 1326 .buffer_bytes_max = 65536, 1327 .period_bytes_min = 256, 1328 .period_bytes_max = 65536, 1329 .periods_min = 1, 1330 .periods_max = 1024, 1331 .fifo_size = 0, 1332 }; 1333 1334 /* ************************* 1335 * DMA memory management * 1336 *************************/ 1337 1338 /* Because the Maestro can only take addresses relative to the PCM base address 1339 register :( */ 1340 1341 static int calc_available_memory_size(struct es1968 *chip) 1342 { 1343 int max_size = 0; 1344 struct esm_memory *buf; 1345 1346 mutex_lock(&chip->memory_mutex); 1347 list_for_each_entry(buf, &chip->buf_list, list) { 1348 if (buf->empty && buf->buf.bytes > max_size) 1349 max_size = buf->buf.bytes; 1350 } 1351 mutex_unlock(&chip->memory_mutex); 1352 if (max_size >= 128*1024) 1353 max_size = 127*1024; 1354 return max_size; 1355 } 1356 1357 /* allocate a new memory chunk with the specified size */ 1358 static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size) 1359 { 1360 struct esm_memory *buf; 1361 1362 size = ALIGN(size, ESM_MEM_ALIGN); 1363 mutex_lock(&chip->memory_mutex); 1364 list_for_each_entry(buf, &chip->buf_list, list) { 1365 if (buf->empty && buf->buf.bytes >= size) 1366 goto __found; 1367 } 1368 mutex_unlock(&chip->memory_mutex); 1369 return NULL; 1370 1371 __found: 1372 if (buf->buf.bytes > size) { 1373 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1374 if (chunk == NULL) { 1375 mutex_unlock(&chip->memory_mutex); 1376 return NULL; 1377 } 1378 chunk->buf = buf->buf; 1379 chunk->buf.bytes -= size; 1380 chunk->buf.area += size; 1381 chunk->buf.addr += size; 1382 chunk->empty = 1; 1383 buf->buf.bytes = size; 1384 list_add(&chunk->list, &buf->list); 1385 } 1386 buf->empty = 0; 1387 mutex_unlock(&chip->memory_mutex); 1388 return buf; 1389 } 1390 1391 /* free a memory chunk */ 1392 static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf) 1393 { 1394 struct esm_memory *chunk; 1395 1396 mutex_lock(&chip->memory_mutex); 1397 buf->empty = 1; 1398 if (buf->list.prev != &chip->buf_list) { 1399 chunk = list_entry(buf->list.prev, struct esm_memory, list); 1400 if (chunk->empty) { 1401 chunk->buf.bytes += buf->buf.bytes; 1402 list_del(&buf->list); 1403 kfree(buf); 1404 buf = chunk; 1405 } 1406 } 1407 if (buf->list.next != &chip->buf_list) { 1408 chunk = list_entry(buf->list.next, struct esm_memory, list); 1409 if (chunk->empty) { 1410 buf->buf.bytes += chunk->buf.bytes; 1411 list_del(&chunk->list); 1412 kfree(chunk); 1413 } 1414 } 1415 mutex_unlock(&chip->memory_mutex); 1416 } 1417 1418 static void snd_es1968_free_dmabuf(struct es1968 *chip) 1419 { 1420 struct list_head *p; 1421 1422 if (! chip->dma.area) 1423 return; 1424 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci)); 1425 while ((p = chip->buf_list.next) != &chip->buf_list) { 1426 struct esm_memory *chunk = list_entry(p, struct esm_memory, list); 1427 list_del(p); 1428 kfree(chunk); 1429 } 1430 } 1431 1432 static int __devinit 1433 snd_es1968_init_dmabuf(struct es1968 *chip) 1434 { 1435 int err; 1436 struct esm_memory *chunk; 1437 1438 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV; 1439 chip->dma.dev.dev = snd_dma_pci_data(chip->pci); 1440 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) { 1441 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV, 1442 snd_dma_pci_data(chip->pci), 1443 chip->total_bufsize, &chip->dma); 1444 if (err < 0 || ! chip->dma.area) { 1445 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n", 1446 chip->total_bufsize); 1447 return -ENOMEM; 1448 } 1449 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) { 1450 snd_dma_free_pages(&chip->dma); 1451 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n"); 1452 return -ENOMEM; 1453 } 1454 } 1455 1456 INIT_LIST_HEAD(&chip->buf_list); 1457 /* allocate an empty chunk */ 1458 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1459 if (chunk == NULL) { 1460 snd_es1968_free_dmabuf(chip); 1461 return -ENOMEM; 1462 } 1463 memset(chip->dma.area, 0, ESM_MEM_ALIGN); 1464 chunk->buf = chip->dma; 1465 chunk->buf.area += ESM_MEM_ALIGN; 1466 chunk->buf.addr += ESM_MEM_ALIGN; 1467 chunk->buf.bytes -= ESM_MEM_ALIGN; 1468 chunk->empty = 1; 1469 list_add(&chunk->list, &chip->buf_list); 1470 1471 return 0; 1472 } 1473 1474 /* setup the dma_areas */ 1475 /* buffer is extracted from the pre-allocated memory chunk */ 1476 static int snd_es1968_hw_params(struct snd_pcm_substream *substream, 1477 struct snd_pcm_hw_params *hw_params) 1478 { 1479 struct es1968 *chip = snd_pcm_substream_chip(substream); 1480 struct snd_pcm_runtime *runtime = substream->runtime; 1481 struct esschan *chan = runtime->private_data; 1482 int size = params_buffer_bytes(hw_params); 1483 1484 if (chan->memory) { 1485 if (chan->memory->buf.bytes >= size) { 1486 runtime->dma_bytes = size; 1487 return 0; 1488 } 1489 snd_es1968_free_memory(chip, chan->memory); 1490 } 1491 chan->memory = snd_es1968_new_memory(chip, size); 1492 if (chan->memory == NULL) { 1493 // snd_printd("cannot allocate dma buffer: size = %d\n", size); 1494 return -ENOMEM; 1495 } 1496 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf); 1497 return 1; /* area was changed */ 1498 } 1499 1500 /* remove dma areas if allocated */ 1501 static int snd_es1968_hw_free(struct snd_pcm_substream *substream) 1502 { 1503 struct es1968 *chip = snd_pcm_substream_chip(substream); 1504 struct snd_pcm_runtime *runtime = substream->runtime; 1505 struct esschan *chan; 1506 1507 if (runtime->private_data == NULL) 1508 return 0; 1509 chan = runtime->private_data; 1510 if (chan->memory) { 1511 snd_es1968_free_memory(chip, chan->memory); 1512 chan->memory = NULL; 1513 } 1514 return 0; 1515 } 1516 1517 1518 /* 1519 * allocate APU pair 1520 */ 1521 static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type) 1522 { 1523 int apu; 1524 1525 for (apu = 0; apu < NR_APUS; apu += 2) { 1526 if (chip->apu[apu] == ESM_APU_FREE && 1527 chip->apu[apu + 1] == ESM_APU_FREE) { 1528 chip->apu[apu] = chip->apu[apu + 1] = type; 1529 return apu; 1530 } 1531 } 1532 return -EBUSY; 1533 } 1534 1535 /* 1536 * release APU pair 1537 */ 1538 static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu) 1539 { 1540 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE; 1541 } 1542 1543 1544 /****************** 1545 * PCM open/close * 1546 ******************/ 1547 1548 static int snd_es1968_playback_open(struct snd_pcm_substream *substream) 1549 { 1550 struct es1968 *chip = snd_pcm_substream_chip(substream); 1551 struct snd_pcm_runtime *runtime = substream->runtime; 1552 struct esschan *es; 1553 int apu1; 1554 1555 /* search 2 APUs */ 1556 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY); 1557 if (apu1 < 0) 1558 return apu1; 1559 1560 es = kzalloc(sizeof(*es), GFP_KERNEL); 1561 if (!es) { 1562 snd_es1968_free_apu_pair(chip, apu1); 1563 return -ENOMEM; 1564 } 1565 1566 es->apu[0] = apu1; 1567 es->apu[1] = apu1 + 1; 1568 es->apu_mode[0] = 0; 1569 es->apu_mode[1] = 0; 1570 es->running = 0; 1571 es->substream = substream; 1572 es->mode = ESM_MODE_PLAY; 1573 1574 runtime->private_data = es; 1575 runtime->hw = snd_es1968_playback; 1576 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1577 calc_available_memory_size(chip); 1578 1579 spin_lock_irq(&chip->substream_lock); 1580 list_add(&es->list, &chip->substream_list); 1581 spin_unlock_irq(&chip->substream_lock); 1582 1583 return 0; 1584 } 1585 1586 static int snd_es1968_capture_open(struct snd_pcm_substream *substream) 1587 { 1588 struct snd_pcm_runtime *runtime = substream->runtime; 1589 struct es1968 *chip = snd_pcm_substream_chip(substream); 1590 struct esschan *es; 1591 int apu1, apu2; 1592 1593 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE); 1594 if (apu1 < 0) 1595 return apu1; 1596 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV); 1597 if (apu2 < 0) { 1598 snd_es1968_free_apu_pair(chip, apu1); 1599 return apu2; 1600 } 1601 1602 es = kzalloc(sizeof(*es), GFP_KERNEL); 1603 if (!es) { 1604 snd_es1968_free_apu_pair(chip, apu1); 1605 snd_es1968_free_apu_pair(chip, apu2); 1606 return -ENOMEM; 1607 } 1608 1609 es->apu[0] = apu1; 1610 es->apu[1] = apu1 + 1; 1611 es->apu[2] = apu2; 1612 es->apu[3] = apu2 + 1; 1613 es->apu_mode[0] = 0; 1614 es->apu_mode[1] = 0; 1615 es->apu_mode[2] = 0; 1616 es->apu_mode[3] = 0; 1617 es->running = 0; 1618 es->substream = substream; 1619 es->mode = ESM_MODE_CAPTURE; 1620 1621 /* get mixbuffer */ 1622 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) { 1623 snd_es1968_free_apu_pair(chip, apu1); 1624 snd_es1968_free_apu_pair(chip, apu2); 1625 kfree(es); 1626 return -ENOMEM; 1627 } 1628 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE); 1629 1630 runtime->private_data = es; 1631 runtime->hw = snd_es1968_capture; 1632 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1633 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */ 1634 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES); 1635 1636 spin_lock_irq(&chip->substream_lock); 1637 list_add(&es->list, &chip->substream_list); 1638 spin_unlock_irq(&chip->substream_lock); 1639 1640 return 0; 1641 } 1642 1643 static int snd_es1968_playback_close(struct snd_pcm_substream *substream) 1644 { 1645 struct es1968 *chip = snd_pcm_substream_chip(substream); 1646 struct esschan *es; 1647 1648 if (substream->runtime->private_data == NULL) 1649 return 0; 1650 es = substream->runtime->private_data; 1651 spin_lock_irq(&chip->substream_lock); 1652 list_del(&es->list); 1653 spin_unlock_irq(&chip->substream_lock); 1654 snd_es1968_free_apu_pair(chip, es->apu[0]); 1655 kfree(es); 1656 1657 return 0; 1658 } 1659 1660 static int snd_es1968_capture_close(struct snd_pcm_substream *substream) 1661 { 1662 struct es1968 *chip = snd_pcm_substream_chip(substream); 1663 struct esschan *es; 1664 1665 if (substream->runtime->private_data == NULL) 1666 return 0; 1667 es = substream->runtime->private_data; 1668 spin_lock_irq(&chip->substream_lock); 1669 list_del(&es->list); 1670 spin_unlock_irq(&chip->substream_lock); 1671 snd_es1968_free_memory(chip, es->mixbuf); 1672 snd_es1968_free_apu_pair(chip, es->apu[0]); 1673 snd_es1968_free_apu_pair(chip, es->apu[2]); 1674 kfree(es); 1675 1676 return 0; 1677 } 1678 1679 static struct snd_pcm_ops snd_es1968_playback_ops = { 1680 .open = snd_es1968_playback_open, 1681 .close = snd_es1968_playback_close, 1682 .ioctl = snd_pcm_lib_ioctl, 1683 .hw_params = snd_es1968_hw_params, 1684 .hw_free = snd_es1968_hw_free, 1685 .prepare = snd_es1968_pcm_prepare, 1686 .trigger = snd_es1968_pcm_trigger, 1687 .pointer = snd_es1968_pcm_pointer, 1688 }; 1689 1690 static struct snd_pcm_ops snd_es1968_capture_ops = { 1691 .open = snd_es1968_capture_open, 1692 .close = snd_es1968_capture_close, 1693 .ioctl = snd_pcm_lib_ioctl, 1694 .hw_params = snd_es1968_hw_params, 1695 .hw_free = snd_es1968_hw_free, 1696 .prepare = snd_es1968_pcm_prepare, 1697 .trigger = snd_es1968_pcm_trigger, 1698 .pointer = snd_es1968_pcm_pointer, 1699 }; 1700 1701 1702 /* 1703 * measure clock 1704 */ 1705 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */ 1706 1707 static void __devinit es1968_measure_clock(struct es1968 *chip) 1708 { 1709 int i, apu; 1710 unsigned int pa, offset, t; 1711 struct esm_memory *memory; 1712 struct timeval start_time, stop_time; 1713 1714 if (chip->clock == 0) 1715 chip->clock = 48000; /* default clock value */ 1716 1717 /* search 2 APUs (although one apu is enough) */ 1718 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) { 1719 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n"); 1720 return; 1721 } 1722 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) { 1723 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock); 1724 snd_es1968_free_apu_pair(chip, apu); 1725 return; 1726 } 1727 1728 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE); 1729 1730 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8); 1731 1732 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1); 1733 pa |= 0x00400000; /* System RAM (Bit 22) */ 1734 1735 /* initialize apu */ 1736 for (i = 0; i < 16; i++) 1737 apu_set_register(chip, apu, i, 0x0000); 1738 1739 apu_set_register(chip, apu, 0, 0x400f); 1740 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8); 1741 apu_set_register(chip, apu, 5, pa & 0xffff); 1742 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff); 1743 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2); 1744 apu_set_register(chip, apu, 8, 0x0000); 1745 apu_set_register(chip, apu, 9, 0xD000); 1746 apu_set_register(chip, apu, 10, 0x8F08); 1747 apu_set_register(chip, apu, 11, 0x0000); 1748 spin_lock_irq(&chip->reg_lock); 1749 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 1750 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */ 1751 spin_unlock_irq(&chip->reg_lock); 1752 1753 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */ 1754 1755 chip->in_measurement = 1; 1756 chip->measure_apu = apu; 1757 spin_lock_irq(&chip->reg_lock); 1758 snd_es1968_bob_inc(chip, ESM_BOB_FREQ); 1759 __apu_set_register(chip, apu, 5, pa & 0xffff); 1760 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR); 1761 do_gettimeofday(&start_time); 1762 spin_unlock_irq(&chip->reg_lock); 1763 msleep(50); 1764 spin_lock_irq(&chip->reg_lock); 1765 offset = __apu_get_register(chip, apu, 5); 1766 do_gettimeofday(&stop_time); 1767 snd_es1968_trigger_apu(chip, apu, 0); /* stop */ 1768 snd_es1968_bob_dec(chip); 1769 chip->in_measurement = 0; 1770 spin_unlock_irq(&chip->reg_lock); 1771 1772 /* check the current position */ 1773 offset -= (pa & 0xffff); 1774 offset &= 0xfffe; 1775 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2); 1776 1777 t = stop_time.tv_sec - start_time.tv_sec; 1778 t *= 1000000; 1779 if (stop_time.tv_usec < start_time.tv_usec) 1780 t -= start_time.tv_usec - stop_time.tv_usec; 1781 else 1782 t += stop_time.tv_usec - start_time.tv_usec; 1783 if (t == 0) { 1784 snd_printk(KERN_ERR "?? calculation error..\n"); 1785 } else { 1786 offset *= 1000; 1787 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t; 1788 if (offset < 47500 || offset > 48500) { 1789 if (offset >= 40000 && offset <= 50000) 1790 chip->clock = (chip->clock * offset) / 48000; 1791 } 1792 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock); 1793 } 1794 snd_es1968_free_memory(chip, memory); 1795 snd_es1968_free_apu_pair(chip, apu); 1796 } 1797 1798 1799 /* 1800 */ 1801 1802 static void snd_es1968_pcm_free(struct snd_pcm *pcm) 1803 { 1804 struct es1968 *esm = pcm->private_data; 1805 snd_es1968_free_dmabuf(esm); 1806 esm->pcm = NULL; 1807 } 1808 1809 static int __devinit 1810 snd_es1968_pcm(struct es1968 *chip, int device) 1811 { 1812 struct snd_pcm *pcm; 1813 int err; 1814 1815 /* get DMA buffer */ 1816 if ((err = snd_es1968_init_dmabuf(chip)) < 0) 1817 return err; 1818 1819 /* set PCMBAR */ 1820 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 1821 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12); 1822 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12); 1823 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12); 1824 1825 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device, 1826 chip->playback_streams, 1827 chip->capture_streams, &pcm)) < 0) 1828 return err; 1829 1830 pcm->private_data = chip; 1831 pcm->private_free = snd_es1968_pcm_free; 1832 1833 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops); 1834 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops); 1835 1836 pcm->info_flags = 0; 1837 1838 strcpy(pcm->name, "ESS Maestro"); 1839 1840 chip->pcm = pcm; 1841 1842 return 0; 1843 } 1844 /* 1845 * suppress jitter on some maestros when playing stereo 1846 */ 1847 static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es) 1848 { 1849 unsigned int cp1; 1850 unsigned int cp2; 1851 unsigned int diff; 1852 1853 cp1 = __apu_get_register(chip, 0, 5); 1854 cp2 = __apu_get_register(chip, 1, 5); 1855 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1); 1856 1857 if (diff > 1) 1858 __maestro_write(chip, IDR0_DATA_PORT, cp1); 1859 } 1860 1861 /* 1862 * update pointer 1863 */ 1864 static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es) 1865 { 1866 unsigned int hwptr; 1867 unsigned int diff; 1868 struct snd_pcm_substream *subs = es->substream; 1869 1870 if (subs == NULL || !es->running) 1871 return; 1872 1873 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1874 hwptr %= es->dma_size; 1875 1876 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size; 1877 1878 es->hwptr = hwptr; 1879 es->count += diff; 1880 1881 if (es->count > es->frag_size) { 1882 spin_unlock(&chip->substream_lock); 1883 snd_pcm_period_elapsed(subs); 1884 spin_lock(&chip->substream_lock); 1885 es->count %= es->frag_size; 1886 } 1887 } 1888 1889 /* The hardware volume works by incrementing / decrementing 2 counters 1890 (without wrap around) in response to volume button presses and then 1891 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7 1892 of a byte wide register. The meaning of bits 0 and 4 is unknown. */ 1893 static void es1968_update_hw_volume(struct work_struct *work) 1894 { 1895 struct es1968 *chip = container_of(work, struct es1968, hwvol_work); 1896 int x, val; 1897 1898 /* Figure out which volume control button was pushed, 1899 based on differences from the default register 1900 values. */ 1901 x = inb(chip->io_port + 0x1c) & 0xee; 1902 /* Reset the volume control registers. */ 1903 outb(0x88, chip->io_port + 0x1c); 1904 outb(0x88, chip->io_port + 0x1d); 1905 outb(0x88, chip->io_port + 0x1e); 1906 outb(0x88, chip->io_port + 0x1f); 1907 1908 if (chip->in_suspend) 1909 return; 1910 1911 #ifndef CONFIG_SND_ES1968_INPUT 1912 if (! chip->master_switch || ! chip->master_volume) 1913 return; 1914 1915 val = snd_ac97_read(chip->ac97, AC97_MASTER); 1916 switch (x) { 1917 case 0x88: 1918 /* mute */ 1919 val ^= 0x8000; 1920 break; 1921 case 0xaa: 1922 /* volume up */ 1923 if ((val & 0x7f) > 0) 1924 val--; 1925 if ((val & 0x7f00) > 0) 1926 val -= 0x0100; 1927 break; 1928 case 0x66: 1929 /* volume down */ 1930 if ((val & 0x7f) < 0x1f) 1931 val++; 1932 if ((val & 0x7f00) < 0x1f00) 1933 val += 0x0100; 1934 break; 1935 } 1936 if (snd_ac97_update(chip->ac97, AC97_MASTER, val)) 1937 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1938 &chip->master_volume->id); 1939 #else 1940 if (!chip->input_dev) 1941 return; 1942 1943 val = 0; 1944 switch (x) { 1945 case 0x88: 1946 /* The counters have not changed, yet we've received a HV 1947 interrupt. According to tests run by various people this 1948 happens when pressing the mute button. */ 1949 val = KEY_MUTE; 1950 break; 1951 case 0xaa: 1952 /* counters increased by 1 -> volume up */ 1953 val = KEY_VOLUMEUP; 1954 break; 1955 case 0x66: 1956 /* counters decreased by 1 -> volume down */ 1957 val = KEY_VOLUMEDOWN; 1958 break; 1959 } 1960 1961 if (val) { 1962 input_report_key(chip->input_dev, val, 1); 1963 input_sync(chip->input_dev); 1964 input_report_key(chip->input_dev, val, 0); 1965 input_sync(chip->input_dev); 1966 } 1967 #endif 1968 } 1969 1970 /* 1971 * interrupt handler 1972 */ 1973 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id) 1974 { 1975 struct es1968 *chip = dev_id; 1976 u32 event; 1977 1978 if (!(event = inb(chip->io_port + 0x1A))) 1979 return IRQ_NONE; 1980 1981 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4); 1982 1983 if (event & ESM_HWVOL_IRQ) 1984 schedule_work(&chip->hwvol_work); 1985 1986 /* else ack 'em all, i imagine */ 1987 outb(0xFF, chip->io_port + 0x1A); 1988 1989 if ((event & ESM_MPU401_IRQ) && chip->rmidi) { 1990 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); 1991 } 1992 1993 if (event & ESM_SOUND_IRQ) { 1994 struct esschan *es; 1995 spin_lock(&chip->substream_lock); 1996 list_for_each_entry(es, &chip->substream_list, list) { 1997 if (es->running) { 1998 snd_es1968_update_pcm(chip, es); 1999 if (es->fmt & ESS_FMT_STEREO) 2000 snd_es1968_suppress_jitter(chip, es); 2001 } 2002 } 2003 spin_unlock(&chip->substream_lock); 2004 if (chip->in_measurement) { 2005 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5); 2006 if (curp < chip->measure_lastpos) 2007 chip->measure_count++; 2008 chip->measure_lastpos = curp; 2009 } 2010 } 2011 2012 return IRQ_HANDLED; 2013 } 2014 2015 /* 2016 * Mixer stuff 2017 */ 2018 2019 static int __devinit 2020 snd_es1968_mixer(struct es1968 *chip) 2021 { 2022 struct snd_ac97_bus *pbus; 2023 struct snd_ac97_template ac97; 2024 #ifndef CONFIG_SND_ES1968_INPUT 2025 struct snd_ctl_elem_id elem_id; 2026 #endif 2027 int err; 2028 static struct snd_ac97_bus_ops ops = { 2029 .write = snd_es1968_ac97_write, 2030 .read = snd_es1968_ac97_read, 2031 }; 2032 2033 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) 2034 return err; 2035 pbus->no_vra = 1; /* ES1968 doesn't need VRA */ 2036 2037 memset(&ac97, 0, sizeof(ac97)); 2038 ac97.private_data = chip; 2039 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0) 2040 return err; 2041 2042 #ifndef CONFIG_SND_ES1968_INPUT 2043 /* attach master switch / volumes for h/w volume control */ 2044 memset(&elem_id, 0, sizeof(elem_id)); 2045 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2046 strcpy(elem_id.name, "Master Playback Switch"); 2047 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id); 2048 memset(&elem_id, 0, sizeof(elem_id)); 2049 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2050 strcpy(elem_id.name, "Master Playback Volume"); 2051 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id); 2052 #endif 2053 2054 return 0; 2055 } 2056 2057 /* 2058 * reset ac97 codec 2059 */ 2060 2061 static void snd_es1968_ac97_reset(struct es1968 *chip) 2062 { 2063 unsigned long ioaddr = chip->io_port; 2064 2065 unsigned short save_ringbus_a; 2066 unsigned short save_68; 2067 unsigned short w; 2068 unsigned int vend; 2069 2070 /* save configuration */ 2071 save_ringbus_a = inw(ioaddr + 0x36); 2072 2073 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */ 2074 /* set command/status address i/o to 1st codec */ 2075 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2076 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2077 2078 /* disable ac link */ 2079 outw(0x0000, ioaddr + 0x36); 2080 save_68 = inw(ioaddr + 0x68); 2081 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */ 2082 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2083 if (w & 1) 2084 save_68 |= 0x10; 2085 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */ 2086 outw(0x0001, ioaddr + 0x68); /* gpio write */ 2087 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */ 2088 udelay(20); 2089 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */ 2090 msleep(20); 2091 2092 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */ 2093 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38); 2094 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a); 2095 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c); 2096 2097 /* now the second codec */ 2098 /* disable ac link */ 2099 outw(0x0000, ioaddr + 0x36); 2100 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */ 2101 save_68 = inw(ioaddr + 0x68); 2102 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */ 2103 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */ 2104 udelay(20); 2105 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */ 2106 msleep(500); 2107 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); 2108 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2109 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2110 2111 #if 0 /* the loop here needs to be much better if we want it.. */ 2112 snd_printk(KERN_INFO "trying software reset\n"); 2113 /* try and do a software reset */ 2114 outb(0x80 | 0x7c, ioaddr + 0x30); 2115 for (w = 0;; w++) { 2116 if ((inw(ioaddr + 0x30) & 1) == 0) { 2117 if (inb(ioaddr + 0x32) != 0) 2118 break; 2119 2120 outb(0x80 | 0x7d, ioaddr + 0x30); 2121 if (((inw(ioaddr + 0x30) & 1) == 0) 2122 && (inb(ioaddr + 0x32) != 0)) 2123 break; 2124 outb(0x80 | 0x7f, ioaddr + 0x30); 2125 if (((inw(ioaddr + 0x30) & 1) == 0) 2126 && (inb(ioaddr + 0x32) != 0)) 2127 break; 2128 } 2129 2130 if (w > 10000) { 2131 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */ 2132 msleep(500); /* oh my.. */ 2133 outb(inb(ioaddr + 0x37) & ~0x08, 2134 ioaddr + 0x37); 2135 udelay(1); 2136 outw(0x80, ioaddr + 0x30); 2137 for (w = 0; w < 10000; w++) { 2138 if ((inw(ioaddr + 0x30) & 1) == 0) 2139 break; 2140 } 2141 } 2142 } 2143 #endif 2144 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) { 2145 /* turn on external amp? */ 2146 outw(0xf9ff, ioaddr + 0x64); 2147 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68); 2148 outw(0x0209, ioaddr + 0x60); 2149 } 2150 2151 /* restore.. */ 2152 outw(save_ringbus_a, ioaddr + 0x36); 2153 2154 /* Turn on the 978 docking chip. 2155 First frob the "master output enable" bit, 2156 then set most of the playback volume control registers to max. */ 2157 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0); 2158 outb(0xff, ioaddr+0xc3); 2159 outb(0xff, ioaddr+0xc4); 2160 outb(0xff, ioaddr+0xc6); 2161 outb(0xff, ioaddr+0xc8); 2162 outb(0x3f, ioaddr+0xcf); 2163 outb(0x3f, ioaddr+0xd0); 2164 } 2165 2166 static void snd_es1968_reset(struct es1968 *chip) 2167 { 2168 /* Reset */ 2169 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND, 2170 chip->io_port + ESM_PORT_HOST_IRQ); 2171 udelay(10); 2172 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ); 2173 udelay(10); 2174 } 2175 2176 /* 2177 * initialize maestro chip 2178 */ 2179 static void snd_es1968_chip_init(struct es1968 *chip) 2180 { 2181 struct pci_dev *pci = chip->pci; 2182 int i; 2183 unsigned long iobase = chip->io_port; 2184 u16 w; 2185 u32 n; 2186 2187 /* We used to muck around with pci config space that 2188 * we had no business messing with. We don't know enough 2189 * about the machine to know which DMA mode is appropriate, 2190 * etc. We were guessing wrong on some machines and making 2191 * them unhappy. We now trust in the BIOS to do things right, 2192 * which almost certainly means a new host of problems will 2193 * arise with broken BIOS implementations. screw 'em. 2194 * We're already intolerant of machines that don't assign 2195 * IRQs. 2196 */ 2197 2198 /* Config Reg A */ 2199 pci_read_config_word(pci, ESM_CONFIG_A, &w); 2200 2201 w &= ~DMA_CLEAR; /* Clear DMA bits */ 2202 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */ 2203 w &= ~SAFEGUARD; /* Safeguard off */ 2204 w |= POST_WRITE; /* Posted write */ 2205 w |= PCI_TIMING; /* PCI timing on */ 2206 /* XXX huh? claims to be reserved.. */ 2207 w &= ~SWAP_LR; /* swap left/right 2208 seems to only have effect on SB 2209 Emulation */ 2210 w &= ~SUBTR_DECODE; /* Subtractive decode off */ 2211 2212 pci_write_config_word(pci, ESM_CONFIG_A, w); 2213 2214 /* Config Reg B */ 2215 2216 pci_read_config_word(pci, ESM_CONFIG_B, &w); 2217 2218 w &= ~(1 << 15); /* Turn off internal clock multiplier */ 2219 /* XXX how do we know which to use? */ 2220 w &= ~(1 << 14); /* External clock */ 2221 2222 w &= ~SPDIF_CONFB; /* disable S/PDIF output */ 2223 w |= HWV_CONFB; /* HWV on */ 2224 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */ 2225 w &= ~GPIO_CONFB; /* GPIO 4:5 */ 2226 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */ 2227 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */ 2228 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */ 2229 w &= ~(1 << 1); /* reserved, always write 0 */ 2230 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */ 2231 2232 pci_write_config_word(pci, ESM_CONFIG_B, w); 2233 2234 /* DDMA off */ 2235 2236 pci_read_config_word(pci, ESM_DDMA, &w); 2237 w &= ~(1 << 0); 2238 pci_write_config_word(pci, ESM_DDMA, w); 2239 2240 /* 2241 * Legacy mode 2242 */ 2243 2244 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w); 2245 2246 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */ 2247 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */ 2248 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */ 2249 2250 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w); 2251 2252 /* Set up 978 docking control chip. */ 2253 pci_read_config_word(pci, 0x58, &w); 2254 w|=1<<2; /* Enable 978. */ 2255 w|=1<<3; /* Turn on 978 hardware volume control. */ 2256 w&=~(1<<11); /* Turn on 978 mixer volume control. */ 2257 pci_write_config_word(pci, 0x58, w); 2258 2259 /* Sound Reset */ 2260 2261 snd_es1968_reset(chip); 2262 2263 /* 2264 * Ring Bus Setup 2265 */ 2266 2267 /* setup usual 0x34 stuff.. 0x36 may be chip specific */ 2268 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */ 2269 udelay(20); 2270 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */ 2271 udelay(20); 2272 2273 /* 2274 * Reset the CODEC 2275 */ 2276 2277 snd_es1968_ac97_reset(chip); 2278 2279 /* Ring Bus Control B */ 2280 2281 n = inl(iobase + ESM_RING_BUS_CONTR_B); 2282 n &= ~RINGB_EN_SPDIF; /* SPDIF off */ 2283 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */ 2284 outl(n, iobase + ESM_RING_BUS_CONTR_B); 2285 2286 /* Set hardware volume control registers to midpoints. 2287 We can tell which button was pushed based on how they change. */ 2288 outb(0x88, iobase+0x1c); 2289 outb(0x88, iobase+0x1d); 2290 outb(0x88, iobase+0x1e); 2291 outb(0x88, iobase+0x1f); 2292 2293 /* it appears some maestros (dell 7500) only work if these are set, 2294 regardless of wether we use the assp or not. */ 2295 2296 outb(0, iobase + ASSP_CONTROL_B); 2297 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */ 2298 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */ 2299 2300 /* 2301 * set up wavecache 2302 */ 2303 for (i = 0; i < 16; i++) { 2304 /* Write 0 into the buffer area 0x1E0->1EF */ 2305 outw(0x01E0 + i, iobase + WC_INDEX); 2306 outw(0x0000, iobase + WC_DATA); 2307 2308 /* The 1.10 test program seem to write 0 into the buffer area 2309 * 0x1D0-0x1DF too.*/ 2310 outw(0x01D0 + i, iobase + WC_INDEX); 2311 outw(0x0000, iobase + WC_DATA); 2312 } 2313 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2314 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00)); 2315 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2316 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100); 2317 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2318 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200); 2319 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2320 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400); 2321 2322 2323 maestro_write(chip, IDR2_CRAM_DATA, 0x0000); 2324 /* Now back to the DirectSound stuff */ 2325 /* audio serial configuration.. ? */ 2326 maestro_write(chip, 0x08, 0xB004); 2327 maestro_write(chip, 0x09, 0x001B); 2328 maestro_write(chip, 0x0A, 0x8000); 2329 maestro_write(chip, 0x0B, 0x3F37); 2330 maestro_write(chip, 0x0C, 0x0098); 2331 2332 /* parallel in, has something to do with recording :) */ 2333 maestro_write(chip, 0x0C, 2334 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000); 2335 /* parallel out */ 2336 maestro_write(chip, 0x0C, 2337 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500); 2338 2339 maestro_write(chip, 0x0D, 0x7632); 2340 2341 /* Wave cache control on - test off, sg off, 2342 enable, enable extra chans 1Mb */ 2343 2344 w = inw(iobase + WC_CONTROL); 2345 2346 w &= ~0xFA00; /* Seems to be reserved? I don't know */ 2347 w |= 0xA000; /* reserved... I don't know */ 2348 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable 2349 Seems to crash the Computer if enabled... */ 2350 w |= 0x0100; /* Wave Cache Operation Enabled */ 2351 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */ 2352 w &= ~0x0060; /* Clear Wavtable Size */ 2353 w |= 0x0020; /* Wavetable Size : 1MB */ 2354 /* Bit 4 is reserved */ 2355 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */ 2356 /* Bit 1 is reserved */ 2357 w &= ~0x0001; /* Test Mode off */ 2358 2359 outw(w, iobase + WC_CONTROL); 2360 2361 /* Now clear the APU control ram */ 2362 for (i = 0; i < NR_APUS; i++) { 2363 for (w = 0; w < NR_APU_REGS; w++) 2364 apu_set_register(chip, i, w, 0); 2365 2366 } 2367 } 2368 2369 /* Enable IRQ's */ 2370 static void snd_es1968_start_irq(struct es1968 *chip) 2371 { 2372 unsigned short w; 2373 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME; 2374 if (chip->rmidi) 2375 w |= ESM_HIRQ_MPU401; 2376 outb(w, chip->io_port + 0x1A); 2377 outw(w, chip->io_port + ESM_PORT_HOST_IRQ); 2378 } 2379 2380 #ifdef CONFIG_PM 2381 /* 2382 * PM support 2383 */ 2384 static int es1968_suspend(struct device *dev) 2385 { 2386 struct pci_dev *pci = to_pci_dev(dev); 2387 struct snd_card *card = dev_get_drvdata(dev); 2388 struct es1968 *chip = card->private_data; 2389 2390 if (! chip->do_pm) 2391 return 0; 2392 2393 chip->in_suspend = 1; 2394 cancel_work_sync(&chip->hwvol_work); 2395 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2396 snd_pcm_suspend_all(chip->pcm); 2397 snd_ac97_suspend(chip->ac97); 2398 snd_es1968_bob_stop(chip); 2399 2400 pci_disable_device(pci); 2401 pci_save_state(pci); 2402 pci_set_power_state(pci, PCI_D3hot); 2403 return 0; 2404 } 2405 2406 static int es1968_resume(struct device *dev) 2407 { 2408 struct pci_dev *pci = to_pci_dev(dev); 2409 struct snd_card *card = dev_get_drvdata(dev); 2410 struct es1968 *chip = card->private_data; 2411 struct esschan *es; 2412 2413 if (! chip->do_pm) 2414 return 0; 2415 2416 /* restore all our config */ 2417 pci_set_power_state(pci, PCI_D0); 2418 pci_restore_state(pci); 2419 if (pci_enable_device(pci) < 0) { 2420 printk(KERN_ERR "es1968: pci_enable_device failed, " 2421 "disabling device\n"); 2422 snd_card_disconnect(card); 2423 return -EIO; 2424 } 2425 pci_set_master(pci); 2426 2427 snd_es1968_chip_init(chip); 2428 2429 /* need to restore the base pointers.. */ 2430 if (chip->dma.addr) { 2431 /* set PCMBAR */ 2432 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 2433 } 2434 2435 snd_es1968_start_irq(chip); 2436 2437 /* restore ac97 state */ 2438 snd_ac97_resume(chip->ac97); 2439 2440 list_for_each_entry(es, &chip->substream_list, list) { 2441 switch (es->mode) { 2442 case ESM_MODE_PLAY: 2443 snd_es1968_playback_setup(chip, es, es->substream->runtime); 2444 break; 2445 case ESM_MODE_CAPTURE: 2446 snd_es1968_capture_setup(chip, es, es->substream->runtime); 2447 break; 2448 } 2449 } 2450 2451 /* start timer again */ 2452 if (chip->bobclient) 2453 snd_es1968_bob_start(chip); 2454 2455 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2456 chip->in_suspend = 0; 2457 return 0; 2458 } 2459 2460 static SIMPLE_DEV_PM_OPS(es1968_pm, es1968_suspend, es1968_resume); 2461 #define ES1968_PM_OPS &es1968_pm 2462 #else 2463 #define ES1968_PM_OPS NULL 2464 #endif /* CONFIG_PM */ 2465 2466 #ifdef SUPPORT_JOYSTICK 2467 #define JOYSTICK_ADDR 0x200 2468 static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev) 2469 { 2470 struct gameport *gp; 2471 struct resource *r; 2472 u16 val; 2473 2474 if (!joystick[dev]) 2475 return -ENODEV; 2476 2477 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport"); 2478 if (!r) 2479 return -EBUSY; 2480 2481 chip->gameport = gp = gameport_allocate_port(); 2482 if (!gp) { 2483 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n"); 2484 release_and_free_resource(r); 2485 return -ENOMEM; 2486 } 2487 2488 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val); 2489 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04); 2490 2491 gameport_set_name(gp, "ES1968 Gameport"); 2492 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2493 gameport_set_dev_parent(gp, &chip->pci->dev); 2494 gp->io = JOYSTICK_ADDR; 2495 gameport_set_port_data(gp, r); 2496 2497 gameport_register_port(gp); 2498 2499 return 0; 2500 } 2501 2502 static void snd_es1968_free_gameport(struct es1968 *chip) 2503 { 2504 if (chip->gameport) { 2505 struct resource *r = gameport_get_port_data(chip->gameport); 2506 2507 gameport_unregister_port(chip->gameport); 2508 chip->gameport = NULL; 2509 2510 release_and_free_resource(r); 2511 } 2512 } 2513 #else 2514 static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; } 2515 static inline void snd_es1968_free_gameport(struct es1968 *chip) { } 2516 #endif 2517 2518 #ifdef CONFIG_SND_ES1968_INPUT 2519 static int __devinit snd_es1968_input_register(struct es1968 *chip) 2520 { 2521 struct input_dev *input_dev; 2522 int err; 2523 2524 input_dev = input_allocate_device(); 2525 if (!input_dev) 2526 return -ENOMEM; 2527 2528 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0", 2529 pci_name(chip->pci)); 2530 2531 input_dev->name = chip->card->driver; 2532 input_dev->phys = chip->phys; 2533 input_dev->id.bustype = BUS_PCI; 2534 input_dev->id.vendor = chip->pci->vendor; 2535 input_dev->id.product = chip->pci->device; 2536 input_dev->dev.parent = &chip->pci->dev; 2537 2538 __set_bit(EV_KEY, input_dev->evbit); 2539 __set_bit(KEY_MUTE, input_dev->keybit); 2540 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit); 2541 __set_bit(KEY_VOLUMEUP, input_dev->keybit); 2542 2543 err = input_register_device(input_dev); 2544 if (err) { 2545 input_free_device(input_dev); 2546 return err; 2547 } 2548 2549 chip->input_dev = input_dev; 2550 return 0; 2551 } 2552 #endif /* CONFIG_SND_ES1968_INPUT */ 2553 2554 #ifdef CONFIG_SND_ES1968_RADIO 2555 #define GPIO_DATA 0x60 2556 #define IO_MASK 4 /* mask register offset from GPIO_DATA 2557 bits 1=unmask write to given bit */ 2558 #define IO_DIR 8 /* direction register offset from GPIO_DATA 2559 bits 0/1=read/write direction */ 2560 /* mask bits for GPIO lines */ 2561 #define STR_DATA 0x0040 /* GPIO6 */ 2562 #define STR_CLK 0x0080 /* GPIO7 */ 2563 #define STR_WREN 0x0100 /* GPIO8 */ 2564 #define STR_MOST 0x0200 /* GPIO9 */ 2565 2566 static void snd_es1968_tea575x_set_pins(struct snd_tea575x *tea, u8 pins) 2567 { 2568 struct es1968 *chip = tea->private_data; 2569 unsigned long io = chip->io_port + GPIO_DATA; 2570 u16 val = 0; 2571 2572 val |= (pins & TEA575X_DATA) ? STR_DATA : 0; 2573 val |= (pins & TEA575X_CLK) ? STR_CLK : 0; 2574 val |= (pins & TEA575X_WREN) ? STR_WREN : 0; 2575 2576 outw(val, io); 2577 } 2578 2579 static u8 snd_es1968_tea575x_get_pins(struct snd_tea575x *tea) 2580 { 2581 struct es1968 *chip = tea->private_data; 2582 unsigned long io = chip->io_port + GPIO_DATA; 2583 u16 val = inw(io); 2584 2585 return (val & STR_DATA) ? TEA575X_DATA : 0 | 2586 (val & STR_MOST) ? TEA575X_MOST : 0; 2587 } 2588 2589 static void snd_es1968_tea575x_set_direction(struct snd_tea575x *tea, bool output) 2590 { 2591 struct es1968 *chip = tea->private_data; 2592 unsigned long io = chip->io_port + GPIO_DATA; 2593 u16 odir = inw(io + IO_DIR); 2594 2595 if (output) { 2596 outw(~(STR_DATA | STR_CLK | STR_WREN), io + IO_MASK); 2597 outw(odir | STR_DATA | STR_CLK | STR_WREN, io + IO_DIR); 2598 } else { 2599 outw(~(STR_CLK | STR_WREN | STR_DATA | STR_MOST), io + IO_MASK); 2600 outw((odir & ~(STR_DATA | STR_MOST)) | STR_CLK | STR_WREN, io + IO_DIR); 2601 } 2602 } 2603 2604 static struct snd_tea575x_ops snd_es1968_tea_ops = { 2605 .set_pins = snd_es1968_tea575x_set_pins, 2606 .get_pins = snd_es1968_tea575x_get_pins, 2607 .set_direction = snd_es1968_tea575x_set_direction, 2608 }; 2609 #endif 2610 2611 static int snd_es1968_free(struct es1968 *chip) 2612 { 2613 cancel_work_sync(&chip->hwvol_work); 2614 #ifdef CONFIG_SND_ES1968_INPUT 2615 if (chip->input_dev) 2616 input_unregister_device(chip->input_dev); 2617 #endif 2618 2619 if (chip->io_port) { 2620 if (chip->irq >= 0) 2621 synchronize_irq(chip->irq); 2622 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 2623 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */ 2624 } 2625 2626 #ifdef CONFIG_SND_ES1968_RADIO 2627 snd_tea575x_exit(&chip->tea); 2628 v4l2_device_unregister(&chip->v4l2_dev); 2629 #endif 2630 2631 if (chip->irq >= 0) 2632 free_irq(chip->irq, chip); 2633 snd_es1968_free_gameport(chip); 2634 pci_release_regions(chip->pci); 2635 pci_disable_device(chip->pci); 2636 kfree(chip); 2637 return 0; 2638 } 2639 2640 static int snd_es1968_dev_free(struct snd_device *device) 2641 { 2642 struct es1968 *chip = device->device_data; 2643 return snd_es1968_free(chip); 2644 } 2645 2646 struct ess_device_list { 2647 unsigned short type; /* chip type */ 2648 unsigned short vendor; /* subsystem vendor id */ 2649 }; 2650 2651 static struct ess_device_list pm_whitelist[] __devinitdata = { 2652 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */ 2653 { TYPE_MAESTRO2E, 0x1028 }, 2654 { TYPE_MAESTRO2E, 0x103c }, 2655 { TYPE_MAESTRO2E, 0x1179 }, 2656 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */ 2657 { TYPE_MAESTRO2E, 0x1558 }, 2658 }; 2659 2660 static struct ess_device_list mpu_blacklist[] __devinitdata = { 2661 { TYPE_MAESTRO2, 0x125d }, 2662 }; 2663 2664 static int __devinit snd_es1968_create(struct snd_card *card, 2665 struct pci_dev *pci, 2666 int total_bufsize, 2667 int play_streams, 2668 int capt_streams, 2669 int chip_type, 2670 int do_pm, 2671 int radio_nr, 2672 struct es1968 **chip_ret) 2673 { 2674 static struct snd_device_ops ops = { 2675 .dev_free = snd_es1968_dev_free, 2676 }; 2677 struct es1968 *chip; 2678 int i, err; 2679 2680 *chip_ret = NULL; 2681 2682 /* enable PCI device */ 2683 if ((err = pci_enable_device(pci)) < 0) 2684 return err; 2685 /* check, if we can restrict PCI DMA transfers to 28 bits */ 2686 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 || 2687 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) { 2688 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n"); 2689 pci_disable_device(pci); 2690 return -ENXIO; 2691 } 2692 2693 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2694 if (! chip) { 2695 pci_disable_device(pci); 2696 return -ENOMEM; 2697 } 2698 2699 /* Set Vars */ 2700 chip->type = chip_type; 2701 spin_lock_init(&chip->reg_lock); 2702 spin_lock_init(&chip->substream_lock); 2703 INIT_LIST_HEAD(&chip->buf_list); 2704 INIT_LIST_HEAD(&chip->substream_list); 2705 mutex_init(&chip->memory_mutex); 2706 INIT_WORK(&chip->hwvol_work, es1968_update_hw_volume); 2707 chip->card = card; 2708 chip->pci = pci; 2709 chip->irq = -1; 2710 chip->total_bufsize = total_bufsize; /* in bytes */ 2711 chip->playback_streams = play_streams; 2712 chip->capture_streams = capt_streams; 2713 2714 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) { 2715 kfree(chip); 2716 pci_disable_device(pci); 2717 return err; 2718 } 2719 chip->io_port = pci_resource_start(pci, 0); 2720 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED, 2721 KBUILD_MODNAME, chip)) { 2722 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2723 snd_es1968_free(chip); 2724 return -EBUSY; 2725 } 2726 chip->irq = pci->irq; 2727 2728 /* Clear Maestro_map */ 2729 for (i = 0; i < 32; i++) 2730 chip->maestro_map[i] = 0; 2731 2732 /* Clear Apu Map */ 2733 for (i = 0; i < NR_APUS; i++) 2734 chip->apu[i] = ESM_APU_FREE; 2735 2736 /* just to be sure */ 2737 pci_set_master(pci); 2738 2739 if (do_pm > 1) { 2740 /* disable power-management if not on the whitelist */ 2741 unsigned short vend; 2742 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2743 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) { 2744 if (chip->type == pm_whitelist[i].type && 2745 vend == pm_whitelist[i].vendor) { 2746 do_pm = 1; 2747 break; 2748 } 2749 } 2750 if (do_pm > 1) { 2751 /* not matched; disabling pm */ 2752 printk(KERN_INFO "es1968: not attempting power management.\n"); 2753 do_pm = 0; 2754 } 2755 } 2756 chip->do_pm = do_pm; 2757 2758 snd_es1968_chip_init(chip); 2759 2760 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2761 snd_es1968_free(chip); 2762 return err; 2763 } 2764 2765 snd_card_set_dev(card, &pci->dev); 2766 2767 #ifdef CONFIG_SND_ES1968_RADIO 2768 err = v4l2_device_register(&pci->dev, &chip->v4l2_dev); 2769 if (err < 0) { 2770 snd_es1968_free(chip); 2771 return err; 2772 } 2773 chip->tea.v4l2_dev = &chip->v4l2_dev; 2774 chip->tea.private_data = chip; 2775 chip->tea.radio_nr = radio_nr; 2776 chip->tea.ops = &snd_es1968_tea_ops; 2777 strlcpy(chip->tea.card, "SF64-PCE2", sizeof(chip->tea.card)); 2778 sprintf(chip->tea.bus_info, "PCI:%s", pci_name(pci)); 2779 if (!snd_tea575x_init(&chip->tea, THIS_MODULE)) 2780 printk(KERN_INFO "es1968: detected TEA575x radio\n"); 2781 #endif 2782 2783 *chip_ret = chip; 2784 2785 return 0; 2786 } 2787 2788 2789 /* 2790 */ 2791 static int __devinit snd_es1968_probe(struct pci_dev *pci, 2792 const struct pci_device_id *pci_id) 2793 { 2794 static int dev; 2795 struct snd_card *card; 2796 struct es1968 *chip; 2797 unsigned int i; 2798 int err; 2799 2800 if (dev >= SNDRV_CARDS) 2801 return -ENODEV; 2802 if (!enable[dev]) { 2803 dev++; 2804 return -ENOENT; 2805 } 2806 2807 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 2808 if (err < 0) 2809 return err; 2810 2811 if (total_bufsize[dev] < 128) 2812 total_bufsize[dev] = 128; 2813 if (total_bufsize[dev] > 4096) 2814 total_bufsize[dev] = 4096; 2815 if ((err = snd_es1968_create(card, pci, 2816 total_bufsize[dev] * 1024, /* in bytes */ 2817 pcm_substreams_p[dev], 2818 pcm_substreams_c[dev], 2819 pci_id->driver_data, 2820 use_pm[dev], 2821 radio_nr[dev], 2822 &chip)) < 0) { 2823 snd_card_free(card); 2824 return err; 2825 } 2826 card->private_data = chip; 2827 2828 switch (chip->type) { 2829 case TYPE_MAESTRO2E: 2830 strcpy(card->driver, "ES1978"); 2831 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)"); 2832 break; 2833 case TYPE_MAESTRO2: 2834 strcpy(card->driver, "ES1968"); 2835 strcpy(card->shortname, "ESS ES1968 (Maestro 2)"); 2836 break; 2837 case TYPE_MAESTRO: 2838 strcpy(card->driver, "ESM1"); 2839 strcpy(card->shortname, "ESS Maestro 1"); 2840 break; 2841 } 2842 2843 if ((err = snd_es1968_pcm(chip, 0)) < 0) { 2844 snd_card_free(card); 2845 return err; 2846 } 2847 2848 if ((err = snd_es1968_mixer(chip)) < 0) { 2849 snd_card_free(card); 2850 return err; 2851 } 2852 2853 if (enable_mpu[dev] == 2) { 2854 /* check the black list */ 2855 unsigned short vend; 2856 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2857 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) { 2858 if (chip->type == mpu_blacklist[i].type && 2859 vend == mpu_blacklist[i].vendor) { 2860 enable_mpu[dev] = 0; 2861 break; 2862 } 2863 } 2864 } 2865 if (enable_mpu[dev]) { 2866 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401, 2867 chip->io_port + ESM_MPU401_PORT, 2868 MPU401_INFO_INTEGRATED | 2869 MPU401_INFO_IRQ_HOOK, 2870 -1, &chip->rmidi)) < 0) { 2871 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n"); 2872 } 2873 } 2874 2875 snd_es1968_create_gameport(chip, dev); 2876 2877 #ifdef CONFIG_SND_ES1968_INPUT 2878 err = snd_es1968_input_register(chip); 2879 if (err) 2880 snd_printk(KERN_WARNING "Input device registration " 2881 "failed with error %i", err); 2882 #endif 2883 2884 snd_es1968_start_irq(chip); 2885 2886 chip->clock = clock[dev]; 2887 if (! chip->clock) 2888 es1968_measure_clock(chip); 2889 2890 sprintf(card->longname, "%s at 0x%lx, irq %i", 2891 card->shortname, chip->io_port, chip->irq); 2892 2893 if ((err = snd_card_register(card)) < 0) { 2894 snd_card_free(card); 2895 return err; 2896 } 2897 pci_set_drvdata(pci, card); 2898 dev++; 2899 return 0; 2900 } 2901 2902 static void __devexit snd_es1968_remove(struct pci_dev *pci) 2903 { 2904 snd_card_free(pci_get_drvdata(pci)); 2905 pci_set_drvdata(pci, NULL); 2906 } 2907 2908 static struct pci_driver es1968_driver = { 2909 .name = KBUILD_MODNAME, 2910 .id_table = snd_es1968_ids, 2911 .probe = snd_es1968_probe, 2912 .remove = __devexit_p(snd_es1968_remove), 2913 .driver = { 2914 .pm = ES1968_PM_OPS, 2915 }, 2916 }; 2917 2918 module_pci_driver(es1968_driver); 2919