1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard 4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 5 * Thomas Sailer <sailer@ife.ee.ethz.ch> 6 */ 7 8 /* Power-Management-Code ( CONFIG_PM ) 9 * for ens1371 only ( FIXME ) 10 * derived from cs4281.c, atiixp.c and via82xx.c 11 * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/ 12 * by Kurt J. Bosch 13 */ 14 15 #include <linux/io.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/init.h> 19 #include <linux/pci.h> 20 #include <linux/slab.h> 21 #include <linux/gameport.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 25 #include <sound/core.h> 26 #include <sound/control.h> 27 #include <sound/pcm.h> 28 #include <sound/rawmidi.h> 29 #ifdef CHIP1371 30 #include <sound/ac97_codec.h> 31 #else 32 #include <sound/ak4531_codec.h> 33 #endif 34 #include <sound/initval.h> 35 #include <sound/asoundef.h> 36 37 #ifndef CHIP1371 38 #undef CHIP1370 39 #define CHIP1370 40 #endif 41 42 #ifdef CHIP1370 43 #define DRIVER_NAME "ENS1370" 44 #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */ 45 #else 46 #define DRIVER_NAME "ENS1371" 47 #define CHIP_NAME "ES1371" 48 #endif 49 50 51 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>"); 52 MODULE_LICENSE("GPL"); 53 #ifdef CHIP1370 54 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370"); 55 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370}," 56 "{Creative Labs,SB PCI64/128 (ES1370)}}"); 57 #endif 58 #ifdef CHIP1371 59 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+"); 60 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73}," 61 "{Ensoniq,AudioPCI ES1373}," 62 "{Creative Labs,Ectiva EV1938}," 63 "{Creative Labs,SB PCI64/128 (ES1371/73)}," 64 "{Creative Labs,Vibra PCI128}," 65 "{Ectiva,EV1938}}"); 66 #endif 67 68 #if IS_REACHABLE(CONFIG_GAMEPORT) 69 #define SUPPORT_JOYSTICK 70 #endif 71 72 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 73 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 74 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 75 #ifdef SUPPORT_JOYSTICK 76 #ifdef CHIP1371 77 static int joystick_port[SNDRV_CARDS]; 78 #else 79 static bool joystick[SNDRV_CARDS]; 80 #endif 81 #endif 82 #ifdef CHIP1371 83 static int spdif[SNDRV_CARDS]; 84 static int lineio[SNDRV_CARDS]; 85 #endif 86 87 module_param_array(index, int, NULL, 0444); 88 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard."); 89 module_param_array(id, charp, NULL, 0444); 90 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard."); 91 module_param_array(enable, bool, NULL, 0444); 92 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard."); 93 #ifdef SUPPORT_JOYSTICK 94 #ifdef CHIP1371 95 module_param_hw_array(joystick_port, int, ioport, NULL, 0444); 96 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 97 #else 98 module_param_array(joystick, bool, NULL, 0444); 99 MODULE_PARM_DESC(joystick, "Enable joystick."); 100 #endif 101 #endif /* SUPPORT_JOYSTICK */ 102 #ifdef CHIP1371 103 module_param_array(spdif, int, NULL, 0444); 104 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force)."); 105 module_param_array(lineio, int, NULL, 0444); 106 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force)."); 107 #endif 108 109 /* ES1371 chip ID */ 110 /* This is a little confusing because all ES1371 compatible chips have the 111 same DEVICE_ID, the only thing differentiating them is the REV_ID field. 112 This is only significant if you want to enable features on the later parts. 113 Yes, I know it's stupid and why didn't we use the sub IDs? 114 */ 115 #define ES1371REV_ES1373_A 0x04 116 #define ES1371REV_ES1373_B 0x06 117 #define ES1371REV_CT5880_A 0x07 118 #define CT5880REV_CT5880_C 0x02 119 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */ 120 #define CT5880REV_CT5880_E 0x04 /* mw */ 121 #define ES1371REV_ES1371_B 0x09 122 #define EV1938REV_EV1938_A 0x00 123 #define ES1371REV_ES1373_8 0x08 124 125 /* 126 * Direct registers 127 */ 128 129 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x) 130 131 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */ 132 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */ 133 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */ 134 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */ 135 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */ 136 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */ 137 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */ 138 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */ 139 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */ 140 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */ 141 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */ 142 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03) 143 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */ 144 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */ 145 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */ 146 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */ 147 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */ 148 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */ 149 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */ 150 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */ 151 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */ 152 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */ 153 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */ 154 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */ 155 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */ 156 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */ 157 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */ 158 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */ 159 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */ 160 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */ 161 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */ 162 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */ 163 #define ES_BREQ (1<<7) /* memory bus request enable */ 164 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */ 165 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */ 166 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */ 167 #define ES_UART_EN (1<<3) /* UART enable */ 168 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */ 169 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */ 170 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */ 171 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */ 172 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */ 173 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */ 174 #define ES_INTR (1<<31) /* Interrupt is pending */ 175 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */ 176 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */ 177 #define ES_1373_REAR_BIT26 (1<<26) 178 #define ES_1373_REAR_BIT24 (1<<24) 179 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */ 180 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */ 181 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */ 182 #define ES_1371_TEST (1<<16) /* test ASIC */ 183 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */ 184 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */ 185 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */ 186 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */ 187 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */ 188 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */ 189 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */ 190 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */ 191 #define ES_MCCB (1<<4) /* CCB interrupt pending */ 192 #define ES_UART (1<<3) /* UART interrupt pending */ 193 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */ 194 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */ 195 #define ES_ADC (1<<0) /* ADC channel interrupt pending */ 196 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */ 197 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */ 198 #define ES_RXINT (1<<7) /* RX interrupt occurred */ 199 #define ES_TXINT (1<<2) /* TX interrupt occurred */ 200 #define ES_TXRDY (1<<1) /* transmitter ready */ 201 #define ES_RXRDY (1<<0) /* receiver ready */ 202 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */ 203 #define ES_RXINTEN (1<<7) /* RX interrupt enable */ 204 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */ 205 #define ES_TXINTENM (0x03<<5) /* mask for above */ 206 #define ES_TXINTENI(i) (((i)>>5)&0x03) 207 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */ 208 #define ES_CNTRLM (0x03<<0) /* mask for above */ 209 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */ 210 #define ES_TEST_MODE (1<<0) /* test mode enabled */ 211 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */ 212 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */ 213 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */ 214 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */ 215 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */ 216 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0)) 217 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */ 218 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */ 219 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */ 220 #define EV_1938_CODEC_MAGIC (1<<26) 221 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */ 222 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0)) 223 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD) 224 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff) 225 226 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ 227 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */ 228 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */ 229 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */ 230 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ 231 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ 232 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */ 233 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ 234 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */ 235 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */ 236 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */ 237 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */ 238 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */ 239 240 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */ 241 #define ES_1371_JFAST (1<<31) /* fast joystick timing */ 242 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */ 243 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */ 244 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */ 245 #define ES_1371_VMPUM (0x03<<27) /* mask for above */ 246 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */ 247 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */ 248 #define ES_1371_VCDCM (0x03<<25) /* mask for above */ 249 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */ 250 #define ES_1371_FIRQ (1<<24) /* force an interrupt */ 251 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */ 252 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */ 253 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */ 254 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */ 255 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */ 256 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */ 257 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */ 258 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */ 259 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */ 260 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */ 261 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */ 262 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */ 263 264 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */ 265 266 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */ 267 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */ 268 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */ 269 #define ES_P2_END_INCM (0x07<<19) /* mask for above */ 270 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */ 271 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */ 272 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */ 273 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */ 274 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */ 275 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */ 276 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */ 277 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */ 278 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */ 279 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */ 280 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */ 281 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */ 282 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */ 283 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */ 284 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */ 285 #define ES_R1_MODEM (0x03<<4) /* mask for above */ 286 #define ES_R1_MODEI(i) (((i)>>4)&0x03) 287 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */ 288 #define ES_P2_MODEM (0x03<<2) /* mask for above */ 289 #define ES_P2_MODEI(i) (((i)>>2)&0x03) 290 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */ 291 #define ES_P1_MODEM (0x03<<0) /* mask for above */ 292 #define ES_P1_MODEI(i) (((i)>>0)&0x03) 293 294 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */ 295 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */ 296 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */ 297 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff) 298 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0) 299 #define ES_REG_COUNTM (0xffff<<0) 300 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff) 301 302 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */ 303 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */ 304 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */ 305 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */ 306 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */ 307 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */ 308 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16) 309 #define ES_REG_FCURR_COUNTM (0xffff<<16) 310 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc) 311 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0) 312 #define ES_REG_FSIZEM (0xffff<<0) 313 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff) 314 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */ 315 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */ 316 317 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */ 318 #define ES_REG_UF_VALID (1<<8) 319 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0) 320 #define ES_REG_UF_BYTEM (0xff<<0) 321 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff) 322 323 324 /* 325 * Pages 326 */ 327 328 #define ES_PAGE_DAC 0x0c 329 #define ES_PAGE_ADC 0x0d 330 #define ES_PAGE_UART 0x0e 331 #define ES_PAGE_UART1 0x0f 332 333 /* 334 * Sample rate converter addresses 335 */ 336 337 #define ES_SMPREG_DAC1 0x70 338 #define ES_SMPREG_DAC2 0x74 339 #define ES_SMPREG_ADC 0x78 340 #define ES_SMPREG_VOL_ADC 0x6c 341 #define ES_SMPREG_VOL_DAC1 0x7c 342 #define ES_SMPREG_VOL_DAC2 0x7e 343 #define ES_SMPREG_TRUNC_N 0x00 344 #define ES_SMPREG_INT_REGS 0x01 345 #define ES_SMPREG_ACCUM_FRAC 0x02 346 #define ES_SMPREG_VFREQ_FRAC 0x03 347 348 /* 349 * Some contants 350 */ 351 352 #define ES_1370_SRCLOCK 1411200 353 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2) 354 355 /* 356 * Open modes 357 */ 358 359 #define ES_MODE_PLAY1 0x0001 360 #define ES_MODE_PLAY2 0x0002 361 #define ES_MODE_CAPTURE 0x0004 362 363 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */ 364 #define ES_MODE_INPUT 0x0002 /* for MIDI */ 365 366 /* 367 368 */ 369 370 struct ensoniq { 371 spinlock_t reg_lock; 372 struct mutex src_mutex; 373 374 int irq; 375 376 unsigned long playback1size; 377 unsigned long playback2size; 378 unsigned long capture3size; 379 380 unsigned long port; 381 unsigned int mode; 382 unsigned int uartm; /* UART mode */ 383 384 unsigned int ctrl; /* control register */ 385 unsigned int sctrl; /* serial control register */ 386 unsigned int cssr; /* control status register */ 387 unsigned int uartc; /* uart control register */ 388 unsigned int rev; /* chip revision */ 389 390 union { 391 #ifdef CHIP1371 392 struct { 393 struct snd_ac97 *ac97; 394 } es1371; 395 #else 396 struct { 397 int pclkdiv_lock; 398 struct snd_ak4531 *ak4531; 399 } es1370; 400 #endif 401 } u; 402 403 struct pci_dev *pci; 404 struct snd_card *card; 405 struct snd_pcm *pcm1; /* DAC1/ADC PCM */ 406 struct snd_pcm *pcm2; /* DAC2 PCM */ 407 struct snd_pcm_substream *playback1_substream; 408 struct snd_pcm_substream *playback2_substream; 409 struct snd_pcm_substream *capture_substream; 410 unsigned int p1_dma_size; 411 unsigned int p2_dma_size; 412 unsigned int c_dma_size; 413 unsigned int p1_period_size; 414 unsigned int p2_period_size; 415 unsigned int c_period_size; 416 struct snd_rawmidi *rmidi; 417 struct snd_rawmidi_substream *midi_input; 418 struct snd_rawmidi_substream *midi_output; 419 420 unsigned int spdif; 421 unsigned int spdif_default; 422 unsigned int spdif_stream; 423 424 #ifdef CHIP1370 425 struct snd_dma_buffer dma_bug; 426 #endif 427 428 #ifdef SUPPORT_JOYSTICK 429 struct gameport *gameport; 430 #endif 431 }; 432 433 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id); 434 435 static const struct pci_device_id snd_audiopci_ids[] = { 436 #ifdef CHIP1370 437 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */ 438 #endif 439 #ifdef CHIP1371 440 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */ 441 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */ 442 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */ 443 #endif 444 { 0, } 445 }; 446 447 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids); 448 449 /* 450 * constants 451 */ 452 453 #define POLL_COUNT 0xa000 454 455 #ifdef CHIP1370 456 static const unsigned int snd_es1370_fixed_rates[] = 457 {5512, 11025, 22050, 44100}; 458 static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = { 459 .count = 4, 460 .list = snd_es1370_fixed_rates, 461 .mask = 0, 462 }; 463 static const struct snd_ratnum es1370_clock = { 464 .num = ES_1370_SRCLOCK, 465 .den_min = 29, 466 .den_max = 353, 467 .den_step = 1, 468 }; 469 static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = { 470 .nrats = 1, 471 .rats = &es1370_clock, 472 }; 473 #else 474 static const struct snd_ratden es1371_dac_clock = { 475 .num_min = 3000 * (1 << 15), 476 .num_max = 48000 * (1 << 15), 477 .num_step = 3000, 478 .den = 1 << 15, 479 }; 480 static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = { 481 .nrats = 1, 482 .rats = &es1371_dac_clock, 483 }; 484 static const struct snd_ratnum es1371_adc_clock = { 485 .num = 48000 << 15, 486 .den_min = 32768, 487 .den_max = 393216, 488 .den_step = 1, 489 }; 490 static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = { 491 .nrats = 1, 492 .rats = &es1371_adc_clock, 493 }; 494 #endif 495 static const unsigned int snd_ensoniq_sample_shift[] = 496 {0, 1, 1, 2}; 497 498 /* 499 * common I/O routines 500 */ 501 502 #ifdef CHIP1371 503 504 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq) 505 { 506 unsigned int t, r = 0; 507 508 for (t = 0; t < POLL_COUNT; t++) { 509 r = inl(ES_REG(ensoniq, 1371_SMPRATE)); 510 if ((r & ES_1371_SRC_RAM_BUSY) == 0) 511 return r; 512 cond_resched(); 513 } 514 dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n", 515 ES_REG(ensoniq, 1371_SMPRATE), r); 516 return 0; 517 } 518 519 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg) 520 { 521 unsigned int temp, i, orig, r; 522 523 /* wait for ready */ 524 temp = orig = snd_es1371_wait_src_ready(ensoniq); 525 526 /* expose the SRC state bits */ 527 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 528 ES_1371_DIS_P2 | ES_1371_DIS_R1); 529 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; 530 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 531 532 /* now, wait for busy and the correct time to read */ 533 temp = snd_es1371_wait_src_ready(ensoniq); 534 535 if ((temp & 0x00870000) != 0x00010000) { 536 /* wait for the right state */ 537 for (i = 0; i < POLL_COUNT; i++) { 538 temp = inl(ES_REG(ensoniq, 1371_SMPRATE)); 539 if ((temp & 0x00870000) == 0x00010000) 540 break; 541 } 542 } 543 544 /* hide the state bits */ 545 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 546 ES_1371_DIS_P2 | ES_1371_DIS_R1); 547 r |= ES_1371_SRC_RAM_ADDRO(reg); 548 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 549 550 return temp; 551 } 552 553 static void snd_es1371_src_write(struct ensoniq * ensoniq, 554 unsigned short reg, unsigned short data) 555 { 556 unsigned int r; 557 558 r = snd_es1371_wait_src_ready(ensoniq) & 559 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 560 ES_1371_DIS_P2 | ES_1371_DIS_R1); 561 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); 562 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE)); 563 } 564 565 #endif /* CHIP1371 */ 566 567 #ifdef CHIP1370 568 569 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531, 570 unsigned short reg, unsigned short val) 571 { 572 struct ensoniq *ensoniq = ak4531->private_data; 573 unsigned long end_time = jiffies + HZ / 10; 574 575 #if 0 576 dev_dbg(ensoniq->card->dev, 577 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", 578 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 579 #endif 580 do { 581 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) { 582 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 583 return; 584 } 585 schedule_timeout_uninterruptible(1); 586 } while (time_after(end_time, jiffies)); 587 dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n", 588 inl(ES_REG(ensoniq, STATUS))); 589 } 590 591 #endif /* CHIP1370 */ 592 593 #ifdef CHIP1371 594 595 static inline bool is_ev1938(struct ensoniq *ensoniq) 596 { 597 return ensoniq->pci->device == 0x8938; 598 } 599 600 static void snd_es1371_codec_write(struct snd_ac97 *ac97, 601 unsigned short reg, unsigned short val) 602 { 603 struct ensoniq *ensoniq = ac97->private_data; 604 unsigned int t, x, flag; 605 606 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0; 607 mutex_lock(&ensoniq->src_mutex); 608 for (t = 0; t < POLL_COUNT; t++) { 609 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 610 /* save the current state for latter */ 611 x = snd_es1371_wait_src_ready(ensoniq); 612 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 613 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 614 ES_REG(ensoniq, 1371_SMPRATE)); 615 /* wait for not busy (state 0) first to avoid 616 transition states */ 617 for (t = 0; t < POLL_COUNT; t++) { 618 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 619 0x00000000) 620 break; 621 } 622 /* wait for a SAFE time to write addr/data and then do it, dammit */ 623 for (t = 0; t < POLL_COUNT; t++) { 624 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 625 0x00010000) 626 break; 627 } 628 outl(ES_1371_CODEC_WRITE(reg, val) | flag, 629 ES_REG(ensoniq, 1371_CODEC)); 630 /* restore SRC reg */ 631 snd_es1371_wait_src_ready(ensoniq); 632 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 633 mutex_unlock(&ensoniq->src_mutex); 634 return; 635 } 636 } 637 mutex_unlock(&ensoniq->src_mutex); 638 dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n", 639 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 640 } 641 642 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97, 643 unsigned short reg) 644 { 645 struct ensoniq *ensoniq = ac97->private_data; 646 unsigned int t, x, flag, fail = 0; 647 648 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0; 649 __again: 650 mutex_lock(&ensoniq->src_mutex); 651 for (t = 0; t < POLL_COUNT; t++) { 652 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 653 /* save the current state for latter */ 654 x = snd_es1371_wait_src_ready(ensoniq); 655 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 656 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 657 ES_REG(ensoniq, 1371_SMPRATE)); 658 /* wait for not busy (state 0) first to avoid 659 transition states */ 660 for (t = 0; t < POLL_COUNT; t++) { 661 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 662 0x00000000) 663 break; 664 } 665 /* wait for a SAFE time to write addr/data and then do it, dammit */ 666 for (t = 0; t < POLL_COUNT; t++) { 667 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 668 0x00010000) 669 break; 670 } 671 outl(ES_1371_CODEC_READS(reg) | flag, 672 ES_REG(ensoniq, 1371_CODEC)); 673 /* restore SRC reg */ 674 snd_es1371_wait_src_ready(ensoniq); 675 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 676 /* wait for WIP again */ 677 for (t = 0; t < POLL_COUNT; t++) { 678 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) 679 break; 680 } 681 /* now wait for the stinkin' data (RDY) */ 682 for (t = 0; t < POLL_COUNT; t++) { 683 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) { 684 if (is_ev1938(ensoniq)) { 685 for (t = 0; t < 100; t++) 686 inl(ES_REG(ensoniq, CONTROL)); 687 x = inl(ES_REG(ensoniq, 1371_CODEC)); 688 } 689 mutex_unlock(&ensoniq->src_mutex); 690 return ES_1371_CODEC_READ(x); 691 } 692 } 693 mutex_unlock(&ensoniq->src_mutex); 694 if (++fail > 10) { 695 dev_err(ensoniq->card->dev, 696 "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", 697 ES_REG(ensoniq, 1371_CODEC), reg, 698 inl(ES_REG(ensoniq, 1371_CODEC))); 699 return 0; 700 } 701 goto __again; 702 } 703 } 704 mutex_unlock(&ensoniq->src_mutex); 705 dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n", 706 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 707 return 0; 708 } 709 710 static void snd_es1371_codec_wait(struct snd_ac97 *ac97) 711 { 712 msleep(750); 713 snd_es1371_codec_read(ac97, AC97_RESET); 714 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); 715 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); 716 msleep(50); 717 } 718 719 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate) 720 { 721 unsigned int n, truncm, freq; 722 723 mutex_lock(&ensoniq->src_mutex); 724 n = rate / 3000; 725 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 726 n--; 727 truncm = (21 * n - 1) | 1; 728 freq = ((48000UL << 15) / rate) * n; 729 if (rate >= 24000) { 730 if (truncm > 239) 731 truncm = 239; 732 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 733 (((239 - truncm) >> 1) << 9) | (n << 4)); 734 } else { 735 if (truncm > 119) 736 truncm = 119; 737 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 738 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 739 } 740 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 741 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + 742 ES_SMPREG_INT_REGS) & 0x00ff) | 743 ((freq >> 5) & 0xfc00)); 744 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 745 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8); 746 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8); 747 mutex_unlock(&ensoniq->src_mutex); 748 } 749 750 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate) 751 { 752 unsigned int freq, r; 753 754 mutex_lock(&ensoniq->src_mutex); 755 freq = ((rate << 15) + 1500) / 3000; 756 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 757 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 758 ES_1371_DIS_P1; 759 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 760 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 761 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + 762 ES_SMPREG_INT_REGS) & 0x00ff) | 763 ((freq >> 5) & 0xfc00)); 764 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 765 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 766 ES_1371_DIS_P2 | ES_1371_DIS_R1)); 767 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 768 mutex_unlock(&ensoniq->src_mutex); 769 } 770 771 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate) 772 { 773 unsigned int freq, r; 774 775 mutex_lock(&ensoniq->src_mutex); 776 freq = ((rate << 15) + 1500) / 3000; 777 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 778 ES_1371_DIS_P1 | ES_1371_DIS_R1)) | 779 ES_1371_DIS_P2; 780 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 781 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 782 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + 783 ES_SMPREG_INT_REGS) & 0x00ff) | 784 ((freq >> 5) & 0xfc00)); 785 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, 786 freq & 0x7fff); 787 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 788 ES_1371_DIS_P1 | ES_1371_DIS_R1)); 789 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 790 mutex_unlock(&ensoniq->src_mutex); 791 } 792 793 #endif /* CHIP1371 */ 794 795 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd) 796 { 797 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 798 switch (cmd) { 799 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 800 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 801 { 802 unsigned int what = 0; 803 struct snd_pcm_substream *s; 804 snd_pcm_group_for_each_entry(s, substream) { 805 if (s == ensoniq->playback1_substream) { 806 what |= ES_P1_PAUSE; 807 snd_pcm_trigger_done(s, substream); 808 } else if (s == ensoniq->playback2_substream) { 809 what |= ES_P2_PAUSE; 810 snd_pcm_trigger_done(s, substream); 811 } else if (s == ensoniq->capture_substream) 812 return -EINVAL; 813 } 814 spin_lock(&ensoniq->reg_lock); 815 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 816 ensoniq->sctrl |= what; 817 else 818 ensoniq->sctrl &= ~what; 819 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 820 spin_unlock(&ensoniq->reg_lock); 821 break; 822 } 823 case SNDRV_PCM_TRIGGER_START: 824 case SNDRV_PCM_TRIGGER_STOP: 825 { 826 unsigned int what = 0; 827 struct snd_pcm_substream *s; 828 snd_pcm_group_for_each_entry(s, substream) { 829 if (s == ensoniq->playback1_substream) { 830 what |= ES_DAC1_EN; 831 snd_pcm_trigger_done(s, substream); 832 } else if (s == ensoniq->playback2_substream) { 833 what |= ES_DAC2_EN; 834 snd_pcm_trigger_done(s, substream); 835 } else if (s == ensoniq->capture_substream) { 836 what |= ES_ADC_EN; 837 snd_pcm_trigger_done(s, substream); 838 } 839 } 840 spin_lock(&ensoniq->reg_lock); 841 if (cmd == SNDRV_PCM_TRIGGER_START) 842 ensoniq->ctrl |= what; 843 else 844 ensoniq->ctrl &= ~what; 845 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 846 spin_unlock(&ensoniq->reg_lock); 847 break; 848 } 849 default: 850 return -EINVAL; 851 } 852 return 0; 853 } 854 855 /* 856 * PCM part 857 */ 858 859 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream) 860 { 861 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 862 struct snd_pcm_runtime *runtime = substream->runtime; 863 unsigned int mode = 0; 864 865 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream); 866 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream); 867 if (snd_pcm_format_width(runtime->format) == 16) 868 mode |= 0x02; 869 if (runtime->channels > 1) 870 mode |= 0x01; 871 spin_lock_irq(&ensoniq->reg_lock); 872 ensoniq->ctrl &= ~ES_DAC1_EN; 873 #ifdef CHIP1371 874 /* 48k doesn't need SRC (it breaks AC3-passthru) */ 875 if (runtime->rate == 48000) 876 ensoniq->ctrl |= ES_1373_BYPASS_P1; 877 else 878 ensoniq->ctrl &= ~ES_1373_BYPASS_P1; 879 #endif 880 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 881 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 882 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME)); 883 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE)); 884 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM); 885 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode); 886 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 887 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 888 ES_REG(ensoniq, DAC1_COUNT)); 889 #ifdef CHIP1370 890 ensoniq->ctrl &= ~ES_1370_WTSRSELM; 891 switch (runtime->rate) { 892 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; 893 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; 894 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; 895 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; 896 default: snd_BUG(); 897 } 898 #endif 899 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 900 spin_unlock_irq(&ensoniq->reg_lock); 901 #ifndef CHIP1370 902 snd_es1371_dac1_rate(ensoniq, runtime->rate); 903 #endif 904 return 0; 905 } 906 907 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream) 908 { 909 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 910 struct snd_pcm_runtime *runtime = substream->runtime; 911 unsigned int mode = 0; 912 913 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream); 914 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream); 915 if (snd_pcm_format_width(runtime->format) == 16) 916 mode |= 0x02; 917 if (runtime->channels > 1) 918 mode |= 0x01; 919 spin_lock_irq(&ensoniq->reg_lock); 920 ensoniq->ctrl &= ~ES_DAC2_EN; 921 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 922 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 923 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME)); 924 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE)); 925 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN | 926 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM); 927 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) | 928 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0); 929 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 930 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 931 ES_REG(ensoniq, DAC2_COUNT)); 932 #ifdef CHIP1370 933 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) { 934 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 935 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 936 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2; 937 } 938 #endif 939 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 940 spin_unlock_irq(&ensoniq->reg_lock); 941 #ifndef CHIP1370 942 snd_es1371_dac2_rate(ensoniq, runtime->rate); 943 #endif 944 return 0; 945 } 946 947 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream) 948 { 949 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 950 struct snd_pcm_runtime *runtime = substream->runtime; 951 unsigned int mode = 0; 952 953 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream); 954 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream); 955 if (snd_pcm_format_width(runtime->format) == 16) 956 mode |= 0x02; 957 if (runtime->channels > 1) 958 mode |= 0x01; 959 spin_lock_irq(&ensoniq->reg_lock); 960 ensoniq->ctrl &= ~ES_ADC_EN; 961 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 962 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 963 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME)); 964 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE)); 965 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM); 966 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode); 967 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 968 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 969 ES_REG(ensoniq, ADC_COUNT)); 970 #ifdef CHIP1370 971 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) { 972 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 973 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 974 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE; 975 } 976 #endif 977 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 978 spin_unlock_irq(&ensoniq->reg_lock); 979 #ifndef CHIP1370 980 snd_es1371_adc_rate(ensoniq, runtime->rate); 981 #endif 982 return 0; 983 } 984 985 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream) 986 { 987 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 988 size_t ptr; 989 990 spin_lock(&ensoniq->reg_lock); 991 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { 992 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 993 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE))); 994 ptr = bytes_to_frames(substream->runtime, ptr); 995 } else { 996 ptr = 0; 997 } 998 spin_unlock(&ensoniq->reg_lock); 999 return ptr; 1000 } 1001 1002 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream) 1003 { 1004 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1005 size_t ptr; 1006 1007 spin_lock(&ensoniq->reg_lock); 1008 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { 1009 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1010 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE))); 1011 ptr = bytes_to_frames(substream->runtime, ptr); 1012 } else { 1013 ptr = 0; 1014 } 1015 spin_unlock(&ensoniq->reg_lock); 1016 return ptr; 1017 } 1018 1019 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream) 1020 { 1021 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1022 size_t ptr; 1023 1024 spin_lock(&ensoniq->reg_lock); 1025 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) { 1026 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1027 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE))); 1028 ptr = bytes_to_frames(substream->runtime, ptr); 1029 } else { 1030 ptr = 0; 1031 } 1032 spin_unlock(&ensoniq->reg_lock); 1033 return ptr; 1034 } 1035 1036 static const struct snd_pcm_hardware snd_ensoniq_playback1 = 1037 { 1038 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1039 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1040 SNDRV_PCM_INFO_MMAP_VALID | 1041 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START), 1042 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1043 .rates = 1044 #ifndef CHIP1370 1045 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1046 #else 1047 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */ 1048 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 1049 SNDRV_PCM_RATE_44100), 1050 #endif 1051 .rate_min = 4000, 1052 .rate_max = 48000, 1053 .channels_min = 1, 1054 .channels_max = 2, 1055 .buffer_bytes_max = (128*1024), 1056 .period_bytes_min = 64, 1057 .period_bytes_max = (128*1024), 1058 .periods_min = 1, 1059 .periods_max = 1024, 1060 .fifo_size = 0, 1061 }; 1062 1063 static const struct snd_pcm_hardware snd_ensoniq_playback2 = 1064 { 1065 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1066 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1067 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 1068 SNDRV_PCM_INFO_SYNC_START), 1069 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1070 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1071 .rate_min = 4000, 1072 .rate_max = 48000, 1073 .channels_min = 1, 1074 .channels_max = 2, 1075 .buffer_bytes_max = (128*1024), 1076 .period_bytes_min = 64, 1077 .period_bytes_max = (128*1024), 1078 .periods_min = 1, 1079 .periods_max = 1024, 1080 .fifo_size = 0, 1081 }; 1082 1083 static const struct snd_pcm_hardware snd_ensoniq_capture = 1084 { 1085 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1086 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1087 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1088 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1089 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1090 .rate_min = 4000, 1091 .rate_max = 48000, 1092 .channels_min = 1, 1093 .channels_max = 2, 1094 .buffer_bytes_max = (128*1024), 1095 .period_bytes_min = 64, 1096 .period_bytes_max = (128*1024), 1097 .periods_min = 1, 1098 .periods_max = 1024, 1099 .fifo_size = 0, 1100 }; 1101 1102 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream) 1103 { 1104 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1105 struct snd_pcm_runtime *runtime = substream->runtime; 1106 1107 ensoniq->mode |= ES_MODE_PLAY1; 1108 ensoniq->playback1_substream = substream; 1109 runtime->hw = snd_ensoniq_playback1; 1110 snd_pcm_set_sync(substream); 1111 spin_lock_irq(&ensoniq->reg_lock); 1112 if (ensoniq->spdif && ensoniq->playback2_substream == NULL) 1113 ensoniq->spdif_stream = ensoniq->spdif_default; 1114 spin_unlock_irq(&ensoniq->reg_lock); 1115 #ifdef CHIP1370 1116 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1117 &snd_es1370_hw_constraints_rates); 1118 #else 1119 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1120 &snd_es1371_hw_constraints_dac_clock); 1121 #endif 1122 return 0; 1123 } 1124 1125 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream) 1126 { 1127 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1128 struct snd_pcm_runtime *runtime = substream->runtime; 1129 1130 ensoniq->mode |= ES_MODE_PLAY2; 1131 ensoniq->playback2_substream = substream; 1132 runtime->hw = snd_ensoniq_playback2; 1133 snd_pcm_set_sync(substream); 1134 spin_lock_irq(&ensoniq->reg_lock); 1135 if (ensoniq->spdif && ensoniq->playback1_substream == NULL) 1136 ensoniq->spdif_stream = ensoniq->spdif_default; 1137 spin_unlock_irq(&ensoniq->reg_lock); 1138 #ifdef CHIP1370 1139 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1140 &snd_es1370_hw_constraints_clock); 1141 #else 1142 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1143 &snd_es1371_hw_constraints_dac_clock); 1144 #endif 1145 return 0; 1146 } 1147 1148 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream) 1149 { 1150 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1151 struct snd_pcm_runtime *runtime = substream->runtime; 1152 1153 ensoniq->mode |= ES_MODE_CAPTURE; 1154 ensoniq->capture_substream = substream; 1155 runtime->hw = snd_ensoniq_capture; 1156 snd_pcm_set_sync(substream); 1157 #ifdef CHIP1370 1158 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1159 &snd_es1370_hw_constraints_clock); 1160 #else 1161 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1162 &snd_es1371_hw_constraints_adc_clock); 1163 #endif 1164 return 0; 1165 } 1166 1167 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream) 1168 { 1169 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1170 1171 ensoniq->playback1_substream = NULL; 1172 ensoniq->mode &= ~ES_MODE_PLAY1; 1173 return 0; 1174 } 1175 1176 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream) 1177 { 1178 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1179 1180 ensoniq->playback2_substream = NULL; 1181 spin_lock_irq(&ensoniq->reg_lock); 1182 #ifdef CHIP1370 1183 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2; 1184 #endif 1185 ensoniq->mode &= ~ES_MODE_PLAY2; 1186 spin_unlock_irq(&ensoniq->reg_lock); 1187 return 0; 1188 } 1189 1190 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream) 1191 { 1192 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1193 1194 ensoniq->capture_substream = NULL; 1195 spin_lock_irq(&ensoniq->reg_lock); 1196 #ifdef CHIP1370 1197 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE; 1198 #endif 1199 ensoniq->mode &= ~ES_MODE_CAPTURE; 1200 spin_unlock_irq(&ensoniq->reg_lock); 1201 return 0; 1202 } 1203 1204 static const struct snd_pcm_ops snd_ensoniq_playback1_ops = { 1205 .open = snd_ensoniq_playback1_open, 1206 .close = snd_ensoniq_playback1_close, 1207 .prepare = snd_ensoniq_playback1_prepare, 1208 .trigger = snd_ensoniq_trigger, 1209 .pointer = snd_ensoniq_playback1_pointer, 1210 }; 1211 1212 static const struct snd_pcm_ops snd_ensoniq_playback2_ops = { 1213 .open = snd_ensoniq_playback2_open, 1214 .close = snd_ensoniq_playback2_close, 1215 .prepare = snd_ensoniq_playback2_prepare, 1216 .trigger = snd_ensoniq_trigger, 1217 .pointer = snd_ensoniq_playback2_pointer, 1218 }; 1219 1220 static const struct snd_pcm_ops snd_ensoniq_capture_ops = { 1221 .open = snd_ensoniq_capture_open, 1222 .close = snd_ensoniq_capture_close, 1223 .prepare = snd_ensoniq_capture_prepare, 1224 .trigger = snd_ensoniq_trigger, 1225 .pointer = snd_ensoniq_capture_pointer, 1226 }; 1227 1228 static const struct snd_pcm_chmap_elem surround_map[] = { 1229 { .channels = 1, 1230 .map = { SNDRV_CHMAP_MONO } }, 1231 { .channels = 2, 1232 .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 1233 { } 1234 }; 1235 1236 static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device) 1237 { 1238 struct snd_pcm *pcm; 1239 int err; 1240 1241 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm); 1242 if (err < 0) 1243 return err; 1244 1245 #ifdef CHIP1370 1246 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1247 #else 1248 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1249 #endif 1250 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops); 1251 1252 pcm->private_data = ensoniq; 1253 pcm->info_flags = 0; 1254 strcpy(pcm->name, CHIP_NAME " DAC2/ADC"); 1255 ensoniq->pcm1 = pcm; 1256 1257 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1258 &ensoniq->pci->dev, 64*1024, 128*1024); 1259 1260 #ifdef CHIP1370 1261 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1262 surround_map, 2, 0, NULL); 1263 #else 1264 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1265 snd_pcm_std_chmaps, 2, 0, NULL); 1266 #endif 1267 return err; 1268 } 1269 1270 static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device) 1271 { 1272 struct snd_pcm *pcm; 1273 int err; 1274 1275 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm); 1276 if (err < 0) 1277 return err; 1278 1279 #ifdef CHIP1370 1280 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1281 #else 1282 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1283 #endif 1284 pcm->private_data = ensoniq; 1285 pcm->info_flags = 0; 1286 strcpy(pcm->name, CHIP_NAME " DAC1"); 1287 ensoniq->pcm2 = pcm; 1288 1289 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1290 &ensoniq->pci->dev, 64*1024, 128*1024); 1291 1292 #ifdef CHIP1370 1293 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1294 snd_pcm_std_chmaps, 2, 0, NULL); 1295 #else 1296 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1297 surround_map, 2, 0, NULL); 1298 #endif 1299 return err; 1300 } 1301 1302 /* 1303 * Mixer section 1304 */ 1305 1306 /* 1307 * ENS1371 mixer (including SPDIF interface) 1308 */ 1309 #ifdef CHIP1371 1310 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol, 1311 struct snd_ctl_elem_info *uinfo) 1312 { 1313 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1314 uinfo->count = 1; 1315 return 0; 1316 } 1317 1318 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol, 1319 struct snd_ctl_elem_value *ucontrol) 1320 { 1321 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1322 spin_lock_irq(&ensoniq->reg_lock); 1323 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff; 1324 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff; 1325 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff; 1326 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff; 1327 spin_unlock_irq(&ensoniq->reg_lock); 1328 return 0; 1329 } 1330 1331 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol, 1332 struct snd_ctl_elem_value *ucontrol) 1333 { 1334 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1335 unsigned int val; 1336 int change; 1337 1338 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1339 ((u32)ucontrol->value.iec958.status[1] << 8) | 1340 ((u32)ucontrol->value.iec958.status[2] << 16) | 1341 ((u32)ucontrol->value.iec958.status[3] << 24); 1342 spin_lock_irq(&ensoniq->reg_lock); 1343 change = ensoniq->spdif_default != val; 1344 ensoniq->spdif_default = val; 1345 if (change && ensoniq->playback1_substream == NULL && 1346 ensoniq->playback2_substream == NULL) 1347 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1348 spin_unlock_irq(&ensoniq->reg_lock); 1349 return change; 1350 } 1351 1352 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol, 1353 struct snd_ctl_elem_value *ucontrol) 1354 { 1355 ucontrol->value.iec958.status[0] = 0xff; 1356 ucontrol->value.iec958.status[1] = 0xff; 1357 ucontrol->value.iec958.status[2] = 0xff; 1358 ucontrol->value.iec958.status[3] = 0xff; 1359 return 0; 1360 } 1361 1362 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol, 1363 struct snd_ctl_elem_value *ucontrol) 1364 { 1365 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1366 spin_lock_irq(&ensoniq->reg_lock); 1367 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff; 1368 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff; 1369 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff; 1370 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff; 1371 spin_unlock_irq(&ensoniq->reg_lock); 1372 return 0; 1373 } 1374 1375 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol, 1376 struct snd_ctl_elem_value *ucontrol) 1377 { 1378 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1379 unsigned int val; 1380 int change; 1381 1382 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1383 ((u32)ucontrol->value.iec958.status[1] << 8) | 1384 ((u32)ucontrol->value.iec958.status[2] << 16) | 1385 ((u32)ucontrol->value.iec958.status[3] << 24); 1386 spin_lock_irq(&ensoniq->reg_lock); 1387 change = ensoniq->spdif_stream != val; 1388 ensoniq->spdif_stream = val; 1389 if (change && (ensoniq->playback1_substream != NULL || 1390 ensoniq->playback2_substream != NULL)) 1391 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1392 spin_unlock_irq(&ensoniq->reg_lock); 1393 return change; 1394 } 1395 1396 #define ES1371_SPDIF(xname) \ 1397 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \ 1398 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put } 1399 1400 #define snd_es1371_spdif_info snd_ctl_boolean_mono_info 1401 1402 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol, 1403 struct snd_ctl_elem_value *ucontrol) 1404 { 1405 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1406 1407 spin_lock_irq(&ensoniq->reg_lock); 1408 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; 1409 spin_unlock_irq(&ensoniq->reg_lock); 1410 return 0; 1411 } 1412 1413 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol, 1414 struct snd_ctl_elem_value *ucontrol) 1415 { 1416 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1417 unsigned int nval1, nval2; 1418 int change; 1419 1420 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0; 1421 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0; 1422 spin_lock_irq(&ensoniq->reg_lock); 1423 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; 1424 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; 1425 ensoniq->ctrl |= nval1; 1426 ensoniq->cssr &= ~ES_1373_SPDIF_EN; 1427 ensoniq->cssr |= nval2; 1428 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1429 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1430 spin_unlock_irq(&ensoniq->reg_lock); 1431 return change; 1432 } 1433 1434 1435 /* spdif controls */ 1436 static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = { 1437 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)), 1438 { 1439 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1440 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1441 .info = snd_ens1373_spdif_info, 1442 .get = snd_ens1373_spdif_default_get, 1443 .put = snd_ens1373_spdif_default_put, 1444 }, 1445 { 1446 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1447 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1448 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 1449 .info = snd_ens1373_spdif_info, 1450 .get = snd_ens1373_spdif_mask_get 1451 }, 1452 { 1453 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1454 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1455 .info = snd_ens1373_spdif_info, 1456 .get = snd_ens1373_spdif_stream_get, 1457 .put = snd_ens1373_spdif_stream_put 1458 }, 1459 }; 1460 1461 1462 #define snd_es1373_rear_info snd_ctl_boolean_mono_info 1463 1464 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol, 1465 struct snd_ctl_elem_value *ucontrol) 1466 { 1467 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1468 int val = 0; 1469 1470 spin_lock_irq(&ensoniq->reg_lock); 1471 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26| 1472 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26) 1473 val = 1; 1474 ucontrol->value.integer.value[0] = val; 1475 spin_unlock_irq(&ensoniq->reg_lock); 1476 return 0; 1477 } 1478 1479 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol, 1480 struct snd_ctl_elem_value *ucontrol) 1481 { 1482 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1483 unsigned int nval1; 1484 int change; 1485 1486 nval1 = ucontrol->value.integer.value[0] ? 1487 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1488 spin_lock_irq(&ensoniq->reg_lock); 1489 change = (ensoniq->cssr & (ES_1373_REAR_BIT27| 1490 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1; 1491 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24); 1492 ensoniq->cssr |= nval1; 1493 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1494 spin_unlock_irq(&ensoniq->reg_lock); 1495 return change; 1496 } 1497 1498 static const struct snd_kcontrol_new snd_ens1373_rear = 1499 { 1500 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1501 .name = "AC97 2ch->4ch Copy Switch", 1502 .info = snd_es1373_rear_info, 1503 .get = snd_es1373_rear_get, 1504 .put = snd_es1373_rear_put, 1505 }; 1506 1507 #define snd_es1373_line_info snd_ctl_boolean_mono_info 1508 1509 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol, 1510 struct snd_ctl_elem_value *ucontrol) 1511 { 1512 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1513 int val = 0; 1514 1515 spin_lock_irq(&ensoniq->reg_lock); 1516 if (ensoniq->ctrl & ES_1371_GPIO_OUT(4)) 1517 val = 1; 1518 ucontrol->value.integer.value[0] = val; 1519 spin_unlock_irq(&ensoniq->reg_lock); 1520 return 0; 1521 } 1522 1523 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol, 1524 struct snd_ctl_elem_value *ucontrol) 1525 { 1526 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1527 int changed; 1528 unsigned int ctrl; 1529 1530 spin_lock_irq(&ensoniq->reg_lock); 1531 ctrl = ensoniq->ctrl; 1532 if (ucontrol->value.integer.value[0]) 1533 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ 1534 else 1535 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); 1536 changed = (ctrl != ensoniq->ctrl); 1537 if (changed) 1538 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1539 spin_unlock_irq(&ensoniq->reg_lock); 1540 return changed; 1541 } 1542 1543 static const struct snd_kcontrol_new snd_ens1373_line = 1544 { 1545 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1546 .name = "Line In->Rear Out Switch", 1547 .info = snd_es1373_line_info, 1548 .get = snd_es1373_line_get, 1549 .put = snd_es1373_line_put, 1550 }; 1551 1552 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97) 1553 { 1554 struct ensoniq *ensoniq = ac97->private_data; 1555 ensoniq->u.es1371.ac97 = NULL; 1556 } 1557 1558 struct es1371_quirk { 1559 unsigned short vid; /* vendor ID */ 1560 unsigned short did; /* device ID */ 1561 unsigned char rev; /* revision */ 1562 }; 1563 1564 static int es1371_quirk_lookup(struct ensoniq *ensoniq, 1565 const struct es1371_quirk *list) 1566 { 1567 while (list->vid != (unsigned short)PCI_ANY_ID) { 1568 if (ensoniq->pci->vendor == list->vid && 1569 ensoniq->pci->device == list->did && 1570 ensoniq->rev == list->rev) 1571 return 1; 1572 list++; 1573 } 1574 return 0; 1575 } 1576 1577 static const struct es1371_quirk es1371_spdif_present[] = { 1578 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1579 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1580 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1581 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1582 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1583 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1584 }; 1585 1586 static const struct snd_pci_quirk ens1373_line_quirk[] = { 1587 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */ 1588 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */ 1589 { } /* end */ 1590 }; 1591 1592 static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq, 1593 int has_spdif, int has_line) 1594 { 1595 struct snd_card *card = ensoniq->card; 1596 struct snd_ac97_bus *pbus; 1597 struct snd_ac97_template ac97; 1598 int err; 1599 static const struct snd_ac97_bus_ops ops = { 1600 .write = snd_es1371_codec_write, 1601 .read = snd_es1371_codec_read, 1602 .wait = snd_es1371_codec_wait, 1603 }; 1604 1605 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0) 1606 return err; 1607 1608 memset(&ac97, 0, sizeof(ac97)); 1609 ac97.private_data = ensoniq; 1610 ac97.private_free = snd_ensoniq_mixer_free_ac97; 1611 ac97.pci = ensoniq->pci; 1612 ac97.scaps = AC97_SCAP_AUDIO; 1613 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0) 1614 return err; 1615 if (has_spdif > 0 || 1616 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) { 1617 struct snd_kcontrol *kctl; 1618 int i, is_spdif = 0; 1619 1620 ensoniq->spdif_default = ensoniq->spdif_stream = 1621 SNDRV_PCM_DEFAULT_CON_SPDIF; 1622 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS)); 1623 1624 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF) 1625 is_spdif++; 1626 1627 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) { 1628 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq); 1629 if (!kctl) 1630 return -ENOMEM; 1631 kctl->id.index = is_spdif; 1632 err = snd_ctl_add(card, kctl); 1633 if (err < 0) 1634 return err; 1635 } 1636 } 1637 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) { 1638 /* mirror rear to front speakers */ 1639 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1640 ensoniq->cssr |= ES_1373_REAR_BIT26; 1641 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq)); 1642 if (err < 0) 1643 return err; 1644 } 1645 if (has_line > 0 || 1646 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) { 1647 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, 1648 ensoniq)); 1649 if (err < 0) 1650 return err; 1651 } 1652 1653 return 0; 1654 } 1655 1656 #endif /* CHIP1371 */ 1657 1658 /* generic control callbacks for ens1370 */ 1659 #ifdef CHIP1370 1660 #define ENSONIQ_CONTROL(xname, mask) \ 1661 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \ 1662 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \ 1663 .private_value = mask } 1664 1665 #define snd_ensoniq_control_info snd_ctl_boolean_mono_info 1666 1667 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol, 1668 struct snd_ctl_elem_value *ucontrol) 1669 { 1670 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1671 int mask = kcontrol->private_value; 1672 1673 spin_lock_irq(&ensoniq->reg_lock); 1674 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; 1675 spin_unlock_irq(&ensoniq->reg_lock); 1676 return 0; 1677 } 1678 1679 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol, 1680 struct snd_ctl_elem_value *ucontrol) 1681 { 1682 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1683 int mask = kcontrol->private_value; 1684 unsigned int nval; 1685 int change; 1686 1687 nval = ucontrol->value.integer.value[0] ? mask : 0; 1688 spin_lock_irq(&ensoniq->reg_lock); 1689 change = (ensoniq->ctrl & mask) != nval; 1690 ensoniq->ctrl &= ~mask; 1691 ensoniq->ctrl |= nval; 1692 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1693 spin_unlock_irq(&ensoniq->reg_lock); 1694 return change; 1695 } 1696 1697 /* 1698 * ENS1370 mixer 1699 */ 1700 1701 static const struct snd_kcontrol_new snd_es1370_controls[2] = { 1702 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0), 1703 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1) 1704 }; 1705 1706 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls) 1707 1708 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531) 1709 { 1710 struct ensoniq *ensoniq = ak4531->private_data; 1711 ensoniq->u.es1370.ak4531 = NULL; 1712 } 1713 1714 static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq) 1715 { 1716 struct snd_card *card = ensoniq->card; 1717 struct snd_ak4531 ak4531; 1718 unsigned int idx; 1719 int err; 1720 1721 /* try reset AK4531 */ 1722 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 1723 inw(ES_REG(ensoniq, 1370_CODEC)); 1724 udelay(100); 1725 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 1726 inw(ES_REG(ensoniq, 1370_CODEC)); 1727 udelay(100); 1728 1729 memset(&ak4531, 0, sizeof(ak4531)); 1730 ak4531.write = snd_es1370_codec_write; 1731 ak4531.private_data = ensoniq; 1732 ak4531.private_free = snd_ensoniq_mixer_free_ak4531; 1733 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0) 1734 return err; 1735 for (idx = 0; idx < ES1370_CONTROLS; idx++) { 1736 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq)); 1737 if (err < 0) 1738 return err; 1739 } 1740 return 0; 1741 } 1742 1743 #endif /* CHIP1370 */ 1744 1745 #ifdef SUPPORT_JOYSTICK 1746 1747 #ifdef CHIP1371 1748 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev) 1749 { 1750 switch (joystick_port[dev]) { 1751 case 0: /* disabled */ 1752 case 1: /* auto-detect */ 1753 case 0x200: 1754 case 0x208: 1755 case 0x210: 1756 case 0x218: 1757 return joystick_port[dev]; 1758 1759 default: 1760 dev_err(ensoniq->card->dev, 1761 "invalid joystick port %#x", joystick_port[dev]); 1762 return 0; 1763 } 1764 } 1765 #else 1766 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev) 1767 { 1768 return joystick[dev] ? 0x200 : 0; 1769 } 1770 #endif 1771 1772 static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev) 1773 { 1774 struct gameport *gp; 1775 int io_port; 1776 1777 io_port = snd_ensoniq_get_joystick_port(ensoniq, dev); 1778 1779 switch (io_port) { 1780 case 0: 1781 return -ENOSYS; 1782 1783 case 1: /* auto_detect */ 1784 for (io_port = 0x200; io_port <= 0x218; io_port += 8) 1785 if (request_region(io_port, 8, "ens137x: gameport")) 1786 break; 1787 if (io_port > 0x218) { 1788 dev_warn(ensoniq->card->dev, 1789 "no gameport ports available\n"); 1790 return -EBUSY; 1791 } 1792 break; 1793 1794 default: 1795 if (!request_region(io_port, 8, "ens137x: gameport")) { 1796 dev_warn(ensoniq->card->dev, 1797 "gameport io port %#x in use\n", 1798 io_port); 1799 return -EBUSY; 1800 } 1801 break; 1802 } 1803 1804 ensoniq->gameport = gp = gameport_allocate_port(); 1805 if (!gp) { 1806 dev_err(ensoniq->card->dev, 1807 "cannot allocate memory for gameport\n"); 1808 release_region(io_port, 8); 1809 return -ENOMEM; 1810 } 1811 1812 gameport_set_name(gp, "ES137x"); 1813 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci)); 1814 gameport_set_dev_parent(gp, &ensoniq->pci->dev); 1815 gp->io = io_port; 1816 1817 ensoniq->ctrl |= ES_JYSTK_EN; 1818 #ifdef CHIP1371 1819 ensoniq->ctrl &= ~ES_1371_JOY_ASELM; 1820 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); 1821 #endif 1822 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1823 1824 gameport_register_port(ensoniq->gameport); 1825 1826 return 0; 1827 } 1828 1829 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) 1830 { 1831 if (ensoniq->gameport) { 1832 int port = ensoniq->gameport->io; 1833 1834 gameport_unregister_port(ensoniq->gameport); 1835 ensoniq->gameport = NULL; 1836 ensoniq->ctrl &= ~ES_JYSTK_EN; 1837 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1838 release_region(port, 8); 1839 } 1840 } 1841 #else 1842 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; } 1843 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { } 1844 #endif /* SUPPORT_JOYSTICK */ 1845 1846 /* 1847 1848 */ 1849 1850 static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 1851 struct snd_info_buffer *buffer) 1852 { 1853 struct ensoniq *ensoniq = entry->private_data; 1854 1855 snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n"); 1856 snd_iprintf(buffer, "Joystick enable : %s\n", 1857 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); 1858 #ifdef CHIP1370 1859 snd_iprintf(buffer, "MIC +5V bias : %s\n", 1860 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); 1861 snd_iprintf(buffer, "Line In to AOUT : %s\n", 1862 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); 1863 #else 1864 snd_iprintf(buffer, "Joystick port : 0x%x\n", 1865 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); 1866 #endif 1867 } 1868 1869 static void snd_ensoniq_proc_init(struct ensoniq *ensoniq) 1870 { 1871 snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq, 1872 snd_ensoniq_proc_read); 1873 } 1874 1875 /* 1876 1877 */ 1878 1879 static int snd_ensoniq_free(struct ensoniq *ensoniq) 1880 { 1881 snd_ensoniq_free_gameport(ensoniq); 1882 if (ensoniq->irq < 0) 1883 goto __hw_end; 1884 #ifdef CHIP1370 1885 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1886 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1887 #else 1888 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1889 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1890 #endif 1891 pci_set_power_state(ensoniq->pci, PCI_D3hot); 1892 __hw_end: 1893 #ifdef CHIP1370 1894 if (ensoniq->dma_bug.area) 1895 snd_dma_free_pages(&ensoniq->dma_bug); 1896 #endif 1897 if (ensoniq->irq >= 0) 1898 free_irq(ensoniq->irq, ensoniq); 1899 pci_release_regions(ensoniq->pci); 1900 pci_disable_device(ensoniq->pci); 1901 kfree(ensoniq); 1902 return 0; 1903 } 1904 1905 static int snd_ensoniq_dev_free(struct snd_device *device) 1906 { 1907 struct ensoniq *ensoniq = device->device_data; 1908 return snd_ensoniq_free(ensoniq); 1909 } 1910 1911 #ifdef CHIP1371 1912 static const struct snd_pci_quirk es1371_amplifier_hack[] = { 1913 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */ 1914 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */ 1915 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */ 1916 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */ 1917 { } /* end */ 1918 }; 1919 1920 static const struct es1371_quirk es1371_ac97_reset_hack[] = { 1921 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1922 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1923 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1924 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1925 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1926 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1927 }; 1928 #endif 1929 1930 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq) 1931 { 1932 #ifdef CHIP1371 1933 int idx; 1934 #endif 1935 /* this code was part of snd_ensoniq_create before intruduction 1936 * of suspend/resume 1937 */ 1938 #ifdef CHIP1370 1939 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1940 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1941 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1942 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME)); 1943 outl(0, ES_REG(ensoniq, PHANTOM_COUNT)); 1944 #else 1945 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1946 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1947 outl(0, ES_REG(ensoniq, 1371_LEGACY)); 1948 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) { 1949 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1950 /* need to delay around 20ms(bleech) to give 1951 some CODECs enough time to wakeup */ 1952 msleep(20); 1953 } 1954 /* AC'97 warm reset to start the bitclk */ 1955 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); 1956 inl(ES_REG(ensoniq, CONTROL)); 1957 udelay(20); 1958 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1959 /* Init the sample rate converter */ 1960 snd_es1371_wait_src_ready(ensoniq); 1961 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE)); 1962 for (idx = 0; idx < 0x80; idx++) 1963 snd_es1371_src_write(ensoniq, idx, 0); 1964 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 1965 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 1966 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 1967 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 1968 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12); 1969 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12); 1970 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12); 1971 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 1972 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12); 1973 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 1974 snd_es1371_adc_rate(ensoniq, 22050); 1975 snd_es1371_dac1_rate(ensoniq, 22050); 1976 snd_es1371_dac2_rate(ensoniq, 22050); 1977 /* WARNING: 1978 * enabling the sample rate converter without properly programming 1979 * its parameters causes the chip to lock up (the SRC busy bit will 1980 * be stuck high, and I've found no way to rectify this other than 1981 * power cycle) - Thomas Sailer 1982 */ 1983 snd_es1371_wait_src_ready(ensoniq); 1984 outl(0, ES_REG(ensoniq, 1371_SMPRATE)); 1985 /* try reset codec directly */ 1986 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC)); 1987 #endif 1988 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL)); 1989 outb(0x00, ES_REG(ensoniq, UART_RES)); 1990 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1991 } 1992 1993 #ifdef CONFIG_PM_SLEEP 1994 static int snd_ensoniq_suspend(struct device *dev) 1995 { 1996 struct snd_card *card = dev_get_drvdata(dev); 1997 struct ensoniq *ensoniq = card->private_data; 1998 1999 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2000 2001 #ifdef CHIP1371 2002 snd_ac97_suspend(ensoniq->u.es1371.ac97); 2003 #else 2004 /* try to reset AK4531 */ 2005 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 2006 inw(ES_REG(ensoniq, 1370_CODEC)); 2007 udelay(100); 2008 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 2009 inw(ES_REG(ensoniq, 1370_CODEC)); 2010 udelay(100); 2011 snd_ak4531_suspend(ensoniq->u.es1370.ak4531); 2012 #endif 2013 return 0; 2014 } 2015 2016 static int snd_ensoniq_resume(struct device *dev) 2017 { 2018 struct snd_card *card = dev_get_drvdata(dev); 2019 struct ensoniq *ensoniq = card->private_data; 2020 2021 snd_ensoniq_chip_init(ensoniq); 2022 2023 #ifdef CHIP1371 2024 snd_ac97_resume(ensoniq->u.es1371.ac97); 2025 #else 2026 snd_ak4531_resume(ensoniq->u.es1370.ak4531); 2027 #endif 2028 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2029 return 0; 2030 } 2031 2032 static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume); 2033 #define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm 2034 #else 2035 #define SND_ENSONIQ_PM_OPS NULL 2036 #endif /* CONFIG_PM_SLEEP */ 2037 2038 static int snd_ensoniq_create(struct snd_card *card, 2039 struct pci_dev *pci, 2040 struct ensoniq **rensoniq) 2041 { 2042 struct ensoniq *ensoniq; 2043 int err; 2044 static const struct snd_device_ops ops = { 2045 .dev_free = snd_ensoniq_dev_free, 2046 }; 2047 2048 *rensoniq = NULL; 2049 if ((err = pci_enable_device(pci)) < 0) 2050 return err; 2051 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL); 2052 if (ensoniq == NULL) { 2053 pci_disable_device(pci); 2054 return -ENOMEM; 2055 } 2056 spin_lock_init(&ensoniq->reg_lock); 2057 mutex_init(&ensoniq->src_mutex); 2058 ensoniq->card = card; 2059 ensoniq->pci = pci; 2060 ensoniq->irq = -1; 2061 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) { 2062 kfree(ensoniq); 2063 pci_disable_device(pci); 2064 return err; 2065 } 2066 ensoniq->port = pci_resource_start(pci, 0); 2067 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED, 2068 KBUILD_MODNAME, ensoniq)) { 2069 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 2070 snd_ensoniq_free(ensoniq); 2071 return -EBUSY; 2072 } 2073 ensoniq->irq = pci->irq; 2074 card->sync_irq = ensoniq->irq; 2075 #ifdef CHIP1370 2076 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 2077 16, &ensoniq->dma_bug) < 0) { 2078 dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n"); 2079 snd_ensoniq_free(ensoniq); 2080 return -EBUSY; 2081 } 2082 #endif 2083 pci_set_master(pci); 2084 ensoniq->rev = pci->revision; 2085 #ifdef CHIP1370 2086 #if 0 2087 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | 2088 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2089 #else /* get microphone working */ 2090 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2091 #endif 2092 ensoniq->sctrl = 0; 2093 #else 2094 ensoniq->ctrl = 0; 2095 ensoniq->sctrl = 0; 2096 ensoniq->cssr = 0; 2097 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack)) 2098 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ 2099 2100 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) 2101 ensoniq->cssr |= ES_1371_ST_AC97_RST; 2102 #endif 2103 2104 snd_ensoniq_chip_init(ensoniq); 2105 2106 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) { 2107 snd_ensoniq_free(ensoniq); 2108 return err; 2109 } 2110 2111 snd_ensoniq_proc_init(ensoniq); 2112 2113 *rensoniq = ensoniq; 2114 return 0; 2115 } 2116 2117 /* 2118 * MIDI section 2119 */ 2120 2121 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq) 2122 { 2123 struct snd_rawmidi *rmidi = ensoniq->rmidi; 2124 unsigned char status, mask, byte; 2125 2126 if (rmidi == NULL) 2127 return; 2128 /* do Rx at first */ 2129 spin_lock(&ensoniq->reg_lock); 2130 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; 2131 while (mask) { 2132 status = inb(ES_REG(ensoniq, UART_STATUS)); 2133 if ((status & mask) == 0) 2134 break; 2135 byte = inb(ES_REG(ensoniq, UART_DATA)); 2136 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1); 2137 } 2138 spin_unlock(&ensoniq->reg_lock); 2139 2140 /* do Tx at second */ 2141 spin_lock(&ensoniq->reg_lock); 2142 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; 2143 while (mask) { 2144 status = inb(ES_REG(ensoniq, UART_STATUS)); 2145 if ((status & mask) == 0) 2146 break; 2147 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) { 2148 ensoniq->uartc &= ~ES_TXINTENM; 2149 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2150 mask &= ~ES_TXRDY; 2151 } else { 2152 outb(byte, ES_REG(ensoniq, UART_DATA)); 2153 } 2154 } 2155 spin_unlock(&ensoniq->reg_lock); 2156 } 2157 2158 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream) 2159 { 2160 struct ensoniq *ensoniq = substream->rmidi->private_data; 2161 2162 spin_lock_irq(&ensoniq->reg_lock); 2163 ensoniq->uartm |= ES_MODE_INPUT; 2164 ensoniq->midi_input = substream; 2165 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2166 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2167 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2168 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2169 } 2170 spin_unlock_irq(&ensoniq->reg_lock); 2171 return 0; 2172 } 2173 2174 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream) 2175 { 2176 struct ensoniq *ensoniq = substream->rmidi->private_data; 2177 2178 spin_lock_irq(&ensoniq->reg_lock); 2179 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2180 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2181 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2182 } else { 2183 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL)); 2184 } 2185 ensoniq->midi_input = NULL; 2186 ensoniq->uartm &= ~ES_MODE_INPUT; 2187 spin_unlock_irq(&ensoniq->reg_lock); 2188 return 0; 2189 } 2190 2191 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream) 2192 { 2193 struct ensoniq *ensoniq = substream->rmidi->private_data; 2194 2195 spin_lock_irq(&ensoniq->reg_lock); 2196 ensoniq->uartm |= ES_MODE_OUTPUT; 2197 ensoniq->midi_output = substream; 2198 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2199 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2200 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2201 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2202 } 2203 spin_unlock_irq(&ensoniq->reg_lock); 2204 return 0; 2205 } 2206 2207 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream) 2208 { 2209 struct ensoniq *ensoniq = substream->rmidi->private_data; 2210 2211 spin_lock_irq(&ensoniq->reg_lock); 2212 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2213 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2214 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2215 } else { 2216 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL)); 2217 } 2218 ensoniq->midi_output = NULL; 2219 ensoniq->uartm &= ~ES_MODE_OUTPUT; 2220 spin_unlock_irq(&ensoniq->reg_lock); 2221 return 0; 2222 } 2223 2224 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2225 { 2226 unsigned long flags; 2227 struct ensoniq *ensoniq = substream->rmidi->private_data; 2228 int idx; 2229 2230 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2231 if (up) { 2232 if ((ensoniq->uartc & ES_RXINTEN) == 0) { 2233 /* empty input FIFO */ 2234 for (idx = 0; idx < 32; idx++) 2235 inb(ES_REG(ensoniq, UART_DATA)); 2236 ensoniq->uartc |= ES_RXINTEN; 2237 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2238 } 2239 } else { 2240 if (ensoniq->uartc & ES_RXINTEN) { 2241 ensoniq->uartc &= ~ES_RXINTEN; 2242 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2243 } 2244 } 2245 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2246 } 2247 2248 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2249 { 2250 unsigned long flags; 2251 struct ensoniq *ensoniq = substream->rmidi->private_data; 2252 unsigned char byte; 2253 2254 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2255 if (up) { 2256 if (ES_TXINTENI(ensoniq->uartc) == 0) { 2257 ensoniq->uartc |= ES_TXINTENO(1); 2258 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2259 while (ES_TXINTENI(ensoniq->uartc) == 1 && 2260 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) { 2261 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2262 ensoniq->uartc &= ~ES_TXINTENM; 2263 } else { 2264 outb(byte, ES_REG(ensoniq, UART_DATA)); 2265 } 2266 } 2267 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2268 } 2269 } else { 2270 if (ES_TXINTENI(ensoniq->uartc) == 1) { 2271 ensoniq->uartc &= ~ES_TXINTENM; 2272 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2273 } 2274 } 2275 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2276 } 2277 2278 static const struct snd_rawmidi_ops snd_ensoniq_midi_output = 2279 { 2280 .open = snd_ensoniq_midi_output_open, 2281 .close = snd_ensoniq_midi_output_close, 2282 .trigger = snd_ensoniq_midi_output_trigger, 2283 }; 2284 2285 static const struct snd_rawmidi_ops snd_ensoniq_midi_input = 2286 { 2287 .open = snd_ensoniq_midi_input_open, 2288 .close = snd_ensoniq_midi_input_close, 2289 .trigger = snd_ensoniq_midi_input_trigger, 2290 }; 2291 2292 static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device) 2293 { 2294 struct snd_rawmidi *rmidi; 2295 int err; 2296 2297 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0) 2298 return err; 2299 strcpy(rmidi->name, CHIP_NAME); 2300 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output); 2301 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input); 2302 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | 2303 SNDRV_RAWMIDI_INFO_DUPLEX; 2304 rmidi->private_data = ensoniq; 2305 ensoniq->rmidi = rmidi; 2306 return 0; 2307 } 2308 2309 /* 2310 * Interrupt handler 2311 */ 2312 2313 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id) 2314 { 2315 struct ensoniq *ensoniq = dev_id; 2316 unsigned int status, sctrl; 2317 2318 if (ensoniq == NULL) 2319 return IRQ_NONE; 2320 2321 status = inl(ES_REG(ensoniq, STATUS)); 2322 if (!(status & ES_INTR)) 2323 return IRQ_NONE; 2324 2325 spin_lock(&ensoniq->reg_lock); 2326 sctrl = ensoniq->sctrl; 2327 if (status & ES_DAC1) 2328 sctrl &= ~ES_P1_INT_EN; 2329 if (status & ES_DAC2) 2330 sctrl &= ~ES_P2_INT_EN; 2331 if (status & ES_ADC) 2332 sctrl &= ~ES_R1_INT_EN; 2333 outl(sctrl, ES_REG(ensoniq, SERIAL)); 2334 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2335 spin_unlock(&ensoniq->reg_lock); 2336 2337 if (status & ES_UART) 2338 snd_ensoniq_midi_interrupt(ensoniq); 2339 if ((status & ES_DAC2) && ensoniq->playback2_substream) 2340 snd_pcm_period_elapsed(ensoniq->playback2_substream); 2341 if ((status & ES_ADC) && ensoniq->capture_substream) 2342 snd_pcm_period_elapsed(ensoniq->capture_substream); 2343 if ((status & ES_DAC1) && ensoniq->playback1_substream) 2344 snd_pcm_period_elapsed(ensoniq->playback1_substream); 2345 return IRQ_HANDLED; 2346 } 2347 2348 static int snd_audiopci_probe(struct pci_dev *pci, 2349 const struct pci_device_id *pci_id) 2350 { 2351 static int dev; 2352 struct snd_card *card; 2353 struct ensoniq *ensoniq; 2354 int err; 2355 2356 if (dev >= SNDRV_CARDS) 2357 return -ENODEV; 2358 if (!enable[dev]) { 2359 dev++; 2360 return -ENOENT; 2361 } 2362 2363 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2364 0, &card); 2365 if (err < 0) 2366 return err; 2367 2368 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) { 2369 snd_card_free(card); 2370 return err; 2371 } 2372 card->private_data = ensoniq; 2373 2374 #ifdef CHIP1370 2375 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) { 2376 snd_card_free(card); 2377 return err; 2378 } 2379 #endif 2380 #ifdef CHIP1371 2381 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) { 2382 snd_card_free(card); 2383 return err; 2384 } 2385 #endif 2386 if ((err = snd_ensoniq_pcm(ensoniq, 0)) < 0) { 2387 snd_card_free(card); 2388 return err; 2389 } 2390 if ((err = snd_ensoniq_pcm2(ensoniq, 1)) < 0) { 2391 snd_card_free(card); 2392 return err; 2393 } 2394 if ((err = snd_ensoniq_midi(ensoniq, 0)) < 0) { 2395 snd_card_free(card); 2396 return err; 2397 } 2398 2399 snd_ensoniq_create_gameport(ensoniq, dev); 2400 2401 strcpy(card->driver, DRIVER_NAME); 2402 2403 strcpy(card->shortname, "Ensoniq AudioPCI"); 2404 sprintf(card->longname, "%s %s at 0x%lx, irq %i", 2405 card->shortname, 2406 card->driver, 2407 ensoniq->port, 2408 ensoniq->irq); 2409 2410 if ((err = snd_card_register(card)) < 0) { 2411 snd_card_free(card); 2412 return err; 2413 } 2414 2415 pci_set_drvdata(pci, card); 2416 dev++; 2417 return 0; 2418 } 2419 2420 static void snd_audiopci_remove(struct pci_dev *pci) 2421 { 2422 snd_card_free(pci_get_drvdata(pci)); 2423 } 2424 2425 static struct pci_driver ens137x_driver = { 2426 .name = KBUILD_MODNAME, 2427 .id_table = snd_audiopci_ids, 2428 .probe = snd_audiopci_probe, 2429 .remove = snd_audiopci_remove, 2430 .driver = { 2431 .pm = SND_ENSONIQ_PM_OPS, 2432 }, 2433 }; 2434 2435 module_pci_driver(ens137x_driver); 2436