1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard 4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 5 * Thomas Sailer <sailer@ife.ee.ethz.ch> 6 */ 7 8 /* Power-Management-Code ( CONFIG_PM ) 9 * for ens1371 only ( FIXME ) 10 * derived from cs4281.c, atiixp.c and via82xx.c 11 * using http://www.alsa-project.org/~tiwai/writing-an-alsa-driver/ 12 * by Kurt J. Bosch 13 */ 14 15 #include <linux/io.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/init.h> 19 #include <linux/pci.h> 20 #include <linux/slab.h> 21 #include <linux/gameport.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 25 #include <sound/core.h> 26 #include <sound/control.h> 27 #include <sound/pcm.h> 28 #include <sound/rawmidi.h> 29 #ifdef CHIP1371 30 #include <sound/ac97_codec.h> 31 #else 32 #include <sound/ak4531_codec.h> 33 #endif 34 #include <sound/initval.h> 35 #include <sound/asoundef.h> 36 37 #ifndef CHIP1371 38 #undef CHIP1370 39 #define CHIP1370 40 #endif 41 42 #ifdef CHIP1370 43 #define DRIVER_NAME "ENS1370" 44 #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */ 45 #else 46 #define DRIVER_NAME "ENS1371" 47 #define CHIP_NAME "ES1371" 48 #endif 49 50 51 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>"); 52 MODULE_LICENSE("GPL"); 53 #ifdef CHIP1370 54 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370"); 55 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370}," 56 "{Creative Labs,SB PCI64/128 (ES1370)}}"); 57 #endif 58 #ifdef CHIP1371 59 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+"); 60 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73}," 61 "{Ensoniq,AudioPCI ES1373}," 62 "{Creative Labs,Ectiva EV1938}," 63 "{Creative Labs,SB PCI64/128 (ES1371/73)}," 64 "{Creative Labs,Vibra PCI128}," 65 "{Ectiva,EV1938}}"); 66 #endif 67 68 #if IS_REACHABLE(CONFIG_GAMEPORT) 69 #define SUPPORT_JOYSTICK 70 #endif 71 72 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 73 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 74 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 75 #ifdef SUPPORT_JOYSTICK 76 #ifdef CHIP1371 77 static int joystick_port[SNDRV_CARDS]; 78 #else 79 static bool joystick[SNDRV_CARDS]; 80 #endif 81 #endif 82 #ifdef CHIP1371 83 static int spdif[SNDRV_CARDS]; 84 static int lineio[SNDRV_CARDS]; 85 #endif 86 87 module_param_array(index, int, NULL, 0444); 88 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard."); 89 module_param_array(id, charp, NULL, 0444); 90 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard."); 91 module_param_array(enable, bool, NULL, 0444); 92 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard."); 93 #ifdef SUPPORT_JOYSTICK 94 #ifdef CHIP1371 95 module_param_hw_array(joystick_port, int, ioport, NULL, 0444); 96 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 97 #else 98 module_param_array(joystick, bool, NULL, 0444); 99 MODULE_PARM_DESC(joystick, "Enable joystick."); 100 #endif 101 #endif /* SUPPORT_JOYSTICK */ 102 #ifdef CHIP1371 103 module_param_array(spdif, int, NULL, 0444); 104 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force)."); 105 module_param_array(lineio, int, NULL, 0444); 106 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force)."); 107 #endif 108 109 /* ES1371 chip ID */ 110 /* This is a little confusing because all ES1371 compatible chips have the 111 same DEVICE_ID, the only thing differentiating them is the REV_ID field. 112 This is only significant if you want to enable features on the later parts. 113 Yes, I know it's stupid and why didn't we use the sub IDs? 114 */ 115 #define ES1371REV_ES1373_A 0x04 116 #define ES1371REV_ES1373_B 0x06 117 #define ES1371REV_CT5880_A 0x07 118 #define CT5880REV_CT5880_C 0x02 119 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */ 120 #define CT5880REV_CT5880_E 0x04 /* mw */ 121 #define ES1371REV_ES1371_B 0x09 122 #define EV1938REV_EV1938_A 0x00 123 #define ES1371REV_ES1373_8 0x08 124 125 /* 126 * Direct registers 127 */ 128 129 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x) 130 131 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */ 132 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */ 133 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */ 134 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */ 135 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */ 136 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */ 137 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */ 138 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */ 139 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */ 140 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */ 141 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */ 142 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03) 143 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */ 144 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */ 145 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */ 146 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */ 147 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */ 148 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */ 149 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */ 150 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */ 151 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */ 152 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */ 153 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */ 154 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */ 155 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */ 156 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */ 157 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */ 158 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */ 159 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */ 160 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */ 161 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */ 162 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */ 163 #define ES_BREQ (1<<7) /* memory bus request enable */ 164 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */ 165 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */ 166 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */ 167 #define ES_UART_EN (1<<3) /* UART enable */ 168 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */ 169 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */ 170 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */ 171 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */ 172 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */ 173 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */ 174 #define ES_INTR (1<<31) /* Interrupt is pending */ 175 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */ 176 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */ 177 #define ES_1373_REAR_BIT26 (1<<26) 178 #define ES_1373_REAR_BIT24 (1<<24) 179 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */ 180 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */ 181 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */ 182 #define ES_1371_TEST (1<<16) /* test ASIC */ 183 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */ 184 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */ 185 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */ 186 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */ 187 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */ 188 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */ 189 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */ 190 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */ 191 #define ES_MCCB (1<<4) /* CCB interrupt pending */ 192 #define ES_UART (1<<3) /* UART interrupt pending */ 193 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */ 194 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */ 195 #define ES_ADC (1<<0) /* ADC channel interrupt pending */ 196 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */ 197 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */ 198 #define ES_RXINT (1<<7) /* RX interrupt occurred */ 199 #define ES_TXINT (1<<2) /* TX interrupt occurred */ 200 #define ES_TXRDY (1<<1) /* transmitter ready */ 201 #define ES_RXRDY (1<<0) /* receiver ready */ 202 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */ 203 #define ES_RXINTEN (1<<7) /* RX interrupt enable */ 204 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */ 205 #define ES_TXINTENM (0x03<<5) /* mask for above */ 206 #define ES_TXINTENI(i) (((i)>>5)&0x03) 207 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */ 208 #define ES_CNTRLM (0x03<<0) /* mask for above */ 209 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */ 210 #define ES_TEST_MODE (1<<0) /* test mode enabled */ 211 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */ 212 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */ 213 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */ 214 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */ 215 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */ 216 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0)) 217 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */ 218 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */ 219 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */ 220 #define EV_1938_CODEC_MAGIC (1<<26) 221 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */ 222 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0)) 223 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD) 224 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff) 225 226 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ 227 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */ 228 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */ 229 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */ 230 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ 231 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ 232 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */ 233 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ 234 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */ 235 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */ 236 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */ 237 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */ 238 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */ 239 240 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */ 241 #define ES_1371_JFAST (1<<31) /* fast joystick timing */ 242 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */ 243 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */ 244 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */ 245 #define ES_1371_VMPUM (0x03<<27) /* mask for above */ 246 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */ 247 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */ 248 #define ES_1371_VCDCM (0x03<<25) /* mask for above */ 249 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */ 250 #define ES_1371_FIRQ (1<<24) /* force an interrupt */ 251 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */ 252 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */ 253 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */ 254 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */ 255 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */ 256 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */ 257 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */ 258 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */ 259 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */ 260 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */ 261 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */ 262 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */ 263 264 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */ 265 266 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */ 267 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */ 268 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */ 269 #define ES_P2_END_INCM (0x07<<19) /* mask for above */ 270 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */ 271 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */ 272 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */ 273 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */ 274 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */ 275 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */ 276 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */ 277 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */ 278 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */ 279 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */ 280 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */ 281 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */ 282 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */ 283 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */ 284 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */ 285 #define ES_R1_MODEM (0x03<<4) /* mask for above */ 286 #define ES_R1_MODEI(i) (((i)>>4)&0x03) 287 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */ 288 #define ES_P2_MODEM (0x03<<2) /* mask for above */ 289 #define ES_P2_MODEI(i) (((i)>>2)&0x03) 290 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */ 291 #define ES_P1_MODEM (0x03<<0) /* mask for above */ 292 #define ES_P1_MODEI(i) (((i)>>0)&0x03) 293 294 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */ 295 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */ 296 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */ 297 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff) 298 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0) 299 #define ES_REG_COUNTM (0xffff<<0) 300 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff) 301 302 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */ 303 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */ 304 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */ 305 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */ 306 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */ 307 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */ 308 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16) 309 #define ES_REG_FCURR_COUNTM (0xffff<<16) 310 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc) 311 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0) 312 #define ES_REG_FSIZEM (0xffff<<0) 313 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff) 314 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */ 315 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */ 316 317 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */ 318 #define ES_REG_UF_VALID (1<<8) 319 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0) 320 #define ES_REG_UF_BYTEM (0xff<<0) 321 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff) 322 323 324 /* 325 * Pages 326 */ 327 328 #define ES_PAGE_DAC 0x0c 329 #define ES_PAGE_ADC 0x0d 330 #define ES_PAGE_UART 0x0e 331 #define ES_PAGE_UART1 0x0f 332 333 /* 334 * Sample rate converter addresses 335 */ 336 337 #define ES_SMPREG_DAC1 0x70 338 #define ES_SMPREG_DAC2 0x74 339 #define ES_SMPREG_ADC 0x78 340 #define ES_SMPREG_VOL_ADC 0x6c 341 #define ES_SMPREG_VOL_DAC1 0x7c 342 #define ES_SMPREG_VOL_DAC2 0x7e 343 #define ES_SMPREG_TRUNC_N 0x00 344 #define ES_SMPREG_INT_REGS 0x01 345 #define ES_SMPREG_ACCUM_FRAC 0x02 346 #define ES_SMPREG_VFREQ_FRAC 0x03 347 348 /* 349 * Some contants 350 */ 351 352 #define ES_1370_SRCLOCK 1411200 353 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2) 354 355 /* 356 * Open modes 357 */ 358 359 #define ES_MODE_PLAY1 0x0001 360 #define ES_MODE_PLAY2 0x0002 361 #define ES_MODE_CAPTURE 0x0004 362 363 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */ 364 #define ES_MODE_INPUT 0x0002 /* for MIDI */ 365 366 /* 367 368 */ 369 370 struct ensoniq { 371 spinlock_t reg_lock; 372 struct mutex src_mutex; 373 374 int irq; 375 376 unsigned long playback1size; 377 unsigned long playback2size; 378 unsigned long capture3size; 379 380 unsigned long port; 381 unsigned int mode; 382 unsigned int uartm; /* UART mode */ 383 384 unsigned int ctrl; /* control register */ 385 unsigned int sctrl; /* serial control register */ 386 unsigned int cssr; /* control status register */ 387 unsigned int uartc; /* uart control register */ 388 unsigned int rev; /* chip revision */ 389 390 union { 391 #ifdef CHIP1371 392 struct { 393 struct snd_ac97 *ac97; 394 } es1371; 395 #else 396 struct { 397 int pclkdiv_lock; 398 struct snd_ak4531 *ak4531; 399 } es1370; 400 #endif 401 } u; 402 403 struct pci_dev *pci; 404 struct snd_card *card; 405 struct snd_pcm *pcm1; /* DAC1/ADC PCM */ 406 struct snd_pcm *pcm2; /* DAC2 PCM */ 407 struct snd_pcm_substream *playback1_substream; 408 struct snd_pcm_substream *playback2_substream; 409 struct snd_pcm_substream *capture_substream; 410 unsigned int p1_dma_size; 411 unsigned int p2_dma_size; 412 unsigned int c_dma_size; 413 unsigned int p1_period_size; 414 unsigned int p2_period_size; 415 unsigned int c_period_size; 416 struct snd_rawmidi *rmidi; 417 struct snd_rawmidi_substream *midi_input; 418 struct snd_rawmidi_substream *midi_output; 419 420 unsigned int spdif; 421 unsigned int spdif_default; 422 unsigned int spdif_stream; 423 424 #ifdef CHIP1370 425 struct snd_dma_buffer dma_bug; 426 #endif 427 428 #ifdef SUPPORT_JOYSTICK 429 struct gameport *gameport; 430 #endif 431 }; 432 433 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id); 434 435 static const struct pci_device_id snd_audiopci_ids[] = { 436 #ifdef CHIP1370 437 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */ 438 #endif 439 #ifdef CHIP1371 440 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */ 441 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */ 442 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */ 443 #endif 444 { 0, } 445 }; 446 447 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids); 448 449 /* 450 * constants 451 */ 452 453 #define POLL_COUNT 0xa000 454 455 #ifdef CHIP1370 456 static const unsigned int snd_es1370_fixed_rates[] = 457 {5512, 11025, 22050, 44100}; 458 static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = { 459 .count = 4, 460 .list = snd_es1370_fixed_rates, 461 .mask = 0, 462 }; 463 static const struct snd_ratnum es1370_clock = { 464 .num = ES_1370_SRCLOCK, 465 .den_min = 29, 466 .den_max = 353, 467 .den_step = 1, 468 }; 469 static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = { 470 .nrats = 1, 471 .rats = &es1370_clock, 472 }; 473 #else 474 static const struct snd_ratden es1371_dac_clock = { 475 .num_min = 3000 * (1 << 15), 476 .num_max = 48000 * (1 << 15), 477 .num_step = 3000, 478 .den = 1 << 15, 479 }; 480 static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = { 481 .nrats = 1, 482 .rats = &es1371_dac_clock, 483 }; 484 static const struct snd_ratnum es1371_adc_clock = { 485 .num = 48000 << 15, 486 .den_min = 32768, 487 .den_max = 393216, 488 .den_step = 1, 489 }; 490 static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = { 491 .nrats = 1, 492 .rats = &es1371_adc_clock, 493 }; 494 #endif 495 static const unsigned int snd_ensoniq_sample_shift[] = 496 {0, 1, 1, 2}; 497 498 /* 499 * common I/O routines 500 */ 501 502 #ifdef CHIP1371 503 504 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq) 505 { 506 unsigned int t, r = 0; 507 508 for (t = 0; t < POLL_COUNT; t++) { 509 r = inl(ES_REG(ensoniq, 1371_SMPRATE)); 510 if ((r & ES_1371_SRC_RAM_BUSY) == 0) 511 return r; 512 cond_resched(); 513 } 514 dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n", 515 ES_REG(ensoniq, 1371_SMPRATE), r); 516 return 0; 517 } 518 519 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg) 520 { 521 unsigned int temp, i, orig, r; 522 523 /* wait for ready */ 524 temp = orig = snd_es1371_wait_src_ready(ensoniq); 525 526 /* expose the SRC state bits */ 527 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 528 ES_1371_DIS_P2 | ES_1371_DIS_R1); 529 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; 530 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 531 532 /* now, wait for busy and the correct time to read */ 533 temp = snd_es1371_wait_src_ready(ensoniq); 534 535 if ((temp & 0x00870000) != 0x00010000) { 536 /* wait for the right state */ 537 for (i = 0; i < POLL_COUNT; i++) { 538 temp = inl(ES_REG(ensoniq, 1371_SMPRATE)); 539 if ((temp & 0x00870000) == 0x00010000) 540 break; 541 } 542 } 543 544 /* hide the state bits */ 545 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 546 ES_1371_DIS_P2 | ES_1371_DIS_R1); 547 r |= ES_1371_SRC_RAM_ADDRO(reg); 548 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 549 550 return temp; 551 } 552 553 static void snd_es1371_src_write(struct ensoniq * ensoniq, 554 unsigned short reg, unsigned short data) 555 { 556 unsigned int r; 557 558 r = snd_es1371_wait_src_ready(ensoniq) & 559 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 560 ES_1371_DIS_P2 | ES_1371_DIS_R1); 561 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); 562 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE)); 563 } 564 565 #endif /* CHIP1371 */ 566 567 #ifdef CHIP1370 568 569 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531, 570 unsigned short reg, unsigned short val) 571 { 572 struct ensoniq *ensoniq = ak4531->private_data; 573 unsigned long end_time = jiffies + HZ / 10; 574 575 #if 0 576 dev_dbg(ensoniq->card->dev, 577 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", 578 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 579 #endif 580 do { 581 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) { 582 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 583 return; 584 } 585 schedule_timeout_uninterruptible(1); 586 } while (time_after(end_time, jiffies)); 587 dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n", 588 inl(ES_REG(ensoniq, STATUS))); 589 } 590 591 #endif /* CHIP1370 */ 592 593 #ifdef CHIP1371 594 595 static inline bool is_ev1938(struct ensoniq *ensoniq) 596 { 597 return ensoniq->pci->device == 0x8938; 598 } 599 600 static void snd_es1371_codec_write(struct snd_ac97 *ac97, 601 unsigned short reg, unsigned short val) 602 { 603 struct ensoniq *ensoniq = ac97->private_data; 604 unsigned int t, x, flag; 605 606 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0; 607 mutex_lock(&ensoniq->src_mutex); 608 for (t = 0; t < POLL_COUNT; t++) { 609 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 610 /* save the current state for latter */ 611 x = snd_es1371_wait_src_ready(ensoniq); 612 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 613 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 614 ES_REG(ensoniq, 1371_SMPRATE)); 615 /* wait for not busy (state 0) first to avoid 616 transition states */ 617 for (t = 0; t < POLL_COUNT; t++) { 618 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 619 0x00000000) 620 break; 621 } 622 /* wait for a SAFE time to write addr/data and then do it, dammit */ 623 for (t = 0; t < POLL_COUNT; t++) { 624 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 625 0x00010000) 626 break; 627 } 628 outl(ES_1371_CODEC_WRITE(reg, val) | flag, 629 ES_REG(ensoniq, 1371_CODEC)); 630 /* restore SRC reg */ 631 snd_es1371_wait_src_ready(ensoniq); 632 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 633 mutex_unlock(&ensoniq->src_mutex); 634 return; 635 } 636 } 637 mutex_unlock(&ensoniq->src_mutex); 638 dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n", 639 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 640 } 641 642 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97, 643 unsigned short reg) 644 { 645 struct ensoniq *ensoniq = ac97->private_data; 646 unsigned int t, x, flag, fail = 0; 647 648 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0; 649 __again: 650 mutex_lock(&ensoniq->src_mutex); 651 for (t = 0; t < POLL_COUNT; t++) { 652 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 653 /* save the current state for latter */ 654 x = snd_es1371_wait_src_ready(ensoniq); 655 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 656 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 657 ES_REG(ensoniq, 1371_SMPRATE)); 658 /* wait for not busy (state 0) first to avoid 659 transition states */ 660 for (t = 0; t < POLL_COUNT; t++) { 661 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 662 0x00000000) 663 break; 664 } 665 /* wait for a SAFE time to write addr/data and then do it, dammit */ 666 for (t = 0; t < POLL_COUNT; t++) { 667 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 668 0x00010000) 669 break; 670 } 671 outl(ES_1371_CODEC_READS(reg) | flag, 672 ES_REG(ensoniq, 1371_CODEC)); 673 /* restore SRC reg */ 674 snd_es1371_wait_src_ready(ensoniq); 675 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 676 /* wait for WIP again */ 677 for (t = 0; t < POLL_COUNT; t++) { 678 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) 679 break; 680 } 681 /* now wait for the stinkin' data (RDY) */ 682 for (t = 0; t < POLL_COUNT; t++) { 683 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) { 684 if (is_ev1938(ensoniq)) { 685 for (t = 0; t < 100; t++) 686 inl(ES_REG(ensoniq, CONTROL)); 687 x = inl(ES_REG(ensoniq, 1371_CODEC)); 688 } 689 mutex_unlock(&ensoniq->src_mutex); 690 return ES_1371_CODEC_READ(x); 691 } 692 } 693 mutex_unlock(&ensoniq->src_mutex); 694 if (++fail > 10) { 695 dev_err(ensoniq->card->dev, 696 "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", 697 ES_REG(ensoniq, 1371_CODEC), reg, 698 inl(ES_REG(ensoniq, 1371_CODEC))); 699 return 0; 700 } 701 goto __again; 702 } 703 } 704 mutex_unlock(&ensoniq->src_mutex); 705 dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n", 706 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 707 return 0; 708 } 709 710 static void snd_es1371_codec_wait(struct snd_ac97 *ac97) 711 { 712 msleep(750); 713 snd_es1371_codec_read(ac97, AC97_RESET); 714 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); 715 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); 716 msleep(50); 717 } 718 719 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate) 720 { 721 unsigned int n, truncm, freq; 722 723 mutex_lock(&ensoniq->src_mutex); 724 n = rate / 3000; 725 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 726 n--; 727 truncm = (21 * n - 1) | 1; 728 freq = ((48000UL << 15) / rate) * n; 729 if (rate >= 24000) { 730 if (truncm > 239) 731 truncm = 239; 732 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 733 (((239 - truncm) >> 1) << 9) | (n << 4)); 734 } else { 735 if (truncm > 119) 736 truncm = 119; 737 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 738 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 739 } 740 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 741 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + 742 ES_SMPREG_INT_REGS) & 0x00ff) | 743 ((freq >> 5) & 0xfc00)); 744 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 745 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8); 746 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8); 747 mutex_unlock(&ensoniq->src_mutex); 748 } 749 750 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate) 751 { 752 unsigned int freq, r; 753 754 mutex_lock(&ensoniq->src_mutex); 755 freq = ((rate << 15) + 1500) / 3000; 756 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 757 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 758 ES_1371_DIS_P1; 759 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 760 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 761 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + 762 ES_SMPREG_INT_REGS) & 0x00ff) | 763 ((freq >> 5) & 0xfc00)); 764 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 765 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 766 ES_1371_DIS_P2 | ES_1371_DIS_R1)); 767 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 768 mutex_unlock(&ensoniq->src_mutex); 769 } 770 771 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate) 772 { 773 unsigned int freq, r; 774 775 mutex_lock(&ensoniq->src_mutex); 776 freq = ((rate << 15) + 1500) / 3000; 777 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 778 ES_1371_DIS_P1 | ES_1371_DIS_R1)) | 779 ES_1371_DIS_P2; 780 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 781 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 782 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + 783 ES_SMPREG_INT_REGS) & 0x00ff) | 784 ((freq >> 5) & 0xfc00)); 785 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, 786 freq & 0x7fff); 787 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 788 ES_1371_DIS_P1 | ES_1371_DIS_R1)); 789 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 790 mutex_unlock(&ensoniq->src_mutex); 791 } 792 793 #endif /* CHIP1371 */ 794 795 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd) 796 { 797 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 798 switch (cmd) { 799 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 800 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 801 { 802 unsigned int what = 0; 803 struct snd_pcm_substream *s; 804 snd_pcm_group_for_each_entry(s, substream) { 805 if (s == ensoniq->playback1_substream) { 806 what |= ES_P1_PAUSE; 807 snd_pcm_trigger_done(s, substream); 808 } else if (s == ensoniq->playback2_substream) { 809 what |= ES_P2_PAUSE; 810 snd_pcm_trigger_done(s, substream); 811 } else if (s == ensoniq->capture_substream) 812 return -EINVAL; 813 } 814 spin_lock(&ensoniq->reg_lock); 815 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 816 ensoniq->sctrl |= what; 817 else 818 ensoniq->sctrl &= ~what; 819 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 820 spin_unlock(&ensoniq->reg_lock); 821 break; 822 } 823 case SNDRV_PCM_TRIGGER_START: 824 case SNDRV_PCM_TRIGGER_STOP: 825 { 826 unsigned int what = 0; 827 struct snd_pcm_substream *s; 828 snd_pcm_group_for_each_entry(s, substream) { 829 if (s == ensoniq->playback1_substream) { 830 what |= ES_DAC1_EN; 831 snd_pcm_trigger_done(s, substream); 832 } else if (s == ensoniq->playback2_substream) { 833 what |= ES_DAC2_EN; 834 snd_pcm_trigger_done(s, substream); 835 } else if (s == ensoniq->capture_substream) { 836 what |= ES_ADC_EN; 837 snd_pcm_trigger_done(s, substream); 838 } 839 } 840 spin_lock(&ensoniq->reg_lock); 841 if (cmd == SNDRV_PCM_TRIGGER_START) 842 ensoniq->ctrl |= what; 843 else 844 ensoniq->ctrl &= ~what; 845 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 846 spin_unlock(&ensoniq->reg_lock); 847 break; 848 } 849 default: 850 return -EINVAL; 851 } 852 return 0; 853 } 854 855 /* 856 * PCM part 857 */ 858 859 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream, 860 struct snd_pcm_hw_params *hw_params) 861 { 862 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 863 } 864 865 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream) 866 { 867 return snd_pcm_lib_free_pages(substream); 868 } 869 870 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream) 871 { 872 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 873 struct snd_pcm_runtime *runtime = substream->runtime; 874 unsigned int mode = 0; 875 876 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream); 877 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream); 878 if (snd_pcm_format_width(runtime->format) == 16) 879 mode |= 0x02; 880 if (runtime->channels > 1) 881 mode |= 0x01; 882 spin_lock_irq(&ensoniq->reg_lock); 883 ensoniq->ctrl &= ~ES_DAC1_EN; 884 #ifdef CHIP1371 885 /* 48k doesn't need SRC (it breaks AC3-passthru) */ 886 if (runtime->rate == 48000) 887 ensoniq->ctrl |= ES_1373_BYPASS_P1; 888 else 889 ensoniq->ctrl &= ~ES_1373_BYPASS_P1; 890 #endif 891 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 892 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 893 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME)); 894 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE)); 895 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM); 896 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode); 897 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 898 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 899 ES_REG(ensoniq, DAC1_COUNT)); 900 #ifdef CHIP1370 901 ensoniq->ctrl &= ~ES_1370_WTSRSELM; 902 switch (runtime->rate) { 903 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; 904 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; 905 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; 906 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; 907 default: snd_BUG(); 908 } 909 #endif 910 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 911 spin_unlock_irq(&ensoniq->reg_lock); 912 #ifndef CHIP1370 913 snd_es1371_dac1_rate(ensoniq, runtime->rate); 914 #endif 915 return 0; 916 } 917 918 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream) 919 { 920 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 921 struct snd_pcm_runtime *runtime = substream->runtime; 922 unsigned int mode = 0; 923 924 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream); 925 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream); 926 if (snd_pcm_format_width(runtime->format) == 16) 927 mode |= 0x02; 928 if (runtime->channels > 1) 929 mode |= 0x01; 930 spin_lock_irq(&ensoniq->reg_lock); 931 ensoniq->ctrl &= ~ES_DAC2_EN; 932 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 933 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 934 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME)); 935 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE)); 936 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN | 937 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM); 938 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) | 939 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0); 940 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 941 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 942 ES_REG(ensoniq, DAC2_COUNT)); 943 #ifdef CHIP1370 944 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) { 945 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 946 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 947 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2; 948 } 949 #endif 950 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 951 spin_unlock_irq(&ensoniq->reg_lock); 952 #ifndef CHIP1370 953 snd_es1371_dac2_rate(ensoniq, runtime->rate); 954 #endif 955 return 0; 956 } 957 958 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream) 959 { 960 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 961 struct snd_pcm_runtime *runtime = substream->runtime; 962 unsigned int mode = 0; 963 964 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream); 965 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream); 966 if (snd_pcm_format_width(runtime->format) == 16) 967 mode |= 0x02; 968 if (runtime->channels > 1) 969 mode |= 0x01; 970 spin_lock_irq(&ensoniq->reg_lock); 971 ensoniq->ctrl &= ~ES_ADC_EN; 972 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 973 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 974 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME)); 975 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE)); 976 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM); 977 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode); 978 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 979 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 980 ES_REG(ensoniq, ADC_COUNT)); 981 #ifdef CHIP1370 982 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) { 983 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 984 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 985 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE; 986 } 987 #endif 988 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 989 spin_unlock_irq(&ensoniq->reg_lock); 990 #ifndef CHIP1370 991 snd_es1371_adc_rate(ensoniq, runtime->rate); 992 #endif 993 return 0; 994 } 995 996 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream) 997 { 998 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 999 size_t ptr; 1000 1001 spin_lock(&ensoniq->reg_lock); 1002 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { 1003 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1004 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE))); 1005 ptr = bytes_to_frames(substream->runtime, ptr); 1006 } else { 1007 ptr = 0; 1008 } 1009 spin_unlock(&ensoniq->reg_lock); 1010 return ptr; 1011 } 1012 1013 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream) 1014 { 1015 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1016 size_t ptr; 1017 1018 spin_lock(&ensoniq->reg_lock); 1019 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { 1020 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1021 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE))); 1022 ptr = bytes_to_frames(substream->runtime, ptr); 1023 } else { 1024 ptr = 0; 1025 } 1026 spin_unlock(&ensoniq->reg_lock); 1027 return ptr; 1028 } 1029 1030 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream) 1031 { 1032 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1033 size_t ptr; 1034 1035 spin_lock(&ensoniq->reg_lock); 1036 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) { 1037 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1038 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE))); 1039 ptr = bytes_to_frames(substream->runtime, ptr); 1040 } else { 1041 ptr = 0; 1042 } 1043 spin_unlock(&ensoniq->reg_lock); 1044 return ptr; 1045 } 1046 1047 static const struct snd_pcm_hardware snd_ensoniq_playback1 = 1048 { 1049 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1050 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1051 SNDRV_PCM_INFO_MMAP_VALID | 1052 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START), 1053 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1054 .rates = 1055 #ifndef CHIP1370 1056 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1057 #else 1058 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */ 1059 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 1060 SNDRV_PCM_RATE_44100), 1061 #endif 1062 .rate_min = 4000, 1063 .rate_max = 48000, 1064 .channels_min = 1, 1065 .channels_max = 2, 1066 .buffer_bytes_max = (128*1024), 1067 .period_bytes_min = 64, 1068 .period_bytes_max = (128*1024), 1069 .periods_min = 1, 1070 .periods_max = 1024, 1071 .fifo_size = 0, 1072 }; 1073 1074 static const struct snd_pcm_hardware snd_ensoniq_playback2 = 1075 { 1076 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1077 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1078 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 1079 SNDRV_PCM_INFO_SYNC_START), 1080 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1081 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1082 .rate_min = 4000, 1083 .rate_max = 48000, 1084 .channels_min = 1, 1085 .channels_max = 2, 1086 .buffer_bytes_max = (128*1024), 1087 .period_bytes_min = 64, 1088 .period_bytes_max = (128*1024), 1089 .periods_min = 1, 1090 .periods_max = 1024, 1091 .fifo_size = 0, 1092 }; 1093 1094 static const struct snd_pcm_hardware snd_ensoniq_capture = 1095 { 1096 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1097 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1098 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1099 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1100 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1101 .rate_min = 4000, 1102 .rate_max = 48000, 1103 .channels_min = 1, 1104 .channels_max = 2, 1105 .buffer_bytes_max = (128*1024), 1106 .period_bytes_min = 64, 1107 .period_bytes_max = (128*1024), 1108 .periods_min = 1, 1109 .periods_max = 1024, 1110 .fifo_size = 0, 1111 }; 1112 1113 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream) 1114 { 1115 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1116 struct snd_pcm_runtime *runtime = substream->runtime; 1117 1118 ensoniq->mode |= ES_MODE_PLAY1; 1119 ensoniq->playback1_substream = substream; 1120 runtime->hw = snd_ensoniq_playback1; 1121 snd_pcm_set_sync(substream); 1122 spin_lock_irq(&ensoniq->reg_lock); 1123 if (ensoniq->spdif && ensoniq->playback2_substream == NULL) 1124 ensoniq->spdif_stream = ensoniq->spdif_default; 1125 spin_unlock_irq(&ensoniq->reg_lock); 1126 #ifdef CHIP1370 1127 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1128 &snd_es1370_hw_constraints_rates); 1129 #else 1130 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1131 &snd_es1371_hw_constraints_dac_clock); 1132 #endif 1133 return 0; 1134 } 1135 1136 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream) 1137 { 1138 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1139 struct snd_pcm_runtime *runtime = substream->runtime; 1140 1141 ensoniq->mode |= ES_MODE_PLAY2; 1142 ensoniq->playback2_substream = substream; 1143 runtime->hw = snd_ensoniq_playback2; 1144 snd_pcm_set_sync(substream); 1145 spin_lock_irq(&ensoniq->reg_lock); 1146 if (ensoniq->spdif && ensoniq->playback1_substream == NULL) 1147 ensoniq->spdif_stream = ensoniq->spdif_default; 1148 spin_unlock_irq(&ensoniq->reg_lock); 1149 #ifdef CHIP1370 1150 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1151 &snd_es1370_hw_constraints_clock); 1152 #else 1153 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1154 &snd_es1371_hw_constraints_dac_clock); 1155 #endif 1156 return 0; 1157 } 1158 1159 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream) 1160 { 1161 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1162 struct snd_pcm_runtime *runtime = substream->runtime; 1163 1164 ensoniq->mode |= ES_MODE_CAPTURE; 1165 ensoniq->capture_substream = substream; 1166 runtime->hw = snd_ensoniq_capture; 1167 snd_pcm_set_sync(substream); 1168 #ifdef CHIP1370 1169 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1170 &snd_es1370_hw_constraints_clock); 1171 #else 1172 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1173 &snd_es1371_hw_constraints_adc_clock); 1174 #endif 1175 return 0; 1176 } 1177 1178 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream) 1179 { 1180 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1181 1182 ensoniq->playback1_substream = NULL; 1183 ensoniq->mode &= ~ES_MODE_PLAY1; 1184 return 0; 1185 } 1186 1187 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream) 1188 { 1189 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1190 1191 ensoniq->playback2_substream = NULL; 1192 spin_lock_irq(&ensoniq->reg_lock); 1193 #ifdef CHIP1370 1194 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2; 1195 #endif 1196 ensoniq->mode &= ~ES_MODE_PLAY2; 1197 spin_unlock_irq(&ensoniq->reg_lock); 1198 return 0; 1199 } 1200 1201 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream) 1202 { 1203 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1204 1205 ensoniq->capture_substream = NULL; 1206 spin_lock_irq(&ensoniq->reg_lock); 1207 #ifdef CHIP1370 1208 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE; 1209 #endif 1210 ensoniq->mode &= ~ES_MODE_CAPTURE; 1211 spin_unlock_irq(&ensoniq->reg_lock); 1212 return 0; 1213 } 1214 1215 static const struct snd_pcm_ops snd_ensoniq_playback1_ops = { 1216 .open = snd_ensoniq_playback1_open, 1217 .close = snd_ensoniq_playback1_close, 1218 .ioctl = snd_pcm_lib_ioctl, 1219 .hw_params = snd_ensoniq_hw_params, 1220 .hw_free = snd_ensoniq_hw_free, 1221 .prepare = snd_ensoniq_playback1_prepare, 1222 .trigger = snd_ensoniq_trigger, 1223 .pointer = snd_ensoniq_playback1_pointer, 1224 }; 1225 1226 static const struct snd_pcm_ops snd_ensoniq_playback2_ops = { 1227 .open = snd_ensoniq_playback2_open, 1228 .close = snd_ensoniq_playback2_close, 1229 .ioctl = snd_pcm_lib_ioctl, 1230 .hw_params = snd_ensoniq_hw_params, 1231 .hw_free = snd_ensoniq_hw_free, 1232 .prepare = snd_ensoniq_playback2_prepare, 1233 .trigger = snd_ensoniq_trigger, 1234 .pointer = snd_ensoniq_playback2_pointer, 1235 }; 1236 1237 static const struct snd_pcm_ops snd_ensoniq_capture_ops = { 1238 .open = snd_ensoniq_capture_open, 1239 .close = snd_ensoniq_capture_close, 1240 .ioctl = snd_pcm_lib_ioctl, 1241 .hw_params = snd_ensoniq_hw_params, 1242 .hw_free = snd_ensoniq_hw_free, 1243 .prepare = snd_ensoniq_capture_prepare, 1244 .trigger = snd_ensoniq_trigger, 1245 .pointer = snd_ensoniq_capture_pointer, 1246 }; 1247 1248 static const struct snd_pcm_chmap_elem surround_map[] = { 1249 { .channels = 1, 1250 .map = { SNDRV_CHMAP_MONO } }, 1251 { .channels = 2, 1252 .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 1253 { } 1254 }; 1255 1256 static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device) 1257 { 1258 struct snd_pcm *pcm; 1259 int err; 1260 1261 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm); 1262 if (err < 0) 1263 return err; 1264 1265 #ifdef CHIP1370 1266 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1267 #else 1268 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1269 #endif 1270 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops); 1271 1272 pcm->private_data = ensoniq; 1273 pcm->info_flags = 0; 1274 strcpy(pcm->name, CHIP_NAME " DAC2/ADC"); 1275 ensoniq->pcm1 = pcm; 1276 1277 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1278 &ensoniq->pci->dev, 1279 64*1024, 128*1024); 1280 1281 #ifdef CHIP1370 1282 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1283 surround_map, 2, 0, NULL); 1284 #else 1285 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1286 snd_pcm_std_chmaps, 2, 0, NULL); 1287 #endif 1288 return err; 1289 } 1290 1291 static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device) 1292 { 1293 struct snd_pcm *pcm; 1294 int err; 1295 1296 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm); 1297 if (err < 0) 1298 return err; 1299 1300 #ifdef CHIP1370 1301 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1302 #else 1303 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1304 #endif 1305 pcm->private_data = ensoniq; 1306 pcm->info_flags = 0; 1307 strcpy(pcm->name, CHIP_NAME " DAC1"); 1308 ensoniq->pcm2 = pcm; 1309 1310 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1311 &ensoniq->pci->dev, 1312 64*1024, 128*1024); 1313 1314 #ifdef CHIP1370 1315 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1316 snd_pcm_std_chmaps, 2, 0, NULL); 1317 #else 1318 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1319 surround_map, 2, 0, NULL); 1320 #endif 1321 return err; 1322 } 1323 1324 /* 1325 * Mixer section 1326 */ 1327 1328 /* 1329 * ENS1371 mixer (including SPDIF interface) 1330 */ 1331 #ifdef CHIP1371 1332 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol, 1333 struct snd_ctl_elem_info *uinfo) 1334 { 1335 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1336 uinfo->count = 1; 1337 return 0; 1338 } 1339 1340 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol, 1341 struct snd_ctl_elem_value *ucontrol) 1342 { 1343 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1344 spin_lock_irq(&ensoniq->reg_lock); 1345 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff; 1346 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff; 1347 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff; 1348 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff; 1349 spin_unlock_irq(&ensoniq->reg_lock); 1350 return 0; 1351 } 1352 1353 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol, 1354 struct snd_ctl_elem_value *ucontrol) 1355 { 1356 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1357 unsigned int val; 1358 int change; 1359 1360 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1361 ((u32)ucontrol->value.iec958.status[1] << 8) | 1362 ((u32)ucontrol->value.iec958.status[2] << 16) | 1363 ((u32)ucontrol->value.iec958.status[3] << 24); 1364 spin_lock_irq(&ensoniq->reg_lock); 1365 change = ensoniq->spdif_default != val; 1366 ensoniq->spdif_default = val; 1367 if (change && ensoniq->playback1_substream == NULL && 1368 ensoniq->playback2_substream == NULL) 1369 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1370 spin_unlock_irq(&ensoniq->reg_lock); 1371 return change; 1372 } 1373 1374 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol, 1375 struct snd_ctl_elem_value *ucontrol) 1376 { 1377 ucontrol->value.iec958.status[0] = 0xff; 1378 ucontrol->value.iec958.status[1] = 0xff; 1379 ucontrol->value.iec958.status[2] = 0xff; 1380 ucontrol->value.iec958.status[3] = 0xff; 1381 return 0; 1382 } 1383 1384 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol, 1385 struct snd_ctl_elem_value *ucontrol) 1386 { 1387 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1388 spin_lock_irq(&ensoniq->reg_lock); 1389 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff; 1390 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff; 1391 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff; 1392 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff; 1393 spin_unlock_irq(&ensoniq->reg_lock); 1394 return 0; 1395 } 1396 1397 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol, 1398 struct snd_ctl_elem_value *ucontrol) 1399 { 1400 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1401 unsigned int val; 1402 int change; 1403 1404 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1405 ((u32)ucontrol->value.iec958.status[1] << 8) | 1406 ((u32)ucontrol->value.iec958.status[2] << 16) | 1407 ((u32)ucontrol->value.iec958.status[3] << 24); 1408 spin_lock_irq(&ensoniq->reg_lock); 1409 change = ensoniq->spdif_stream != val; 1410 ensoniq->spdif_stream = val; 1411 if (change && (ensoniq->playback1_substream != NULL || 1412 ensoniq->playback2_substream != NULL)) 1413 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1414 spin_unlock_irq(&ensoniq->reg_lock); 1415 return change; 1416 } 1417 1418 #define ES1371_SPDIF(xname) \ 1419 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \ 1420 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put } 1421 1422 #define snd_es1371_spdif_info snd_ctl_boolean_mono_info 1423 1424 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol, 1425 struct snd_ctl_elem_value *ucontrol) 1426 { 1427 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1428 1429 spin_lock_irq(&ensoniq->reg_lock); 1430 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; 1431 spin_unlock_irq(&ensoniq->reg_lock); 1432 return 0; 1433 } 1434 1435 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol, 1436 struct snd_ctl_elem_value *ucontrol) 1437 { 1438 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1439 unsigned int nval1, nval2; 1440 int change; 1441 1442 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0; 1443 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0; 1444 spin_lock_irq(&ensoniq->reg_lock); 1445 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; 1446 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; 1447 ensoniq->ctrl |= nval1; 1448 ensoniq->cssr &= ~ES_1373_SPDIF_EN; 1449 ensoniq->cssr |= nval2; 1450 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1451 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1452 spin_unlock_irq(&ensoniq->reg_lock); 1453 return change; 1454 } 1455 1456 1457 /* spdif controls */ 1458 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] = { 1459 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)), 1460 { 1461 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1462 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1463 .info = snd_ens1373_spdif_info, 1464 .get = snd_ens1373_spdif_default_get, 1465 .put = snd_ens1373_spdif_default_put, 1466 }, 1467 { 1468 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1469 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1470 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 1471 .info = snd_ens1373_spdif_info, 1472 .get = snd_ens1373_spdif_mask_get 1473 }, 1474 { 1475 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1476 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1477 .info = snd_ens1373_spdif_info, 1478 .get = snd_ens1373_spdif_stream_get, 1479 .put = snd_ens1373_spdif_stream_put 1480 }, 1481 }; 1482 1483 1484 #define snd_es1373_rear_info snd_ctl_boolean_mono_info 1485 1486 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol, 1487 struct snd_ctl_elem_value *ucontrol) 1488 { 1489 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1490 int val = 0; 1491 1492 spin_lock_irq(&ensoniq->reg_lock); 1493 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26| 1494 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26) 1495 val = 1; 1496 ucontrol->value.integer.value[0] = val; 1497 spin_unlock_irq(&ensoniq->reg_lock); 1498 return 0; 1499 } 1500 1501 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol, 1502 struct snd_ctl_elem_value *ucontrol) 1503 { 1504 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1505 unsigned int nval1; 1506 int change; 1507 1508 nval1 = ucontrol->value.integer.value[0] ? 1509 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1510 spin_lock_irq(&ensoniq->reg_lock); 1511 change = (ensoniq->cssr & (ES_1373_REAR_BIT27| 1512 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1; 1513 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24); 1514 ensoniq->cssr |= nval1; 1515 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1516 spin_unlock_irq(&ensoniq->reg_lock); 1517 return change; 1518 } 1519 1520 static const struct snd_kcontrol_new snd_ens1373_rear = 1521 { 1522 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1523 .name = "AC97 2ch->4ch Copy Switch", 1524 .info = snd_es1373_rear_info, 1525 .get = snd_es1373_rear_get, 1526 .put = snd_es1373_rear_put, 1527 }; 1528 1529 #define snd_es1373_line_info snd_ctl_boolean_mono_info 1530 1531 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol, 1532 struct snd_ctl_elem_value *ucontrol) 1533 { 1534 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1535 int val = 0; 1536 1537 spin_lock_irq(&ensoniq->reg_lock); 1538 if (ensoniq->ctrl & ES_1371_GPIO_OUT(4)) 1539 val = 1; 1540 ucontrol->value.integer.value[0] = val; 1541 spin_unlock_irq(&ensoniq->reg_lock); 1542 return 0; 1543 } 1544 1545 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol, 1546 struct snd_ctl_elem_value *ucontrol) 1547 { 1548 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1549 int changed; 1550 unsigned int ctrl; 1551 1552 spin_lock_irq(&ensoniq->reg_lock); 1553 ctrl = ensoniq->ctrl; 1554 if (ucontrol->value.integer.value[0]) 1555 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ 1556 else 1557 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); 1558 changed = (ctrl != ensoniq->ctrl); 1559 if (changed) 1560 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1561 spin_unlock_irq(&ensoniq->reg_lock); 1562 return changed; 1563 } 1564 1565 static const struct snd_kcontrol_new snd_ens1373_line = 1566 { 1567 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1568 .name = "Line In->Rear Out Switch", 1569 .info = snd_es1373_line_info, 1570 .get = snd_es1373_line_get, 1571 .put = snd_es1373_line_put, 1572 }; 1573 1574 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97) 1575 { 1576 struct ensoniq *ensoniq = ac97->private_data; 1577 ensoniq->u.es1371.ac97 = NULL; 1578 } 1579 1580 struct es1371_quirk { 1581 unsigned short vid; /* vendor ID */ 1582 unsigned short did; /* device ID */ 1583 unsigned char rev; /* revision */ 1584 }; 1585 1586 static int es1371_quirk_lookup(struct ensoniq *ensoniq, 1587 struct es1371_quirk *list) 1588 { 1589 while (list->vid != (unsigned short)PCI_ANY_ID) { 1590 if (ensoniq->pci->vendor == list->vid && 1591 ensoniq->pci->device == list->did && 1592 ensoniq->rev == list->rev) 1593 return 1; 1594 list++; 1595 } 1596 return 0; 1597 } 1598 1599 static struct es1371_quirk es1371_spdif_present[] = { 1600 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1601 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1602 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1603 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1604 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1605 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1606 }; 1607 1608 static struct snd_pci_quirk ens1373_line_quirk[] = { 1609 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */ 1610 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */ 1611 { } /* end */ 1612 }; 1613 1614 static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq, 1615 int has_spdif, int has_line) 1616 { 1617 struct snd_card *card = ensoniq->card; 1618 struct snd_ac97_bus *pbus; 1619 struct snd_ac97_template ac97; 1620 int err; 1621 static struct snd_ac97_bus_ops ops = { 1622 .write = snd_es1371_codec_write, 1623 .read = snd_es1371_codec_read, 1624 .wait = snd_es1371_codec_wait, 1625 }; 1626 1627 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0) 1628 return err; 1629 1630 memset(&ac97, 0, sizeof(ac97)); 1631 ac97.private_data = ensoniq; 1632 ac97.private_free = snd_ensoniq_mixer_free_ac97; 1633 ac97.pci = ensoniq->pci; 1634 ac97.scaps = AC97_SCAP_AUDIO; 1635 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0) 1636 return err; 1637 if (has_spdif > 0 || 1638 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) { 1639 struct snd_kcontrol *kctl; 1640 int i, is_spdif = 0; 1641 1642 ensoniq->spdif_default = ensoniq->spdif_stream = 1643 SNDRV_PCM_DEFAULT_CON_SPDIF; 1644 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS)); 1645 1646 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF) 1647 is_spdif++; 1648 1649 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) { 1650 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq); 1651 if (!kctl) 1652 return -ENOMEM; 1653 kctl->id.index = is_spdif; 1654 err = snd_ctl_add(card, kctl); 1655 if (err < 0) 1656 return err; 1657 } 1658 } 1659 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) { 1660 /* mirror rear to front speakers */ 1661 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1662 ensoniq->cssr |= ES_1373_REAR_BIT26; 1663 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq)); 1664 if (err < 0) 1665 return err; 1666 } 1667 if (has_line > 0 || 1668 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) { 1669 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, 1670 ensoniq)); 1671 if (err < 0) 1672 return err; 1673 } 1674 1675 return 0; 1676 } 1677 1678 #endif /* CHIP1371 */ 1679 1680 /* generic control callbacks for ens1370 */ 1681 #ifdef CHIP1370 1682 #define ENSONIQ_CONTROL(xname, mask) \ 1683 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \ 1684 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \ 1685 .private_value = mask } 1686 1687 #define snd_ensoniq_control_info snd_ctl_boolean_mono_info 1688 1689 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol, 1690 struct snd_ctl_elem_value *ucontrol) 1691 { 1692 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1693 int mask = kcontrol->private_value; 1694 1695 spin_lock_irq(&ensoniq->reg_lock); 1696 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; 1697 spin_unlock_irq(&ensoniq->reg_lock); 1698 return 0; 1699 } 1700 1701 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol, 1702 struct snd_ctl_elem_value *ucontrol) 1703 { 1704 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1705 int mask = kcontrol->private_value; 1706 unsigned int nval; 1707 int change; 1708 1709 nval = ucontrol->value.integer.value[0] ? mask : 0; 1710 spin_lock_irq(&ensoniq->reg_lock); 1711 change = (ensoniq->ctrl & mask) != nval; 1712 ensoniq->ctrl &= ~mask; 1713 ensoniq->ctrl |= nval; 1714 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1715 spin_unlock_irq(&ensoniq->reg_lock); 1716 return change; 1717 } 1718 1719 /* 1720 * ENS1370 mixer 1721 */ 1722 1723 static struct snd_kcontrol_new snd_es1370_controls[2] = { 1724 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0), 1725 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1) 1726 }; 1727 1728 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls) 1729 1730 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531) 1731 { 1732 struct ensoniq *ensoniq = ak4531->private_data; 1733 ensoniq->u.es1370.ak4531 = NULL; 1734 } 1735 1736 static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq) 1737 { 1738 struct snd_card *card = ensoniq->card; 1739 struct snd_ak4531 ak4531; 1740 unsigned int idx; 1741 int err; 1742 1743 /* try reset AK4531 */ 1744 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 1745 inw(ES_REG(ensoniq, 1370_CODEC)); 1746 udelay(100); 1747 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 1748 inw(ES_REG(ensoniq, 1370_CODEC)); 1749 udelay(100); 1750 1751 memset(&ak4531, 0, sizeof(ak4531)); 1752 ak4531.write = snd_es1370_codec_write; 1753 ak4531.private_data = ensoniq; 1754 ak4531.private_free = snd_ensoniq_mixer_free_ak4531; 1755 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0) 1756 return err; 1757 for (idx = 0; idx < ES1370_CONTROLS; idx++) { 1758 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq)); 1759 if (err < 0) 1760 return err; 1761 } 1762 return 0; 1763 } 1764 1765 #endif /* CHIP1370 */ 1766 1767 #ifdef SUPPORT_JOYSTICK 1768 1769 #ifdef CHIP1371 1770 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev) 1771 { 1772 switch (joystick_port[dev]) { 1773 case 0: /* disabled */ 1774 case 1: /* auto-detect */ 1775 case 0x200: 1776 case 0x208: 1777 case 0x210: 1778 case 0x218: 1779 return joystick_port[dev]; 1780 1781 default: 1782 dev_err(ensoniq->card->dev, 1783 "invalid joystick port %#x", joystick_port[dev]); 1784 return 0; 1785 } 1786 } 1787 #else 1788 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev) 1789 { 1790 return joystick[dev] ? 0x200 : 0; 1791 } 1792 #endif 1793 1794 static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev) 1795 { 1796 struct gameport *gp; 1797 int io_port; 1798 1799 io_port = snd_ensoniq_get_joystick_port(ensoniq, dev); 1800 1801 switch (io_port) { 1802 case 0: 1803 return -ENOSYS; 1804 1805 case 1: /* auto_detect */ 1806 for (io_port = 0x200; io_port <= 0x218; io_port += 8) 1807 if (request_region(io_port, 8, "ens137x: gameport")) 1808 break; 1809 if (io_port > 0x218) { 1810 dev_warn(ensoniq->card->dev, 1811 "no gameport ports available\n"); 1812 return -EBUSY; 1813 } 1814 break; 1815 1816 default: 1817 if (!request_region(io_port, 8, "ens137x: gameport")) { 1818 dev_warn(ensoniq->card->dev, 1819 "gameport io port %#x in use\n", 1820 io_port); 1821 return -EBUSY; 1822 } 1823 break; 1824 } 1825 1826 ensoniq->gameport = gp = gameport_allocate_port(); 1827 if (!gp) { 1828 dev_err(ensoniq->card->dev, 1829 "cannot allocate memory for gameport\n"); 1830 release_region(io_port, 8); 1831 return -ENOMEM; 1832 } 1833 1834 gameport_set_name(gp, "ES137x"); 1835 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci)); 1836 gameport_set_dev_parent(gp, &ensoniq->pci->dev); 1837 gp->io = io_port; 1838 1839 ensoniq->ctrl |= ES_JYSTK_EN; 1840 #ifdef CHIP1371 1841 ensoniq->ctrl &= ~ES_1371_JOY_ASELM; 1842 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); 1843 #endif 1844 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1845 1846 gameport_register_port(ensoniq->gameport); 1847 1848 return 0; 1849 } 1850 1851 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) 1852 { 1853 if (ensoniq->gameport) { 1854 int port = ensoniq->gameport->io; 1855 1856 gameport_unregister_port(ensoniq->gameport); 1857 ensoniq->gameport = NULL; 1858 ensoniq->ctrl &= ~ES_JYSTK_EN; 1859 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1860 release_region(port, 8); 1861 } 1862 } 1863 #else 1864 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; } 1865 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { } 1866 #endif /* SUPPORT_JOYSTICK */ 1867 1868 /* 1869 1870 */ 1871 1872 static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 1873 struct snd_info_buffer *buffer) 1874 { 1875 struct ensoniq *ensoniq = entry->private_data; 1876 1877 snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n"); 1878 snd_iprintf(buffer, "Joystick enable : %s\n", 1879 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); 1880 #ifdef CHIP1370 1881 snd_iprintf(buffer, "MIC +5V bias : %s\n", 1882 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); 1883 snd_iprintf(buffer, "Line In to AOUT : %s\n", 1884 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); 1885 #else 1886 snd_iprintf(buffer, "Joystick port : 0x%x\n", 1887 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); 1888 #endif 1889 } 1890 1891 static void snd_ensoniq_proc_init(struct ensoniq *ensoniq) 1892 { 1893 snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq, 1894 snd_ensoniq_proc_read); 1895 } 1896 1897 /* 1898 1899 */ 1900 1901 static int snd_ensoniq_free(struct ensoniq *ensoniq) 1902 { 1903 snd_ensoniq_free_gameport(ensoniq); 1904 if (ensoniq->irq < 0) 1905 goto __hw_end; 1906 #ifdef CHIP1370 1907 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1908 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1909 #else 1910 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1911 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1912 #endif 1913 if (ensoniq->irq >= 0) 1914 synchronize_irq(ensoniq->irq); 1915 pci_set_power_state(ensoniq->pci, PCI_D3hot); 1916 __hw_end: 1917 #ifdef CHIP1370 1918 if (ensoniq->dma_bug.area) 1919 snd_dma_free_pages(&ensoniq->dma_bug); 1920 #endif 1921 if (ensoniq->irq >= 0) 1922 free_irq(ensoniq->irq, ensoniq); 1923 pci_release_regions(ensoniq->pci); 1924 pci_disable_device(ensoniq->pci); 1925 kfree(ensoniq); 1926 return 0; 1927 } 1928 1929 static int snd_ensoniq_dev_free(struct snd_device *device) 1930 { 1931 struct ensoniq *ensoniq = device->device_data; 1932 return snd_ensoniq_free(ensoniq); 1933 } 1934 1935 #ifdef CHIP1371 1936 static struct snd_pci_quirk es1371_amplifier_hack[] = { 1937 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */ 1938 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */ 1939 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */ 1940 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */ 1941 { } /* end */ 1942 }; 1943 1944 static struct es1371_quirk es1371_ac97_reset_hack[] = { 1945 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1946 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1947 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1948 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1949 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1950 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1951 }; 1952 #endif 1953 1954 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq) 1955 { 1956 #ifdef CHIP1371 1957 int idx; 1958 #endif 1959 /* this code was part of snd_ensoniq_create before intruduction 1960 * of suspend/resume 1961 */ 1962 #ifdef CHIP1370 1963 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1964 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1965 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1966 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME)); 1967 outl(0, ES_REG(ensoniq, PHANTOM_COUNT)); 1968 #else 1969 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1970 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1971 outl(0, ES_REG(ensoniq, 1371_LEGACY)); 1972 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) { 1973 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1974 /* need to delay around 20ms(bleech) to give 1975 some CODECs enough time to wakeup */ 1976 msleep(20); 1977 } 1978 /* AC'97 warm reset to start the bitclk */ 1979 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); 1980 inl(ES_REG(ensoniq, CONTROL)); 1981 udelay(20); 1982 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1983 /* Init the sample rate converter */ 1984 snd_es1371_wait_src_ready(ensoniq); 1985 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE)); 1986 for (idx = 0; idx < 0x80; idx++) 1987 snd_es1371_src_write(ensoniq, idx, 0); 1988 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 1989 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 1990 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 1991 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 1992 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12); 1993 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12); 1994 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12); 1995 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 1996 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12); 1997 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 1998 snd_es1371_adc_rate(ensoniq, 22050); 1999 snd_es1371_dac1_rate(ensoniq, 22050); 2000 snd_es1371_dac2_rate(ensoniq, 22050); 2001 /* WARNING: 2002 * enabling the sample rate converter without properly programming 2003 * its parameters causes the chip to lock up (the SRC busy bit will 2004 * be stuck high, and I've found no way to rectify this other than 2005 * power cycle) - Thomas Sailer 2006 */ 2007 snd_es1371_wait_src_ready(ensoniq); 2008 outl(0, ES_REG(ensoniq, 1371_SMPRATE)); 2009 /* try reset codec directly */ 2010 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC)); 2011 #endif 2012 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL)); 2013 outb(0x00, ES_REG(ensoniq, UART_RES)); 2014 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2015 synchronize_irq(ensoniq->irq); 2016 } 2017 2018 #ifdef CONFIG_PM_SLEEP 2019 static int snd_ensoniq_suspend(struct device *dev) 2020 { 2021 struct snd_card *card = dev_get_drvdata(dev); 2022 struct ensoniq *ensoniq = card->private_data; 2023 2024 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2025 2026 #ifdef CHIP1371 2027 snd_ac97_suspend(ensoniq->u.es1371.ac97); 2028 #else 2029 /* try to reset AK4531 */ 2030 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 2031 inw(ES_REG(ensoniq, 1370_CODEC)); 2032 udelay(100); 2033 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 2034 inw(ES_REG(ensoniq, 1370_CODEC)); 2035 udelay(100); 2036 snd_ak4531_suspend(ensoniq->u.es1370.ak4531); 2037 #endif 2038 return 0; 2039 } 2040 2041 static int snd_ensoniq_resume(struct device *dev) 2042 { 2043 struct snd_card *card = dev_get_drvdata(dev); 2044 struct ensoniq *ensoniq = card->private_data; 2045 2046 snd_ensoniq_chip_init(ensoniq); 2047 2048 #ifdef CHIP1371 2049 snd_ac97_resume(ensoniq->u.es1371.ac97); 2050 #else 2051 snd_ak4531_resume(ensoniq->u.es1370.ak4531); 2052 #endif 2053 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2054 return 0; 2055 } 2056 2057 static SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume); 2058 #define SND_ENSONIQ_PM_OPS &snd_ensoniq_pm 2059 #else 2060 #define SND_ENSONIQ_PM_OPS NULL 2061 #endif /* CONFIG_PM_SLEEP */ 2062 2063 static int snd_ensoniq_create(struct snd_card *card, 2064 struct pci_dev *pci, 2065 struct ensoniq **rensoniq) 2066 { 2067 struct ensoniq *ensoniq; 2068 int err; 2069 static struct snd_device_ops ops = { 2070 .dev_free = snd_ensoniq_dev_free, 2071 }; 2072 2073 *rensoniq = NULL; 2074 if ((err = pci_enable_device(pci)) < 0) 2075 return err; 2076 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL); 2077 if (ensoniq == NULL) { 2078 pci_disable_device(pci); 2079 return -ENOMEM; 2080 } 2081 spin_lock_init(&ensoniq->reg_lock); 2082 mutex_init(&ensoniq->src_mutex); 2083 ensoniq->card = card; 2084 ensoniq->pci = pci; 2085 ensoniq->irq = -1; 2086 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) { 2087 kfree(ensoniq); 2088 pci_disable_device(pci); 2089 return err; 2090 } 2091 ensoniq->port = pci_resource_start(pci, 0); 2092 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED, 2093 KBUILD_MODNAME, ensoniq)) { 2094 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 2095 snd_ensoniq_free(ensoniq); 2096 return -EBUSY; 2097 } 2098 ensoniq->irq = pci->irq; 2099 #ifdef CHIP1370 2100 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 2101 16, &ensoniq->dma_bug) < 0) { 2102 dev_err(card->dev, "unable to allocate space for phantom area - dma_bug\n"); 2103 snd_ensoniq_free(ensoniq); 2104 return -EBUSY; 2105 } 2106 #endif 2107 pci_set_master(pci); 2108 ensoniq->rev = pci->revision; 2109 #ifdef CHIP1370 2110 #if 0 2111 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | 2112 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2113 #else /* get microphone working */ 2114 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2115 #endif 2116 ensoniq->sctrl = 0; 2117 #else 2118 ensoniq->ctrl = 0; 2119 ensoniq->sctrl = 0; 2120 ensoniq->cssr = 0; 2121 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack)) 2122 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ 2123 2124 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) 2125 ensoniq->cssr |= ES_1371_ST_AC97_RST; 2126 #endif 2127 2128 snd_ensoniq_chip_init(ensoniq); 2129 2130 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) { 2131 snd_ensoniq_free(ensoniq); 2132 return err; 2133 } 2134 2135 snd_ensoniq_proc_init(ensoniq); 2136 2137 *rensoniq = ensoniq; 2138 return 0; 2139 } 2140 2141 /* 2142 * MIDI section 2143 */ 2144 2145 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq) 2146 { 2147 struct snd_rawmidi *rmidi = ensoniq->rmidi; 2148 unsigned char status, mask, byte; 2149 2150 if (rmidi == NULL) 2151 return; 2152 /* do Rx at first */ 2153 spin_lock(&ensoniq->reg_lock); 2154 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; 2155 while (mask) { 2156 status = inb(ES_REG(ensoniq, UART_STATUS)); 2157 if ((status & mask) == 0) 2158 break; 2159 byte = inb(ES_REG(ensoniq, UART_DATA)); 2160 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1); 2161 } 2162 spin_unlock(&ensoniq->reg_lock); 2163 2164 /* do Tx at second */ 2165 spin_lock(&ensoniq->reg_lock); 2166 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; 2167 while (mask) { 2168 status = inb(ES_REG(ensoniq, UART_STATUS)); 2169 if ((status & mask) == 0) 2170 break; 2171 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) { 2172 ensoniq->uartc &= ~ES_TXINTENM; 2173 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2174 mask &= ~ES_TXRDY; 2175 } else { 2176 outb(byte, ES_REG(ensoniq, UART_DATA)); 2177 } 2178 } 2179 spin_unlock(&ensoniq->reg_lock); 2180 } 2181 2182 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream) 2183 { 2184 struct ensoniq *ensoniq = substream->rmidi->private_data; 2185 2186 spin_lock_irq(&ensoniq->reg_lock); 2187 ensoniq->uartm |= ES_MODE_INPUT; 2188 ensoniq->midi_input = substream; 2189 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2190 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2191 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2192 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2193 } 2194 spin_unlock_irq(&ensoniq->reg_lock); 2195 return 0; 2196 } 2197 2198 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream) 2199 { 2200 struct ensoniq *ensoniq = substream->rmidi->private_data; 2201 2202 spin_lock_irq(&ensoniq->reg_lock); 2203 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2204 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2205 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2206 } else { 2207 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL)); 2208 } 2209 ensoniq->midi_input = NULL; 2210 ensoniq->uartm &= ~ES_MODE_INPUT; 2211 spin_unlock_irq(&ensoniq->reg_lock); 2212 return 0; 2213 } 2214 2215 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream) 2216 { 2217 struct ensoniq *ensoniq = substream->rmidi->private_data; 2218 2219 spin_lock_irq(&ensoniq->reg_lock); 2220 ensoniq->uartm |= ES_MODE_OUTPUT; 2221 ensoniq->midi_output = substream; 2222 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2223 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2224 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2225 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2226 } 2227 spin_unlock_irq(&ensoniq->reg_lock); 2228 return 0; 2229 } 2230 2231 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream) 2232 { 2233 struct ensoniq *ensoniq = substream->rmidi->private_data; 2234 2235 spin_lock_irq(&ensoniq->reg_lock); 2236 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2237 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2238 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2239 } else { 2240 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL)); 2241 } 2242 ensoniq->midi_output = NULL; 2243 ensoniq->uartm &= ~ES_MODE_OUTPUT; 2244 spin_unlock_irq(&ensoniq->reg_lock); 2245 return 0; 2246 } 2247 2248 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2249 { 2250 unsigned long flags; 2251 struct ensoniq *ensoniq = substream->rmidi->private_data; 2252 int idx; 2253 2254 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2255 if (up) { 2256 if ((ensoniq->uartc & ES_RXINTEN) == 0) { 2257 /* empty input FIFO */ 2258 for (idx = 0; idx < 32; idx++) 2259 inb(ES_REG(ensoniq, UART_DATA)); 2260 ensoniq->uartc |= ES_RXINTEN; 2261 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2262 } 2263 } else { 2264 if (ensoniq->uartc & ES_RXINTEN) { 2265 ensoniq->uartc &= ~ES_RXINTEN; 2266 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2267 } 2268 } 2269 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2270 } 2271 2272 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2273 { 2274 unsigned long flags; 2275 struct ensoniq *ensoniq = substream->rmidi->private_data; 2276 unsigned char byte; 2277 2278 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2279 if (up) { 2280 if (ES_TXINTENI(ensoniq->uartc) == 0) { 2281 ensoniq->uartc |= ES_TXINTENO(1); 2282 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2283 while (ES_TXINTENI(ensoniq->uartc) == 1 && 2284 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) { 2285 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2286 ensoniq->uartc &= ~ES_TXINTENM; 2287 } else { 2288 outb(byte, ES_REG(ensoniq, UART_DATA)); 2289 } 2290 } 2291 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2292 } 2293 } else { 2294 if (ES_TXINTENI(ensoniq->uartc) == 1) { 2295 ensoniq->uartc &= ~ES_TXINTENM; 2296 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2297 } 2298 } 2299 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2300 } 2301 2302 static const struct snd_rawmidi_ops snd_ensoniq_midi_output = 2303 { 2304 .open = snd_ensoniq_midi_output_open, 2305 .close = snd_ensoniq_midi_output_close, 2306 .trigger = snd_ensoniq_midi_output_trigger, 2307 }; 2308 2309 static const struct snd_rawmidi_ops snd_ensoniq_midi_input = 2310 { 2311 .open = snd_ensoniq_midi_input_open, 2312 .close = snd_ensoniq_midi_input_close, 2313 .trigger = snd_ensoniq_midi_input_trigger, 2314 }; 2315 2316 static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device) 2317 { 2318 struct snd_rawmidi *rmidi; 2319 int err; 2320 2321 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0) 2322 return err; 2323 strcpy(rmidi->name, CHIP_NAME); 2324 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output); 2325 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input); 2326 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | 2327 SNDRV_RAWMIDI_INFO_DUPLEX; 2328 rmidi->private_data = ensoniq; 2329 ensoniq->rmidi = rmidi; 2330 return 0; 2331 } 2332 2333 /* 2334 * Interrupt handler 2335 */ 2336 2337 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id) 2338 { 2339 struct ensoniq *ensoniq = dev_id; 2340 unsigned int status, sctrl; 2341 2342 if (ensoniq == NULL) 2343 return IRQ_NONE; 2344 2345 status = inl(ES_REG(ensoniq, STATUS)); 2346 if (!(status & ES_INTR)) 2347 return IRQ_NONE; 2348 2349 spin_lock(&ensoniq->reg_lock); 2350 sctrl = ensoniq->sctrl; 2351 if (status & ES_DAC1) 2352 sctrl &= ~ES_P1_INT_EN; 2353 if (status & ES_DAC2) 2354 sctrl &= ~ES_P2_INT_EN; 2355 if (status & ES_ADC) 2356 sctrl &= ~ES_R1_INT_EN; 2357 outl(sctrl, ES_REG(ensoniq, SERIAL)); 2358 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2359 spin_unlock(&ensoniq->reg_lock); 2360 2361 if (status & ES_UART) 2362 snd_ensoniq_midi_interrupt(ensoniq); 2363 if ((status & ES_DAC2) && ensoniq->playback2_substream) 2364 snd_pcm_period_elapsed(ensoniq->playback2_substream); 2365 if ((status & ES_ADC) && ensoniq->capture_substream) 2366 snd_pcm_period_elapsed(ensoniq->capture_substream); 2367 if ((status & ES_DAC1) && ensoniq->playback1_substream) 2368 snd_pcm_period_elapsed(ensoniq->playback1_substream); 2369 return IRQ_HANDLED; 2370 } 2371 2372 static int snd_audiopci_probe(struct pci_dev *pci, 2373 const struct pci_device_id *pci_id) 2374 { 2375 static int dev; 2376 struct snd_card *card; 2377 struct ensoniq *ensoniq; 2378 int err; 2379 2380 if (dev >= SNDRV_CARDS) 2381 return -ENODEV; 2382 if (!enable[dev]) { 2383 dev++; 2384 return -ENOENT; 2385 } 2386 2387 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2388 0, &card); 2389 if (err < 0) 2390 return err; 2391 2392 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) { 2393 snd_card_free(card); 2394 return err; 2395 } 2396 card->private_data = ensoniq; 2397 2398 #ifdef CHIP1370 2399 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) { 2400 snd_card_free(card); 2401 return err; 2402 } 2403 #endif 2404 #ifdef CHIP1371 2405 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) { 2406 snd_card_free(card); 2407 return err; 2408 } 2409 #endif 2410 if ((err = snd_ensoniq_pcm(ensoniq, 0)) < 0) { 2411 snd_card_free(card); 2412 return err; 2413 } 2414 if ((err = snd_ensoniq_pcm2(ensoniq, 1)) < 0) { 2415 snd_card_free(card); 2416 return err; 2417 } 2418 if ((err = snd_ensoniq_midi(ensoniq, 0)) < 0) { 2419 snd_card_free(card); 2420 return err; 2421 } 2422 2423 snd_ensoniq_create_gameport(ensoniq, dev); 2424 2425 strcpy(card->driver, DRIVER_NAME); 2426 2427 strcpy(card->shortname, "Ensoniq AudioPCI"); 2428 sprintf(card->longname, "%s %s at 0x%lx, irq %i", 2429 card->shortname, 2430 card->driver, 2431 ensoniq->port, 2432 ensoniq->irq); 2433 2434 if ((err = snd_card_register(card)) < 0) { 2435 snd_card_free(card); 2436 return err; 2437 } 2438 2439 pci_set_drvdata(pci, card); 2440 dev++; 2441 return 0; 2442 } 2443 2444 static void snd_audiopci_remove(struct pci_dev *pci) 2445 { 2446 snd_card_free(pci_get_drvdata(pci)); 2447 } 2448 2449 static struct pci_driver ens137x_driver = { 2450 .name = KBUILD_MODNAME, 2451 .id_table = snd_audiopci_ids, 2452 .probe = snd_audiopci_probe, 2453 .remove = snd_audiopci_remove, 2454 .driver = { 2455 .pm = SND_ENSONIQ_PM_OPS, 2456 }, 2457 }; 2458 2459 module_pci_driver(ens137x_driver); 2460