1 /* 2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 4 * Thomas Sailer <sailer@ife.ee.ethz.ch> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 /* Power-Management-Code ( CONFIG_PM ) 23 * for ens1371 only ( FIXME ) 24 * derived from cs4281.c, atiixp.c and via82xx.c 25 * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm 26 * by Kurt J. Bosch 27 */ 28 29 #include <asm/io.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/pci.h> 34 #include <linux/slab.h> 35 #include <linux/gameport.h> 36 #include <linux/moduleparam.h> 37 #include <linux/mutex.h> 38 39 #include <sound/core.h> 40 #include <sound/control.h> 41 #include <sound/pcm.h> 42 #include <sound/rawmidi.h> 43 #ifdef CHIP1371 44 #include <sound/ac97_codec.h> 45 #else 46 #include <sound/ak4531_codec.h> 47 #endif 48 #include <sound/initval.h> 49 #include <sound/asoundef.h> 50 51 #ifndef CHIP1371 52 #undef CHIP1370 53 #define CHIP1370 54 #endif 55 56 #ifdef CHIP1370 57 #define DRIVER_NAME "ENS1370" 58 #else 59 #define DRIVER_NAME "ENS1371" 60 #endif 61 62 63 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>"); 64 MODULE_LICENSE("GPL"); 65 #ifdef CHIP1370 66 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370"); 67 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370}," 68 "{Creative Labs,SB PCI64/128 (ES1370)}}"); 69 #endif 70 #ifdef CHIP1371 71 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+"); 72 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73}," 73 "{Ensoniq,AudioPCI ES1373}," 74 "{Creative Labs,Ectiva EV1938}," 75 "{Creative Labs,SB PCI64/128 (ES1371/73)}," 76 "{Creative Labs,Vibra PCI128}," 77 "{Ectiva,EV1938}}"); 78 #endif 79 80 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 81 #define SUPPORT_JOYSTICK 82 #endif 83 84 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 85 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 86 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 87 #ifdef SUPPORT_JOYSTICK 88 #ifdef CHIP1371 89 static int joystick_port[SNDRV_CARDS]; 90 #else 91 static int joystick[SNDRV_CARDS]; 92 #endif 93 #endif 94 #ifdef CHIP1371 95 static int spdif[SNDRV_CARDS]; 96 static int lineio[SNDRV_CARDS]; 97 #endif 98 99 module_param_array(index, int, NULL, 0444); 100 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard."); 101 module_param_array(id, charp, NULL, 0444); 102 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard."); 103 module_param_array(enable, bool, NULL, 0444); 104 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard."); 105 #ifdef SUPPORT_JOYSTICK 106 #ifdef CHIP1371 107 module_param_array(joystick_port, int, NULL, 0444); 108 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 109 #else 110 module_param_array(joystick, bool, NULL, 0444); 111 MODULE_PARM_DESC(joystick, "Enable joystick."); 112 #endif 113 #endif /* SUPPORT_JOYSTICK */ 114 #ifdef CHIP1371 115 module_param_array(spdif, int, NULL, 0444); 116 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force)."); 117 module_param_array(lineio, int, NULL, 0444); 118 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force)."); 119 #endif 120 121 /* ES1371 chip ID */ 122 /* This is a little confusing because all ES1371 compatible chips have the 123 same DEVICE_ID, the only thing differentiating them is the REV_ID field. 124 This is only significant if you want to enable features on the later parts. 125 Yes, I know it's stupid and why didn't we use the sub IDs? 126 */ 127 #define ES1371REV_ES1373_A 0x04 128 #define ES1371REV_ES1373_B 0x06 129 #define ES1371REV_CT5880_A 0x07 130 #define CT5880REV_CT5880_C 0x02 131 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */ 132 #define CT5880REV_CT5880_E 0x04 /* mw */ 133 #define ES1371REV_ES1371_B 0x09 134 #define EV1938REV_EV1938_A 0x00 135 #define ES1371REV_ES1373_8 0x08 136 137 /* 138 * Direct registers 139 */ 140 141 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x) 142 143 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */ 144 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */ 145 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */ 146 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */ 147 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */ 148 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */ 149 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */ 150 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */ 151 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */ 152 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */ 153 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */ 154 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03) 155 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */ 156 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */ 157 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */ 158 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */ 159 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */ 160 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */ 161 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */ 162 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */ 163 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */ 164 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */ 165 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */ 166 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */ 167 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */ 168 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */ 169 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */ 170 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */ 171 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */ 172 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */ 173 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */ 174 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */ 175 #define ES_BREQ (1<<7) /* memory bus request enable */ 176 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */ 177 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */ 178 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */ 179 #define ES_UART_EN (1<<3) /* UART enable */ 180 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */ 181 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */ 182 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */ 183 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */ 184 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */ 185 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */ 186 #define ES_INTR (1<<31) /* Interrupt is pending */ 187 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */ 188 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */ 189 #define ES_1373_REAR_BIT26 (1<<26) 190 #define ES_1373_REAR_BIT24 (1<<24) 191 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */ 192 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */ 193 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */ 194 #define ES_1371_TEST (1<<16) /* test ASIC */ 195 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */ 196 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */ 197 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */ 198 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */ 199 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */ 200 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */ 201 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */ 202 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */ 203 #define ES_MCCB (1<<4) /* CCB interrupt pending */ 204 #define ES_UART (1<<3) /* UART interrupt pending */ 205 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */ 206 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */ 207 #define ES_ADC (1<<0) /* ADC channel interrupt pending */ 208 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */ 209 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */ 210 #define ES_RXINT (1<<7) /* RX interrupt occurred */ 211 #define ES_TXINT (1<<2) /* TX interrupt occurred */ 212 #define ES_TXRDY (1<<1) /* transmitter ready */ 213 #define ES_RXRDY (1<<0) /* receiver ready */ 214 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */ 215 #define ES_RXINTEN (1<<7) /* RX interrupt enable */ 216 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */ 217 #define ES_TXINTENM (0x03<<5) /* mask for above */ 218 #define ES_TXINTENI(i) (((i)>>5)&0x03) 219 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */ 220 #define ES_CNTRLM (0x03<<0) /* mask for above */ 221 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */ 222 #define ES_TEST_MODE (1<<0) /* test mode enabled */ 223 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */ 224 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */ 225 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */ 226 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */ 227 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */ 228 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0)) 229 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */ 230 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */ 231 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */ 232 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */ 233 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0)) 234 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD) 235 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff) 236 237 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ 238 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */ 239 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */ 240 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */ 241 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ 242 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ 243 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */ 244 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ 245 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */ 246 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */ 247 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */ 248 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */ 249 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */ 250 251 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */ 252 #define ES_1371_JFAST (1<<31) /* fast joystick timing */ 253 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */ 254 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */ 255 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */ 256 #define ES_1371_VMPUM (0x03<<27) /* mask for above */ 257 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */ 258 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */ 259 #define ES_1371_VCDCM (0x03<<25) /* mask for above */ 260 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */ 261 #define ES_1371_FIRQ (1<<24) /* force an interrupt */ 262 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */ 263 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */ 264 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */ 265 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */ 266 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */ 267 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */ 268 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */ 269 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */ 270 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */ 271 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */ 272 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */ 273 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */ 274 275 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */ 276 277 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */ 278 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */ 279 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */ 280 #define ES_P2_END_INCM (0x07<<19) /* mask for above */ 281 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */ 282 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */ 283 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */ 284 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */ 285 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */ 286 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */ 287 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */ 288 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */ 289 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */ 290 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */ 291 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */ 292 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */ 293 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */ 294 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */ 295 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */ 296 #define ES_R1_MODEM (0x03<<4) /* mask for above */ 297 #define ES_R1_MODEI(i) (((i)>>4)&0x03) 298 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */ 299 #define ES_P2_MODEM (0x03<<2) /* mask for above */ 300 #define ES_P2_MODEI(i) (((i)>>2)&0x03) 301 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */ 302 #define ES_P1_MODEM (0x03<<0) /* mask for above */ 303 #define ES_P1_MODEI(i) (((i)>>0)&0x03) 304 305 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */ 306 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */ 307 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */ 308 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff) 309 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0) 310 #define ES_REG_COUNTM (0xffff<<0) 311 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff) 312 313 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */ 314 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */ 315 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */ 316 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */ 317 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */ 318 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */ 319 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16) 320 #define ES_REG_FCURR_COUNTM (0xffff<<16) 321 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc) 322 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0) 323 #define ES_REG_FSIZEM (0xffff<<0) 324 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff) 325 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */ 326 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */ 327 328 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */ 329 #define ES_REG_UF_VALID (1<<8) 330 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0) 331 #define ES_REG_UF_BYTEM (0xff<<0) 332 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff) 333 334 335 /* 336 * Pages 337 */ 338 339 #define ES_PAGE_DAC 0x0c 340 #define ES_PAGE_ADC 0x0d 341 #define ES_PAGE_UART 0x0e 342 #define ES_PAGE_UART1 0x0f 343 344 /* 345 * Sample rate converter addresses 346 */ 347 348 #define ES_SMPREG_DAC1 0x70 349 #define ES_SMPREG_DAC2 0x74 350 #define ES_SMPREG_ADC 0x78 351 #define ES_SMPREG_VOL_ADC 0x6c 352 #define ES_SMPREG_VOL_DAC1 0x7c 353 #define ES_SMPREG_VOL_DAC2 0x7e 354 #define ES_SMPREG_TRUNC_N 0x00 355 #define ES_SMPREG_INT_REGS 0x01 356 #define ES_SMPREG_ACCUM_FRAC 0x02 357 #define ES_SMPREG_VFREQ_FRAC 0x03 358 359 /* 360 * Some contants 361 */ 362 363 #define ES_1370_SRCLOCK 1411200 364 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2) 365 366 /* 367 * Open modes 368 */ 369 370 #define ES_MODE_PLAY1 0x0001 371 #define ES_MODE_PLAY2 0x0002 372 #define ES_MODE_CAPTURE 0x0004 373 374 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */ 375 #define ES_MODE_INPUT 0x0002 /* for MIDI */ 376 377 /* 378 379 */ 380 381 struct ensoniq { 382 spinlock_t reg_lock; 383 struct mutex src_mutex; 384 385 int irq; 386 387 unsigned long playback1size; 388 unsigned long playback2size; 389 unsigned long capture3size; 390 391 unsigned long port; 392 unsigned int mode; 393 unsigned int uartm; /* UART mode */ 394 395 unsigned int ctrl; /* control register */ 396 unsigned int sctrl; /* serial control register */ 397 unsigned int cssr; /* control status register */ 398 unsigned int uartc; /* uart control register */ 399 unsigned int rev; /* chip revision */ 400 401 union { 402 #ifdef CHIP1371 403 struct { 404 struct snd_ac97 *ac97; 405 } es1371; 406 #else 407 struct { 408 int pclkdiv_lock; 409 struct snd_ak4531 *ak4531; 410 } es1370; 411 #endif 412 } u; 413 414 struct pci_dev *pci; 415 struct snd_card *card; 416 struct snd_pcm *pcm1; /* DAC1/ADC PCM */ 417 struct snd_pcm *pcm2; /* DAC2 PCM */ 418 struct snd_pcm_substream *playback1_substream; 419 struct snd_pcm_substream *playback2_substream; 420 struct snd_pcm_substream *capture_substream; 421 unsigned int p1_dma_size; 422 unsigned int p2_dma_size; 423 unsigned int c_dma_size; 424 unsigned int p1_period_size; 425 unsigned int p2_period_size; 426 unsigned int c_period_size; 427 struct snd_rawmidi *rmidi; 428 struct snd_rawmidi_substream *midi_input; 429 struct snd_rawmidi_substream *midi_output; 430 431 unsigned int spdif; 432 unsigned int spdif_default; 433 unsigned int spdif_stream; 434 435 #ifdef CHIP1370 436 struct snd_dma_buffer dma_bug; 437 #endif 438 439 #ifdef SUPPORT_JOYSTICK 440 struct gameport *gameport; 441 #endif 442 }; 443 444 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id); 445 446 static struct pci_device_id snd_audiopci_ids[] = { 447 #ifdef CHIP1370 448 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */ 449 #endif 450 #ifdef CHIP1371 451 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */ 452 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */ 453 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */ 454 #endif 455 { 0, } 456 }; 457 458 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids); 459 460 /* 461 * constants 462 */ 463 464 #define POLL_COUNT 0xa000 465 466 #ifdef CHIP1370 467 static unsigned int snd_es1370_fixed_rates[] = 468 {5512, 11025, 22050, 44100}; 469 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = { 470 .count = 4, 471 .list = snd_es1370_fixed_rates, 472 .mask = 0, 473 }; 474 static struct snd_ratnum es1370_clock = { 475 .num = ES_1370_SRCLOCK, 476 .den_min = 29, 477 .den_max = 353, 478 .den_step = 1, 479 }; 480 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = { 481 .nrats = 1, 482 .rats = &es1370_clock, 483 }; 484 #else 485 static struct snd_ratden es1371_dac_clock = { 486 .num_min = 3000 * (1 << 15), 487 .num_max = 48000 * (1 << 15), 488 .num_step = 3000, 489 .den = 1 << 15, 490 }; 491 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = { 492 .nrats = 1, 493 .rats = &es1371_dac_clock, 494 }; 495 static struct snd_ratnum es1371_adc_clock = { 496 .num = 48000 << 15, 497 .den_min = 32768, 498 .den_max = 393216, 499 .den_step = 1, 500 }; 501 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = { 502 .nrats = 1, 503 .rats = &es1371_adc_clock, 504 }; 505 #endif 506 static const unsigned int snd_ensoniq_sample_shift[] = 507 {0, 1, 1, 2}; 508 509 /* 510 * common I/O routines 511 */ 512 513 #ifdef CHIP1371 514 515 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq) 516 { 517 unsigned int t, r = 0; 518 519 for (t = 0; t < POLL_COUNT; t++) { 520 r = inl(ES_REG(ensoniq, 1371_SMPRATE)); 521 if ((r & ES_1371_SRC_RAM_BUSY) == 0) 522 return r; 523 cond_resched(); 524 } 525 snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n", 526 ES_REG(ensoniq, 1371_SMPRATE), r); 527 return 0; 528 } 529 530 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg) 531 { 532 unsigned int temp, i, orig, r; 533 534 /* wait for ready */ 535 temp = orig = snd_es1371_wait_src_ready(ensoniq); 536 537 /* expose the SRC state bits */ 538 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 539 ES_1371_DIS_P2 | ES_1371_DIS_R1); 540 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; 541 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 542 543 /* now, wait for busy and the correct time to read */ 544 temp = snd_es1371_wait_src_ready(ensoniq); 545 546 if ((temp & 0x00870000) != 0x00010000) { 547 /* wait for the right state */ 548 for (i = 0; i < POLL_COUNT; i++) { 549 temp = inl(ES_REG(ensoniq, 1371_SMPRATE)); 550 if ((temp & 0x00870000) == 0x00010000) 551 break; 552 } 553 } 554 555 /* hide the state bits */ 556 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 557 ES_1371_DIS_P2 | ES_1371_DIS_R1); 558 r |= ES_1371_SRC_RAM_ADDRO(reg); 559 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 560 561 return temp; 562 } 563 564 static void snd_es1371_src_write(struct ensoniq * ensoniq, 565 unsigned short reg, unsigned short data) 566 { 567 unsigned int r; 568 569 r = snd_es1371_wait_src_ready(ensoniq) & 570 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 571 ES_1371_DIS_P2 | ES_1371_DIS_R1); 572 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); 573 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE)); 574 } 575 576 #endif /* CHIP1371 */ 577 578 #ifdef CHIP1370 579 580 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531, 581 unsigned short reg, unsigned short val) 582 { 583 struct ensoniq *ensoniq = ak4531->private_data; 584 unsigned long end_time = jiffies + HZ / 10; 585 586 #if 0 587 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", 588 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 589 #endif 590 do { 591 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) { 592 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 593 return; 594 } 595 schedule_timeout_uninterruptible(1); 596 } while (time_after(end_time, jiffies)); 597 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n", 598 inl(ES_REG(ensoniq, STATUS))); 599 } 600 601 #endif /* CHIP1370 */ 602 603 #ifdef CHIP1371 604 605 static void snd_es1371_codec_write(struct snd_ac97 *ac97, 606 unsigned short reg, unsigned short val) 607 { 608 struct ensoniq *ensoniq = ac97->private_data; 609 unsigned int t, x; 610 611 mutex_lock(&ensoniq->src_mutex); 612 for (t = 0; t < POLL_COUNT; t++) { 613 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 614 /* save the current state for latter */ 615 x = snd_es1371_wait_src_ready(ensoniq); 616 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 617 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 618 ES_REG(ensoniq, 1371_SMPRATE)); 619 /* wait for not busy (state 0) first to avoid 620 transition states */ 621 for (t = 0; t < POLL_COUNT; t++) { 622 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 623 0x00000000) 624 break; 625 } 626 /* wait for a SAFE time to write addr/data and then do it, dammit */ 627 for (t = 0; t < POLL_COUNT; t++) { 628 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 629 0x00010000) 630 break; 631 } 632 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC)); 633 /* restore SRC reg */ 634 snd_es1371_wait_src_ready(ensoniq); 635 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 636 mutex_unlock(&ensoniq->src_mutex); 637 return; 638 } 639 } 640 mutex_unlock(&ensoniq->src_mutex); 641 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n", 642 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 643 } 644 645 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97, 646 unsigned short reg) 647 { 648 struct ensoniq *ensoniq = ac97->private_data; 649 unsigned int t, x, fail = 0; 650 651 __again: 652 mutex_lock(&ensoniq->src_mutex); 653 for (t = 0; t < POLL_COUNT; t++) { 654 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 655 /* save the current state for latter */ 656 x = snd_es1371_wait_src_ready(ensoniq); 657 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 658 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 659 ES_REG(ensoniq, 1371_SMPRATE)); 660 /* wait for not busy (state 0) first to avoid 661 transition states */ 662 for (t = 0; t < POLL_COUNT; t++) { 663 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 664 0x00000000) 665 break; 666 } 667 /* wait for a SAFE time to write addr/data and then do it, dammit */ 668 for (t = 0; t < POLL_COUNT; t++) { 669 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 670 0x00010000) 671 break; 672 } 673 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC)); 674 /* restore SRC reg */ 675 snd_es1371_wait_src_ready(ensoniq); 676 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 677 /* wait for WIP again */ 678 for (t = 0; t < POLL_COUNT; t++) { 679 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) 680 break; 681 } 682 /* now wait for the stinkin' data (RDY) */ 683 for (t = 0; t < POLL_COUNT; t++) { 684 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) { 685 mutex_unlock(&ensoniq->src_mutex); 686 return ES_1371_CODEC_READ(x); 687 } 688 } 689 mutex_unlock(&ensoniq->src_mutex); 690 if (++fail > 10) { 691 snd_printk(KERN_ERR "codec read timeout (final) " 692 "at 0x%lx, reg = 0x%x [0x%x]\n", 693 ES_REG(ensoniq, 1371_CODEC), reg, 694 inl(ES_REG(ensoniq, 1371_CODEC))); 695 return 0; 696 } 697 goto __again; 698 } 699 } 700 mutex_unlock(&ensoniq->src_mutex); 701 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n", 702 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 703 return 0; 704 } 705 706 static void snd_es1371_codec_wait(struct snd_ac97 *ac97) 707 { 708 msleep(750); 709 snd_es1371_codec_read(ac97, AC97_RESET); 710 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); 711 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); 712 msleep(50); 713 } 714 715 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate) 716 { 717 unsigned int n, truncm, freq, result; 718 719 mutex_lock(&ensoniq->src_mutex); 720 n = rate / 3000; 721 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 722 n--; 723 truncm = (21 * n - 1) | 1; 724 freq = ((48000UL << 15) / rate) * n; 725 result = (48000UL << 15) / (freq / n); 726 if (rate >= 24000) { 727 if (truncm > 239) 728 truncm = 239; 729 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 730 (((239 - truncm) >> 1) << 9) | (n << 4)); 731 } else { 732 if (truncm > 119) 733 truncm = 119; 734 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 735 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 736 } 737 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 738 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + 739 ES_SMPREG_INT_REGS) & 0x00ff) | 740 ((freq >> 5) & 0xfc00)); 741 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 742 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8); 743 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8); 744 mutex_unlock(&ensoniq->src_mutex); 745 } 746 747 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate) 748 { 749 unsigned int freq, r; 750 751 mutex_lock(&ensoniq->src_mutex); 752 freq = ((rate << 15) + 1500) / 3000; 753 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 754 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 755 ES_1371_DIS_P1; 756 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 757 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 758 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + 759 ES_SMPREG_INT_REGS) & 0x00ff) | 760 ((freq >> 5) & 0xfc00)); 761 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 762 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 763 ES_1371_DIS_P2 | ES_1371_DIS_R1)); 764 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 765 mutex_unlock(&ensoniq->src_mutex); 766 } 767 768 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate) 769 { 770 unsigned int freq, r; 771 772 mutex_lock(&ensoniq->src_mutex); 773 freq = ((rate << 15) + 1500) / 3000; 774 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 775 ES_1371_DIS_P1 | ES_1371_DIS_R1)) | 776 ES_1371_DIS_P2; 777 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 778 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 779 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + 780 ES_SMPREG_INT_REGS) & 0x00ff) | 781 ((freq >> 5) & 0xfc00)); 782 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, 783 freq & 0x7fff); 784 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 785 ES_1371_DIS_P1 | ES_1371_DIS_R1)); 786 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 787 mutex_unlock(&ensoniq->src_mutex); 788 } 789 790 #endif /* CHIP1371 */ 791 792 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd) 793 { 794 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 795 switch (cmd) { 796 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 797 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 798 { 799 unsigned int what = 0; 800 struct snd_pcm_substream *s; 801 snd_pcm_group_for_each_entry(s, substream) { 802 if (s == ensoniq->playback1_substream) { 803 what |= ES_P1_PAUSE; 804 snd_pcm_trigger_done(s, substream); 805 } else if (s == ensoniq->playback2_substream) { 806 what |= ES_P2_PAUSE; 807 snd_pcm_trigger_done(s, substream); 808 } else if (s == ensoniq->capture_substream) 809 return -EINVAL; 810 } 811 spin_lock(&ensoniq->reg_lock); 812 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 813 ensoniq->sctrl |= what; 814 else 815 ensoniq->sctrl &= ~what; 816 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 817 spin_unlock(&ensoniq->reg_lock); 818 break; 819 } 820 case SNDRV_PCM_TRIGGER_START: 821 case SNDRV_PCM_TRIGGER_STOP: 822 { 823 unsigned int what = 0; 824 struct snd_pcm_substream *s; 825 snd_pcm_group_for_each_entry(s, substream) { 826 if (s == ensoniq->playback1_substream) { 827 what |= ES_DAC1_EN; 828 snd_pcm_trigger_done(s, substream); 829 } else if (s == ensoniq->playback2_substream) { 830 what |= ES_DAC2_EN; 831 snd_pcm_trigger_done(s, substream); 832 } else if (s == ensoniq->capture_substream) { 833 what |= ES_ADC_EN; 834 snd_pcm_trigger_done(s, substream); 835 } 836 } 837 spin_lock(&ensoniq->reg_lock); 838 if (cmd == SNDRV_PCM_TRIGGER_START) 839 ensoniq->ctrl |= what; 840 else 841 ensoniq->ctrl &= ~what; 842 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 843 spin_unlock(&ensoniq->reg_lock); 844 break; 845 } 846 default: 847 return -EINVAL; 848 } 849 return 0; 850 } 851 852 /* 853 * PCM part 854 */ 855 856 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream, 857 struct snd_pcm_hw_params *hw_params) 858 { 859 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 860 } 861 862 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream) 863 { 864 return snd_pcm_lib_free_pages(substream); 865 } 866 867 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream) 868 { 869 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 870 struct snd_pcm_runtime *runtime = substream->runtime; 871 unsigned int mode = 0; 872 873 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream); 874 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream); 875 if (snd_pcm_format_width(runtime->format) == 16) 876 mode |= 0x02; 877 if (runtime->channels > 1) 878 mode |= 0x01; 879 spin_lock_irq(&ensoniq->reg_lock); 880 ensoniq->ctrl &= ~ES_DAC1_EN; 881 #ifdef CHIP1371 882 /* 48k doesn't need SRC (it breaks AC3-passthru) */ 883 if (runtime->rate == 48000) 884 ensoniq->ctrl |= ES_1373_BYPASS_P1; 885 else 886 ensoniq->ctrl &= ~ES_1373_BYPASS_P1; 887 #endif 888 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 889 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 890 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME)); 891 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE)); 892 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM); 893 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode); 894 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 895 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 896 ES_REG(ensoniq, DAC1_COUNT)); 897 #ifdef CHIP1370 898 ensoniq->ctrl &= ~ES_1370_WTSRSELM; 899 switch (runtime->rate) { 900 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; 901 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; 902 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; 903 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; 904 default: snd_BUG(); 905 } 906 #endif 907 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 908 spin_unlock_irq(&ensoniq->reg_lock); 909 #ifndef CHIP1370 910 snd_es1371_dac1_rate(ensoniq, runtime->rate); 911 #endif 912 return 0; 913 } 914 915 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream) 916 { 917 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 918 struct snd_pcm_runtime *runtime = substream->runtime; 919 unsigned int mode = 0; 920 921 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream); 922 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream); 923 if (snd_pcm_format_width(runtime->format) == 16) 924 mode |= 0x02; 925 if (runtime->channels > 1) 926 mode |= 0x01; 927 spin_lock_irq(&ensoniq->reg_lock); 928 ensoniq->ctrl &= ~ES_DAC2_EN; 929 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 930 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 931 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME)); 932 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE)); 933 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN | 934 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM); 935 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) | 936 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0); 937 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 938 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 939 ES_REG(ensoniq, DAC2_COUNT)); 940 #ifdef CHIP1370 941 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) { 942 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 943 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 944 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2; 945 } 946 #endif 947 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 948 spin_unlock_irq(&ensoniq->reg_lock); 949 #ifndef CHIP1370 950 snd_es1371_dac2_rate(ensoniq, runtime->rate); 951 #endif 952 return 0; 953 } 954 955 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream) 956 { 957 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 958 struct snd_pcm_runtime *runtime = substream->runtime; 959 unsigned int mode = 0; 960 961 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream); 962 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream); 963 if (snd_pcm_format_width(runtime->format) == 16) 964 mode |= 0x02; 965 if (runtime->channels > 1) 966 mode |= 0x01; 967 spin_lock_irq(&ensoniq->reg_lock); 968 ensoniq->ctrl &= ~ES_ADC_EN; 969 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 970 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 971 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME)); 972 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE)); 973 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM); 974 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode); 975 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 976 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 977 ES_REG(ensoniq, ADC_COUNT)); 978 #ifdef CHIP1370 979 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) { 980 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 981 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 982 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE; 983 } 984 #endif 985 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 986 spin_unlock_irq(&ensoniq->reg_lock); 987 #ifndef CHIP1370 988 snd_es1371_adc_rate(ensoniq, runtime->rate); 989 #endif 990 return 0; 991 } 992 993 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream) 994 { 995 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 996 size_t ptr; 997 998 spin_lock(&ensoniq->reg_lock); 999 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { 1000 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1001 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE))); 1002 ptr = bytes_to_frames(substream->runtime, ptr); 1003 } else { 1004 ptr = 0; 1005 } 1006 spin_unlock(&ensoniq->reg_lock); 1007 return ptr; 1008 } 1009 1010 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream) 1011 { 1012 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1013 size_t ptr; 1014 1015 spin_lock(&ensoniq->reg_lock); 1016 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { 1017 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1018 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE))); 1019 ptr = bytes_to_frames(substream->runtime, ptr); 1020 } else { 1021 ptr = 0; 1022 } 1023 spin_unlock(&ensoniq->reg_lock); 1024 return ptr; 1025 } 1026 1027 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream) 1028 { 1029 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1030 size_t ptr; 1031 1032 spin_lock(&ensoniq->reg_lock); 1033 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) { 1034 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1035 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE))); 1036 ptr = bytes_to_frames(substream->runtime, ptr); 1037 } else { 1038 ptr = 0; 1039 } 1040 spin_unlock(&ensoniq->reg_lock); 1041 return ptr; 1042 } 1043 1044 static struct snd_pcm_hardware snd_ensoniq_playback1 = 1045 { 1046 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1047 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1048 SNDRV_PCM_INFO_MMAP_VALID | 1049 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START), 1050 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1051 .rates = 1052 #ifndef CHIP1370 1053 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1054 #else 1055 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */ 1056 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 1057 SNDRV_PCM_RATE_44100), 1058 #endif 1059 .rate_min = 4000, 1060 .rate_max = 48000, 1061 .channels_min = 1, 1062 .channels_max = 2, 1063 .buffer_bytes_max = (128*1024), 1064 .period_bytes_min = 64, 1065 .period_bytes_max = (128*1024), 1066 .periods_min = 1, 1067 .periods_max = 1024, 1068 .fifo_size = 0, 1069 }; 1070 1071 static struct snd_pcm_hardware snd_ensoniq_playback2 = 1072 { 1073 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1074 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1075 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 1076 SNDRV_PCM_INFO_SYNC_START), 1077 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1078 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1079 .rate_min = 4000, 1080 .rate_max = 48000, 1081 .channels_min = 1, 1082 .channels_max = 2, 1083 .buffer_bytes_max = (128*1024), 1084 .period_bytes_min = 64, 1085 .period_bytes_max = (128*1024), 1086 .periods_min = 1, 1087 .periods_max = 1024, 1088 .fifo_size = 0, 1089 }; 1090 1091 static struct snd_pcm_hardware snd_ensoniq_capture = 1092 { 1093 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1094 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1095 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1096 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1097 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1098 .rate_min = 4000, 1099 .rate_max = 48000, 1100 .channels_min = 1, 1101 .channels_max = 2, 1102 .buffer_bytes_max = (128*1024), 1103 .period_bytes_min = 64, 1104 .period_bytes_max = (128*1024), 1105 .periods_min = 1, 1106 .periods_max = 1024, 1107 .fifo_size = 0, 1108 }; 1109 1110 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream) 1111 { 1112 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1113 struct snd_pcm_runtime *runtime = substream->runtime; 1114 1115 ensoniq->mode |= ES_MODE_PLAY1; 1116 ensoniq->playback1_substream = substream; 1117 runtime->hw = snd_ensoniq_playback1; 1118 snd_pcm_set_sync(substream); 1119 spin_lock_irq(&ensoniq->reg_lock); 1120 if (ensoniq->spdif && ensoniq->playback2_substream == NULL) 1121 ensoniq->spdif_stream = ensoniq->spdif_default; 1122 spin_unlock_irq(&ensoniq->reg_lock); 1123 #ifdef CHIP1370 1124 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1125 &snd_es1370_hw_constraints_rates); 1126 #else 1127 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1128 &snd_es1371_hw_constraints_dac_clock); 1129 #endif 1130 return 0; 1131 } 1132 1133 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream) 1134 { 1135 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1136 struct snd_pcm_runtime *runtime = substream->runtime; 1137 1138 ensoniq->mode |= ES_MODE_PLAY2; 1139 ensoniq->playback2_substream = substream; 1140 runtime->hw = snd_ensoniq_playback2; 1141 snd_pcm_set_sync(substream); 1142 spin_lock_irq(&ensoniq->reg_lock); 1143 if (ensoniq->spdif && ensoniq->playback1_substream == NULL) 1144 ensoniq->spdif_stream = ensoniq->spdif_default; 1145 spin_unlock_irq(&ensoniq->reg_lock); 1146 #ifdef CHIP1370 1147 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1148 &snd_es1370_hw_constraints_clock); 1149 #else 1150 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1151 &snd_es1371_hw_constraints_dac_clock); 1152 #endif 1153 return 0; 1154 } 1155 1156 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream) 1157 { 1158 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1159 struct snd_pcm_runtime *runtime = substream->runtime; 1160 1161 ensoniq->mode |= ES_MODE_CAPTURE; 1162 ensoniq->capture_substream = substream; 1163 runtime->hw = snd_ensoniq_capture; 1164 snd_pcm_set_sync(substream); 1165 #ifdef CHIP1370 1166 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1167 &snd_es1370_hw_constraints_clock); 1168 #else 1169 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1170 &snd_es1371_hw_constraints_adc_clock); 1171 #endif 1172 return 0; 1173 } 1174 1175 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream) 1176 { 1177 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1178 1179 ensoniq->playback1_substream = NULL; 1180 ensoniq->mode &= ~ES_MODE_PLAY1; 1181 return 0; 1182 } 1183 1184 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream) 1185 { 1186 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1187 1188 ensoniq->playback2_substream = NULL; 1189 spin_lock_irq(&ensoniq->reg_lock); 1190 #ifdef CHIP1370 1191 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2; 1192 #endif 1193 ensoniq->mode &= ~ES_MODE_PLAY2; 1194 spin_unlock_irq(&ensoniq->reg_lock); 1195 return 0; 1196 } 1197 1198 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream) 1199 { 1200 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1201 1202 ensoniq->capture_substream = NULL; 1203 spin_lock_irq(&ensoniq->reg_lock); 1204 #ifdef CHIP1370 1205 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE; 1206 #endif 1207 ensoniq->mode &= ~ES_MODE_CAPTURE; 1208 spin_unlock_irq(&ensoniq->reg_lock); 1209 return 0; 1210 } 1211 1212 static struct snd_pcm_ops snd_ensoniq_playback1_ops = { 1213 .open = snd_ensoniq_playback1_open, 1214 .close = snd_ensoniq_playback1_close, 1215 .ioctl = snd_pcm_lib_ioctl, 1216 .hw_params = snd_ensoniq_hw_params, 1217 .hw_free = snd_ensoniq_hw_free, 1218 .prepare = snd_ensoniq_playback1_prepare, 1219 .trigger = snd_ensoniq_trigger, 1220 .pointer = snd_ensoniq_playback1_pointer, 1221 }; 1222 1223 static struct snd_pcm_ops snd_ensoniq_playback2_ops = { 1224 .open = snd_ensoniq_playback2_open, 1225 .close = snd_ensoniq_playback2_close, 1226 .ioctl = snd_pcm_lib_ioctl, 1227 .hw_params = snd_ensoniq_hw_params, 1228 .hw_free = snd_ensoniq_hw_free, 1229 .prepare = snd_ensoniq_playback2_prepare, 1230 .trigger = snd_ensoniq_trigger, 1231 .pointer = snd_ensoniq_playback2_pointer, 1232 }; 1233 1234 static struct snd_pcm_ops snd_ensoniq_capture_ops = { 1235 .open = snd_ensoniq_capture_open, 1236 .close = snd_ensoniq_capture_close, 1237 .ioctl = snd_pcm_lib_ioctl, 1238 .hw_params = snd_ensoniq_hw_params, 1239 .hw_free = snd_ensoniq_hw_free, 1240 .prepare = snd_ensoniq_capture_prepare, 1241 .trigger = snd_ensoniq_trigger, 1242 .pointer = snd_ensoniq_capture_pointer, 1243 }; 1244 1245 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device, 1246 struct snd_pcm ** rpcm) 1247 { 1248 struct snd_pcm *pcm; 1249 int err; 1250 1251 if (rpcm) 1252 *rpcm = NULL; 1253 #ifdef CHIP1370 1254 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm); 1255 #else 1256 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm); 1257 #endif 1258 if (err < 0) 1259 return err; 1260 1261 #ifdef CHIP1370 1262 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1263 #else 1264 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1265 #endif 1266 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops); 1267 1268 pcm->private_data = ensoniq; 1269 pcm->info_flags = 0; 1270 #ifdef CHIP1370 1271 strcpy(pcm->name, "ES1370 DAC2/ADC"); 1272 #else 1273 strcpy(pcm->name, "ES1371 DAC2/ADC"); 1274 #endif 1275 ensoniq->pcm1 = pcm; 1276 1277 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1278 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1279 1280 if (rpcm) 1281 *rpcm = pcm; 1282 return 0; 1283 } 1284 1285 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device, 1286 struct snd_pcm ** rpcm) 1287 { 1288 struct snd_pcm *pcm; 1289 int err; 1290 1291 if (rpcm) 1292 *rpcm = NULL; 1293 #ifdef CHIP1370 1294 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm); 1295 #else 1296 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm); 1297 #endif 1298 if (err < 0) 1299 return err; 1300 1301 #ifdef CHIP1370 1302 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1303 #else 1304 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1305 #endif 1306 pcm->private_data = ensoniq; 1307 pcm->info_flags = 0; 1308 #ifdef CHIP1370 1309 strcpy(pcm->name, "ES1370 DAC1"); 1310 #else 1311 strcpy(pcm->name, "ES1371 DAC1"); 1312 #endif 1313 ensoniq->pcm2 = pcm; 1314 1315 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1316 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1317 1318 if (rpcm) 1319 *rpcm = pcm; 1320 return 0; 1321 } 1322 1323 /* 1324 * Mixer section 1325 */ 1326 1327 /* 1328 * ENS1371 mixer (including SPDIF interface) 1329 */ 1330 #ifdef CHIP1371 1331 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol, 1332 struct snd_ctl_elem_info *uinfo) 1333 { 1334 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1335 uinfo->count = 1; 1336 return 0; 1337 } 1338 1339 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol, 1340 struct snd_ctl_elem_value *ucontrol) 1341 { 1342 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1343 spin_lock_irq(&ensoniq->reg_lock); 1344 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff; 1345 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff; 1346 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff; 1347 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff; 1348 spin_unlock_irq(&ensoniq->reg_lock); 1349 return 0; 1350 } 1351 1352 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol, 1353 struct snd_ctl_elem_value *ucontrol) 1354 { 1355 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1356 unsigned int val; 1357 int change; 1358 1359 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1360 ((u32)ucontrol->value.iec958.status[1] << 8) | 1361 ((u32)ucontrol->value.iec958.status[2] << 16) | 1362 ((u32)ucontrol->value.iec958.status[3] << 24); 1363 spin_lock_irq(&ensoniq->reg_lock); 1364 change = ensoniq->spdif_default != val; 1365 ensoniq->spdif_default = val; 1366 if (change && ensoniq->playback1_substream == NULL && 1367 ensoniq->playback2_substream == NULL) 1368 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1369 spin_unlock_irq(&ensoniq->reg_lock); 1370 return change; 1371 } 1372 1373 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol, 1374 struct snd_ctl_elem_value *ucontrol) 1375 { 1376 ucontrol->value.iec958.status[0] = 0xff; 1377 ucontrol->value.iec958.status[1] = 0xff; 1378 ucontrol->value.iec958.status[2] = 0xff; 1379 ucontrol->value.iec958.status[3] = 0xff; 1380 return 0; 1381 } 1382 1383 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol, 1384 struct snd_ctl_elem_value *ucontrol) 1385 { 1386 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1387 spin_lock_irq(&ensoniq->reg_lock); 1388 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff; 1389 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff; 1390 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff; 1391 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff; 1392 spin_unlock_irq(&ensoniq->reg_lock); 1393 return 0; 1394 } 1395 1396 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol, 1397 struct snd_ctl_elem_value *ucontrol) 1398 { 1399 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1400 unsigned int val; 1401 int change; 1402 1403 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1404 ((u32)ucontrol->value.iec958.status[1] << 8) | 1405 ((u32)ucontrol->value.iec958.status[2] << 16) | 1406 ((u32)ucontrol->value.iec958.status[3] << 24); 1407 spin_lock_irq(&ensoniq->reg_lock); 1408 change = ensoniq->spdif_stream != val; 1409 ensoniq->spdif_stream = val; 1410 if (change && (ensoniq->playback1_substream != NULL || 1411 ensoniq->playback2_substream != NULL)) 1412 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1413 spin_unlock_irq(&ensoniq->reg_lock); 1414 return change; 1415 } 1416 1417 #define ES1371_SPDIF(xname) \ 1418 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \ 1419 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put } 1420 1421 #define snd_es1371_spdif_info snd_ctl_boolean_mono_info 1422 1423 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol, 1424 struct snd_ctl_elem_value *ucontrol) 1425 { 1426 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1427 1428 spin_lock_irq(&ensoniq->reg_lock); 1429 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; 1430 spin_unlock_irq(&ensoniq->reg_lock); 1431 return 0; 1432 } 1433 1434 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol, 1435 struct snd_ctl_elem_value *ucontrol) 1436 { 1437 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1438 unsigned int nval1, nval2; 1439 int change; 1440 1441 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0; 1442 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0; 1443 spin_lock_irq(&ensoniq->reg_lock); 1444 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; 1445 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; 1446 ensoniq->ctrl |= nval1; 1447 ensoniq->cssr &= ~ES_1373_SPDIF_EN; 1448 ensoniq->cssr |= nval2; 1449 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1450 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1451 spin_unlock_irq(&ensoniq->reg_lock); 1452 return change; 1453 } 1454 1455 1456 /* spdif controls */ 1457 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = { 1458 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)), 1459 { 1460 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1461 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1462 .info = snd_ens1373_spdif_info, 1463 .get = snd_ens1373_spdif_default_get, 1464 .put = snd_ens1373_spdif_default_put, 1465 }, 1466 { 1467 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1468 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1469 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 1470 .info = snd_ens1373_spdif_info, 1471 .get = snd_ens1373_spdif_mask_get 1472 }, 1473 { 1474 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1475 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1476 .info = snd_ens1373_spdif_info, 1477 .get = snd_ens1373_spdif_stream_get, 1478 .put = snd_ens1373_spdif_stream_put 1479 }, 1480 }; 1481 1482 1483 #define snd_es1373_rear_info snd_ctl_boolean_mono_info 1484 1485 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol, 1486 struct snd_ctl_elem_value *ucontrol) 1487 { 1488 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1489 int val = 0; 1490 1491 spin_lock_irq(&ensoniq->reg_lock); 1492 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26| 1493 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26) 1494 val = 1; 1495 ucontrol->value.integer.value[0] = val; 1496 spin_unlock_irq(&ensoniq->reg_lock); 1497 return 0; 1498 } 1499 1500 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol, 1501 struct snd_ctl_elem_value *ucontrol) 1502 { 1503 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1504 unsigned int nval1; 1505 int change; 1506 1507 nval1 = ucontrol->value.integer.value[0] ? 1508 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1509 spin_lock_irq(&ensoniq->reg_lock); 1510 change = (ensoniq->cssr & (ES_1373_REAR_BIT27| 1511 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1; 1512 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24); 1513 ensoniq->cssr |= nval1; 1514 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1515 spin_unlock_irq(&ensoniq->reg_lock); 1516 return change; 1517 } 1518 1519 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata = 1520 { 1521 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1522 .name = "AC97 2ch->4ch Copy Switch", 1523 .info = snd_es1373_rear_info, 1524 .get = snd_es1373_rear_get, 1525 .put = snd_es1373_rear_put, 1526 }; 1527 1528 #define snd_es1373_line_info snd_ctl_boolean_mono_info 1529 1530 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol, 1531 struct snd_ctl_elem_value *ucontrol) 1532 { 1533 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1534 int val = 0; 1535 1536 spin_lock_irq(&ensoniq->reg_lock); 1537 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4) 1538 val = 1; 1539 ucontrol->value.integer.value[0] = val; 1540 spin_unlock_irq(&ensoniq->reg_lock); 1541 return 0; 1542 } 1543 1544 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol, 1545 struct snd_ctl_elem_value *ucontrol) 1546 { 1547 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1548 int changed; 1549 unsigned int ctrl; 1550 1551 spin_lock_irq(&ensoniq->reg_lock); 1552 ctrl = ensoniq->ctrl; 1553 if (ucontrol->value.integer.value[0]) 1554 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ 1555 else 1556 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); 1557 changed = (ctrl != ensoniq->ctrl); 1558 if (changed) 1559 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1560 spin_unlock_irq(&ensoniq->reg_lock); 1561 return changed; 1562 } 1563 1564 static struct snd_kcontrol_new snd_ens1373_line __devinitdata = 1565 { 1566 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1567 .name = "Line In->Rear Out Switch", 1568 .info = snd_es1373_line_info, 1569 .get = snd_es1373_line_get, 1570 .put = snd_es1373_line_put, 1571 }; 1572 1573 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97) 1574 { 1575 struct ensoniq *ensoniq = ac97->private_data; 1576 ensoniq->u.es1371.ac97 = NULL; 1577 } 1578 1579 struct es1371_quirk { 1580 unsigned short vid; /* vendor ID */ 1581 unsigned short did; /* device ID */ 1582 unsigned char rev; /* revision */ 1583 }; 1584 1585 static int es1371_quirk_lookup(struct ensoniq *ensoniq, 1586 struct es1371_quirk *list) 1587 { 1588 while (list->vid != (unsigned short)PCI_ANY_ID) { 1589 if (ensoniq->pci->vendor == list->vid && 1590 ensoniq->pci->device == list->did && 1591 ensoniq->rev == list->rev) 1592 return 1; 1593 list++; 1594 } 1595 return 0; 1596 } 1597 1598 static struct es1371_quirk es1371_spdif_present[] __devinitdata = { 1599 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1600 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1601 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1602 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1603 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1604 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1605 }; 1606 1607 static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = { 1608 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */ 1609 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */ 1610 { } /* end */ 1611 }; 1612 1613 static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq, 1614 int has_spdif, int has_line) 1615 { 1616 struct snd_card *card = ensoniq->card; 1617 struct snd_ac97_bus *pbus; 1618 struct snd_ac97_template ac97; 1619 int err; 1620 static struct snd_ac97_bus_ops ops = { 1621 .write = snd_es1371_codec_write, 1622 .read = snd_es1371_codec_read, 1623 .wait = snd_es1371_codec_wait, 1624 }; 1625 1626 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0) 1627 return err; 1628 1629 memset(&ac97, 0, sizeof(ac97)); 1630 ac97.private_data = ensoniq; 1631 ac97.private_free = snd_ensoniq_mixer_free_ac97; 1632 ac97.scaps = AC97_SCAP_AUDIO; 1633 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0) 1634 return err; 1635 if (has_spdif > 0 || 1636 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) { 1637 struct snd_kcontrol *kctl; 1638 int i, index = 0; 1639 1640 ensoniq->spdif_default = ensoniq->spdif_stream = 1641 SNDRV_PCM_DEFAULT_CON_SPDIF; 1642 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS)); 1643 1644 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF) 1645 index++; 1646 1647 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) { 1648 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq); 1649 if (!kctl) 1650 return -ENOMEM; 1651 kctl->id.index = index; 1652 err = snd_ctl_add(card, kctl); 1653 if (err < 0) 1654 return err; 1655 } 1656 } 1657 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) { 1658 /* mirror rear to front speakers */ 1659 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1660 ensoniq->cssr |= ES_1373_REAR_BIT26; 1661 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq)); 1662 if (err < 0) 1663 return err; 1664 } 1665 if (has_line > 0 || 1666 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) { 1667 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, 1668 ensoniq)); 1669 if (err < 0) 1670 return err; 1671 } 1672 1673 return 0; 1674 } 1675 1676 #endif /* CHIP1371 */ 1677 1678 /* generic control callbacks for ens1370 */ 1679 #ifdef CHIP1370 1680 #define ENSONIQ_CONTROL(xname, mask) \ 1681 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \ 1682 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \ 1683 .private_value = mask } 1684 1685 #define snd_ensoniq_control_info snd_ctl_boolean_mono_info 1686 1687 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol, 1688 struct snd_ctl_elem_value *ucontrol) 1689 { 1690 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1691 int mask = kcontrol->private_value; 1692 1693 spin_lock_irq(&ensoniq->reg_lock); 1694 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; 1695 spin_unlock_irq(&ensoniq->reg_lock); 1696 return 0; 1697 } 1698 1699 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol, 1700 struct snd_ctl_elem_value *ucontrol) 1701 { 1702 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1703 int mask = kcontrol->private_value; 1704 unsigned int nval; 1705 int change; 1706 1707 nval = ucontrol->value.integer.value[0] ? mask : 0; 1708 spin_lock_irq(&ensoniq->reg_lock); 1709 change = (ensoniq->ctrl & mask) != nval; 1710 ensoniq->ctrl &= ~mask; 1711 ensoniq->ctrl |= nval; 1712 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1713 spin_unlock_irq(&ensoniq->reg_lock); 1714 return change; 1715 } 1716 1717 /* 1718 * ENS1370 mixer 1719 */ 1720 1721 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = { 1722 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0), 1723 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1) 1724 }; 1725 1726 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls) 1727 1728 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531) 1729 { 1730 struct ensoniq *ensoniq = ak4531->private_data; 1731 ensoniq->u.es1370.ak4531 = NULL; 1732 } 1733 1734 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq) 1735 { 1736 struct snd_card *card = ensoniq->card; 1737 struct snd_ak4531 ak4531; 1738 unsigned int idx; 1739 int err; 1740 1741 /* try reset AK4531 */ 1742 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 1743 inw(ES_REG(ensoniq, 1370_CODEC)); 1744 udelay(100); 1745 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 1746 inw(ES_REG(ensoniq, 1370_CODEC)); 1747 udelay(100); 1748 1749 memset(&ak4531, 0, sizeof(ak4531)); 1750 ak4531.write = snd_es1370_codec_write; 1751 ak4531.private_data = ensoniq; 1752 ak4531.private_free = snd_ensoniq_mixer_free_ak4531; 1753 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0) 1754 return err; 1755 for (idx = 0; idx < ES1370_CONTROLS; idx++) { 1756 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq)); 1757 if (err < 0) 1758 return err; 1759 } 1760 return 0; 1761 } 1762 1763 #endif /* CHIP1370 */ 1764 1765 #ifdef SUPPORT_JOYSTICK 1766 1767 #ifdef CHIP1371 1768 static int __devinit snd_ensoniq_get_joystick_port(int dev) 1769 { 1770 switch (joystick_port[dev]) { 1771 case 0: /* disabled */ 1772 case 1: /* auto-detect */ 1773 case 0x200: 1774 case 0x208: 1775 case 0x210: 1776 case 0x218: 1777 return joystick_port[dev]; 1778 1779 default: 1780 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]); 1781 return 0; 1782 } 1783 } 1784 #else 1785 static inline int snd_ensoniq_get_joystick_port(int dev) 1786 { 1787 return joystick[dev] ? 0x200 : 0; 1788 } 1789 #endif 1790 1791 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev) 1792 { 1793 struct gameport *gp; 1794 int io_port; 1795 1796 io_port = snd_ensoniq_get_joystick_port(dev); 1797 1798 switch (io_port) { 1799 case 0: 1800 return -ENOSYS; 1801 1802 case 1: /* auto_detect */ 1803 for (io_port = 0x200; io_port <= 0x218; io_port += 8) 1804 if (request_region(io_port, 8, "ens137x: gameport")) 1805 break; 1806 if (io_port > 0x218) { 1807 printk(KERN_WARNING "ens137x: no gameport ports available\n"); 1808 return -EBUSY; 1809 } 1810 break; 1811 1812 default: 1813 if (!request_region(io_port, 8, "ens137x: gameport")) { 1814 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", 1815 io_port); 1816 return -EBUSY; 1817 } 1818 break; 1819 } 1820 1821 ensoniq->gameport = gp = gameport_allocate_port(); 1822 if (!gp) { 1823 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n"); 1824 release_region(io_port, 8); 1825 return -ENOMEM; 1826 } 1827 1828 gameport_set_name(gp, "ES137x"); 1829 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci)); 1830 gameport_set_dev_parent(gp, &ensoniq->pci->dev); 1831 gp->io = io_port; 1832 1833 ensoniq->ctrl |= ES_JYSTK_EN; 1834 #ifdef CHIP1371 1835 ensoniq->ctrl &= ~ES_1371_JOY_ASELM; 1836 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); 1837 #endif 1838 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1839 1840 gameport_register_port(ensoniq->gameport); 1841 1842 return 0; 1843 } 1844 1845 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) 1846 { 1847 if (ensoniq->gameport) { 1848 int port = ensoniq->gameport->io; 1849 1850 gameport_unregister_port(ensoniq->gameport); 1851 ensoniq->gameport = NULL; 1852 ensoniq->ctrl &= ~ES_JYSTK_EN; 1853 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1854 release_region(port, 8); 1855 } 1856 } 1857 #else 1858 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; } 1859 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { } 1860 #endif /* SUPPORT_JOYSTICK */ 1861 1862 /* 1863 1864 */ 1865 1866 static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 1867 struct snd_info_buffer *buffer) 1868 { 1869 struct ensoniq *ensoniq = entry->private_data; 1870 1871 #ifdef CHIP1370 1872 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n"); 1873 #else 1874 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n"); 1875 #endif 1876 snd_iprintf(buffer, "Joystick enable : %s\n", 1877 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); 1878 #ifdef CHIP1370 1879 snd_iprintf(buffer, "MIC +5V bias : %s\n", 1880 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); 1881 snd_iprintf(buffer, "Line In to AOUT : %s\n", 1882 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); 1883 #else 1884 snd_iprintf(buffer, "Joystick port : 0x%x\n", 1885 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); 1886 #endif 1887 } 1888 1889 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq) 1890 { 1891 struct snd_info_entry *entry; 1892 1893 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry)) 1894 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read); 1895 } 1896 1897 /* 1898 1899 */ 1900 1901 static int snd_ensoniq_free(struct ensoniq *ensoniq) 1902 { 1903 snd_ensoniq_free_gameport(ensoniq); 1904 if (ensoniq->irq < 0) 1905 goto __hw_end; 1906 #ifdef CHIP1370 1907 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1908 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1909 #else 1910 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1911 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1912 #endif 1913 synchronize_irq(ensoniq->irq); 1914 pci_set_power_state(ensoniq->pci, 3); 1915 __hw_end: 1916 #ifdef CHIP1370 1917 if (ensoniq->dma_bug.area) 1918 snd_dma_free_pages(&ensoniq->dma_bug); 1919 #endif 1920 if (ensoniq->irq >= 0) 1921 free_irq(ensoniq->irq, ensoniq); 1922 pci_release_regions(ensoniq->pci); 1923 pci_disable_device(ensoniq->pci); 1924 kfree(ensoniq); 1925 return 0; 1926 } 1927 1928 static int snd_ensoniq_dev_free(struct snd_device *device) 1929 { 1930 struct ensoniq *ensoniq = device->device_data; 1931 return snd_ensoniq_free(ensoniq); 1932 } 1933 1934 #ifdef CHIP1371 1935 static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = { 1936 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */ 1937 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */ 1938 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */ 1939 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */ 1940 { } /* end */ 1941 }; 1942 1943 static struct es1371_quirk es1371_ac97_reset_hack[] = { 1944 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1945 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1946 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1947 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1948 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1949 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1950 }; 1951 #endif 1952 1953 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq) 1954 { 1955 #ifdef CHIP1371 1956 int idx; 1957 #endif 1958 /* this code was part of snd_ensoniq_create before intruduction 1959 * of suspend/resume 1960 */ 1961 #ifdef CHIP1370 1962 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1963 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1964 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1965 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME)); 1966 outl(0, ES_REG(ensoniq, PHANTOM_COUNT)); 1967 #else 1968 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1969 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 1970 outl(0, ES_REG(ensoniq, 1371_LEGACY)); 1971 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) { 1972 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1973 /* need to delay around 20ms(bleech) to give 1974 some CODECs enough time to wakeup */ 1975 msleep(20); 1976 } 1977 /* AC'97 warm reset to start the bitclk */ 1978 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); 1979 inl(ES_REG(ensoniq, CONTROL)); 1980 udelay(20); 1981 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1982 /* Init the sample rate converter */ 1983 snd_es1371_wait_src_ready(ensoniq); 1984 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE)); 1985 for (idx = 0; idx < 0x80; idx++) 1986 snd_es1371_src_write(ensoniq, idx, 0); 1987 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 1988 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 1989 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 1990 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 1991 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12); 1992 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12); 1993 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12); 1994 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 1995 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12); 1996 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 1997 snd_es1371_adc_rate(ensoniq, 22050); 1998 snd_es1371_dac1_rate(ensoniq, 22050); 1999 snd_es1371_dac2_rate(ensoniq, 22050); 2000 /* WARNING: 2001 * enabling the sample rate converter without properly programming 2002 * its parameters causes the chip to lock up (the SRC busy bit will 2003 * be stuck high, and I've found no way to rectify this other than 2004 * power cycle) - Thomas Sailer 2005 */ 2006 snd_es1371_wait_src_ready(ensoniq); 2007 outl(0, ES_REG(ensoniq, 1371_SMPRATE)); 2008 /* try reset codec directly */ 2009 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC)); 2010 #endif 2011 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL)); 2012 outb(0x00, ES_REG(ensoniq, UART_RES)); 2013 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2014 synchronize_irq(ensoniq->irq); 2015 } 2016 2017 #ifdef CONFIG_PM 2018 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state) 2019 { 2020 struct snd_card *card = pci_get_drvdata(pci); 2021 struct ensoniq *ensoniq = card->private_data; 2022 2023 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2024 2025 snd_pcm_suspend_all(ensoniq->pcm1); 2026 snd_pcm_suspend_all(ensoniq->pcm2); 2027 2028 #ifdef CHIP1371 2029 snd_ac97_suspend(ensoniq->u.es1371.ac97); 2030 #else 2031 /* try to reset AK4531 */ 2032 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 2033 inw(ES_REG(ensoniq, 1370_CODEC)); 2034 udelay(100); 2035 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 2036 inw(ES_REG(ensoniq, 1370_CODEC)); 2037 udelay(100); 2038 snd_ak4531_suspend(ensoniq->u.es1370.ak4531); 2039 #endif 2040 2041 pci_disable_device(pci); 2042 pci_save_state(pci); 2043 pci_set_power_state(pci, pci_choose_state(pci, state)); 2044 return 0; 2045 } 2046 2047 static int snd_ensoniq_resume(struct pci_dev *pci) 2048 { 2049 struct snd_card *card = pci_get_drvdata(pci); 2050 struct ensoniq *ensoniq = card->private_data; 2051 2052 pci_set_power_state(pci, PCI_D0); 2053 pci_restore_state(pci); 2054 if (pci_enable_device(pci) < 0) { 2055 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, " 2056 "disabling device\n"); 2057 snd_card_disconnect(card); 2058 return -EIO; 2059 } 2060 pci_set_master(pci); 2061 2062 snd_ensoniq_chip_init(ensoniq); 2063 2064 #ifdef CHIP1371 2065 snd_ac97_resume(ensoniq->u.es1371.ac97); 2066 #else 2067 snd_ak4531_resume(ensoniq->u.es1370.ak4531); 2068 #endif 2069 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2070 return 0; 2071 } 2072 #endif /* CONFIG_PM */ 2073 2074 2075 static int __devinit snd_ensoniq_create(struct snd_card *card, 2076 struct pci_dev *pci, 2077 struct ensoniq ** rensoniq) 2078 { 2079 struct ensoniq *ensoniq; 2080 int err; 2081 static struct snd_device_ops ops = { 2082 .dev_free = snd_ensoniq_dev_free, 2083 }; 2084 2085 *rensoniq = NULL; 2086 if ((err = pci_enable_device(pci)) < 0) 2087 return err; 2088 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL); 2089 if (ensoniq == NULL) { 2090 pci_disable_device(pci); 2091 return -ENOMEM; 2092 } 2093 spin_lock_init(&ensoniq->reg_lock); 2094 mutex_init(&ensoniq->src_mutex); 2095 ensoniq->card = card; 2096 ensoniq->pci = pci; 2097 ensoniq->irq = -1; 2098 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) { 2099 kfree(ensoniq); 2100 pci_disable_device(pci); 2101 return err; 2102 } 2103 ensoniq->port = pci_resource_start(pci, 0); 2104 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED, 2105 "Ensoniq AudioPCI", ensoniq)) { 2106 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2107 snd_ensoniq_free(ensoniq); 2108 return -EBUSY; 2109 } 2110 ensoniq->irq = pci->irq; 2111 #ifdef CHIP1370 2112 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2113 16, &ensoniq->dma_bug) < 0) { 2114 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n"); 2115 snd_ensoniq_free(ensoniq); 2116 return -EBUSY; 2117 } 2118 #endif 2119 pci_set_master(pci); 2120 ensoniq->rev = pci->revision; 2121 #ifdef CHIP1370 2122 #if 0 2123 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | 2124 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2125 #else /* get microphone working */ 2126 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2127 #endif 2128 ensoniq->sctrl = 0; 2129 #else 2130 ensoniq->ctrl = 0; 2131 ensoniq->sctrl = 0; 2132 ensoniq->cssr = 0; 2133 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack)) 2134 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ 2135 2136 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) 2137 ensoniq->cssr |= ES_1371_ST_AC97_RST; 2138 #endif 2139 2140 snd_ensoniq_chip_init(ensoniq); 2141 2142 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) { 2143 snd_ensoniq_free(ensoniq); 2144 return err; 2145 } 2146 2147 snd_ensoniq_proc_init(ensoniq); 2148 2149 snd_card_set_dev(card, &pci->dev); 2150 2151 *rensoniq = ensoniq; 2152 return 0; 2153 } 2154 2155 /* 2156 * MIDI section 2157 */ 2158 2159 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq) 2160 { 2161 struct snd_rawmidi *rmidi = ensoniq->rmidi; 2162 unsigned char status, mask, byte; 2163 2164 if (rmidi == NULL) 2165 return; 2166 /* do Rx at first */ 2167 spin_lock(&ensoniq->reg_lock); 2168 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; 2169 while (mask) { 2170 status = inb(ES_REG(ensoniq, UART_STATUS)); 2171 if ((status & mask) == 0) 2172 break; 2173 byte = inb(ES_REG(ensoniq, UART_DATA)); 2174 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1); 2175 } 2176 spin_unlock(&ensoniq->reg_lock); 2177 2178 /* do Tx at second */ 2179 spin_lock(&ensoniq->reg_lock); 2180 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; 2181 while (mask) { 2182 status = inb(ES_REG(ensoniq, UART_STATUS)); 2183 if ((status & mask) == 0) 2184 break; 2185 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) { 2186 ensoniq->uartc &= ~ES_TXINTENM; 2187 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2188 mask &= ~ES_TXRDY; 2189 } else { 2190 outb(byte, ES_REG(ensoniq, UART_DATA)); 2191 } 2192 } 2193 spin_unlock(&ensoniq->reg_lock); 2194 } 2195 2196 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream) 2197 { 2198 struct ensoniq *ensoniq = substream->rmidi->private_data; 2199 2200 spin_lock_irq(&ensoniq->reg_lock); 2201 ensoniq->uartm |= ES_MODE_INPUT; 2202 ensoniq->midi_input = substream; 2203 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2204 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2205 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2206 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2207 } 2208 spin_unlock_irq(&ensoniq->reg_lock); 2209 return 0; 2210 } 2211 2212 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream) 2213 { 2214 struct ensoniq *ensoniq = substream->rmidi->private_data; 2215 2216 spin_lock_irq(&ensoniq->reg_lock); 2217 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2218 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2219 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2220 } else { 2221 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL)); 2222 } 2223 ensoniq->midi_input = NULL; 2224 ensoniq->uartm &= ~ES_MODE_INPUT; 2225 spin_unlock_irq(&ensoniq->reg_lock); 2226 return 0; 2227 } 2228 2229 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream) 2230 { 2231 struct ensoniq *ensoniq = substream->rmidi->private_data; 2232 2233 spin_lock_irq(&ensoniq->reg_lock); 2234 ensoniq->uartm |= ES_MODE_OUTPUT; 2235 ensoniq->midi_output = substream; 2236 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2237 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2238 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2239 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2240 } 2241 spin_unlock_irq(&ensoniq->reg_lock); 2242 return 0; 2243 } 2244 2245 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream) 2246 { 2247 struct ensoniq *ensoniq = substream->rmidi->private_data; 2248 2249 spin_lock_irq(&ensoniq->reg_lock); 2250 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2251 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2252 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2253 } else { 2254 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL)); 2255 } 2256 ensoniq->midi_output = NULL; 2257 ensoniq->uartm &= ~ES_MODE_OUTPUT; 2258 spin_unlock_irq(&ensoniq->reg_lock); 2259 return 0; 2260 } 2261 2262 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2263 { 2264 unsigned long flags; 2265 struct ensoniq *ensoniq = substream->rmidi->private_data; 2266 int idx; 2267 2268 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2269 if (up) { 2270 if ((ensoniq->uartc & ES_RXINTEN) == 0) { 2271 /* empty input FIFO */ 2272 for (idx = 0; idx < 32; idx++) 2273 inb(ES_REG(ensoniq, UART_DATA)); 2274 ensoniq->uartc |= ES_RXINTEN; 2275 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2276 } 2277 } else { 2278 if (ensoniq->uartc & ES_RXINTEN) { 2279 ensoniq->uartc &= ~ES_RXINTEN; 2280 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2281 } 2282 } 2283 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2284 } 2285 2286 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2287 { 2288 unsigned long flags; 2289 struct ensoniq *ensoniq = substream->rmidi->private_data; 2290 unsigned char byte; 2291 2292 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2293 if (up) { 2294 if (ES_TXINTENI(ensoniq->uartc) == 0) { 2295 ensoniq->uartc |= ES_TXINTENO(1); 2296 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2297 while (ES_TXINTENI(ensoniq->uartc) == 1 && 2298 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) { 2299 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2300 ensoniq->uartc &= ~ES_TXINTENM; 2301 } else { 2302 outb(byte, ES_REG(ensoniq, UART_DATA)); 2303 } 2304 } 2305 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2306 } 2307 } else { 2308 if (ES_TXINTENI(ensoniq->uartc) == 1) { 2309 ensoniq->uartc &= ~ES_TXINTENM; 2310 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2311 } 2312 } 2313 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2314 } 2315 2316 static struct snd_rawmidi_ops snd_ensoniq_midi_output = 2317 { 2318 .open = snd_ensoniq_midi_output_open, 2319 .close = snd_ensoniq_midi_output_close, 2320 .trigger = snd_ensoniq_midi_output_trigger, 2321 }; 2322 2323 static struct snd_rawmidi_ops snd_ensoniq_midi_input = 2324 { 2325 .open = snd_ensoniq_midi_input_open, 2326 .close = snd_ensoniq_midi_input_close, 2327 .trigger = snd_ensoniq_midi_input_trigger, 2328 }; 2329 2330 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device, 2331 struct snd_rawmidi **rrawmidi) 2332 { 2333 struct snd_rawmidi *rmidi; 2334 int err; 2335 2336 if (rrawmidi) 2337 *rrawmidi = NULL; 2338 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0) 2339 return err; 2340 #ifdef CHIP1370 2341 strcpy(rmidi->name, "ES1370"); 2342 #else 2343 strcpy(rmidi->name, "ES1371"); 2344 #endif 2345 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output); 2346 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input); 2347 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | 2348 SNDRV_RAWMIDI_INFO_DUPLEX; 2349 rmidi->private_data = ensoniq; 2350 ensoniq->rmidi = rmidi; 2351 if (rrawmidi) 2352 *rrawmidi = rmidi; 2353 return 0; 2354 } 2355 2356 /* 2357 * Interrupt handler 2358 */ 2359 2360 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id) 2361 { 2362 struct ensoniq *ensoniq = dev_id; 2363 unsigned int status, sctrl; 2364 2365 if (ensoniq == NULL) 2366 return IRQ_NONE; 2367 2368 status = inl(ES_REG(ensoniq, STATUS)); 2369 if (!(status & ES_INTR)) 2370 return IRQ_NONE; 2371 2372 spin_lock(&ensoniq->reg_lock); 2373 sctrl = ensoniq->sctrl; 2374 if (status & ES_DAC1) 2375 sctrl &= ~ES_P1_INT_EN; 2376 if (status & ES_DAC2) 2377 sctrl &= ~ES_P2_INT_EN; 2378 if (status & ES_ADC) 2379 sctrl &= ~ES_R1_INT_EN; 2380 outl(sctrl, ES_REG(ensoniq, SERIAL)); 2381 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2382 spin_unlock(&ensoniq->reg_lock); 2383 2384 if (status & ES_UART) 2385 snd_ensoniq_midi_interrupt(ensoniq); 2386 if ((status & ES_DAC2) && ensoniq->playback2_substream) 2387 snd_pcm_period_elapsed(ensoniq->playback2_substream); 2388 if ((status & ES_ADC) && ensoniq->capture_substream) 2389 snd_pcm_period_elapsed(ensoniq->capture_substream); 2390 if ((status & ES_DAC1) && ensoniq->playback1_substream) 2391 snd_pcm_period_elapsed(ensoniq->playback1_substream); 2392 return IRQ_HANDLED; 2393 } 2394 2395 static int __devinit snd_audiopci_probe(struct pci_dev *pci, 2396 const struct pci_device_id *pci_id) 2397 { 2398 static int dev; 2399 struct snd_card *card; 2400 struct ensoniq *ensoniq; 2401 int err, pcm_devs[2]; 2402 2403 if (dev >= SNDRV_CARDS) 2404 return -ENODEV; 2405 if (!enable[dev]) { 2406 dev++; 2407 return -ENOENT; 2408 } 2409 2410 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2411 if (card == NULL) 2412 return -ENOMEM; 2413 2414 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) { 2415 snd_card_free(card); 2416 return err; 2417 } 2418 card->private_data = ensoniq; 2419 2420 pcm_devs[0] = 0; pcm_devs[1] = 1; 2421 #ifdef CHIP1370 2422 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) { 2423 snd_card_free(card); 2424 return err; 2425 } 2426 #endif 2427 #ifdef CHIP1371 2428 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) { 2429 snd_card_free(card); 2430 return err; 2431 } 2432 #endif 2433 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) { 2434 snd_card_free(card); 2435 return err; 2436 } 2437 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) { 2438 snd_card_free(card); 2439 return err; 2440 } 2441 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) { 2442 snd_card_free(card); 2443 return err; 2444 } 2445 2446 snd_ensoniq_create_gameport(ensoniq, dev); 2447 2448 strcpy(card->driver, DRIVER_NAME); 2449 2450 strcpy(card->shortname, "Ensoniq AudioPCI"); 2451 sprintf(card->longname, "%s %s at 0x%lx, irq %i", 2452 card->shortname, 2453 card->driver, 2454 ensoniq->port, 2455 ensoniq->irq); 2456 2457 if ((err = snd_card_register(card)) < 0) { 2458 snd_card_free(card); 2459 return err; 2460 } 2461 2462 pci_set_drvdata(pci, card); 2463 dev++; 2464 return 0; 2465 } 2466 2467 static void __devexit snd_audiopci_remove(struct pci_dev *pci) 2468 { 2469 snd_card_free(pci_get_drvdata(pci)); 2470 pci_set_drvdata(pci, NULL); 2471 } 2472 2473 static struct pci_driver driver = { 2474 .name = DRIVER_NAME, 2475 .id_table = snd_audiopci_ids, 2476 .probe = snd_audiopci_probe, 2477 .remove = __devexit_p(snd_audiopci_remove), 2478 #ifdef CONFIG_PM 2479 .suspend = snd_ensoniq_suspend, 2480 .resume = snd_ensoniq_resume, 2481 #endif 2482 }; 2483 2484 static int __init alsa_card_ens137x_init(void) 2485 { 2486 return pci_register_driver(&driver); 2487 } 2488 2489 static void __exit alsa_card_ens137x_exit(void) 2490 { 2491 pci_unregister_driver(&driver); 2492 } 2493 2494 module_init(alsa_card_ens137x_init) 2495 module_exit(alsa_card_ens137x_exit) 2496