13969f617SJames Courtier-Dutton /* 23969f617SJames Courtier-Dutton * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk> 33969f617SJames Courtier-Dutton * Driver p17v chips 43969f617SJames Courtier-Dutton * Version: 0.01 53969f617SJames Courtier-Dutton * 63969f617SJames Courtier-Dutton * This program is free software; you can redistribute it and/or modify 73969f617SJames Courtier-Dutton * it under the terms of the GNU General Public License as published by 83969f617SJames Courtier-Dutton * the Free Software Foundation; either version 2 of the License, or 93969f617SJames Courtier-Dutton * (at your option) any later version. 103969f617SJames Courtier-Dutton * 113969f617SJames Courtier-Dutton * This program is distributed in the hope that it will be useful, 123969f617SJames Courtier-Dutton * but WITHOUT ANY WARRANTY; without even the implied warranty of 133969f617SJames Courtier-Dutton * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 143969f617SJames Courtier-Dutton * GNU General Public License for more details. 153969f617SJames Courtier-Dutton * 163969f617SJames Courtier-Dutton * You should have received a copy of the GNU General Public License 173969f617SJames Courtier-Dutton * along with this program; if not, write to the Free Software 183969f617SJames Courtier-Dutton * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 193969f617SJames Courtier-Dutton * 203969f617SJames Courtier-Dutton */ 213969f617SJames Courtier-Dutton 223969f617SJames Courtier-Dutton /******************************************************************************/ 233969f617SJames Courtier-Dutton /* Audigy2Value Tina (P17V) pointer-offset register set, 243969f617SJames Courtier-Dutton * accessed through the PTR20 and DATA24 registers */ 253969f617SJames Courtier-Dutton /******************************************************************************/ 263969f617SJames Courtier-Dutton 273969f617SJames Courtier-Dutton /* 00 - 07: Not used */ 283969f617SJames Courtier-Dutton #define P17V_PLAYBACK_FIFO_PTR 0x08 /* Current playback fifo pointer 293969f617SJames Courtier-Dutton * and number of sound samples in cache. 303969f617SJames Courtier-Dutton */ 313969f617SJames Courtier-Dutton /* 09 - 12: Not used */ 323969f617SJames Courtier-Dutton #define P17V_CAPTURE_FIFO_PTR 0x13 /* Current capture fifo pointer 333969f617SJames Courtier-Dutton * and number of sound samples in cache. 343969f617SJames Courtier-Dutton */ 353969f617SJames Courtier-Dutton /* 14 - 17: Not used */ 363969f617SJames Courtier-Dutton #define P17V_PB_CHN_SEL 0x18 /* P17v playback channel select */ 373969f617SJames Courtier-Dutton #define P17V_SE_SLOT_SEL_L 0x19 /* Sound Engine slot select low */ 383969f617SJames Courtier-Dutton #define P17V_SE_SLOT_SEL_H 0x1a /* Sound Engine slot select high */ 393969f617SJames Courtier-Dutton /* 1b - 1f: Not used */ 403969f617SJames Courtier-Dutton /* 20 - 2f: Not used */ 413969f617SJames Courtier-Dutton /* 30 - 3b: Not used */ 423969f617SJames Courtier-Dutton #define P17V_SPI 0x3c /* SPI interface register */ 433969f617SJames Courtier-Dutton #define P17V_I2C_ADDR 0x3d /* I2C Address */ 443969f617SJames Courtier-Dutton #define P17V_I2C_0 0x3e /* I2C Data */ 453969f617SJames Courtier-Dutton #define P17V_I2C_1 0x3f /* I2C Data */ 46184c1e2cSJames Courtier-Dutton /* I2C values */ 47184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_ADD_MASK 0x000000fe /*The address is a 7 bit address */ 48184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_RW_MASK 0x00000001 /*bit mask for R/W */ 49184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_TRANS_MASK 0x00000010 /*Bit mask for I2c address DAC value */ 50184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_ABORT_MASK 0x00000020 /*Bit mask for I2C transaction abort flag */ 51184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_LAST_MASK 0x00000040 /*Bit mask for Last word transaction */ 52184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_BYTE_MASK 0x00000080 /*Bit mask for Byte Mode */ 53184c1e2cSJames Courtier-Dutton 54184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_ADD 0x00000034 /*This is the Device address for ADC */ 55184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_READ 0x00000001 /*To perform a read operation */ 56184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_START 0x00000100 /*Start I2C transaction */ 57184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_ABORT 0x00000200 /*I2C transaction abort */ 58184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_LAST 0x00000400 /*I2C last transaction */ 59184c1e2cSJames Courtier-Dutton #define I2C_A_ADC_BYTE 0x00000800 /*I2C one byte mode */ 60184c1e2cSJames Courtier-Dutton 61184c1e2cSJames Courtier-Dutton #define I2C_D_ADC_REG_MASK 0xfe000000 /*ADC address register */ 62184c1e2cSJames Courtier-Dutton #define I2C_D_ADC_DAT_MASK 0x01ff0000 /*ADC data register */ 63184c1e2cSJames Courtier-Dutton 64184c1e2cSJames Courtier-Dutton #define ADC_TIMEOUT 0x00000007 /*ADC Timeout Clock Disable */ 65184c1e2cSJames Courtier-Dutton #define ADC_IFC_CTRL 0x0000000b /*ADC Interface Control */ 66184c1e2cSJames Courtier-Dutton #define ADC_MASTER 0x0000000c /*ADC Master Mode Control */ 67184c1e2cSJames Courtier-Dutton #define ADC_POWER 0x0000000d /*ADC PowerDown Control */ 68184c1e2cSJames Courtier-Dutton #define ADC_ATTEN_ADCL 0x0000000e /*ADC Attenuation ADCL */ 69184c1e2cSJames Courtier-Dutton #define ADC_ATTEN_ADCR 0x0000000f /*ADC Attenuation ADCR */ 70184c1e2cSJames Courtier-Dutton #define ADC_ALC_CTRL1 0x00000010 /*ADC ALC Control 1 */ 71184c1e2cSJames Courtier-Dutton #define ADC_ALC_CTRL2 0x00000011 /*ADC ALC Control 2 */ 72184c1e2cSJames Courtier-Dutton #define ADC_ALC_CTRL3 0x00000012 /*ADC ALC Control 3 */ 73184c1e2cSJames Courtier-Dutton #define ADC_NOISE_CTRL 0x00000013 /*ADC Noise Gate Control */ 74184c1e2cSJames Courtier-Dutton #define ADC_LIMIT_CTRL 0x00000014 /*ADC Limiter Control */ 75184c1e2cSJames Courtier-Dutton #define ADC_MUX 0x00000015 /*ADC Mux offset */ 76184c1e2cSJames Courtier-Dutton #if 0 77184c1e2cSJames Courtier-Dutton /* FIXME: Not tested yet. */ 78184c1e2cSJames Courtier-Dutton #define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain 79184c1e2cSJames Courtier-Dutton #define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB 80184c1e2cSJames Courtier-Dutton #define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute 81184c1e2cSJames Courtier-Dutton #define ADC_MUTE 0x000000c0 //Value to mute ADC 82184c1e2cSJames Courtier-Dutton #define ADC_OSR 0x00000008 //Mask for ADC oversample rate select 83184c1e2cSJames Courtier-Dutton #define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock 84184c1e2cSJames Courtier-Dutton #define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter 85184c1e2cSJames Courtier-Dutton #define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window 86184c1e2cSJames Courtier-Dutton #endif 87184c1e2cSJames Courtier-Dutton 88184c1e2cSJames Courtier-Dutton #define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux 89184c1e2cSJames Courtier-Dutton #define ADC_MUX_0 0x00000001 //Value to select Unknown at ADC Mux (Not used) 90184c1e2cSJames Courtier-Dutton #define ADC_MUX_1 0x00000002 //Value to select Unknown at ADC Mux (Not used) 91184c1e2cSJames Courtier-Dutton #define ADC_MUX_2 0x00000004 //Value to select Mic at ADC Mux 92184c1e2cSJames Courtier-Dutton #define ADC_MUX_3 0x00000008 //Value to select Line-In at ADC Mux 933969f617SJames Courtier-Dutton 943969f617SJames Courtier-Dutton #define P17V_START_AUDIO 0x40 /* Start Audio bit */ 953969f617SJames Courtier-Dutton /* 41 - 47: Reserved */ 963969f617SJames Courtier-Dutton #define P17V_START_CAPTURE 0x48 /* Start Capture bit */ 973969f617SJames Courtier-Dutton #define P17V_CAPTURE_FIFO_BASE 0x49 /* Record FIFO base address */ 983969f617SJames Courtier-Dutton #define P17V_CAPTURE_FIFO_SIZE 0x4a /* Record FIFO buffer size */ 993969f617SJames Courtier-Dutton #define P17V_CAPTURE_FIFO_INDEX 0x4b /* Record FIFO capture index */ 1003969f617SJames Courtier-Dutton #define P17V_CAPTURE_VOL_H 0x4c /* P17v capture volume control */ 1013969f617SJames Courtier-Dutton #define P17V_CAPTURE_VOL_L 0x4d /* P17v capture volume control */ 1023969f617SJames Courtier-Dutton /* 4e - 4f: Not used */ 1033969f617SJames Courtier-Dutton /* 50 - 5f: Not used */ 1043969f617SJames Courtier-Dutton #define P17V_SRCSel 0x60 /* SRC48 and SRCMulti sample rate select 1053969f617SJames Courtier-Dutton * and output select 1063969f617SJames Courtier-Dutton */ 1073969f617SJames Courtier-Dutton #define P17V_MIXER_AC97_10K1_VOL_L 0x61 /* 10K to Mixer_AC97 input volume control */ 1083969f617SJames Courtier-Dutton #define P17V_MIXER_AC97_10K1_VOL_H 0x62 /* 10K to Mixer_AC97 input volume control */ 1093969f617SJames Courtier-Dutton #define P17V_MIXER_AC97_P17V_VOL_L 0x63 /* P17V to Mixer_AC97 input volume control */ 1103969f617SJames Courtier-Dutton #define P17V_MIXER_AC97_P17V_VOL_H 0x64 /* P17V to Mixer_AC97 input volume control */ 1113969f617SJames Courtier-Dutton #define P17V_MIXER_AC97_SRP_REC_VOL_L 0x65 /* SRP Record to Mixer_AC97 input volume control */ 1123969f617SJames Courtier-Dutton #define P17V_MIXER_AC97_SRP_REC_VOL_H 0x66 /* SRP Record to Mixer_AC97 input volume control */ 1133969f617SJames Courtier-Dutton /* 67 - 68: Reserved */ 1143969f617SJames Courtier-Dutton #define P17V_MIXER_Spdif_10K1_VOL_L 0x69 /* 10K to Mixer_Spdif input volume control */ 1153969f617SJames Courtier-Dutton #define P17V_MIXER_Spdif_10K1_VOL_H 0x6A /* 10K to Mixer_Spdif input volume control */ 1163969f617SJames Courtier-Dutton #define P17V_MIXER_Spdif_P17V_VOL_L 0x6B /* P17V to Mixer_Spdif input volume control */ 1173969f617SJames Courtier-Dutton #define P17V_MIXER_Spdif_P17V_VOL_H 0x6C /* P17V to Mixer_Spdif input volume control */ 1183969f617SJames Courtier-Dutton #define P17V_MIXER_Spdif_SRP_REC_VOL_L 0x6D /* SRP Record to Mixer_Spdif input volume control */ 1193969f617SJames Courtier-Dutton #define P17V_MIXER_Spdif_SRP_REC_VOL_H 0x6E /* SRP Record to Mixer_Spdif input volume control */ 1203969f617SJames Courtier-Dutton /* 6f - 70: Reserved */ 1213969f617SJames Courtier-Dutton #define P17V_MIXER_I2S_10K1_VOL_L 0x71 /* 10K to Mixer_I2S input volume control */ 1223969f617SJames Courtier-Dutton #define P17V_MIXER_I2S_10K1_VOL_H 0x72 /* 10K to Mixer_I2S input volume control */ 1233969f617SJames Courtier-Dutton #define P17V_MIXER_I2S_P17V_VOL_L 0x73 /* P17V to Mixer_I2S input volume control */ 1243969f617SJames Courtier-Dutton #define P17V_MIXER_I2S_P17V_VOL_H 0x74 /* P17V to Mixer_I2S input volume control */ 1253969f617SJames Courtier-Dutton #define P17V_MIXER_I2S_SRP_REC_VOL_L 0x75 /* SRP Record to Mixer_I2S input volume control */ 1263969f617SJames Courtier-Dutton #define P17V_MIXER_I2S_SRP_REC_VOL_H 0x76 /* SRP Record to Mixer_I2S input volume control */ 1273969f617SJames Courtier-Dutton /* 77 - 78: Reserved */ 1283969f617SJames Courtier-Dutton #define P17V_MIXER_AC97_ENABLE 0x79 /* Mixer AC97 input audio enable */ 1293969f617SJames Courtier-Dutton #define P17V_MIXER_SPDIF_ENABLE 0x7A /* Mixer SPDIF input audio enable */ 1303969f617SJames Courtier-Dutton #define P17V_MIXER_I2S_ENABLE 0x7B /* Mixer I2S input audio enable */ 1313969f617SJames Courtier-Dutton #define P17V_AUDIO_OUT_ENABLE 0x7C /* Audio out enable */ 1323969f617SJames Courtier-Dutton #define P17V_MIXER_ATT 0x7D /* SRP Mixer Attenuation Select */ 1333969f617SJames Courtier-Dutton #define P17V_SRP_RECORD_SRR 0x7E /* SRP Record channel source Select */ 1343969f617SJames Courtier-Dutton #define P17V_SOFT_RESET_SRP_MIXER 0x7F /* SRP and mixer soft reset */ 1353969f617SJames Courtier-Dutton 1363969f617SJames Courtier-Dutton #define P17V_AC97_OUT_MASTER_VOL_L 0x80 /* AC97 Output master volume control */ 1373969f617SJames Courtier-Dutton #define P17V_AC97_OUT_MASTER_VOL_H 0x81 /* AC97 Output master volume control */ 1383969f617SJames Courtier-Dutton #define P17V_SPDIF_OUT_MASTER_VOL_L 0x82 /* SPDIF Output master volume control */ 1393969f617SJames Courtier-Dutton #define P17V_SPDIF_OUT_MASTER_VOL_H 0x83 /* SPDIF Output master volume control */ 1403969f617SJames Courtier-Dutton #define P17V_I2S_OUT_MASTER_VOL_L 0x84 /* I2S Output master volume control */ 1413969f617SJames Courtier-Dutton #define P17V_I2S_OUT_MASTER_VOL_H 0x85 /* I2S Output master volume control */ 1423969f617SJames Courtier-Dutton /* 86 - 87: Not used */ 1433969f617SJames Courtier-Dutton #define P17V_I2S_CHANNEL_SWAP_PHASE_INVERSE 0x88 /* I2S out mono channel swap 1443969f617SJames Courtier-Dutton * and phase inverse */ 1453969f617SJames Courtier-Dutton #define P17V_SPDIF_CHANNEL_SWAP_PHASE_INVERSE 0x89 /* SPDIF out mono channel swap 1463969f617SJames Courtier-Dutton * and phase inverse */ 1473969f617SJames Courtier-Dutton /* 8A: Not used */ 1483969f617SJames Courtier-Dutton #define P17V_SRP_P17V_ESR 0x8B /* SRP_P17V estimated sample rate and rate lock */ 1493969f617SJames Courtier-Dutton #define P17V_SRP_REC_ESR 0x8C /* SRP_REC estimated sample rate and rate lock */ 1503969f617SJames Courtier-Dutton #define P17V_SRP_BYPASS 0x8D /* srps channel bypass and srps bypass */ 1513969f617SJames Courtier-Dutton /* 8E - 92: Not used */ 1523969f617SJames Courtier-Dutton #define P17V_I2S_SRC_SEL 0x93 /* I2SIN mode sel */ 1533969f617SJames Courtier-Dutton 1543969f617SJames Courtier-Dutton 1553969f617SJames Courtier-Dutton 1563969f617SJames Courtier-Dutton 1573969f617SJames Courtier-Dutton 1583969f617SJames Courtier-Dutton 159