1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Lee Revell <rlrevell@joe-job.com> 5 * James Courtier-Dutton <James@superbug.co.uk> 6 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> 7 * Creative Labs, Inc. 8 * 9 * Routines for control of EMU10K1 chips 10 */ 11 12 #include <linux/time.h> 13 #include <sound/core.h> 14 #include <sound/emu10k1.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include "p17v.h" 18 19 static inline bool check_ptr_reg(struct snd_emu10k1 *emu, unsigned int reg) 20 { 21 if (snd_BUG_ON(!emu)) 22 return false; 23 if (snd_BUG_ON(reg & (emu->audigy ? (0xffff0000 & ~A_PTR_ADDRESS_MASK) 24 : (0xffff0000 & ~PTR_ADDRESS_MASK)))) 25 return false; 26 if (snd_BUG_ON(reg & 0x0000ffff & ~PTR_CHANNELNUM_MASK)) 27 return false; 28 return true; 29 } 30 31 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn) 32 { 33 unsigned long flags; 34 unsigned int regptr, val; 35 unsigned int mask; 36 37 regptr = (reg << 16) | chn; 38 if (!check_ptr_reg(emu, regptr)) 39 return 0; 40 41 spin_lock_irqsave(&emu->emu_lock, flags); 42 outl(regptr, emu->port + PTR); 43 val = inl(emu->port + DATA); 44 spin_unlock_irqrestore(&emu->emu_lock, flags); 45 46 if (reg & 0xff000000) { 47 unsigned char size, offset; 48 49 size = (reg >> 24) & 0x3f; 50 offset = (reg >> 16) & 0x1f; 51 mask = (1 << size) - 1; 52 53 return (val >> offset) & mask; 54 } else { 55 return val; 56 } 57 } 58 59 EXPORT_SYMBOL(snd_emu10k1_ptr_read); 60 61 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data) 62 { 63 unsigned int regptr; 64 unsigned long flags; 65 unsigned int mask; 66 67 regptr = (reg << 16) | chn; 68 if (!check_ptr_reg(emu, regptr)) 69 return; 70 71 if (reg & 0xff000000) { 72 unsigned char size, offset; 73 74 size = (reg >> 24) & 0x3f; 75 offset = (reg >> 16) & 0x1f; 76 mask = (1 << size) - 1; 77 if (snd_BUG_ON(data & ~mask)) 78 return; 79 mask <<= offset; 80 data <<= offset; 81 82 spin_lock_irqsave(&emu->emu_lock, flags); 83 outl(regptr, emu->port + PTR); 84 data |= inl(emu->port + DATA) & ~mask; 85 } else { 86 spin_lock_irqsave(&emu->emu_lock, flags); 87 outl(regptr, emu->port + PTR); 88 } 89 outl(data, emu->port + DATA); 90 spin_unlock_irqrestore(&emu->emu_lock, flags); 91 } 92 93 EXPORT_SYMBOL(snd_emu10k1_ptr_write); 94 95 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...) 96 { 97 va_list va; 98 u32 addr_mask; 99 unsigned long flags; 100 101 if (snd_BUG_ON(!emu)) 102 return; 103 if (snd_BUG_ON(chn & ~PTR_CHANNELNUM_MASK)) 104 return; 105 addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16); 106 107 va_start(va, chn); 108 spin_lock_irqsave(&emu->emu_lock, flags); 109 for (;;) { 110 u32 data; 111 u32 reg = va_arg(va, u32); 112 if (reg == REGLIST_END) 113 break; 114 data = va_arg(va, u32); 115 if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here 116 continue; 117 outl((reg << 16) | chn, emu->port + PTR); 118 outl(data, emu->port + DATA); 119 } 120 spin_unlock_irqrestore(&emu->emu_lock, flags); 121 va_end(va); 122 } 123 124 EXPORT_SYMBOL(snd_emu10k1_ptr_write_multiple); 125 126 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, 127 unsigned int reg, 128 unsigned int chn) 129 { 130 unsigned long flags; 131 unsigned int regptr, val; 132 133 regptr = (reg << 16) | chn; 134 135 spin_lock_irqsave(&emu->emu_lock, flags); 136 outl(regptr, emu->port + PTR2); 137 val = inl(emu->port + DATA2); 138 spin_unlock_irqrestore(&emu->emu_lock, flags); 139 return val; 140 } 141 142 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, 143 unsigned int reg, 144 unsigned int chn, 145 unsigned int data) 146 { 147 unsigned int regptr; 148 unsigned long flags; 149 150 regptr = (reg << 16) | chn; 151 152 spin_lock_irqsave(&emu->emu_lock, flags); 153 outl(regptr, emu->port + PTR2); 154 outl(data, emu->port + DATA2); 155 spin_unlock_irqrestore(&emu->emu_lock, flags); 156 } 157 158 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, 159 unsigned int data) 160 { 161 unsigned int reset, set; 162 unsigned int reg, tmp; 163 int n, result; 164 int err = 0; 165 166 /* This function is not re-entrant, so protect against it. */ 167 spin_lock(&emu->spi_lock); 168 if (emu->card_capabilities->ca0108_chip) 169 reg = P17V_SPI; 170 else { 171 /* For other chip types the SPI register 172 * is currently unknown. */ 173 err = 1; 174 goto spi_write_exit; 175 } 176 if (data > 0xffff) { 177 /* Only 16bit values allowed */ 178 err = 1; 179 goto spi_write_exit; 180 } 181 182 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); 183 reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */ 184 set = reset | 0x10000; /* Set xxx1xxxx */ 185 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data); 186 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */ 187 snd_emu10k1_ptr20_write(emu, reg, 0, set | data); 188 result = 1; 189 /* Wait for status bit to return to 0 */ 190 for (n = 0; n < 100; n++) { 191 udelay(10); 192 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); 193 if (!(tmp & 0x10000)) { 194 result = 0; 195 break; 196 } 197 } 198 if (result) { 199 /* Timed out */ 200 err = 1; 201 goto spi_write_exit; 202 } 203 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data); 204 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */ 205 err = 0; 206 spi_write_exit: 207 spin_unlock(&emu->spi_lock); 208 return err; 209 } 210 211 /* The ADC does not support i2c read, so only write is implemented */ 212 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, 213 u32 reg, 214 u32 value) 215 { 216 u32 tmp; 217 int timeout = 0; 218 int status; 219 int retry; 220 int err = 0; 221 222 if ((reg > 0x7f) || (value > 0x1ff)) { 223 dev_err(emu->card->dev, "i2c_write: invalid values.\n"); 224 return -EINVAL; 225 } 226 227 /* This function is not re-entrant, so protect against it. */ 228 spin_lock(&emu->i2c_lock); 229 230 tmp = reg << 25 | value << 16; 231 232 /* This controls the I2C connected to the WM8775 ADC Codec */ 233 snd_emu10k1_ptr20_write(emu, P17V_I2C_1, 0, tmp); 234 tmp = snd_emu10k1_ptr20_read(emu, P17V_I2C_1, 0); /* write post */ 235 236 for (retry = 0; retry < 10; retry++) { 237 /* Send the data to i2c */ 238 tmp = 0; 239 tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD); 240 snd_emu10k1_ptr20_write(emu, P17V_I2C_ADDR, 0, tmp); 241 242 /* Wait till the transaction ends */ 243 while (1) { 244 mdelay(1); 245 status = snd_emu10k1_ptr20_read(emu, P17V_I2C_ADDR, 0); 246 timeout++; 247 if ((status & I2C_A_ADC_START) == 0) 248 break; 249 250 if (timeout > 1000) { 251 dev_warn(emu->card->dev, 252 "emu10k1:I2C:timeout status=0x%x\n", 253 status); 254 break; 255 } 256 } 257 //Read back and see if the transaction is successful 258 if ((status & I2C_A_ADC_ABORT) == 0) 259 break; 260 } 261 262 if (retry == 10) { 263 dev_err(emu->card->dev, "Writing to ADC failed!\n"); 264 dev_err(emu->card->dev, "status=0x%x, reg=%d, value=%d\n", 265 status, reg, value); 266 /* dump_stack(); */ 267 err = -EINVAL; 268 } 269 270 spin_unlock(&emu->i2c_lock); 271 return err; 272 } 273 274 static void snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value) 275 { 276 if (snd_BUG_ON(reg > 0x3f)) 277 return; 278 reg += 0x40; /* 0x40 upwards are registers. */ 279 if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */ 280 return; 281 outw(reg, emu->port + A_GPIO); 282 udelay(10); 283 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 284 udelay(10); 285 outw(value, emu->port + A_GPIO); 286 udelay(10); 287 outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 288 udelay(10); 289 } 290 291 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value) 292 { 293 unsigned long flags; 294 295 spin_lock_irqsave(&emu->emu_lock, flags); 296 snd_emu1010_fpga_write_locked(emu, reg, value); 297 spin_unlock_irqrestore(&emu->emu_lock, flags); 298 } 299 300 static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value) 301 { 302 // The higest input pin is used as the designated interrupt trigger, 303 // so it needs to be masked out. 304 // But note that any other input pin change will also cause an IRQ, 305 // so using this function often causes an IRQ as a side effect. 306 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f; 307 if (snd_BUG_ON(reg > 0x3f)) 308 return; 309 reg += 0x40; /* 0x40 upwards are registers. */ 310 outw(reg, emu->port + A_GPIO); 311 udelay(10); 312 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 313 udelay(10); 314 *value = ((inw(emu->port + A_GPIO) >> 8) & mask); 315 } 316 317 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value) 318 { 319 unsigned long flags; 320 321 spin_lock_irqsave(&emu->emu_lock, flags); 322 snd_emu1010_fpga_read_locked(emu, reg, value); 323 spin_unlock_irqrestore(&emu->emu_lock, flags); 324 } 325 326 /* Each Destination has one and only one Source, 327 * but one Source can feed any number of Destinations simultaneously. 328 */ 329 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src) 330 { 331 unsigned long flags; 332 333 if (snd_BUG_ON(dst & ~0x71f)) 334 return; 335 if (snd_BUG_ON(src & ~0x71f)) 336 return; 337 spin_lock_irqsave(&emu->emu_lock, flags); 338 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 339 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 340 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8); 341 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f); 342 spin_unlock_irqrestore(&emu->emu_lock, flags); 343 } 344 345 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst) 346 { 347 unsigned long flags; 348 u32 hi, lo; 349 350 if (snd_BUG_ON(dst & ~0x71f)) 351 return 0; 352 spin_lock_irqsave(&emu->emu_lock, flags); 353 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 354 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 355 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi); 356 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo); 357 spin_unlock_irqrestore(&emu->emu_lock, flags); 358 return (hi << 8) | lo; 359 } 360 361 int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src) 362 { 363 u32 reg_lo, reg_hi, value, value2; 364 365 switch (src) { 366 case EMU_HANA_WCLOCK_HANA_SPDIF_IN: 367 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &value); 368 if (value & EMU_HANA_SPDIF_MODE_RX_INVALID) 369 return 0; 370 reg_lo = EMU_HANA_WC_SPDIF_LO; 371 reg_hi = EMU_HANA_WC_SPDIF_HI; 372 break; 373 case EMU_HANA_WCLOCK_HANA_ADAT_IN: 374 reg_lo = EMU_HANA_WC_ADAT_LO; 375 reg_hi = EMU_HANA_WC_ADAT_HI; 376 break; 377 case EMU_HANA_WCLOCK_SYNC_BNC: 378 reg_lo = EMU_HANA_WC_BNC_LO; 379 reg_hi = EMU_HANA_WC_BNC_HI; 380 break; 381 case EMU_HANA_WCLOCK_2ND_HANA: 382 reg_lo = EMU_HANA2_WC_SPDIF_LO; 383 reg_hi = EMU_HANA2_WC_SPDIF_HI; 384 break; 385 default: 386 return 0; 387 } 388 snd_emu1010_fpga_read(emu, reg_hi, &value); 389 snd_emu1010_fpga_read(emu, reg_lo, &value2); 390 // FIXME: The /4 is valid for 0404b, but contradicts all other info. 391 return 0x1770000 / 4 / (((value << 5) | value2) + 1); 392 } 393 394 void snd_emu1010_update_clock(struct snd_emu10k1 *emu) 395 { 396 int clock; 397 u32 leds; 398 399 switch (emu->emu1010.wclock) { 400 case EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X: 401 clock = 44100; 402 leds = EMU_HANA_DOCK_LEDS_2_44K; 403 break; 404 case EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X: 405 clock = 48000; 406 leds = EMU_HANA_DOCK_LEDS_2_48K; 407 break; 408 default: 409 clock = snd_emu1010_get_raw_rate( 410 emu, emu->emu1010.wclock & EMU_HANA_WCLOCK_SRC_MASK); 411 // The raw rate reading is rather coarse (it cannot accurately 412 // represent 44.1 kHz) and fluctuates slightly. Luckily, the 413 // clock comes from digital inputs, which use standardized rates. 414 // So we round to the closest standard rate and ignore discrepancies. 415 if (clock < 46000) { 416 clock = 44100; 417 leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_44K; 418 } else { 419 clock = 48000; 420 leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_48K; 421 } 422 break; 423 } 424 emu->emu1010.word_clock = clock; 425 426 // FIXME: this should probably represent the AND of all currently 427 // used sources' lock status. But we don't know how to get that ... 428 leds |= EMU_HANA_DOCK_LEDS_2_LOCK; 429 430 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, leds); 431 } 432 433 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb) 434 { 435 unsigned long flags; 436 unsigned int enable; 437 438 spin_lock_irqsave(&emu->emu_lock, flags); 439 enable = inl(emu->port + INTE) | intrenb; 440 outl(enable, emu->port + INTE); 441 spin_unlock_irqrestore(&emu->emu_lock, flags); 442 } 443 444 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb) 445 { 446 unsigned long flags; 447 unsigned int enable; 448 449 spin_lock_irqsave(&emu->emu_lock, flags); 450 enable = inl(emu->port + INTE) & ~intrenb; 451 outl(enable, emu->port + INTE); 452 spin_unlock_irqrestore(&emu->emu_lock, flags); 453 } 454 455 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum) 456 { 457 unsigned long flags; 458 unsigned int val; 459 460 spin_lock_irqsave(&emu->emu_lock, flags); 461 if (voicenum >= 32) { 462 outl(CLIEH << 16, emu->port + PTR); 463 val = inl(emu->port + DATA); 464 val |= 1 << (voicenum - 32); 465 } else { 466 outl(CLIEL << 16, emu->port + PTR); 467 val = inl(emu->port + DATA); 468 val |= 1 << voicenum; 469 } 470 outl(val, emu->port + DATA); 471 spin_unlock_irqrestore(&emu->emu_lock, flags); 472 } 473 474 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum) 475 { 476 unsigned long flags; 477 unsigned int val; 478 479 spin_lock_irqsave(&emu->emu_lock, flags); 480 if (voicenum >= 32) { 481 outl(CLIEH << 16, emu->port + PTR); 482 val = inl(emu->port + DATA); 483 val &= ~(1 << (voicenum - 32)); 484 } else { 485 outl(CLIEL << 16, emu->port + PTR); 486 val = inl(emu->port + DATA); 487 val &= ~(1 << voicenum); 488 } 489 outl(val, emu->port + DATA); 490 spin_unlock_irqrestore(&emu->emu_lock, flags); 491 } 492 493 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum) 494 { 495 unsigned long flags; 496 497 spin_lock_irqsave(&emu->emu_lock, flags); 498 if (voicenum >= 32) { 499 outl(CLIPH << 16, emu->port + PTR); 500 voicenum = 1 << (voicenum - 32); 501 } else { 502 outl(CLIPL << 16, emu->port + PTR); 503 voicenum = 1 << voicenum; 504 } 505 outl(voicenum, emu->port + DATA); 506 spin_unlock_irqrestore(&emu->emu_lock, flags); 507 } 508 509 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum) 510 { 511 unsigned long flags; 512 unsigned int val; 513 514 spin_lock_irqsave(&emu->emu_lock, flags); 515 if (voicenum >= 32) { 516 outl(HLIEH << 16, emu->port + PTR); 517 val = inl(emu->port + DATA); 518 val |= 1 << (voicenum - 32); 519 } else { 520 outl(HLIEL << 16, emu->port + PTR); 521 val = inl(emu->port + DATA); 522 val |= 1 << voicenum; 523 } 524 outl(val, emu->port + DATA); 525 spin_unlock_irqrestore(&emu->emu_lock, flags); 526 } 527 528 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum) 529 { 530 unsigned long flags; 531 unsigned int val; 532 533 spin_lock_irqsave(&emu->emu_lock, flags); 534 if (voicenum >= 32) { 535 outl(HLIEH << 16, emu->port + PTR); 536 val = inl(emu->port + DATA); 537 val &= ~(1 << (voicenum - 32)); 538 } else { 539 outl(HLIEL << 16, emu->port + PTR); 540 val = inl(emu->port + DATA); 541 val &= ~(1 << voicenum); 542 } 543 outl(val, emu->port + DATA); 544 spin_unlock_irqrestore(&emu->emu_lock, flags); 545 } 546 547 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum) 548 { 549 unsigned long flags; 550 551 spin_lock_irqsave(&emu->emu_lock, flags); 552 if (voicenum >= 32) { 553 outl(HLIPH << 16, emu->port + PTR); 554 voicenum = 1 << (voicenum - 32); 555 } else { 556 outl(HLIPL << 16, emu->port + PTR); 557 voicenum = 1 << voicenum; 558 } 559 outl(voicenum, emu->port + DATA); 560 spin_unlock_irqrestore(&emu->emu_lock, flags); 561 } 562 563 #if 0 564 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum) 565 { 566 unsigned long flags; 567 unsigned int sol; 568 569 spin_lock_irqsave(&emu->emu_lock, flags); 570 if (voicenum >= 32) { 571 outl(SOLEH << 16, emu->port + PTR); 572 sol = inl(emu->port + DATA); 573 sol |= 1 << (voicenum - 32); 574 } else { 575 outl(SOLEL << 16, emu->port + PTR); 576 sol = inl(emu->port + DATA); 577 sol |= 1 << voicenum; 578 } 579 outl(sol, emu->port + DATA); 580 spin_unlock_irqrestore(&emu->emu_lock, flags); 581 } 582 583 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum) 584 { 585 unsigned long flags; 586 unsigned int sol; 587 588 spin_lock_irqsave(&emu->emu_lock, flags); 589 if (voicenum >= 32) { 590 outl(SOLEH << 16, emu->port + PTR); 591 sol = inl(emu->port + DATA); 592 sol &= ~(1 << (voicenum - 32)); 593 } else { 594 outl(SOLEL << 16, emu->port + PTR); 595 sol = inl(emu->port + DATA); 596 sol &= ~(1 << voicenum); 597 } 598 outl(sol, emu->port + DATA); 599 spin_unlock_irqrestore(&emu->emu_lock, flags); 600 } 601 #endif 602 603 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices) 604 { 605 unsigned long flags; 606 607 spin_lock_irqsave(&emu->emu_lock, flags); 608 outl(SOLEL << 16, emu->port + PTR); 609 outl(inl(emu->port + DATA) | (u32)voices, emu->port + DATA); 610 outl(SOLEH << 16, emu->port + PTR); 611 outl(inl(emu->port + DATA) | (u32)(voices >> 32), emu->port + DATA); 612 spin_unlock_irqrestore(&emu->emu_lock, flags); 613 } 614 615 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices) 616 { 617 unsigned long flags; 618 619 spin_lock_irqsave(&emu->emu_lock, flags); 620 outl(SOLEL << 16, emu->port + PTR); 621 outl(inl(emu->port + DATA) & (u32)~voices, emu->port + DATA); 622 outl(SOLEH << 16, emu->port + PTR); 623 outl(inl(emu->port + DATA) & (u32)(~voices >> 32), emu->port + DATA); 624 spin_unlock_irqrestore(&emu->emu_lock, flags); 625 } 626 627 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices) 628 { 629 unsigned long flags; 630 u32 soll, solh; 631 int ret = -EIO; 632 633 spin_lock_irqsave(&emu->emu_lock, flags); 634 635 outl(SOLEL << 16, emu->port + PTR); 636 soll = inl(emu->port + DATA); 637 outl(SOLEH << 16, emu->port + PTR); 638 solh = inl(emu->port + DATA); 639 640 soll &= (u32)~voices; 641 solh &= (u32)(~voices >> 32); 642 643 for (int tries = 0; tries < 1000; tries++) { 644 const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2); 645 // First we wait for the third quarter of the sample cycle ... 646 u32 wc = inl(emu->port + WC); 647 u32 cc = REG_VAL_GET(WC_CURRENTCHANNEL, wc); 648 if (cc >= quart * 2 && cc < quart * 3) { 649 // ... and release the low voices, while the high ones are serviced. 650 outl(SOLEL << 16, emu->port + PTR); 651 outl(soll, emu->port + DATA); 652 // Then we wait for the first quarter of the next sample cycle ... 653 for (; tries < 1000; tries++) { 654 cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC)); 655 if (cc < quart) 656 goto good; 657 // We will block for 10+ us with interrupts disabled. This is 658 // not nice at all, but necessary for reasonable reliability. 659 udelay(1); 660 } 661 break; 662 good: 663 // ... and release the high voices, while the low ones are serviced. 664 outl(SOLEH << 16, emu->port + PTR); 665 outl(solh, emu->port + DATA); 666 // Finally we verify that nothing interfered in fact. 667 if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) == 668 ((REG_VAL_GET(WC_SAMPLECOUNTER, wc) + 1) & REG_MASK0(WC_SAMPLECOUNTER))) { 669 ret = 0; 670 } else { 671 ret = -EAGAIN; 672 } 673 break; 674 } 675 // Don't block for too long 676 spin_unlock_irqrestore(&emu->emu_lock, flags); 677 udelay(1); 678 spin_lock_irqsave(&emu->emu_lock, flags); 679 } 680 681 spin_unlock_irqrestore(&emu->emu_lock, flags); 682 return ret; 683 } 684 685 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait) 686 { 687 volatile unsigned count; 688 unsigned int newtime = 0, curtime; 689 690 curtime = inl(emu->port + WC) >> 6; 691 while (wait-- > 0) { 692 count = 0; 693 while (count++ < 16384) { 694 newtime = inl(emu->port + WC) >> 6; 695 if (newtime != curtime) 696 break; 697 } 698 if (count > 16384) 699 break; 700 curtime = newtime; 701 } 702 } 703 704 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 705 { 706 struct snd_emu10k1 *emu = ac97->private_data; 707 unsigned long flags; 708 unsigned short val; 709 710 spin_lock_irqsave(&emu->emu_lock, flags); 711 outb(reg, emu->port + AC97ADDRESS); 712 val = inw(emu->port + AC97DATA); 713 spin_unlock_irqrestore(&emu->emu_lock, flags); 714 return val; 715 } 716 717 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data) 718 { 719 struct snd_emu10k1 *emu = ac97->private_data; 720 unsigned long flags; 721 722 spin_lock_irqsave(&emu->emu_lock, flags); 723 outb(reg, emu->port + AC97ADDRESS); 724 outw(data, emu->port + AC97DATA); 725 spin_unlock_irqrestore(&emu->emu_lock, flags); 726 } 727