1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for control of EMU10K1 chips 6 * 7 * BUGS: 8 * -- 9 * 10 * TODO: 11 * -- 12 */ 13 14 #include <linux/time.h> 15 #include <sound/core.h> 16 #include <sound/emu10k1.h> 17 #include <linux/delay.h> 18 #include <linux/export.h> 19 #include "p17v.h" 20 21 static inline bool check_ptr_reg(struct snd_emu10k1 *emu, unsigned int reg) 22 { 23 if (snd_BUG_ON(!emu)) 24 return false; 25 if (snd_BUG_ON(reg & (emu->audigy ? (0xffff0000 & ~A_PTR_ADDRESS_MASK) 26 : (0xffff0000 & ~PTR_ADDRESS_MASK)))) 27 return false; 28 if (snd_BUG_ON(reg & 0x0000ffff & ~PTR_CHANNELNUM_MASK)) 29 return false; 30 return true; 31 } 32 33 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn) 34 { 35 unsigned long flags; 36 unsigned int regptr, val; 37 unsigned int mask; 38 39 regptr = (reg << 16) | chn; 40 if (!check_ptr_reg(emu, regptr)) 41 return 0; 42 43 spin_lock_irqsave(&emu->emu_lock, flags); 44 outl(regptr, emu->port + PTR); 45 val = inl(emu->port + DATA); 46 spin_unlock_irqrestore(&emu->emu_lock, flags); 47 48 if (reg & 0xff000000) { 49 unsigned char size, offset; 50 51 size = (reg >> 24) & 0x3f; 52 offset = (reg >> 16) & 0x1f; 53 mask = (1 << size) - 1; 54 55 return (val >> offset) & mask; 56 } else { 57 return val; 58 } 59 } 60 61 EXPORT_SYMBOL(snd_emu10k1_ptr_read); 62 63 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data) 64 { 65 unsigned int regptr; 66 unsigned long flags; 67 unsigned int mask; 68 69 regptr = (reg << 16) | chn; 70 if (!check_ptr_reg(emu, regptr)) 71 return; 72 73 if (reg & 0xff000000) { 74 unsigned char size, offset; 75 76 size = (reg >> 24) & 0x3f; 77 offset = (reg >> 16) & 0x1f; 78 mask = (1 << size) - 1; 79 if (snd_BUG_ON(data & ~mask)) 80 return; 81 mask <<= offset; 82 data <<= offset; 83 84 spin_lock_irqsave(&emu->emu_lock, flags); 85 outl(regptr, emu->port + PTR); 86 data |= inl(emu->port + DATA) & ~mask; 87 } else { 88 spin_lock_irqsave(&emu->emu_lock, flags); 89 outl(regptr, emu->port + PTR); 90 } 91 outl(data, emu->port + DATA); 92 spin_unlock_irqrestore(&emu->emu_lock, flags); 93 } 94 95 EXPORT_SYMBOL(snd_emu10k1_ptr_write); 96 97 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...) 98 { 99 va_list va; 100 u32 addr_mask; 101 unsigned long flags; 102 103 if (snd_BUG_ON(!emu)) 104 return; 105 if (snd_BUG_ON(chn & ~PTR_CHANNELNUM_MASK)) 106 return; 107 addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16); 108 109 va_start(va, chn); 110 spin_lock_irqsave(&emu->emu_lock, flags); 111 for (;;) { 112 u32 data; 113 u32 reg = va_arg(va, u32); 114 if (reg == REGLIST_END) 115 break; 116 data = va_arg(va, u32); 117 if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here 118 continue; 119 outl((reg << 16) | chn, emu->port + PTR); 120 outl(data, emu->port + DATA); 121 } 122 spin_unlock_irqrestore(&emu->emu_lock, flags); 123 va_end(va); 124 } 125 126 EXPORT_SYMBOL(snd_emu10k1_ptr_write_multiple); 127 128 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, 129 unsigned int reg, 130 unsigned int chn) 131 { 132 unsigned long flags; 133 unsigned int regptr, val; 134 135 regptr = (reg << 16) | chn; 136 137 spin_lock_irqsave(&emu->emu_lock, flags); 138 outl(regptr, emu->port + PTR2); 139 val = inl(emu->port + DATA2); 140 spin_unlock_irqrestore(&emu->emu_lock, flags); 141 return val; 142 } 143 144 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, 145 unsigned int reg, 146 unsigned int chn, 147 unsigned int data) 148 { 149 unsigned int regptr; 150 unsigned long flags; 151 152 regptr = (reg << 16) | chn; 153 154 spin_lock_irqsave(&emu->emu_lock, flags); 155 outl(regptr, emu->port + PTR2); 156 outl(data, emu->port + DATA2); 157 spin_unlock_irqrestore(&emu->emu_lock, flags); 158 } 159 160 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, 161 unsigned int data) 162 { 163 unsigned int reset, set; 164 unsigned int reg, tmp; 165 int n, result; 166 int err = 0; 167 168 /* This function is not re-entrant, so protect against it. */ 169 spin_lock(&emu->spi_lock); 170 if (emu->card_capabilities->ca0108_chip) 171 reg = P17V_SPI; 172 else { 173 /* For other chip types the SPI register 174 * is currently unknown. */ 175 err = 1; 176 goto spi_write_exit; 177 } 178 if (data > 0xffff) { 179 /* Only 16bit values allowed */ 180 err = 1; 181 goto spi_write_exit; 182 } 183 184 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); 185 reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */ 186 set = reset | 0x10000; /* Set xxx1xxxx */ 187 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data); 188 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */ 189 snd_emu10k1_ptr20_write(emu, reg, 0, set | data); 190 result = 1; 191 /* Wait for status bit to return to 0 */ 192 for (n = 0; n < 100; n++) { 193 udelay(10); 194 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); 195 if (!(tmp & 0x10000)) { 196 result = 0; 197 break; 198 } 199 } 200 if (result) { 201 /* Timed out */ 202 err = 1; 203 goto spi_write_exit; 204 } 205 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data); 206 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */ 207 err = 0; 208 spi_write_exit: 209 spin_unlock(&emu->spi_lock); 210 return err; 211 } 212 213 /* The ADC does not support i2c read, so only write is implemented */ 214 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, 215 u32 reg, 216 u32 value) 217 { 218 u32 tmp; 219 int timeout = 0; 220 int status; 221 int retry; 222 int err = 0; 223 224 if ((reg > 0x7f) || (value > 0x1ff)) { 225 dev_err(emu->card->dev, "i2c_write: invalid values.\n"); 226 return -EINVAL; 227 } 228 229 /* This function is not re-entrant, so protect against it. */ 230 spin_lock(&emu->i2c_lock); 231 232 tmp = reg << 25 | value << 16; 233 234 /* This controls the I2C connected to the WM8775 ADC Codec */ 235 snd_emu10k1_ptr20_write(emu, P17V_I2C_1, 0, tmp); 236 tmp = snd_emu10k1_ptr20_read(emu, P17V_I2C_1, 0); /* write post */ 237 238 for (retry = 0; retry < 10; retry++) { 239 /* Send the data to i2c */ 240 tmp = 0; 241 tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD); 242 snd_emu10k1_ptr20_write(emu, P17V_I2C_ADDR, 0, tmp); 243 244 /* Wait till the transaction ends */ 245 while (1) { 246 mdelay(1); 247 status = snd_emu10k1_ptr20_read(emu, P17V_I2C_ADDR, 0); 248 timeout++; 249 if ((status & I2C_A_ADC_START) == 0) 250 break; 251 252 if (timeout > 1000) { 253 dev_warn(emu->card->dev, 254 "emu10k1:I2C:timeout status=0x%x\n", 255 status); 256 break; 257 } 258 } 259 //Read back and see if the transaction is successful 260 if ((status & I2C_A_ADC_ABORT) == 0) 261 break; 262 } 263 264 if (retry == 10) { 265 dev_err(emu->card->dev, "Writing to ADC failed!\n"); 266 dev_err(emu->card->dev, "status=0x%x, reg=%d, value=%d\n", 267 status, reg, value); 268 /* dump_stack(); */ 269 err = -EINVAL; 270 } 271 272 spin_unlock(&emu->i2c_lock); 273 return err; 274 } 275 276 static void snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value) 277 { 278 if (snd_BUG_ON(reg > 0x3f)) 279 return; 280 reg += 0x40; /* 0x40 upwards are registers. */ 281 if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */ 282 return; 283 outw(reg, emu->port + A_GPIO); 284 udelay(10); 285 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 286 udelay(10); 287 outw(value, emu->port + A_GPIO); 288 udelay(10); 289 outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 290 } 291 292 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value) 293 { 294 unsigned long flags; 295 296 spin_lock_irqsave(&emu->emu_lock, flags); 297 snd_emu1010_fpga_write_locked(emu, reg, value); 298 spin_unlock_irqrestore(&emu->emu_lock, flags); 299 } 300 301 static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value) 302 { 303 // The higest input pin is used as the designated interrupt trigger, 304 // so it needs to be masked out. 305 // But note that any other input pin change will also cause an IRQ, 306 // so using this function often causes an IRQ as a side effect. 307 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f; 308 if (snd_BUG_ON(reg > 0x3f)) 309 return; 310 reg += 0x40; /* 0x40 upwards are registers. */ 311 outw(reg, emu->port + A_GPIO); 312 udelay(10); 313 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 314 udelay(10); 315 *value = ((inw(emu->port + A_GPIO) >> 8) & mask); 316 } 317 318 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value) 319 { 320 unsigned long flags; 321 322 spin_lock_irqsave(&emu->emu_lock, flags); 323 snd_emu1010_fpga_read_locked(emu, reg, value); 324 spin_unlock_irqrestore(&emu->emu_lock, flags); 325 } 326 327 /* Each Destination has one and only one Source, 328 * but one Source can feed any number of Destinations simultaneously. 329 */ 330 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src) 331 { 332 unsigned long flags; 333 334 if (snd_BUG_ON(dst & ~0x71f)) 335 return; 336 if (snd_BUG_ON(src & ~0x71f)) 337 return; 338 spin_lock_irqsave(&emu->emu_lock, flags); 339 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 340 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 341 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8); 342 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f); 343 spin_unlock_irqrestore(&emu->emu_lock, flags); 344 } 345 346 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst) 347 { 348 unsigned long flags; 349 u32 hi, lo; 350 351 if (snd_BUG_ON(dst & ~0x71f)) 352 return 0; 353 spin_lock_irqsave(&emu->emu_lock, flags); 354 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 355 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 356 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi); 357 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo); 358 spin_unlock_irqrestore(&emu->emu_lock, flags); 359 return (hi << 8) | lo; 360 } 361 362 int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src) 363 { 364 u32 reg_lo, reg_hi, value, value2; 365 366 switch (src) { 367 case EMU_HANA_WCLOCK_HANA_SPDIF_IN: 368 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &value); 369 if (value & EMU_HANA_SPDIF_MODE_RX_INVALID) 370 return 0; 371 reg_lo = EMU_HANA_WC_SPDIF_LO; 372 reg_hi = EMU_HANA_WC_SPDIF_HI; 373 break; 374 case EMU_HANA_WCLOCK_HANA_ADAT_IN: 375 reg_lo = EMU_HANA_WC_ADAT_LO; 376 reg_hi = EMU_HANA_WC_ADAT_HI; 377 break; 378 case EMU_HANA_WCLOCK_SYNC_BNC: 379 reg_lo = EMU_HANA_WC_BNC_LO; 380 reg_hi = EMU_HANA_WC_BNC_HI; 381 break; 382 case EMU_HANA_WCLOCK_2ND_HANA: 383 reg_lo = EMU_HANA2_WC_SPDIF_LO; 384 reg_hi = EMU_HANA2_WC_SPDIF_HI; 385 break; 386 default: 387 return 0; 388 } 389 snd_emu1010_fpga_read(emu, reg_hi, &value); 390 snd_emu1010_fpga_read(emu, reg_lo, &value2); 391 // FIXME: The /4 is valid for 0404b, but contradicts all other info. 392 return 0x1770000 / 4 / (((value << 5) | value2) + 1); 393 } 394 395 void snd_emu1010_update_clock(struct snd_emu10k1 *emu) 396 { 397 int clock; 398 u32 leds; 399 400 switch (emu->emu1010.wclock) { 401 case EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X: 402 clock = 44100; 403 leds = EMU_HANA_DOCK_LEDS_2_44K; 404 break; 405 case EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X: 406 clock = 48000; 407 leds = EMU_HANA_DOCK_LEDS_2_48K; 408 break; 409 default: 410 clock = snd_emu1010_get_raw_rate( 411 emu, emu->emu1010.wclock & EMU_HANA_WCLOCK_SRC_MASK); 412 // The raw rate reading is rather coarse (it cannot accurately 413 // represent 44.1 kHz) and fluctuates slightly. Luckily, the 414 // clock comes from digital inputs, which use standardized rates. 415 // So we round to the closest standard rate and ignore discrepancies. 416 if (clock < 46000) { 417 clock = 44100; 418 leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_44K; 419 } else { 420 clock = 48000; 421 leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_48K; 422 } 423 break; 424 } 425 emu->emu1010.word_clock = clock; 426 427 // FIXME: this should probably represent the AND of all currently 428 // used sources' lock status. But we don't know how to get that ... 429 leds |= EMU_HANA_DOCK_LEDS_2_LOCK; 430 431 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, leds); 432 } 433 434 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb) 435 { 436 unsigned long flags; 437 unsigned int enable; 438 439 spin_lock_irqsave(&emu->emu_lock, flags); 440 enable = inl(emu->port + INTE) | intrenb; 441 outl(enable, emu->port + INTE); 442 spin_unlock_irqrestore(&emu->emu_lock, flags); 443 } 444 445 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb) 446 { 447 unsigned long flags; 448 unsigned int enable; 449 450 spin_lock_irqsave(&emu->emu_lock, flags); 451 enable = inl(emu->port + INTE) & ~intrenb; 452 outl(enable, emu->port + INTE); 453 spin_unlock_irqrestore(&emu->emu_lock, flags); 454 } 455 456 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum) 457 { 458 unsigned long flags; 459 unsigned int val; 460 461 spin_lock_irqsave(&emu->emu_lock, flags); 462 if (voicenum >= 32) { 463 outl(CLIEH << 16, emu->port + PTR); 464 val = inl(emu->port + DATA); 465 val |= 1 << (voicenum - 32); 466 } else { 467 outl(CLIEL << 16, emu->port + PTR); 468 val = inl(emu->port + DATA); 469 val |= 1 << voicenum; 470 } 471 outl(val, emu->port + DATA); 472 spin_unlock_irqrestore(&emu->emu_lock, flags); 473 } 474 475 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum) 476 { 477 unsigned long flags; 478 unsigned int val; 479 480 spin_lock_irqsave(&emu->emu_lock, flags); 481 if (voicenum >= 32) { 482 outl(CLIEH << 16, emu->port + PTR); 483 val = inl(emu->port + DATA); 484 val &= ~(1 << (voicenum - 32)); 485 } else { 486 outl(CLIEL << 16, emu->port + PTR); 487 val = inl(emu->port + DATA); 488 val &= ~(1 << voicenum); 489 } 490 outl(val, emu->port + DATA); 491 spin_unlock_irqrestore(&emu->emu_lock, flags); 492 } 493 494 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum) 495 { 496 unsigned long flags; 497 498 spin_lock_irqsave(&emu->emu_lock, flags); 499 if (voicenum >= 32) { 500 outl(CLIPH << 16, emu->port + PTR); 501 voicenum = 1 << (voicenum - 32); 502 } else { 503 outl(CLIPL << 16, emu->port + PTR); 504 voicenum = 1 << voicenum; 505 } 506 outl(voicenum, emu->port + DATA); 507 spin_unlock_irqrestore(&emu->emu_lock, flags); 508 } 509 510 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum) 511 { 512 unsigned long flags; 513 unsigned int val; 514 515 spin_lock_irqsave(&emu->emu_lock, flags); 516 if (voicenum >= 32) { 517 outl(HLIEH << 16, emu->port + PTR); 518 val = inl(emu->port + DATA); 519 val |= 1 << (voicenum - 32); 520 } else { 521 outl(HLIEL << 16, emu->port + PTR); 522 val = inl(emu->port + DATA); 523 val |= 1 << voicenum; 524 } 525 outl(val, emu->port + DATA); 526 spin_unlock_irqrestore(&emu->emu_lock, flags); 527 } 528 529 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum) 530 { 531 unsigned long flags; 532 unsigned int val; 533 534 spin_lock_irqsave(&emu->emu_lock, flags); 535 if (voicenum >= 32) { 536 outl(HLIEH << 16, emu->port + PTR); 537 val = inl(emu->port + DATA); 538 val &= ~(1 << (voicenum - 32)); 539 } else { 540 outl(HLIEL << 16, emu->port + PTR); 541 val = inl(emu->port + DATA); 542 val &= ~(1 << voicenum); 543 } 544 outl(val, emu->port + DATA); 545 spin_unlock_irqrestore(&emu->emu_lock, flags); 546 } 547 548 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum) 549 { 550 unsigned long flags; 551 552 spin_lock_irqsave(&emu->emu_lock, flags); 553 if (voicenum >= 32) { 554 outl(HLIPH << 16, emu->port + PTR); 555 voicenum = 1 << (voicenum - 32); 556 } else { 557 outl(HLIPL << 16, emu->port + PTR); 558 voicenum = 1 << voicenum; 559 } 560 outl(voicenum, emu->port + DATA); 561 spin_unlock_irqrestore(&emu->emu_lock, flags); 562 } 563 564 #if 0 565 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum) 566 { 567 unsigned long flags; 568 unsigned int sol; 569 570 spin_lock_irqsave(&emu->emu_lock, flags); 571 if (voicenum >= 32) { 572 outl(SOLEH << 16, emu->port + PTR); 573 sol = inl(emu->port + DATA); 574 sol |= 1 << (voicenum - 32); 575 } else { 576 outl(SOLEL << 16, emu->port + PTR); 577 sol = inl(emu->port + DATA); 578 sol |= 1 << voicenum; 579 } 580 outl(sol, emu->port + DATA); 581 spin_unlock_irqrestore(&emu->emu_lock, flags); 582 } 583 584 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum) 585 { 586 unsigned long flags; 587 unsigned int sol; 588 589 spin_lock_irqsave(&emu->emu_lock, flags); 590 if (voicenum >= 32) { 591 outl(SOLEH << 16, emu->port + PTR); 592 sol = inl(emu->port + DATA); 593 sol &= ~(1 << (voicenum - 32)); 594 } else { 595 outl(SOLEL << 16, emu->port + PTR); 596 sol = inl(emu->port + DATA); 597 sol &= ~(1 << voicenum); 598 } 599 outl(sol, emu->port + DATA); 600 spin_unlock_irqrestore(&emu->emu_lock, flags); 601 } 602 #endif 603 604 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices) 605 { 606 unsigned long flags; 607 608 spin_lock_irqsave(&emu->emu_lock, flags); 609 outl(SOLEL << 16, emu->port + PTR); 610 outl(inl(emu->port + DATA) | (u32)voices, emu->port + DATA); 611 outl(SOLEH << 16, emu->port + PTR); 612 outl(inl(emu->port + DATA) | (u32)(voices >> 32), emu->port + DATA); 613 spin_unlock_irqrestore(&emu->emu_lock, flags); 614 } 615 616 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices) 617 { 618 unsigned long flags; 619 620 spin_lock_irqsave(&emu->emu_lock, flags); 621 outl(SOLEL << 16, emu->port + PTR); 622 outl(inl(emu->port + DATA) & (u32)~voices, emu->port + DATA); 623 outl(SOLEH << 16, emu->port + PTR); 624 outl(inl(emu->port + DATA) & (u32)(~voices >> 32), emu->port + DATA); 625 spin_unlock_irqrestore(&emu->emu_lock, flags); 626 } 627 628 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices) 629 { 630 unsigned long flags; 631 u32 soll, solh; 632 int ret = -EIO; 633 634 spin_lock_irqsave(&emu->emu_lock, flags); 635 636 outl(SOLEL << 16, emu->port + PTR); 637 soll = inl(emu->port + DATA); 638 outl(SOLEH << 16, emu->port + PTR); 639 solh = inl(emu->port + DATA); 640 641 soll &= (u32)~voices; 642 solh &= (u32)(~voices >> 32); 643 644 for (int tries = 0; tries < 1000; tries++) { 645 const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2); 646 // First we wait for the third quarter of the sample cycle ... 647 u32 wc = inl(emu->port + WC); 648 u32 cc = REG_VAL_GET(WC_CURRENTCHANNEL, wc); 649 if (cc >= quart * 2 && cc < quart * 3) { 650 // ... and release the low voices, while the high ones are serviced. 651 outl(SOLEL << 16, emu->port + PTR); 652 outl(soll, emu->port + DATA); 653 // Then we wait for the first quarter of the next sample cycle ... 654 for (; tries < 1000; tries++) { 655 cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC)); 656 if (cc < quart) 657 goto good; 658 // We will block for 10+ us with interrupts disabled. This is 659 // not nice at all, but necessary for reasonable reliability. 660 udelay(1); 661 } 662 break; 663 good: 664 // ... and release the high voices, while the low ones are serviced. 665 outl(SOLEH << 16, emu->port + PTR); 666 outl(solh, emu->port + DATA); 667 // Finally we verify that nothing interfered in fact. 668 if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) == 669 ((REG_VAL_GET(WC_SAMPLECOUNTER, wc) + 1) & REG_MASK0(WC_SAMPLECOUNTER))) { 670 ret = 0; 671 } else { 672 ret = -EAGAIN; 673 } 674 break; 675 } 676 // Don't block for too long 677 spin_unlock_irqrestore(&emu->emu_lock, flags); 678 udelay(1); 679 spin_lock_irqsave(&emu->emu_lock, flags); 680 } 681 682 spin_unlock_irqrestore(&emu->emu_lock, flags); 683 return ret; 684 } 685 686 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait) 687 { 688 volatile unsigned count; 689 unsigned int newtime = 0, curtime; 690 691 curtime = inl(emu->port + WC) >> 6; 692 while (wait-- > 0) { 693 count = 0; 694 while (count++ < 16384) { 695 newtime = inl(emu->port + WC) >> 6; 696 if (newtime != curtime) 697 break; 698 } 699 if (count > 16384) 700 break; 701 curtime = newtime; 702 } 703 } 704 705 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 706 { 707 struct snd_emu10k1 *emu = ac97->private_data; 708 unsigned long flags; 709 unsigned short val; 710 711 spin_lock_irqsave(&emu->emu_lock, flags); 712 outb(reg, emu->port + AC97ADDRESS); 713 val = inw(emu->port + AC97DATA); 714 spin_unlock_irqrestore(&emu->emu_lock, flags); 715 return val; 716 } 717 718 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data) 719 { 720 struct snd_emu10k1 *emu = ac97->private_data; 721 unsigned long flags; 722 723 spin_lock_irqsave(&emu->emu_lock, flags); 724 outb(reg, emu->port + AC97ADDRESS); 725 outw(data, emu->port + AC97DATA); 726 spin_unlock_irqrestore(&emu->emu_lock, flags); 727 } 728