1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for effect processor FX8010 6 * 7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk> 8 * Added EMU 1010 support. 9 * 10 * BUGS: 11 * -- 12 * 13 * TODO: 14 * -- 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/capability.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/vmalloc.h> 22 #include <linux/init.h> 23 #include <linux/mutex.h> 24 #include <linux/moduleparam.h> 25 #include <linux/nospec.h> 26 27 #include <sound/core.h> 28 #include <sound/tlv.h> 29 #include <sound/emu10k1.h> 30 31 #if 0 /* for testing purposes - digital out -> capture */ 32 #define EMU10K1_CAPTURE_DIGITAL_OUT 33 #endif 34 #if 0 /* for testing purposes - set S/PDIF to AC3 output */ 35 #define EMU10K1_SET_AC3_IEC958 36 #endif 37 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */ 38 #define EMU10K1_CENTER_LFE_FROM_FRONT 39 #endif 40 41 static bool high_res_gpr_volume; 42 module_param(high_res_gpr_volume, bool, 0444); 43 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range."); 44 45 /* 46 * Tables 47 */ 48 49 static const char * const fxbuses[16] = { 50 /* 0x00 */ "PCM Left", 51 /* 0x01 */ "PCM Right", 52 /* 0x02 */ "PCM Surround Left", 53 /* 0x03 */ "PCM Surround Right", 54 /* 0x04 */ "MIDI Left", 55 /* 0x05 */ "MIDI Right", 56 /* 0x06 */ "Center", 57 /* 0x07 */ "LFE", 58 /* 0x08 */ NULL, 59 /* 0x09 */ NULL, 60 /* 0x0a */ NULL, 61 /* 0x0b */ NULL, 62 /* 0x0c */ "MIDI Reverb", 63 /* 0x0d */ "MIDI Chorus", 64 /* 0x0e */ NULL, 65 /* 0x0f */ NULL 66 }; 67 68 static const char * const creative_ins[16] = { 69 /* 0x00 */ "AC97 Left", 70 /* 0x01 */ "AC97 Right", 71 /* 0x02 */ "TTL IEC958 Left", 72 /* 0x03 */ "TTL IEC958 Right", 73 /* 0x04 */ "Zoom Video Left", 74 /* 0x05 */ "Zoom Video Right", 75 /* 0x06 */ "Optical IEC958 Left", 76 /* 0x07 */ "Optical IEC958 Right", 77 /* 0x08 */ "Line/Mic 1 Left", 78 /* 0x09 */ "Line/Mic 1 Right", 79 /* 0x0a */ "Coaxial IEC958 Left", 80 /* 0x0b */ "Coaxial IEC958 Right", 81 /* 0x0c */ "Line/Mic 2 Left", 82 /* 0x0d */ "Line/Mic 2 Right", 83 /* 0x0e */ NULL, 84 /* 0x0f */ NULL 85 }; 86 87 static const char * const audigy_ins[16] = { 88 /* 0x00 */ "AC97 Left", 89 /* 0x01 */ "AC97 Right", 90 /* 0x02 */ "Audigy CD Left", 91 /* 0x03 */ "Audigy CD Right", 92 /* 0x04 */ "Optical IEC958 Left", 93 /* 0x05 */ "Optical IEC958 Right", 94 /* 0x06 */ NULL, 95 /* 0x07 */ NULL, 96 /* 0x08 */ "Line/Mic 2 Left", 97 /* 0x09 */ "Line/Mic 2 Right", 98 /* 0x0a */ "SPDIF Left", 99 /* 0x0b */ "SPDIF Right", 100 /* 0x0c */ "Aux2 Left", 101 /* 0x0d */ "Aux2 Right", 102 /* 0x0e */ NULL, 103 /* 0x0f */ NULL 104 }; 105 106 static const char * const creative_outs[32] = { 107 /* 0x00 */ "AC97 Left", 108 /* 0x01 */ "AC97 Right", 109 /* 0x02 */ "Optical IEC958 Left", 110 /* 0x03 */ "Optical IEC958 Right", 111 /* 0x04 */ "Center", 112 /* 0x05 */ "LFE", 113 /* 0x06 */ "Headphone Left", 114 /* 0x07 */ "Headphone Right", 115 /* 0x08 */ "Surround Left", 116 /* 0x09 */ "Surround Right", 117 /* 0x0a */ "PCM Capture Left", 118 /* 0x0b */ "PCM Capture Right", 119 /* 0x0c */ "MIC Capture", 120 /* 0x0d */ "AC97 Surround Left", 121 /* 0x0e */ "AC97 Surround Right", 122 /* 0x0f */ NULL, 123 /* 0x10 */ NULL, 124 /* 0x11 */ "Analog Center", 125 /* 0x12 */ "Analog LFE", 126 /* 0x13 */ NULL, 127 /* 0x14 */ NULL, 128 /* 0x15 */ NULL, 129 /* 0x16 */ NULL, 130 /* 0x17 */ NULL, 131 /* 0x18 */ NULL, 132 /* 0x19 */ NULL, 133 /* 0x1a */ NULL, 134 /* 0x1b */ NULL, 135 /* 0x1c */ NULL, 136 /* 0x1d */ NULL, 137 /* 0x1e */ NULL, 138 /* 0x1f */ NULL, 139 }; 140 141 static const char * const audigy_outs[32] = { 142 /* 0x00 */ "Digital Front Left", 143 /* 0x01 */ "Digital Front Right", 144 /* 0x02 */ "Digital Center", 145 /* 0x03 */ "Digital LEF", 146 /* 0x04 */ "Headphone Left", 147 /* 0x05 */ "Headphone Right", 148 /* 0x06 */ "Digital Rear Left", 149 /* 0x07 */ "Digital Rear Right", 150 /* 0x08 */ "Front Left", 151 /* 0x09 */ "Front Right", 152 /* 0x0a */ "Center", 153 /* 0x0b */ "LFE", 154 /* 0x0c */ NULL, 155 /* 0x0d */ NULL, 156 /* 0x0e */ "Rear Left", 157 /* 0x0f */ "Rear Right", 158 /* 0x10 */ "AC97 Front Left", 159 /* 0x11 */ "AC97 Front Right", 160 /* 0x12 */ "ADC Capture Left", 161 /* 0x13 */ "ADC Capture Right", 162 /* 0x14 */ NULL, 163 /* 0x15 */ NULL, 164 /* 0x16 */ NULL, 165 /* 0x17 */ NULL, 166 /* 0x18 */ NULL, 167 /* 0x19 */ NULL, 168 /* 0x1a */ NULL, 169 /* 0x1b */ NULL, 170 /* 0x1c */ NULL, 171 /* 0x1d */ NULL, 172 /* 0x1e */ NULL, 173 /* 0x1f */ NULL, 174 }; 175 176 static const u32 bass_table[41][5] = { 177 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 }, 178 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d }, 179 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee }, 180 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c }, 181 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b }, 182 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 }, 183 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f }, 184 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 }, 185 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 }, 186 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 }, 187 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 }, 188 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be }, 189 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b }, 190 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c }, 191 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b }, 192 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 }, 193 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a }, 194 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 }, 195 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 }, 196 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e }, 197 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee }, 198 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 }, 199 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 }, 200 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 }, 201 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 }, 202 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e }, 203 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 }, 204 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 }, 205 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 }, 206 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 }, 207 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 }, 208 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca }, 209 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 }, 210 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 }, 211 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 }, 212 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 }, 213 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a }, 214 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f }, 215 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 }, 216 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 }, 217 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 } 218 }; 219 220 static const u32 treble_table[41][5] = { 221 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 }, 222 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 }, 223 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 }, 224 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca }, 225 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 }, 226 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 }, 227 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 }, 228 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 }, 229 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 }, 230 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df }, 231 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff }, 232 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 }, 233 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c }, 234 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 }, 235 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 }, 236 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 }, 237 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 }, 238 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d }, 239 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 }, 240 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 }, 241 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f }, 242 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb }, 243 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 }, 244 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 }, 245 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd }, 246 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 }, 247 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad }, 248 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 }, 249 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 }, 250 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c }, 251 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 }, 252 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 }, 253 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 }, 254 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 }, 255 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 }, 256 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 }, 257 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d }, 258 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b }, 259 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 }, 260 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd }, 261 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 } 262 }; 263 264 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */ 265 static const u32 db_table[101] = { 266 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540, 267 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8, 268 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1, 269 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0, 270 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9, 271 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb, 272 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005, 273 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d, 274 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd, 275 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8, 276 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481, 277 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333, 278 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d, 279 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6, 280 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d, 281 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf, 282 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038, 283 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a, 284 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea, 285 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272, 286 0x7fffffff, 287 }; 288 289 /* EMU10k1/EMU10k2 DSP control db gain */ 290 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1); 291 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0); 292 293 /* EMU10K1 bass/treble db gain */ 294 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0); 295 296 static const u32 onoff_table[2] = { 297 0x00000000, 0x00000001 298 }; 299 300 /* 301 * controls 302 */ 303 304 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 305 { 306 struct snd_emu10k1_fx8010_ctl *ctl = 307 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 308 309 if (ctl->min == 0 && ctl->max == 1) 310 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 311 else 312 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 313 uinfo->count = ctl->vcount; 314 uinfo->value.integer.min = ctl->min; 315 uinfo->value.integer.max = ctl->max; 316 return 0; 317 } 318 319 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 320 { 321 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 322 struct snd_emu10k1_fx8010_ctl *ctl = 323 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 324 unsigned long flags; 325 unsigned int i; 326 327 spin_lock_irqsave(&emu->reg_lock, flags); 328 for (i = 0; i < ctl->vcount; i++) 329 ucontrol->value.integer.value[i] = ctl->value[i]; 330 spin_unlock_irqrestore(&emu->reg_lock, flags); 331 return 0; 332 } 333 334 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 335 { 336 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 337 struct snd_emu10k1_fx8010_ctl *ctl = 338 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 339 unsigned long flags; 340 unsigned int nval, val; 341 unsigned int i, j; 342 int change = 0; 343 344 spin_lock_irqsave(&emu->reg_lock, flags); 345 for (i = 0; i < ctl->vcount; i++) { 346 nval = ucontrol->value.integer.value[i]; 347 if (nval < ctl->min) 348 nval = ctl->min; 349 if (nval > ctl->max) 350 nval = ctl->max; 351 if (nval != ctl->value[i]) 352 change = 1; 353 val = ctl->value[i] = nval; 354 switch (ctl->translation) { 355 case EMU10K1_GPR_TRANSLATION_NONE: 356 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val); 357 break; 358 case EMU10K1_GPR_TRANSLATION_TABLE100: 359 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]); 360 break; 361 case EMU10K1_GPR_TRANSLATION_BASS: 362 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 363 change = -EIO; 364 goto __error; 365 } 366 for (j = 0; j < 5; j++) 367 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]); 368 break; 369 case EMU10K1_GPR_TRANSLATION_TREBLE: 370 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 371 change = -EIO; 372 goto __error; 373 } 374 for (j = 0; j < 5; j++) 375 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]); 376 break; 377 case EMU10K1_GPR_TRANSLATION_ONOFF: 378 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]); 379 break; 380 } 381 } 382 __error: 383 spin_unlock_irqrestore(&emu->reg_lock, flags); 384 return change; 385 } 386 387 /* 388 * Interrupt handler 389 */ 390 391 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu) 392 { 393 struct snd_emu10k1_fx8010_irq *irq, *nirq; 394 395 irq = emu->fx8010.irq_handlers; 396 while (irq) { 397 nirq = irq->next; /* irq ptr can be removed from list */ 398 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) { 399 if (irq->handler) 400 irq->handler(emu, irq->private_data); 401 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1); 402 } 403 irq = nirq; 404 } 405 } 406 407 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, 408 snd_fx8010_irq_handler_t *handler, 409 unsigned char gpr_running, 410 void *private_data, 411 struct snd_emu10k1_fx8010_irq *irq) 412 { 413 unsigned long flags; 414 415 irq->handler = handler; 416 irq->gpr_running = gpr_running; 417 irq->private_data = private_data; 418 irq->next = NULL; 419 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 420 if (emu->fx8010.irq_handlers == NULL) { 421 emu->fx8010.irq_handlers = irq; 422 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt; 423 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE); 424 } else { 425 irq->next = emu->fx8010.irq_handlers; 426 emu->fx8010.irq_handlers = irq; 427 } 428 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 429 return 0; 430 } 431 432 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, 433 struct snd_emu10k1_fx8010_irq *irq) 434 { 435 struct snd_emu10k1_fx8010_irq *tmp; 436 unsigned long flags; 437 438 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 439 tmp = emu->fx8010.irq_handlers; 440 if (tmp == irq) { 441 emu->fx8010.irq_handlers = tmp->next; 442 if (emu->fx8010.irq_handlers == NULL) { 443 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE); 444 emu->dsp_interrupt = NULL; 445 } 446 } else { 447 while (tmp && tmp->next != irq) 448 tmp = tmp->next; 449 if (tmp) 450 tmp->next = tmp->next->next; 451 } 452 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 453 return 0; 454 } 455 456 /************************************************************************* 457 * EMU10K1 effect manager 458 *************************************************************************/ 459 460 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode, 461 unsigned int *ptr, 462 u32 op, u32 r, u32 a, u32 x, u32 y) 463 { 464 u_int32_t *code; 465 if (snd_BUG_ON(*ptr >= 512)) 466 return; 467 code = icode->code + (*ptr) * 2; 468 set_bit(*ptr, icode->code_valid); 469 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff); 470 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff); 471 (*ptr)++; 472 } 473 474 #define OP(icode, ptr, op, r, a, x, y) \ 475 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y) 476 477 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode, 478 unsigned int *ptr, 479 u32 op, u32 r, u32 a, u32 x, u32 y) 480 { 481 u_int32_t *code; 482 if (snd_BUG_ON(*ptr >= 1024)) 483 return; 484 code = icode->code + (*ptr) * 2; 485 set_bit(*ptr, icode->code_valid); 486 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff); 487 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff); 488 (*ptr)++; 489 } 490 491 #define A_OP(icode, ptr, op, r, a, x, y) \ 492 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y) 493 494 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data) 495 { 496 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 497 snd_emu10k1_ptr_write(emu, pc, 0, data); 498 } 499 500 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc) 501 { 502 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 503 return snd_emu10k1_ptr_read(emu, pc, 0); 504 } 505 506 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu, 507 struct snd_emu10k1_fx8010_code *icode, 508 bool in_kernel) 509 { 510 int gpr; 511 u32 val; 512 513 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 514 if (!test_bit(gpr, icode->gpr_valid)) 515 continue; 516 if (in_kernel) 517 val = icode->gpr_map[gpr]; 518 else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr])) 519 return -EFAULT; 520 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val); 521 } 522 return 0; 523 } 524 525 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu, 526 struct snd_emu10k1_fx8010_code *icode) 527 { 528 int gpr; 529 u32 val; 530 531 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 532 set_bit(gpr, icode->gpr_valid); 533 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0); 534 if (put_user(val, (__user u32 *)&icode->gpr_map[gpr])) 535 return -EFAULT; 536 } 537 return 0; 538 } 539 540 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu, 541 struct snd_emu10k1_fx8010_code *icode, 542 bool in_kernel) 543 { 544 int tram; 545 u32 addr, val; 546 547 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 548 if (!test_bit(tram, icode->tram_valid)) 549 continue; 550 if (in_kernel) { 551 val = icode->tram_data_map[tram]; 552 addr = icode->tram_addr_map[tram]; 553 } else { 554 if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) || 555 get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram])) 556 return -EFAULT; 557 } 558 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val); 559 if (!emu->audigy) { 560 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr); 561 } else { 562 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12); 563 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20); 564 } 565 } 566 return 0; 567 } 568 569 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu, 570 struct snd_emu10k1_fx8010_code *icode) 571 { 572 int tram; 573 u32 val, addr; 574 575 memset(icode->tram_valid, 0, sizeof(icode->tram_valid)); 576 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 577 set_bit(tram, icode->tram_valid); 578 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0); 579 if (!emu->audigy) { 580 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0); 581 } else { 582 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12; 583 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20; 584 } 585 if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) || 586 put_user(addr, (__user u32 *)&icode->tram_addr_map[tram])) 587 return -EFAULT; 588 } 589 return 0; 590 } 591 592 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu, 593 struct snd_emu10k1_fx8010_code *icode, 594 bool in_kernel) 595 { 596 u32 pc, lo, hi; 597 598 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 599 if (!test_bit(pc / 2, icode->code_valid)) 600 continue; 601 if (in_kernel) { 602 lo = icode->code[pc + 0]; 603 hi = icode->code[pc + 1]; 604 } else { 605 if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) || 606 get_user(hi, (__user u32 *)&icode->code[pc + 1])) 607 return -EFAULT; 608 } 609 snd_emu10k1_efx_write(emu, pc + 0, lo); 610 snd_emu10k1_efx_write(emu, pc + 1, hi); 611 } 612 return 0; 613 } 614 615 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu, 616 struct snd_emu10k1_fx8010_code *icode) 617 { 618 u32 pc; 619 620 memset(icode->code_valid, 0, sizeof(icode->code_valid)); 621 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 622 set_bit(pc / 2, icode->code_valid); 623 if (put_user(snd_emu10k1_efx_read(emu, pc + 0), 624 (__user u32 *)&icode->code[pc + 0])) 625 return -EFAULT; 626 if (put_user(snd_emu10k1_efx_read(emu, pc + 1), 627 (__user u32 *)&icode->code[pc + 1])) 628 return -EFAULT; 629 } 630 return 0; 631 } 632 633 static struct snd_emu10k1_fx8010_ctl * 634 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, 635 struct emu10k1_ctl_elem_id *_id) 636 { 637 struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id; 638 struct snd_emu10k1_fx8010_ctl *ctl; 639 struct snd_kcontrol *kcontrol; 640 641 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 642 kcontrol = ctl->kcontrol; 643 if (kcontrol->id.iface == id->iface && 644 kcontrol->id.index == id->index && 645 !strcmp(kcontrol->id.name, id->name)) 646 return ctl; 647 } 648 return NULL; 649 } 650 651 #define MAX_TLV_SIZE 256 652 653 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel) 654 { 655 unsigned int data[2]; 656 unsigned int *tlv; 657 658 if (!_tlv) 659 return NULL; 660 if (in_kernel) 661 memcpy(data, (__force void *)_tlv, sizeof(data)); 662 else if (copy_from_user(data, _tlv, sizeof(data))) 663 return NULL; 664 if (data[1] >= MAX_TLV_SIZE) 665 return NULL; 666 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL); 667 if (!tlv) 668 return NULL; 669 memcpy(tlv, data, sizeof(data)); 670 if (in_kernel) { 671 memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]); 672 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) { 673 kfree(tlv); 674 return NULL; 675 } 676 return tlv; 677 } 678 679 static int copy_gctl(struct snd_emu10k1 *emu, 680 struct snd_emu10k1_fx8010_control_gpr *dst, 681 struct snd_emu10k1_fx8010_control_gpr *src, 682 int idx, bool in_kernel) 683 { 684 struct snd_emu10k1_fx8010_control_gpr __user *_src; 685 struct snd_emu10k1_fx8010_control_old_gpr *octl; 686 struct snd_emu10k1_fx8010_control_old_gpr __user *_octl; 687 688 _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src; 689 if (emu->support_tlv) { 690 if (in_kernel) 691 *dst = src[idx]; 692 else if (copy_from_user(dst, &_src[idx], sizeof(*src))) 693 return -EFAULT; 694 return 0; 695 } 696 697 octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src; 698 _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl; 699 if (in_kernel) 700 memcpy(dst, &octl[idx], sizeof(*octl)); 701 else if (copy_from_user(dst, &_octl[idx], sizeof(*octl))) 702 return -EFAULT; 703 dst->tlv = NULL; 704 return 0; 705 } 706 707 static int copy_gctl_to_user(struct snd_emu10k1 *emu, 708 struct snd_emu10k1_fx8010_control_gpr *dst, 709 struct snd_emu10k1_fx8010_control_gpr *src, 710 int idx) 711 { 712 struct snd_emu10k1_fx8010_control_gpr __user *_dst; 713 struct snd_emu10k1_fx8010_control_old_gpr __user *octl; 714 715 _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst; 716 if (emu->support_tlv) 717 return copy_to_user(&_dst[idx], src, sizeof(*src)); 718 719 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst; 720 return copy_to_user(&octl[idx], src, sizeof(*octl)); 721 } 722 723 static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i, 724 struct emu10k1_ctl_elem_id *ret, bool in_kernel) 725 { 726 struct emu10k1_ctl_elem_id __user *_id = 727 (struct emu10k1_ctl_elem_id __user *)&list[i]; 728 729 if (in_kernel) 730 *ret = list[i]; 731 else if (copy_from_user(ret, _id, sizeof(*ret))) 732 return -EFAULT; 733 return 0; 734 } 735 736 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu, 737 struct snd_emu10k1_fx8010_code *icode, 738 bool in_kernel) 739 { 740 unsigned int i; 741 struct emu10k1_ctl_elem_id id; 742 struct snd_emu10k1_fx8010_control_gpr *gctl; 743 struct snd_ctl_elem_id *gctl_id; 744 int err; 745 746 for (i = 0; i < icode->gpr_del_control_count; i++) { 747 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id, 748 in_kernel); 749 if (err < 0) 750 return err; 751 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL) 752 return -ENOENT; 753 } 754 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 755 if (! gctl) 756 return -ENOMEM; 757 err = 0; 758 for (i = 0; i < icode->gpr_add_control_count; i++) { 759 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 760 in_kernel)) { 761 err = -EFAULT; 762 goto __error; 763 } 764 if (snd_emu10k1_look_for_ctl(emu, &gctl->id)) 765 continue; 766 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 767 down_read(&emu->card->controls_rwsem); 768 if (snd_ctl_find_id(emu->card, gctl_id)) { 769 up_read(&emu->card->controls_rwsem); 770 err = -EEXIST; 771 goto __error; 772 } 773 up_read(&emu->card->controls_rwsem); 774 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 775 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 776 err = -EINVAL; 777 goto __error; 778 } 779 } 780 for (i = 0; i < icode->gpr_list_control_count; i++) { 781 /* FIXME: we need to check the WRITE access */ 782 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i, 783 in_kernel)) { 784 err = -EFAULT; 785 goto __error; 786 } 787 } 788 __error: 789 kfree(gctl); 790 return err; 791 } 792 793 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl) 794 { 795 struct snd_emu10k1_fx8010_ctl *ctl; 796 797 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value; 798 kctl->private_value = 0; 799 list_del(&ctl->list); 800 kfree(ctl); 801 kfree(kctl->tlv.p); 802 } 803 804 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu, 805 struct snd_emu10k1_fx8010_code *icode, 806 bool in_kernel) 807 { 808 unsigned int i, j; 809 struct snd_emu10k1_fx8010_control_gpr *gctl; 810 struct snd_ctl_elem_id *gctl_id; 811 struct snd_emu10k1_fx8010_ctl *ctl, *nctl; 812 struct snd_kcontrol_new knew; 813 struct snd_kcontrol *kctl; 814 struct snd_ctl_elem_value *val; 815 int err = 0; 816 817 val = kmalloc(sizeof(*val), GFP_KERNEL); 818 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 819 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL); 820 if (!val || !gctl || !nctl) { 821 err = -ENOMEM; 822 goto __error; 823 } 824 825 for (i = 0; i < icode->gpr_add_control_count; i++) { 826 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 827 in_kernel)) { 828 err = -EFAULT; 829 goto __error; 830 } 831 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 832 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 833 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 834 err = -EINVAL; 835 goto __error; 836 } 837 if (!*gctl_id->name) { 838 err = -EINVAL; 839 goto __error; 840 } 841 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id); 842 memset(&knew, 0, sizeof(knew)); 843 knew.iface = gctl_id->iface; 844 knew.name = gctl_id->name; 845 knew.index = gctl_id->index; 846 knew.device = gctl_id->device; 847 knew.subdevice = gctl_id->subdevice; 848 knew.info = snd_emu10k1_gpr_ctl_info; 849 knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel); 850 if (knew.tlv.p) 851 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 852 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 853 knew.get = snd_emu10k1_gpr_ctl_get; 854 knew.put = snd_emu10k1_gpr_ctl_put; 855 memset(nctl, 0, sizeof(*nctl)); 856 nctl->vcount = gctl->vcount; 857 nctl->count = gctl->count; 858 for (j = 0; j < 32; j++) { 859 nctl->gpr[j] = gctl->gpr[j]; 860 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */ 861 val->value.integer.value[j] = gctl->value[j]; 862 } 863 nctl->min = gctl->min; 864 nctl->max = gctl->max; 865 nctl->translation = gctl->translation; 866 if (ctl == NULL) { 867 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL); 868 if (ctl == NULL) { 869 err = -ENOMEM; 870 kfree(knew.tlv.p); 871 goto __error; 872 } 873 knew.private_value = (unsigned long)ctl; 874 *ctl = *nctl; 875 kctl = snd_ctl_new1(&knew, emu); 876 err = snd_ctl_add(emu->card, kctl); 877 if (err < 0) { 878 kfree(ctl); 879 kfree(knew.tlv.p); 880 goto __error; 881 } 882 kctl->private_free = snd_emu10k1_ctl_private_free; 883 ctl->kcontrol = kctl; 884 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl); 885 } else { 886 /* overwrite */ 887 nctl->list = ctl->list; 888 nctl->kcontrol = ctl->kcontrol; 889 *ctl = *nctl; 890 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE | 891 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id); 892 } 893 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val); 894 } 895 __error: 896 kfree(nctl); 897 kfree(gctl); 898 kfree(val); 899 return err; 900 } 901 902 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu, 903 struct snd_emu10k1_fx8010_code *icode, 904 bool in_kernel) 905 { 906 unsigned int i; 907 struct emu10k1_ctl_elem_id id; 908 struct snd_emu10k1_fx8010_ctl *ctl; 909 struct snd_card *card = emu->card; 910 int err; 911 912 for (i = 0; i < icode->gpr_del_control_count; i++) { 913 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id, 914 in_kernel); 915 if (err < 0) 916 return err; 917 down_write(&card->controls_rwsem); 918 ctl = snd_emu10k1_look_for_ctl(emu, &id); 919 if (ctl) 920 snd_ctl_remove(card, ctl->kcontrol); 921 up_write(&card->controls_rwsem); 922 } 923 return 0; 924 } 925 926 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu, 927 struct snd_emu10k1_fx8010_code *icode) 928 { 929 unsigned int i = 0, j; 930 unsigned int total = 0; 931 struct snd_emu10k1_fx8010_control_gpr *gctl; 932 struct snd_emu10k1_fx8010_ctl *ctl; 933 struct snd_ctl_elem_id *id; 934 935 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 936 if (! gctl) 937 return -ENOMEM; 938 939 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 940 total++; 941 if (icode->gpr_list_controls && 942 i < icode->gpr_list_control_count) { 943 memset(gctl, 0, sizeof(*gctl)); 944 id = &ctl->kcontrol->id; 945 gctl->id.iface = (__force int)id->iface; 946 strscpy(gctl->id.name, id->name, sizeof(gctl->id.name)); 947 gctl->id.index = id->index; 948 gctl->id.device = id->device; 949 gctl->id.subdevice = id->subdevice; 950 gctl->vcount = ctl->vcount; 951 gctl->count = ctl->count; 952 for (j = 0; j < 32; j++) { 953 gctl->gpr[j] = ctl->gpr[j]; 954 gctl->value[j] = ctl->value[j]; 955 } 956 gctl->min = ctl->min; 957 gctl->max = ctl->max; 958 gctl->translation = ctl->translation; 959 if (copy_gctl_to_user(emu, icode->gpr_list_controls, 960 gctl, i)) { 961 kfree(gctl); 962 return -EFAULT; 963 } 964 i++; 965 } 966 } 967 icode->gpr_list_control_total = total; 968 kfree(gctl); 969 return 0; 970 } 971 972 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu, 973 struct snd_emu10k1_fx8010_code *icode, 974 bool in_kernel) 975 { 976 int err = 0; 977 978 mutex_lock(&emu->fx8010.lock); 979 err = snd_emu10k1_verify_controls(emu, icode, in_kernel); 980 if (err < 0) 981 goto __error; 982 strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name)); 983 /* stop FX processor - this may be dangerous, but it's better to miss 984 some samples than generate wrong ones - [jk] */ 985 if (emu->audigy) 986 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 987 else 988 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 989 /* ok, do the main job */ 990 err = snd_emu10k1_del_controls(emu, icode, in_kernel); 991 if (err < 0) 992 goto __error; 993 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel); 994 if (err < 0) 995 goto __error; 996 err = snd_emu10k1_tram_poke(emu, icode, in_kernel); 997 if (err < 0) 998 goto __error; 999 err = snd_emu10k1_code_poke(emu, icode, in_kernel); 1000 if (err < 0) 1001 goto __error; 1002 err = snd_emu10k1_add_controls(emu, icode, in_kernel); 1003 if (err < 0) 1004 goto __error; 1005 /* start FX processor when the DSP code is updated */ 1006 if (emu->audigy) 1007 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 1008 else 1009 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 1010 __error: 1011 mutex_unlock(&emu->fx8010.lock); 1012 return err; 1013 } 1014 1015 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu, 1016 struct snd_emu10k1_fx8010_code *icode) 1017 { 1018 int err; 1019 1020 mutex_lock(&emu->fx8010.lock); 1021 strscpy(icode->name, emu->fx8010.name, sizeof(icode->name)); 1022 /* ok, do the main job */ 1023 err = snd_emu10k1_gpr_peek(emu, icode); 1024 if (err >= 0) 1025 err = snd_emu10k1_tram_peek(emu, icode); 1026 if (err >= 0) 1027 err = snd_emu10k1_code_peek(emu, icode); 1028 if (err >= 0) 1029 err = snd_emu10k1_list_controls(emu, icode); 1030 mutex_unlock(&emu->fx8010.lock); 1031 return err; 1032 } 1033 1034 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu, 1035 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1036 { 1037 unsigned int i; 1038 int err = 0; 1039 struct snd_emu10k1_fx8010_pcm *pcm; 1040 1041 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1042 return -EINVAL; 1043 ipcm->substream = array_index_nospec(ipcm->substream, 1044 EMU10K1_FX8010_PCM_COUNT); 1045 if (ipcm->channels > 32) 1046 return -EINVAL; 1047 pcm = &emu->fx8010.pcm[ipcm->substream]; 1048 mutex_lock(&emu->fx8010.lock); 1049 spin_lock_irq(&emu->reg_lock); 1050 if (pcm->opened) { 1051 err = -EBUSY; 1052 goto __error; 1053 } 1054 if (ipcm->channels == 0) { /* remove */ 1055 pcm->valid = 0; 1056 } else { 1057 /* FIXME: we need to add universal code to the PCM transfer routine */ 1058 if (ipcm->channels != 2) { 1059 err = -EINVAL; 1060 goto __error; 1061 } 1062 pcm->valid = 1; 1063 pcm->opened = 0; 1064 pcm->channels = ipcm->channels; 1065 pcm->tram_start = ipcm->tram_start; 1066 pcm->buffer_size = ipcm->buffer_size; 1067 pcm->gpr_size = ipcm->gpr_size; 1068 pcm->gpr_count = ipcm->gpr_count; 1069 pcm->gpr_tmpcount = ipcm->gpr_tmpcount; 1070 pcm->gpr_ptr = ipcm->gpr_ptr; 1071 pcm->gpr_trigger = ipcm->gpr_trigger; 1072 pcm->gpr_running = ipcm->gpr_running; 1073 for (i = 0; i < pcm->channels; i++) 1074 pcm->etram[i] = ipcm->etram[i]; 1075 } 1076 __error: 1077 spin_unlock_irq(&emu->reg_lock); 1078 mutex_unlock(&emu->fx8010.lock); 1079 return err; 1080 } 1081 1082 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu, 1083 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1084 { 1085 unsigned int i; 1086 int err = 0; 1087 struct snd_emu10k1_fx8010_pcm *pcm; 1088 1089 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1090 return -EINVAL; 1091 ipcm->substream = array_index_nospec(ipcm->substream, 1092 EMU10K1_FX8010_PCM_COUNT); 1093 pcm = &emu->fx8010.pcm[ipcm->substream]; 1094 mutex_lock(&emu->fx8010.lock); 1095 spin_lock_irq(&emu->reg_lock); 1096 ipcm->channels = pcm->channels; 1097 ipcm->tram_start = pcm->tram_start; 1098 ipcm->buffer_size = pcm->buffer_size; 1099 ipcm->gpr_size = pcm->gpr_size; 1100 ipcm->gpr_ptr = pcm->gpr_ptr; 1101 ipcm->gpr_count = pcm->gpr_count; 1102 ipcm->gpr_tmpcount = pcm->gpr_tmpcount; 1103 ipcm->gpr_trigger = pcm->gpr_trigger; 1104 ipcm->gpr_running = pcm->gpr_running; 1105 for (i = 0; i < pcm->channels; i++) 1106 ipcm->etram[i] = pcm->etram[i]; 1107 ipcm->res1 = ipcm->res2 = 0; 1108 ipcm->pad = 0; 1109 spin_unlock_irq(&emu->reg_lock); 1110 mutex_unlock(&emu->fx8010.lock); 1111 return err; 1112 } 1113 1114 #define SND_EMU10K1_GPR_CONTROLS 44 1115 #define SND_EMU10K1_INPUTS 12 1116 #define SND_EMU10K1_PLAYBACK_CHANNELS 8 1117 #define SND_EMU10K1_CAPTURE_CHANNELS 4 1118 1119 static void 1120 snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1121 const char *name, int gpr, int defval) 1122 { 1123 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1124 strcpy(ctl->id.name, name); 1125 ctl->vcount = ctl->count = 1; 1126 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1127 if (high_res_gpr_volume) { 1128 ctl->min = 0; 1129 ctl->max = 0x7fffffff; 1130 ctl->tlv = snd_emu10k1_db_linear; 1131 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE; 1132 } else { 1133 ctl->min = 0; 1134 ctl->max = 100; 1135 ctl->tlv = snd_emu10k1_db_scale1; 1136 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100; 1137 } 1138 } 1139 1140 static void 1141 snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1142 const char *name, int gpr, int defval) 1143 { 1144 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1145 strcpy(ctl->id.name, name); 1146 ctl->vcount = ctl->count = 2; 1147 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1148 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1149 if (high_res_gpr_volume) { 1150 ctl->min = 0; 1151 ctl->max = 0x7fffffff; 1152 ctl->tlv = snd_emu10k1_db_linear; 1153 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE; 1154 } else { 1155 ctl->min = 0; 1156 ctl->max = 100; 1157 ctl->tlv = snd_emu10k1_db_scale1; 1158 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100; 1159 } 1160 } 1161 1162 static void 1163 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1164 const char *name, int gpr, int defval) 1165 { 1166 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1167 strcpy(ctl->id.name, name); 1168 ctl->vcount = ctl->count = 1; 1169 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1170 ctl->min = 0; 1171 ctl->max = 1; 1172 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1173 } 1174 1175 static void 1176 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1177 const char *name, int gpr, int defval) 1178 { 1179 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1180 strcpy(ctl->id.name, name); 1181 ctl->vcount = ctl->count = 2; 1182 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1183 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1184 ctl->min = 0; 1185 ctl->max = 1; 1186 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1187 } 1188 1189 /* 1190 * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA 1191 * to 2 x 16-bit registers in Audigy - their values are read via DMA. 1192 * Conversion is performed by Audigy DSP instructions of FX8010. 1193 */ 1194 static int snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1195 struct snd_emu10k1_fx8010_code *icode, 1196 u32 *ptr, int tmp, int bit_shifter16, 1197 int reg_in, int reg_out) 1198 { 1199 A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000); 1200 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000); 1201 A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2)); 1202 A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000); 1203 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000); 1204 A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000); 1205 A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2)); 1206 A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000); 1207 return 1; 1208 } 1209 1210 /* 1211 * initial DSP configuration for Audigy 1212 */ 1213 1214 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu) 1215 { 1216 int err, z, gpr, nctl; 1217 int bit_shifter16; 1218 const int playback = 10; 1219 const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */ 1220 const int stereo_mix = capture + 2; 1221 const int tmp = 0x88; 1222 u32 ptr; 1223 struct snd_emu10k1_fx8010_code *icode = NULL; 1224 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1225 u32 *gpr_map; 1226 1227 err = -ENOMEM; 1228 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1229 if (!icode) 1230 return err; 1231 1232 icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024, 1233 sizeof(u_int32_t), GFP_KERNEL); 1234 if (!icode->gpr_map) 1235 goto __err_gpr; 1236 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1237 sizeof(*controls), GFP_KERNEL); 1238 if (!controls) 1239 goto __err_ctrls; 1240 1241 gpr_map = icode->gpr_map; 1242 1243 icode->tram_data_map = icode->gpr_map + 512; 1244 icode->tram_addr_map = icode->tram_data_map + 256; 1245 icode->code = icode->tram_addr_map + 256; 1246 1247 /* clear free GPRs */ 1248 memset(icode->gpr_valid, 0xff, 512 / 8); 1249 1250 /* clear TRAM data & address lines */ 1251 memset(icode->tram_valid, 0xff, 256 / 8); 1252 1253 strcpy(icode->name, "Audigy DSP code for ALSA"); 1254 ptr = 0; 1255 nctl = 0; 1256 gpr = stereo_mix + 10; 1257 gpr_map[gpr++] = 0x00007fff; 1258 gpr_map[gpr++] = 0x00008000; 1259 gpr_map[gpr++] = 0x0000ffff; 1260 bit_shifter16 = gpr; 1261 1262 #if 1 1263 /* PCM front Playback Volume (independent from stereo mix) 1264 * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31) 1265 * where gpr contains attenuation from corresponding mixer control 1266 * (snd_emu10k1_init_stereo_control) 1267 */ 1268 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT)); 1269 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT)); 1270 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100); 1271 gpr += 2; 1272 1273 /* PCM Surround Playback (independent from stereo mix) */ 1274 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR)); 1275 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR)); 1276 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100); 1277 gpr += 2; 1278 1279 /* PCM Side Playback (independent from stereo mix) */ 1280 if (emu->card_capabilities->spk71) { 1281 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE)); 1282 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE)); 1283 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100); 1284 gpr += 2; 1285 } 1286 1287 /* PCM Center Playback (independent from stereo mix) */ 1288 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER)); 1289 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100); 1290 gpr++; 1291 1292 /* PCM LFE Playback (independent from stereo mix) */ 1293 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE)); 1294 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100); 1295 gpr++; 1296 1297 /* 1298 * Stereo Mix 1299 */ 1300 /* Wave (PCM) Playback Volume (will be renamed later) */ 1301 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1302 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1303 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100); 1304 gpr += 2; 1305 1306 /* Synth Playback */ 1307 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1308 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1309 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100); 1310 gpr += 2; 1311 1312 /* Wave (PCM) Capture */ 1313 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1314 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1315 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0); 1316 gpr += 2; 1317 1318 /* Synth Capture */ 1319 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1320 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1321 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0); 1322 gpr += 2; 1323 1324 /* 1325 * inputs 1326 */ 1327 #define A_ADD_VOLUME_IN(var,vol,input) \ 1328 A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) 1329 1330 if (emu->card_capabilities->emu_model) { 1331 /* EMU1010 DSP 0 and DSP 1 Capture */ 1332 // The 24 MSB hold the actual value. We implicitly discard the 16 LSB. 1333 if (emu->card_capabilities->ca0108_chip) { 1334 /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */ 1335 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001); 1336 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp)); 1337 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001); 1338 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp)); 1339 } else { 1340 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0)); 1341 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1)); 1342 } 1343 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0); 1344 gpr += 2; 1345 } 1346 /* AC'97 Playback Volume - used only for mic (renamed later) */ 1347 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L); 1348 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R); 1349 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0); 1350 gpr += 2; 1351 /* AC'97 Capture Volume - used only for mic */ 1352 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L); 1353 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R); 1354 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0); 1355 gpr += 2; 1356 1357 /* mic capture buffer */ 1358 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R)); 1359 1360 /* Audigy CD Playback Volume */ 1361 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L); 1362 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1363 snd_emu10k1_init_stereo_control(&controls[nctl++], 1364 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume", 1365 gpr, 0); 1366 gpr += 2; 1367 /* Audigy CD Capture Volume */ 1368 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L); 1369 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1370 snd_emu10k1_init_stereo_control(&controls[nctl++], 1371 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume", 1372 gpr, 0); 1373 gpr += 2; 1374 1375 /* Optical SPDIF Playback Volume */ 1376 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L); 1377 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1378 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0); 1379 gpr += 2; 1380 /* Optical SPDIF Capture Volume */ 1381 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L); 1382 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1383 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0); 1384 gpr += 2; 1385 1386 /* Line2 Playback Volume */ 1387 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L); 1388 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R); 1389 snd_emu10k1_init_stereo_control(&controls[nctl++], 1390 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume", 1391 gpr, 0); 1392 gpr += 2; 1393 /* Line2 Capture Volume */ 1394 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L); 1395 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R); 1396 snd_emu10k1_init_stereo_control(&controls[nctl++], 1397 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume", 1398 gpr, 0); 1399 gpr += 2; 1400 1401 /* Philips ADC Playback Volume */ 1402 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L); 1403 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R); 1404 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0); 1405 gpr += 2; 1406 /* Philips ADC Capture Volume */ 1407 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L); 1408 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R); 1409 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0); 1410 gpr += 2; 1411 1412 /* Aux2 Playback Volume */ 1413 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L); 1414 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R); 1415 snd_emu10k1_init_stereo_control(&controls[nctl++], 1416 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume", 1417 gpr, 0); 1418 gpr += 2; 1419 /* Aux2 Capture Volume */ 1420 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L); 1421 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R); 1422 snd_emu10k1_init_stereo_control(&controls[nctl++], 1423 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume", 1424 gpr, 0); 1425 gpr += 2; 1426 1427 /* Stereo Mix Front Playback Volume */ 1428 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix)); 1429 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1430 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100); 1431 gpr += 2; 1432 1433 /* Stereo Mix Surround Playback */ 1434 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix)); 1435 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1436 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0); 1437 gpr += 2; 1438 1439 /* Stereo Mix Center Playback */ 1440 /* Center = sub = Left/2 + Right/2 */ 1441 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1)); 1442 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp)); 1443 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0); 1444 gpr++; 1445 1446 /* Stereo Mix LFE Playback */ 1447 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp)); 1448 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0); 1449 gpr++; 1450 1451 if (emu->card_capabilities->spk71) { 1452 /* Stereo Mix Side Playback */ 1453 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix)); 1454 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1455 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0); 1456 gpr += 2; 1457 } 1458 1459 /* 1460 * outputs 1461 */ 1462 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src)) 1463 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \ 1464 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);} 1465 1466 #define _A_SWITCH(icode, ptr, dst, src, sw) \ 1467 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw); 1468 #define A_SWITCH(icode, ptr, dst, src, sw) \ 1469 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw)) 1470 #define _A_SWITCH_NEG(icode, ptr, dst, src) \ 1471 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001); 1472 #define A_SWITCH_NEG(icode, ptr, dst, src) \ 1473 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src)) 1474 1475 1476 /* 1477 * Process tone control 1478 */ 1479 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */ 1480 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */ 1481 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */ 1482 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */ 1483 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */ 1484 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */ 1485 if (emu->card_capabilities->spk71) { 1486 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */ 1487 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */ 1488 } 1489 1490 1491 ctl = &controls[nctl + 0]; 1492 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1493 strcpy(ctl->id.name, "Tone Control - Bass"); 1494 ctl->vcount = 2; 1495 ctl->count = 10; 1496 ctl->min = 0; 1497 ctl->max = 40; 1498 ctl->value[0] = ctl->value[1] = 20; 1499 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 1500 ctl = &controls[nctl + 1]; 1501 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1502 strcpy(ctl->id.name, "Tone Control - Treble"); 1503 ctl->vcount = 2; 1504 ctl->count = 10; 1505 ctl->min = 0; 1506 ctl->max = 40; 1507 ctl->value[0] = ctl->value[1] = 20; 1508 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 1509 1510 #define BASS_GPR 0x8c 1511 #define TREBLE_GPR 0x96 1512 1513 for (z = 0; z < 5; z++) { 1514 int j; 1515 for (j = 0; j < 2; j++) { 1516 controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j; 1517 controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j; 1518 } 1519 } 1520 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */ 1521 int j, k, l, d; 1522 for (j = 0; j < 2; j++) { /* left/right */ 1523 k = 0xb0 + (z * 8) + (j * 4); 1524 l = 0xe0 + (z * 8) + (j * 4); 1525 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j; 1526 1527 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j)); 1528 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j)); 1529 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j)); 1530 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j)); 1531 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j)); 1532 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000); 1533 1534 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j)); 1535 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j)); 1536 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j)); 1537 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j)); 1538 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j)); 1539 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010); 1540 1541 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000); 1542 1543 if (z == 2) /* center */ 1544 break; 1545 } 1546 } 1547 nctl += 2; 1548 1549 #undef BASS_GPR 1550 #undef TREBLE_GPR 1551 1552 for (z = 0; z < 8; z++) { 1553 A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0); 1554 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0); 1555 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 1556 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1557 } 1558 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0); 1559 gpr += 2; 1560 1561 /* Master volume (will be renamed later) */ 1562 A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS)); 1563 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS)); 1564 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS)); 1565 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS)); 1566 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS)); 1567 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS)); 1568 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS)); 1569 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS)); 1570 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0); 1571 gpr += 2; 1572 1573 /* analog speakers */ 1574 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); 1575 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS); 1576 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS); 1577 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS); 1578 if (emu->card_capabilities->spk71) 1579 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS); 1580 1581 /* headphone */ 1582 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); 1583 1584 /* digital outputs */ 1585 /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */ 1586 if (emu->card_capabilities->emu_model) { 1587 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */ 1588 dev_info(emu->card->dev, "EMU outputs on\n"); 1589 for (z = 0; z < 8; z++) { 1590 if (emu->card_capabilities->ca0108_chip) { 1591 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000); 1592 } else { 1593 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000); 1594 } 1595 } 1596 } 1597 1598 /* IEC958 Optical Raw Playback Switch */ 1599 gpr_map[gpr++] = 0; 1600 gpr_map[gpr++] = 0x1008; 1601 gpr_map[gpr++] = 0xffff0000; 1602 for (z = 0; z < 2; z++) { 1603 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000); 1604 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001); 1605 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2)); 1606 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000); 1607 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z); 1608 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 1609 A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1); 1610 if ((z==1) && (emu->card_capabilities->spdif_bug)) { 1611 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */ 1612 dev_info(emu->card->dev, 1613 "Installing spdif_bug patch: %s\n", 1614 emu->card_capabilities->name); 1615 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000); 1616 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1617 } else { 1618 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1619 } 1620 } 1621 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 1622 gpr += 2; 1623 1624 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS); 1625 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS); 1626 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS); 1627 1628 /* ADC buffer */ 1629 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 1630 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); 1631 #else 1632 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture); 1633 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1); 1634 #endif 1635 1636 if (emu->card_capabilities->emu_model) { 1637 /* Capture 16 channels of S32_LE sound. */ 1638 if (emu->card_capabilities->ca0108_chip) { 1639 dev_info(emu->card->dev, "EMU2 inputs on\n"); 1640 /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */ 1641 1642 for (z = 0; z < 0x10; z++) { 1643 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, 1644 bit_shifter16, 1645 A3_EMU32IN(z), 1646 A_FXBUS2(z*2) ); 1647 } 1648 } else { 1649 dev_info(emu->card->dev, "EMU inputs on\n"); 1650 /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */ 1651 1652 /* 1653 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n", 1654 gpr, tmp); 1655 */ 1656 /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */ 1657 /* A_P16VIN(0) is delayed by one sample, 1658 * so all other A_P16VIN channels will need to also be delayed 1659 */ 1660 /* Left ADC in. 1 of 2 */ 1661 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) ); 1662 /* Right ADC in 1 of 2 */ 1663 gpr_map[gpr++] = 0x00000000; 1664 /* Delaying by one sample: instead of copying the input 1665 * value A_P16VIN to output A_FXBUS2 as in the first channel, 1666 * we use an auxiliary register, delaying the value by one 1667 * sample 1668 */ 1669 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) ); 1670 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000); 1671 gpr_map[gpr++] = 0x00000000; 1672 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) ); 1673 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000); 1674 gpr_map[gpr++] = 0x00000000; 1675 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) ); 1676 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000); 1677 /* For 96kHz mode */ 1678 /* Left ADC in. 2 of 2 */ 1679 gpr_map[gpr++] = 0x00000000; 1680 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) ); 1681 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000); 1682 /* Right ADC in 2 of 2 */ 1683 gpr_map[gpr++] = 0x00000000; 1684 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) ); 1685 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000); 1686 gpr_map[gpr++] = 0x00000000; 1687 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) ); 1688 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000); 1689 gpr_map[gpr++] = 0x00000000; 1690 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) ); 1691 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000); 1692 /* Pavel Hofman - we still have voices, A_FXBUS2s, and 1693 * A_P16VINs available - 1694 * let's add 8 more capture channels - total of 16 1695 */ 1696 gpr_map[gpr++] = 0x00000000; 1697 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1698 bit_shifter16, 1699 A_GPR(gpr - 1), 1700 A_FXBUS2(0x10)); 1701 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8), 1702 A_C_00000000, A_C_00000000); 1703 gpr_map[gpr++] = 0x00000000; 1704 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1705 bit_shifter16, 1706 A_GPR(gpr - 1), 1707 A_FXBUS2(0x12)); 1708 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9), 1709 A_C_00000000, A_C_00000000); 1710 gpr_map[gpr++] = 0x00000000; 1711 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1712 bit_shifter16, 1713 A_GPR(gpr - 1), 1714 A_FXBUS2(0x14)); 1715 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa), 1716 A_C_00000000, A_C_00000000); 1717 gpr_map[gpr++] = 0x00000000; 1718 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1719 bit_shifter16, 1720 A_GPR(gpr - 1), 1721 A_FXBUS2(0x16)); 1722 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb), 1723 A_C_00000000, A_C_00000000); 1724 gpr_map[gpr++] = 0x00000000; 1725 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1726 bit_shifter16, 1727 A_GPR(gpr - 1), 1728 A_FXBUS2(0x18)); 1729 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc), 1730 A_C_00000000, A_C_00000000); 1731 gpr_map[gpr++] = 0x00000000; 1732 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1733 bit_shifter16, 1734 A_GPR(gpr - 1), 1735 A_FXBUS2(0x1a)); 1736 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd), 1737 A_C_00000000, A_C_00000000); 1738 gpr_map[gpr++] = 0x00000000; 1739 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1740 bit_shifter16, 1741 A_GPR(gpr - 1), 1742 A_FXBUS2(0x1c)); 1743 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe), 1744 A_C_00000000, A_C_00000000); 1745 gpr_map[gpr++] = 0x00000000; 1746 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1747 bit_shifter16, 1748 A_GPR(gpr - 1), 1749 A_FXBUS2(0x1e)); 1750 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf), 1751 A_C_00000000, A_C_00000000); 1752 } 1753 1754 #if 0 1755 for (z = 4; z < 8; z++) { 1756 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1757 } 1758 for (z = 0xc; z < 0x10; z++) { 1759 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1760 } 1761 #endif 1762 } else { 1763 /* EFX capture - capture the 16 EXTINs */ 1764 /* Capture 16 channels of S16_LE sound */ 1765 for (z = 0; z < 16; z++) { 1766 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z)); 1767 } 1768 } 1769 1770 #endif /* JCD test */ 1771 /* 1772 * ok, set up done.. 1773 */ 1774 1775 if (gpr > tmp) { 1776 snd_BUG(); 1777 err = -EIO; 1778 goto __err; 1779 } 1780 /* clear remaining instruction memory */ 1781 while (ptr < 0x400) 1782 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0); 1783 1784 icode->gpr_add_control_count = nctl; 1785 icode->gpr_add_controls = controls; 1786 emu->support_tlv = 1; /* support TLV */ 1787 err = snd_emu10k1_icode_poke(emu, icode, true); 1788 emu->support_tlv = 0; /* clear again */ 1789 1790 __err: 1791 kfree(controls); 1792 __err_ctrls: 1793 kfree(icode->gpr_map); 1794 __err_gpr: 1795 kfree(icode); 1796 return err; 1797 } 1798 1799 1800 /* 1801 * initial DSP configuration for Emu10k1 1802 */ 1803 1804 /* when volume = max, then copy only to avoid volume modification */ 1805 /* with iMAC0 (negative values) */ 1806 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1807 { 1808 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol); 1809 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1810 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001); 1811 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000); 1812 } 1813 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1814 { 1815 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1816 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1817 OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001); 1818 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001); 1819 OP(icode, ptr, iMAC0, dst, dst, src, vol); 1820 } 1821 static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1822 { 1823 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1824 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1825 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000); 1826 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001); 1827 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol); 1828 } 1829 1830 #define VOLUME(icode, ptr, dst, src, vol) \ 1831 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1832 #define VOLUME_IN(icode, ptr, dst, src, vol) \ 1833 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1834 #define VOLUME_ADD(icode, ptr, dst, src, vol) \ 1835 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1836 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \ 1837 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1838 #define VOLUME_OUT(icode, ptr, dst, src, vol) \ 1839 _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol)) 1840 #define _SWITCH(icode, ptr, dst, src, sw) \ 1841 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw); 1842 #define SWITCH(icode, ptr, dst, src, sw) \ 1843 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw)) 1844 #define SWITCH_IN(icode, ptr, dst, src, sw) \ 1845 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw)) 1846 #define _SWITCH_NEG(icode, ptr, dst, src) \ 1847 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001); 1848 #define SWITCH_NEG(icode, ptr, dst, src) \ 1849 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src)) 1850 1851 1852 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 1853 { 1854 int err, i, z, gpr, tmp, playback, capture; 1855 u32 ptr; 1856 struct snd_emu10k1_fx8010_code *icode; 1857 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL; 1858 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1859 u32 *gpr_map; 1860 1861 err = -ENOMEM; 1862 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1863 if (!icode) 1864 return err; 1865 1866 icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512, 1867 sizeof(u_int32_t), GFP_KERNEL); 1868 if (!icode->gpr_map) 1869 goto __err_gpr; 1870 1871 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1872 sizeof(struct snd_emu10k1_fx8010_control_gpr), 1873 GFP_KERNEL); 1874 if (!controls) 1875 goto __err_ctrls; 1876 1877 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL); 1878 if (!ipcm) 1879 goto __err_ipcm; 1880 1881 gpr_map = icode->gpr_map; 1882 1883 icode->tram_data_map = icode->gpr_map + 256; 1884 icode->tram_addr_map = icode->tram_data_map + 160; 1885 icode->code = icode->tram_addr_map + 160; 1886 1887 /* clear free GPRs */ 1888 memset(icode->gpr_valid, 0xff, 256 / 8); 1889 1890 /* clear TRAM data & address lines */ 1891 memset(icode->tram_valid, 0xff, 160 / 8); 1892 1893 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela"); 1894 ptr = 0; i = 0; 1895 /* we have 12 inputs */ 1896 playback = SND_EMU10K1_INPUTS; 1897 /* we have 6 playback channels and tone control doubles */ 1898 capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); 1899 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS; 1900 tmp = 0x88; /* we need 4 temporary GPR */ 1901 /* from 0x8c to 0xff is the area for tone control */ 1902 1903 /* 1904 * Process FX Buses 1905 */ 1906 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004); 1907 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004); 1908 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004); 1909 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004); 1910 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004); 1911 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004); 1912 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004); 1913 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004); 1914 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */ 1915 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */ 1916 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004); 1917 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004); 1918 1919 /* Raw S/PDIF PCM */ 1920 ipcm->substream = 0; 1921 ipcm->channels = 2; 1922 ipcm->tram_start = 0; 1923 ipcm->buffer_size = (64 * 1024) / 2; 1924 ipcm->gpr_size = gpr++; 1925 ipcm->gpr_ptr = gpr++; 1926 ipcm->gpr_count = gpr++; 1927 ipcm->gpr_tmpcount = gpr++; 1928 ipcm->gpr_trigger = gpr++; 1929 ipcm->gpr_running = gpr++; 1930 ipcm->etram[0] = 0; 1931 ipcm->etram[1] = 1; 1932 1933 gpr_map[gpr + 0] = 0xfffff000; 1934 gpr_map[gpr + 1] = 0xffff0000; 1935 gpr_map[gpr + 2] = 0x70000000; 1936 gpr_map[gpr + 3] = 0x00000007; 1937 gpr_map[gpr + 4] = 0x001f << 11; 1938 gpr_map[gpr + 5] = 0x001c << 11; 1939 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */ 1940 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */ 1941 gpr_map[gpr + 8] = 0x2000000 + (2<<11); 1942 gpr_map[gpr + 9] = 0x4000000 + (2<<11); 1943 gpr_map[gpr + 10] = 1<<11; 1944 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */ 1945 gpr_map[gpr + 12] = 0; 1946 1947 /* if the trigger flag is not set, skip */ 1948 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000); 1949 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6)); 1950 /* if the running flag is set, we're running */ 1951 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000); 1952 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004); 1953 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */ 1954 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000); 1955 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5)); 1956 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7)); 1957 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000); 1958 1959 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001); 1960 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000); 1961 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11)); 1962 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000); 1963 1964 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000); 1965 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1966 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1967 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1968 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2)); 1969 1970 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000); 1971 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1972 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1973 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1974 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2)); 1975 1976 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000); 1977 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size)); 1978 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001); 1979 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000); 1980 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000); 1981 1982 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000); 1983 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1984 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000); 1985 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000); 1986 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000); 1987 1988 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001); 1989 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002); 1990 1991 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff); 1992 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff); 1993 1994 /* 24: */ 1995 gpr += 13; 1996 1997 /* Wave Playback Volume */ 1998 for (z = 0; z < 2; z++) 1999 VOLUME(icode, &ptr, playback + z, z, gpr + z); 2000 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100); 2001 gpr += 2; 2002 2003 /* Wave Surround Playback Volume */ 2004 for (z = 0; z < 2; z++) 2005 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z); 2006 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0); 2007 gpr += 2; 2008 2009 /* Wave Center/LFE Playback Volume */ 2010 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000); 2011 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002); 2012 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr); 2013 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0); 2014 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr); 2015 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0); 2016 2017 /* Wave Capture Volume + Switch */ 2018 for (z = 0; z < 2; z++) { 2019 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z); 2020 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z); 2021 } 2022 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0); 2023 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0); 2024 gpr += 4; 2025 2026 /* Synth Playback Volume */ 2027 for (z = 0; z < 2; z++) 2028 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z); 2029 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100); 2030 gpr += 2; 2031 2032 /* Synth Capture Volume + Switch */ 2033 for (z = 0; z < 2; z++) { 2034 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z); 2035 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2036 } 2037 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0); 2038 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0); 2039 gpr += 4; 2040 2041 /* Surround Digital Playback Volume (renamed later without Digital) */ 2042 for (z = 0; z < 2; z++) 2043 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z); 2044 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100); 2045 gpr += 2; 2046 2047 /* Surround Capture Volume + Switch */ 2048 for (z = 0; z < 2; z++) { 2049 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z); 2050 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2051 } 2052 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0); 2053 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0); 2054 gpr += 4; 2055 2056 /* Center Playback Volume (renamed later without Digital) */ 2057 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr); 2058 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100); 2059 2060 /* LFE Playback Volume + Switch (renamed later without Digital) */ 2061 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr); 2062 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100); 2063 2064 /* Front Playback Volume */ 2065 for (z = 0; z < 2; z++) 2066 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z); 2067 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100); 2068 gpr += 2; 2069 2070 /* Front Capture Volume + Switch */ 2071 for (z = 0; z < 2; z++) { 2072 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2); 2073 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2074 } 2075 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0); 2076 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0); 2077 gpr += 3; 2078 2079 /* 2080 * Process inputs 2081 */ 2082 2083 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) { 2084 /* AC'97 Playback Volume */ 2085 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++; 2086 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++; 2087 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0); 2088 /* AC'97 Capture Volume */ 2089 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++; 2090 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++; 2091 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100); 2092 } 2093 2094 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) { 2095 /* IEC958 TTL Playback Volume */ 2096 for (z = 0; z < 2; z++) 2097 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z); 2098 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0); 2099 gpr += 2; 2100 2101 /* IEC958 TTL Capture Volume + Switch */ 2102 for (z = 0; z < 2; z++) { 2103 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z); 2104 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2105 } 2106 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0); 2107 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0); 2108 gpr += 4; 2109 } 2110 2111 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) { 2112 /* Zoom Video Playback Volume */ 2113 for (z = 0; z < 2; z++) 2114 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z); 2115 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0); 2116 gpr += 2; 2117 2118 /* Zoom Video Capture Volume + Switch */ 2119 for (z = 0; z < 2; z++) { 2120 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z); 2121 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2122 } 2123 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0); 2124 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0); 2125 gpr += 4; 2126 } 2127 2128 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) { 2129 /* IEC958 Optical Playback Volume */ 2130 for (z = 0; z < 2; z++) 2131 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z); 2132 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0); 2133 gpr += 2; 2134 2135 /* IEC958 Optical Capture Volume */ 2136 for (z = 0; z < 2; z++) { 2137 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z); 2138 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2139 } 2140 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0); 2141 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0); 2142 gpr += 4; 2143 } 2144 2145 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) { 2146 /* Line LiveDrive Playback Volume */ 2147 for (z = 0; z < 2; z++) 2148 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z); 2149 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0); 2150 gpr += 2; 2151 2152 /* Line LiveDrive Capture Volume + Switch */ 2153 for (z = 0; z < 2; z++) { 2154 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z); 2155 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2156 } 2157 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0); 2158 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0); 2159 gpr += 4; 2160 } 2161 2162 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) { 2163 /* IEC958 Coax Playback Volume */ 2164 for (z = 0; z < 2; z++) 2165 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z); 2166 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0); 2167 gpr += 2; 2168 2169 /* IEC958 Coax Capture Volume + Switch */ 2170 for (z = 0; z < 2; z++) { 2171 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z); 2172 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2173 } 2174 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0); 2175 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0); 2176 gpr += 4; 2177 } 2178 2179 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) { 2180 /* Line LiveDrive Playback Volume */ 2181 for (z = 0; z < 2; z++) 2182 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z); 2183 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0); 2184 controls[i-1].id.index = 1; 2185 gpr += 2; 2186 2187 /* Line LiveDrive Capture Volume */ 2188 for (z = 0; z < 2; z++) { 2189 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z); 2190 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2191 } 2192 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0); 2193 controls[i-1].id.index = 1; 2194 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0); 2195 controls[i-1].id.index = 1; 2196 gpr += 4; 2197 } 2198 2199 /* 2200 * Process tone control 2201 */ 2202 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */ 2203 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */ 2204 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */ 2205 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */ 2206 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */ 2207 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */ 2208 2209 ctl = &controls[i + 0]; 2210 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 2211 strcpy(ctl->id.name, "Tone Control - Bass"); 2212 ctl->vcount = 2; 2213 ctl->count = 10; 2214 ctl->min = 0; 2215 ctl->max = 40; 2216 ctl->value[0] = ctl->value[1] = 20; 2217 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2218 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 2219 ctl = &controls[i + 1]; 2220 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 2221 strcpy(ctl->id.name, "Tone Control - Treble"); 2222 ctl->vcount = 2; 2223 ctl->count = 10; 2224 ctl->min = 0; 2225 ctl->max = 40; 2226 ctl->value[0] = ctl->value[1] = 20; 2227 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2228 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 2229 2230 #define BASS_GPR 0x8c 2231 #define TREBLE_GPR 0x96 2232 2233 for (z = 0; z < 5; z++) { 2234 int j; 2235 for (j = 0; j < 2; j++) { 2236 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j; 2237 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j; 2238 } 2239 } 2240 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */ 2241 int j, k, l, d; 2242 for (j = 0; j < 2; j++) { /* left/right */ 2243 k = 0xa0 + (z * 8) + (j * 4); 2244 l = 0xd0 + (z * 8) + (j * 4); 2245 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j; 2246 2247 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j)); 2248 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j)); 2249 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j)); 2250 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j)); 2251 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j)); 2252 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000); 2253 2254 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j)); 2255 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j)); 2256 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j)); 2257 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j)); 2258 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j)); 2259 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010); 2260 2261 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000); 2262 2263 if (z == 2) /* center */ 2264 break; 2265 } 2266 } 2267 i += 2; 2268 2269 #undef BASS_GPR 2270 #undef TREBLE_GPR 2271 2272 for (z = 0; z < 6; z++) { 2273 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0); 2274 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0); 2275 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2276 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2277 } 2278 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0); 2279 gpr += 2; 2280 2281 /* 2282 * Process outputs 2283 */ 2284 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) { 2285 /* AC'97 Playback Volume */ 2286 2287 for (z = 0; z < 2; z++) 2288 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000); 2289 } 2290 2291 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) { 2292 /* IEC958 Optical Raw Playback Switch */ 2293 2294 for (z = 0; z < 2; z++) { 2295 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z); 2296 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 2297 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1); 2298 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2299 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 2300 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2301 #endif 2302 } 2303 2304 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 2305 gpr += 2; 2306 } 2307 2308 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) { 2309 /* Headphone Playback Volume */ 2310 2311 for (z = 0; z < 2; z++) { 2312 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z); 2313 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z); 2314 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1); 2315 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2316 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z); 2317 } 2318 2319 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0); 2320 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */ 2321 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0); 2322 controls[i-1].id.index = 1; 2323 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0); 2324 controls[i-1].id.index = 1; 2325 2326 gpr += 4; 2327 } 2328 2329 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R))) 2330 for (z = 0; z < 2; z++) 2331 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000); 2332 2333 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R))) 2334 for (z = 0; z < 2; z++) 2335 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000); 2336 2337 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) { 2338 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2339 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000); 2340 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000); 2341 #else 2342 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000); 2343 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000); 2344 #endif 2345 } 2346 2347 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) { 2348 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2349 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000); 2350 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000); 2351 #else 2352 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000); 2353 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000); 2354 #endif 2355 } 2356 2357 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT 2358 for (z = 0; z < 2; z++) 2359 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000); 2360 #endif 2361 2362 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP)) 2363 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000); 2364 2365 /* EFX capture - capture the 16 EXTINS */ 2366 if (emu->card_capabilities->sblive51) { 2367 /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER 2368 * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording. 2369 * 2370 * Since only 14 of the 16 EXTINs are used, this is not a big problem. 2371 * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture 2372 * 0 and 3, then the rest of the EXTINs to the corresponding FX capture 2373 * channel. Multitrack recorders will still see the center/lfe output signal 2374 * on the second and third channels. 2375 */ 2376 OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0)); 2377 OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1)); 2378 OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2)); 2379 OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3)); 2380 for (z = 4; z < 14; z++) 2381 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2382 } else { 2383 for (z = 0; z < 16; z++) 2384 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2385 } 2386 2387 2388 if (gpr > tmp) { 2389 snd_BUG(); 2390 err = -EIO; 2391 goto __err; 2392 } 2393 if (i > SND_EMU10K1_GPR_CONTROLS) { 2394 snd_BUG(); 2395 err = -EIO; 2396 goto __err; 2397 } 2398 2399 /* clear remaining instruction memory */ 2400 while (ptr < 0x200) 2401 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000); 2402 2403 err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size); 2404 if (err < 0) 2405 goto __err; 2406 icode->gpr_add_control_count = i; 2407 icode->gpr_add_controls = controls; 2408 emu->support_tlv = 1; /* support TLV */ 2409 err = snd_emu10k1_icode_poke(emu, icode, true); 2410 emu->support_tlv = 0; /* clear again */ 2411 if (err >= 0) 2412 err = snd_emu10k1_ipcm_poke(emu, ipcm); 2413 __err: 2414 kfree(ipcm); 2415 __err_ipcm: 2416 kfree(controls); 2417 __err_ctrls: 2418 kfree(icode->gpr_map); 2419 __err_gpr: 2420 kfree(icode); 2421 return err; 2422 } 2423 2424 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 2425 { 2426 spin_lock_init(&emu->fx8010.irq_lock); 2427 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl); 2428 if (emu->audigy) 2429 return _snd_emu10k1_audigy_init_efx(emu); 2430 else 2431 return _snd_emu10k1_init_efx(emu); 2432 } 2433 2434 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu) 2435 { 2436 /* stop processor */ 2437 if (emu->audigy) 2438 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP); 2439 else 2440 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP); 2441 } 2442 2443 #if 0 /* FIXME: who use them? */ 2444 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output) 2445 { 2446 if (output < 0 || output >= 6) 2447 return -EINVAL; 2448 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1); 2449 return 0; 2450 } 2451 2452 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output) 2453 { 2454 if (output < 0 || output >= 6) 2455 return -EINVAL; 2456 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0); 2457 return 0; 2458 } 2459 #endif 2460 2461 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size) 2462 { 2463 u8 size_reg = 0; 2464 2465 /* size is in samples */ 2466 if (size != 0) { 2467 size = (size - 1) >> 13; 2468 2469 while (size) { 2470 size >>= 1; 2471 size_reg++; 2472 } 2473 size = 0x2000 << size_reg; 2474 } 2475 if ((emu->fx8010.etram_pages.bytes / 2) == size) 2476 return 0; 2477 spin_lock_irq(&emu->emu_lock); 2478 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2479 spin_unlock_irq(&emu->emu_lock); 2480 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 2481 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 2482 if (emu->fx8010.etram_pages.area != NULL) { 2483 snd_dma_free_pages(&emu->fx8010.etram_pages); 2484 emu->fx8010.etram_pages.area = NULL; 2485 emu->fx8010.etram_pages.bytes = 0; 2486 } 2487 2488 if (size > 0) { 2489 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev, 2490 size * 2, &emu->fx8010.etram_pages) < 0) 2491 return -ENOMEM; 2492 memset(emu->fx8010.etram_pages.area, 0, size * 2); 2493 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2494 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2495 spin_lock_irq(&emu->emu_lock); 2496 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2497 spin_unlock_irq(&emu->emu_lock); 2498 } 2499 2500 return 0; 2501 } 2502 2503 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file) 2504 { 2505 return 0; 2506 } 2507 2508 static void copy_string(char *dst, const char *src, const char *null, int idx) 2509 { 2510 if (src == NULL) 2511 sprintf(dst, "%s %02X", null, idx); 2512 else 2513 strcpy(dst, src); 2514 } 2515 2516 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu, 2517 struct snd_emu10k1_fx8010_info *info) 2518 { 2519 const char * const *fxbus, * const *extin, * const *extout; 2520 unsigned short extin_mask, extout_mask; 2521 int res; 2522 2523 info->internal_tram_size = emu->fx8010.itram_size; 2524 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2; 2525 fxbus = fxbuses; 2526 extin = emu->audigy ? audigy_ins : creative_ins; 2527 extout = emu->audigy ? audigy_outs : creative_outs; 2528 extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask; 2529 extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask; 2530 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) { 2531 copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res); 2532 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res); 2533 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2534 } 2535 for (res = 16; res < 32; res++, extout++) 2536 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2537 info->gpr_controls = emu->fx8010.gpr_count; 2538 } 2539 2540 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg) 2541 { 2542 struct snd_emu10k1 *emu = hw->private_data; 2543 struct snd_emu10k1_fx8010_info *info; 2544 struct snd_emu10k1_fx8010_code *icode; 2545 struct snd_emu10k1_fx8010_pcm_rec *ipcm; 2546 unsigned int addr; 2547 void __user *argp = (void __user *)arg; 2548 int res; 2549 2550 switch (cmd) { 2551 case SNDRV_EMU10K1_IOCTL_PVERSION: 2552 emu->support_tlv = 1; 2553 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp); 2554 case SNDRV_EMU10K1_IOCTL_INFO: 2555 info = kzalloc(sizeof(*info), GFP_KERNEL); 2556 if (!info) 2557 return -ENOMEM; 2558 snd_emu10k1_fx8010_info(emu, info); 2559 if (copy_to_user(argp, info, sizeof(*info))) { 2560 kfree(info); 2561 return -EFAULT; 2562 } 2563 kfree(info); 2564 return 0; 2565 case SNDRV_EMU10K1_IOCTL_CODE_POKE: 2566 if (!capable(CAP_SYS_ADMIN)) 2567 return -EPERM; 2568 2569 icode = memdup_user(argp, sizeof(*icode)); 2570 if (IS_ERR(icode)) 2571 return PTR_ERR(icode); 2572 res = snd_emu10k1_icode_poke(emu, icode, false); 2573 kfree(icode); 2574 return res; 2575 case SNDRV_EMU10K1_IOCTL_CODE_PEEK: 2576 icode = memdup_user(argp, sizeof(*icode)); 2577 if (IS_ERR(icode)) 2578 return PTR_ERR(icode); 2579 res = snd_emu10k1_icode_peek(emu, icode); 2580 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) { 2581 kfree(icode); 2582 return -EFAULT; 2583 } 2584 kfree(icode); 2585 return res; 2586 case SNDRV_EMU10K1_IOCTL_PCM_POKE: 2587 ipcm = memdup_user(argp, sizeof(*ipcm)); 2588 if (IS_ERR(ipcm)) 2589 return PTR_ERR(ipcm); 2590 res = snd_emu10k1_ipcm_poke(emu, ipcm); 2591 kfree(ipcm); 2592 return res; 2593 case SNDRV_EMU10K1_IOCTL_PCM_PEEK: 2594 ipcm = memdup_user(argp, sizeof(*ipcm)); 2595 if (IS_ERR(ipcm)) 2596 return PTR_ERR(ipcm); 2597 res = snd_emu10k1_ipcm_peek(emu, ipcm); 2598 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) { 2599 kfree(ipcm); 2600 return -EFAULT; 2601 } 2602 kfree(ipcm); 2603 return res; 2604 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP: 2605 if (!capable(CAP_SYS_ADMIN)) 2606 return -EPERM; 2607 if (get_user(addr, (unsigned int __user *)argp)) 2608 return -EFAULT; 2609 mutex_lock(&emu->fx8010.lock); 2610 res = snd_emu10k1_fx8010_tram_setup(emu, addr); 2611 mutex_unlock(&emu->fx8010.lock); 2612 return res; 2613 case SNDRV_EMU10K1_IOCTL_STOP: 2614 if (!capable(CAP_SYS_ADMIN)) 2615 return -EPERM; 2616 if (emu->audigy) 2617 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2618 else 2619 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2620 return 0; 2621 case SNDRV_EMU10K1_IOCTL_CONTINUE: 2622 if (!capable(CAP_SYS_ADMIN)) 2623 return -EPERM; 2624 if (emu->audigy) 2625 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0); 2626 else 2627 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0); 2628 return 0; 2629 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER: 2630 if (!capable(CAP_SYS_ADMIN)) 2631 return -EPERM; 2632 if (emu->audigy) 2633 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC); 2634 else 2635 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC); 2636 udelay(10); 2637 if (emu->audigy) 2638 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2639 else 2640 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2641 return 0; 2642 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP: 2643 if (!capable(CAP_SYS_ADMIN)) 2644 return -EPERM; 2645 if (get_user(addr, (unsigned int __user *)argp)) 2646 return -EFAULT; 2647 if (emu->audigy) { 2648 if (addr > A_DBG_STEP_ADDR) 2649 return -EINVAL; 2650 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2651 udelay(10); 2652 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr); 2653 } else { 2654 if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR) 2655 return -EINVAL; 2656 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2657 udelay(10); 2658 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr); 2659 } 2660 return 0; 2661 case SNDRV_EMU10K1_IOCTL_DBG_READ: 2662 if (emu->audigy) 2663 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0); 2664 else 2665 addr = snd_emu10k1_ptr_read(emu, DBG, 0); 2666 if (put_user(addr, (unsigned int __user *)argp)) 2667 return -EFAULT; 2668 return 0; 2669 } 2670 return -ENOTTY; 2671 } 2672 2673 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file) 2674 { 2675 return 0; 2676 } 2677 2678 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device) 2679 { 2680 struct snd_hwdep *hw; 2681 int err; 2682 2683 err = snd_hwdep_new(emu->card, "FX8010", device, &hw); 2684 if (err < 0) 2685 return err; 2686 strcpy(hw->name, "EMU10K1 (FX8010)"); 2687 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1; 2688 hw->ops.open = snd_emu10k1_fx8010_open; 2689 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl; 2690 hw->ops.release = snd_emu10k1_fx8010_release; 2691 hw->private_data = emu; 2692 return 0; 2693 } 2694 2695 #ifdef CONFIG_PM_SLEEP 2696 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu) 2697 { 2698 int len; 2699 2700 len = emu->audigy ? 0x200 : 0x100; 2701 emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL); 2702 if (! emu->saved_gpr) 2703 return -ENOMEM; 2704 len = emu->audigy ? 0x100 : 0xa0; 2705 emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL); 2706 emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL); 2707 if (! emu->tram_val_saved || ! emu->tram_addr_saved) 2708 return -ENOMEM; 2709 len = emu->audigy ? 2 * 1024 : 2 * 512; 2710 emu->saved_icode = vmalloc(array_size(len, 4)); 2711 if (! emu->saved_icode) 2712 return -ENOMEM; 2713 return 0; 2714 } 2715 2716 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu) 2717 { 2718 kfree(emu->saved_gpr); 2719 kfree(emu->tram_val_saved); 2720 kfree(emu->tram_addr_saved); 2721 vfree(emu->saved_icode); 2722 } 2723 2724 /* 2725 * save/restore GPR, TRAM and codes 2726 */ 2727 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu) 2728 { 2729 int i, len; 2730 2731 len = emu->audigy ? 0x200 : 0x100; 2732 for (i = 0; i < len; i++) 2733 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0); 2734 2735 len = emu->audigy ? 0x100 : 0xa0; 2736 for (i = 0; i < len; i++) { 2737 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0); 2738 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0); 2739 if (emu->audigy) { 2740 emu->tram_addr_saved[i] >>= 12; 2741 emu->tram_addr_saved[i] |= 2742 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20; 2743 } 2744 } 2745 2746 len = emu->audigy ? 2 * 1024 : 2 * 512; 2747 for (i = 0; i < len; i++) 2748 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i); 2749 } 2750 2751 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu) 2752 { 2753 int i, len; 2754 2755 /* set up TRAM */ 2756 if (emu->fx8010.etram_pages.bytes > 0) { 2757 unsigned size, size_reg = 0; 2758 size = emu->fx8010.etram_pages.bytes / 2; 2759 size = (size - 1) >> 13; 2760 while (size) { 2761 size >>= 1; 2762 size_reg++; 2763 } 2764 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2765 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2766 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2767 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2768 } 2769 2770 if (emu->audigy) 2771 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 2772 else 2773 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 2774 2775 len = emu->audigy ? 0x200 : 0x100; 2776 for (i = 0; i < len; i++) 2777 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]); 2778 2779 len = emu->audigy ? 0x100 : 0xa0; 2780 for (i = 0; i < len; i++) { 2781 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0, 2782 emu->tram_val_saved[i]); 2783 if (! emu->audigy) 2784 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2785 emu->tram_addr_saved[i]); 2786 else { 2787 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2788 emu->tram_addr_saved[i] << 12); 2789 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2790 emu->tram_addr_saved[i] >> 20); 2791 } 2792 } 2793 2794 len = emu->audigy ? 2 * 1024 : 2 * 512; 2795 for (i = 0; i < len; i++) 2796 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]); 2797 2798 /* start FX processor when the DSP code is updated */ 2799 if (emu->audigy) 2800 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2801 else 2802 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2803 } 2804 #endif 2805