1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for effect processor FX8010 6 * 7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk> 8 * Added EMU 1010 support. 9 * 10 * BUGS: 11 * -- 12 * 13 * TODO: 14 * -- 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/capability.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/vmalloc.h> 22 #include <linux/init.h> 23 #include <linux/mutex.h> 24 #include <linux/moduleparam.h> 25 #include <linux/nospec.h> 26 27 #include <sound/core.h> 28 #include <sound/tlv.h> 29 #include <sound/emu10k1.h> 30 31 #if 0 /* for testing purposes - digital out -> capture */ 32 #define EMU10K1_CAPTURE_DIGITAL_OUT 33 #endif 34 #if 0 /* for testing purposes - set S/PDIF to AC3 output */ 35 #define EMU10K1_SET_AC3_IEC958 36 #endif 37 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */ 38 #define EMU10K1_CENTER_LFE_FROM_FRONT 39 #endif 40 41 static bool high_res_gpr_volume; 42 module_param(high_res_gpr_volume, bool, 0444); 43 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range."); 44 45 /* 46 * Tables 47 */ 48 49 static char *fxbuses[16] = { 50 /* 0x00 */ "PCM Left", 51 /* 0x01 */ "PCM Right", 52 /* 0x02 */ "PCM Surround Left", 53 /* 0x03 */ "PCM Surround Right", 54 /* 0x04 */ "MIDI Left", 55 /* 0x05 */ "MIDI Right", 56 /* 0x06 */ "Center", 57 /* 0x07 */ "LFE", 58 /* 0x08 */ NULL, 59 /* 0x09 */ NULL, 60 /* 0x0a */ NULL, 61 /* 0x0b */ NULL, 62 /* 0x0c */ "MIDI Reverb", 63 /* 0x0d */ "MIDI Chorus", 64 /* 0x0e */ NULL, 65 /* 0x0f */ NULL 66 }; 67 68 static char *creative_ins[16] = { 69 /* 0x00 */ "AC97 Left", 70 /* 0x01 */ "AC97 Right", 71 /* 0x02 */ "TTL IEC958 Left", 72 /* 0x03 */ "TTL IEC958 Right", 73 /* 0x04 */ "Zoom Video Left", 74 /* 0x05 */ "Zoom Video Right", 75 /* 0x06 */ "Optical IEC958 Left", 76 /* 0x07 */ "Optical IEC958 Right", 77 /* 0x08 */ "Line/Mic 1 Left", 78 /* 0x09 */ "Line/Mic 1 Right", 79 /* 0x0a */ "Coaxial IEC958 Left", 80 /* 0x0b */ "Coaxial IEC958 Right", 81 /* 0x0c */ "Line/Mic 2 Left", 82 /* 0x0d */ "Line/Mic 2 Right", 83 /* 0x0e */ NULL, 84 /* 0x0f */ NULL 85 }; 86 87 static char *audigy_ins[16] = { 88 /* 0x00 */ "AC97 Left", 89 /* 0x01 */ "AC97 Right", 90 /* 0x02 */ "Audigy CD Left", 91 /* 0x03 */ "Audigy CD Right", 92 /* 0x04 */ "Optical IEC958 Left", 93 /* 0x05 */ "Optical IEC958 Right", 94 /* 0x06 */ NULL, 95 /* 0x07 */ NULL, 96 /* 0x08 */ "Line/Mic 2 Left", 97 /* 0x09 */ "Line/Mic 2 Right", 98 /* 0x0a */ "SPDIF Left", 99 /* 0x0b */ "SPDIF Right", 100 /* 0x0c */ "Aux2 Left", 101 /* 0x0d */ "Aux2 Right", 102 /* 0x0e */ NULL, 103 /* 0x0f */ NULL 104 }; 105 106 static char *creative_outs[32] = { 107 /* 0x00 */ "AC97 Left", 108 /* 0x01 */ "AC97 Right", 109 /* 0x02 */ "Optical IEC958 Left", 110 /* 0x03 */ "Optical IEC958 Right", 111 /* 0x04 */ "Center", 112 /* 0x05 */ "LFE", 113 /* 0x06 */ "Headphone Left", 114 /* 0x07 */ "Headphone Right", 115 /* 0x08 */ "Surround Left", 116 /* 0x09 */ "Surround Right", 117 /* 0x0a */ "PCM Capture Left", 118 /* 0x0b */ "PCM Capture Right", 119 /* 0x0c */ "MIC Capture", 120 /* 0x0d */ "AC97 Surround Left", 121 /* 0x0e */ "AC97 Surround Right", 122 /* 0x0f */ NULL, 123 /* 0x10 */ NULL, 124 /* 0x11 */ "Analog Center", 125 /* 0x12 */ "Analog LFE", 126 /* 0x13 */ NULL, 127 /* 0x14 */ NULL, 128 /* 0x15 */ NULL, 129 /* 0x16 */ NULL, 130 /* 0x17 */ NULL, 131 /* 0x18 */ NULL, 132 /* 0x19 */ NULL, 133 /* 0x1a */ NULL, 134 /* 0x1b */ NULL, 135 /* 0x1c */ NULL, 136 /* 0x1d */ NULL, 137 /* 0x1e */ NULL, 138 /* 0x1f */ NULL, 139 }; 140 141 static char *audigy_outs[32] = { 142 /* 0x00 */ "Digital Front Left", 143 /* 0x01 */ "Digital Front Right", 144 /* 0x02 */ "Digital Center", 145 /* 0x03 */ "Digital LEF", 146 /* 0x04 */ "Headphone Left", 147 /* 0x05 */ "Headphone Right", 148 /* 0x06 */ "Digital Rear Left", 149 /* 0x07 */ "Digital Rear Right", 150 /* 0x08 */ "Front Left", 151 /* 0x09 */ "Front Right", 152 /* 0x0a */ "Center", 153 /* 0x0b */ "LFE", 154 /* 0x0c */ NULL, 155 /* 0x0d */ NULL, 156 /* 0x0e */ "Rear Left", 157 /* 0x0f */ "Rear Right", 158 /* 0x10 */ "AC97 Front Left", 159 /* 0x11 */ "AC97 Front Right", 160 /* 0x12 */ "ADC Capture Left", 161 /* 0x13 */ "ADC Capture Right", 162 /* 0x14 */ NULL, 163 /* 0x15 */ NULL, 164 /* 0x16 */ NULL, 165 /* 0x17 */ NULL, 166 /* 0x18 */ NULL, 167 /* 0x19 */ NULL, 168 /* 0x1a */ NULL, 169 /* 0x1b */ NULL, 170 /* 0x1c */ NULL, 171 /* 0x1d */ NULL, 172 /* 0x1e */ NULL, 173 /* 0x1f */ NULL, 174 }; 175 176 static const u32 bass_table[41][5] = { 177 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 }, 178 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d }, 179 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee }, 180 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c }, 181 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b }, 182 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 }, 183 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f }, 184 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 }, 185 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 }, 186 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 }, 187 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 }, 188 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be }, 189 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b }, 190 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c }, 191 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b }, 192 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 }, 193 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a }, 194 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 }, 195 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 }, 196 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e }, 197 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee }, 198 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 }, 199 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 }, 200 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 }, 201 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 }, 202 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e }, 203 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 }, 204 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 }, 205 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 }, 206 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 }, 207 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 }, 208 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca }, 209 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 }, 210 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 }, 211 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 }, 212 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 }, 213 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a }, 214 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f }, 215 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 }, 216 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 }, 217 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 } 218 }; 219 220 static const u32 treble_table[41][5] = { 221 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 }, 222 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 }, 223 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 }, 224 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca }, 225 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 }, 226 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 }, 227 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 }, 228 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 }, 229 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 }, 230 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df }, 231 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff }, 232 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 }, 233 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c }, 234 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 }, 235 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 }, 236 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 }, 237 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 }, 238 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d }, 239 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 }, 240 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 }, 241 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f }, 242 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb }, 243 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 }, 244 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 }, 245 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd }, 246 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 }, 247 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad }, 248 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 }, 249 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 }, 250 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c }, 251 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 }, 252 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 }, 253 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 }, 254 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 }, 255 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 }, 256 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 }, 257 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d }, 258 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b }, 259 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 }, 260 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd }, 261 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 } 262 }; 263 264 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */ 265 static const u32 db_table[101] = { 266 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540, 267 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8, 268 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1, 269 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0, 270 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9, 271 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb, 272 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005, 273 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d, 274 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd, 275 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8, 276 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481, 277 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333, 278 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d, 279 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6, 280 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d, 281 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf, 282 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038, 283 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a, 284 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea, 285 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272, 286 0x7fffffff, 287 }; 288 289 /* EMU10k1/EMU10k2 DSP control db gain */ 290 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1); 291 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0); 292 293 /* EMU10K1 bass/treble db gain */ 294 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0); 295 296 static const u32 onoff_table[2] = { 297 0x00000000, 0x00000001 298 }; 299 300 /* 301 * controls 302 */ 303 304 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 305 { 306 struct snd_emu10k1_fx8010_ctl *ctl = 307 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 308 309 if (ctl->min == 0 && ctl->max == 1) 310 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 311 else 312 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 313 uinfo->count = ctl->vcount; 314 uinfo->value.integer.min = ctl->min; 315 uinfo->value.integer.max = ctl->max; 316 return 0; 317 } 318 319 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 320 { 321 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 322 struct snd_emu10k1_fx8010_ctl *ctl = 323 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 324 unsigned long flags; 325 unsigned int i; 326 327 spin_lock_irqsave(&emu->reg_lock, flags); 328 for (i = 0; i < ctl->vcount; i++) 329 ucontrol->value.integer.value[i] = ctl->value[i]; 330 spin_unlock_irqrestore(&emu->reg_lock, flags); 331 return 0; 332 } 333 334 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 335 { 336 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 337 struct snd_emu10k1_fx8010_ctl *ctl = 338 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 339 unsigned long flags; 340 unsigned int nval, val; 341 unsigned int i, j; 342 int change = 0; 343 344 spin_lock_irqsave(&emu->reg_lock, flags); 345 for (i = 0; i < ctl->vcount; i++) { 346 nval = ucontrol->value.integer.value[i]; 347 if (nval < ctl->min) 348 nval = ctl->min; 349 if (nval > ctl->max) 350 nval = ctl->max; 351 if (nval != ctl->value[i]) 352 change = 1; 353 val = ctl->value[i] = nval; 354 switch (ctl->translation) { 355 case EMU10K1_GPR_TRANSLATION_NONE: 356 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val); 357 break; 358 case EMU10K1_GPR_TRANSLATION_TABLE100: 359 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]); 360 break; 361 case EMU10K1_GPR_TRANSLATION_BASS: 362 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 363 change = -EIO; 364 goto __error; 365 } 366 for (j = 0; j < 5; j++) 367 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]); 368 break; 369 case EMU10K1_GPR_TRANSLATION_TREBLE: 370 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 371 change = -EIO; 372 goto __error; 373 } 374 for (j = 0; j < 5; j++) 375 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]); 376 break; 377 case EMU10K1_GPR_TRANSLATION_ONOFF: 378 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]); 379 break; 380 } 381 } 382 __error: 383 spin_unlock_irqrestore(&emu->reg_lock, flags); 384 return change; 385 } 386 387 /* 388 * Interrupt handler 389 */ 390 391 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu) 392 { 393 struct snd_emu10k1_fx8010_irq *irq, *nirq; 394 395 irq = emu->fx8010.irq_handlers; 396 while (irq) { 397 nirq = irq->next; /* irq ptr can be removed from list */ 398 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) { 399 if (irq->handler) 400 irq->handler(emu, irq->private_data); 401 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1); 402 } 403 irq = nirq; 404 } 405 } 406 407 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, 408 snd_fx8010_irq_handler_t *handler, 409 unsigned char gpr_running, 410 void *private_data, 411 struct snd_emu10k1_fx8010_irq *irq) 412 { 413 unsigned long flags; 414 415 irq->handler = handler; 416 irq->gpr_running = gpr_running; 417 irq->private_data = private_data; 418 irq->next = NULL; 419 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 420 if (emu->fx8010.irq_handlers == NULL) { 421 emu->fx8010.irq_handlers = irq; 422 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt; 423 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE); 424 } else { 425 irq->next = emu->fx8010.irq_handlers; 426 emu->fx8010.irq_handlers = irq; 427 } 428 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 429 return 0; 430 } 431 432 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, 433 struct snd_emu10k1_fx8010_irq *irq) 434 { 435 struct snd_emu10k1_fx8010_irq *tmp; 436 unsigned long flags; 437 438 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 439 if ((tmp = emu->fx8010.irq_handlers) == irq) { 440 emu->fx8010.irq_handlers = tmp->next; 441 if (emu->fx8010.irq_handlers == NULL) { 442 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE); 443 emu->dsp_interrupt = NULL; 444 } 445 } else { 446 while (tmp && tmp->next != irq) 447 tmp = tmp->next; 448 if (tmp) 449 tmp->next = tmp->next->next; 450 } 451 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 452 return 0; 453 } 454 455 /************************************************************************* 456 * EMU10K1 effect manager 457 *************************************************************************/ 458 459 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode, 460 unsigned int *ptr, 461 u32 op, u32 r, u32 a, u32 x, u32 y) 462 { 463 u_int32_t *code; 464 if (snd_BUG_ON(*ptr >= 512)) 465 return; 466 code = (u_int32_t __force *)icode->code + (*ptr) * 2; 467 set_bit(*ptr, icode->code_valid); 468 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff); 469 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff); 470 (*ptr)++; 471 } 472 473 #define OP(icode, ptr, op, r, a, x, y) \ 474 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y) 475 476 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode, 477 unsigned int *ptr, 478 u32 op, u32 r, u32 a, u32 x, u32 y) 479 { 480 u_int32_t *code; 481 if (snd_BUG_ON(*ptr >= 1024)) 482 return; 483 code = (u_int32_t __force *)icode->code + (*ptr) * 2; 484 set_bit(*ptr, icode->code_valid); 485 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff); 486 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff); 487 (*ptr)++; 488 } 489 490 #define A_OP(icode, ptr, op, r, a, x, y) \ 491 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y) 492 493 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data) 494 { 495 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 496 snd_emu10k1_ptr_write(emu, pc, 0, data); 497 } 498 499 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc) 500 { 501 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 502 return snd_emu10k1_ptr_read(emu, pc, 0); 503 } 504 505 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu, 506 struct snd_emu10k1_fx8010_code *icode, 507 bool in_kernel) 508 { 509 int gpr; 510 u32 val; 511 512 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 513 if (!test_bit(gpr, icode->gpr_valid)) 514 continue; 515 if (in_kernel) 516 val = *(__force u32 *)&icode->gpr_map[gpr]; 517 else if (get_user(val, &icode->gpr_map[gpr])) 518 return -EFAULT; 519 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val); 520 } 521 return 0; 522 } 523 524 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu, 525 struct snd_emu10k1_fx8010_code *icode) 526 { 527 int gpr; 528 u32 val; 529 530 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 531 set_bit(gpr, icode->gpr_valid); 532 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0); 533 if (put_user(val, &icode->gpr_map[gpr])) 534 return -EFAULT; 535 } 536 return 0; 537 } 538 539 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu, 540 struct snd_emu10k1_fx8010_code *icode, 541 bool in_kernel) 542 { 543 int tram; 544 u32 addr, val; 545 546 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 547 if (!test_bit(tram, icode->tram_valid)) 548 continue; 549 if (in_kernel) { 550 val = *(__force u32 *)&icode->tram_data_map[tram]; 551 addr = *(__force u32 *)&icode->tram_addr_map[tram]; 552 } else { 553 if (get_user(val, &icode->tram_data_map[tram]) || 554 get_user(addr, &icode->tram_addr_map[tram])) 555 return -EFAULT; 556 } 557 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val); 558 if (!emu->audigy) { 559 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr); 560 } else { 561 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12); 562 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20); 563 } 564 } 565 return 0; 566 } 567 568 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu, 569 struct snd_emu10k1_fx8010_code *icode) 570 { 571 int tram; 572 u32 val, addr; 573 574 memset(icode->tram_valid, 0, sizeof(icode->tram_valid)); 575 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 576 set_bit(tram, icode->tram_valid); 577 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0); 578 if (!emu->audigy) { 579 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0); 580 } else { 581 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12; 582 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20; 583 } 584 if (put_user(val, &icode->tram_data_map[tram]) || 585 put_user(addr, &icode->tram_addr_map[tram])) 586 return -EFAULT; 587 } 588 return 0; 589 } 590 591 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu, 592 struct snd_emu10k1_fx8010_code *icode, 593 bool in_kernel) 594 { 595 u32 pc, lo, hi; 596 597 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 598 if (!test_bit(pc / 2, icode->code_valid)) 599 continue; 600 if (in_kernel) { 601 lo = *(__force u32 *)&icode->code[pc + 0]; 602 hi = *(__force u32 *)&icode->code[pc + 1]; 603 } else { 604 if (get_user(lo, &icode->code[pc + 0]) || 605 get_user(hi, &icode->code[pc + 1])) 606 return -EFAULT; 607 } 608 snd_emu10k1_efx_write(emu, pc + 0, lo); 609 snd_emu10k1_efx_write(emu, pc + 1, hi); 610 } 611 return 0; 612 } 613 614 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu, 615 struct snd_emu10k1_fx8010_code *icode) 616 { 617 u32 pc; 618 619 memset(icode->code_valid, 0, sizeof(icode->code_valid)); 620 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 621 set_bit(pc / 2, icode->code_valid); 622 if (put_user(snd_emu10k1_efx_read(emu, pc + 0), &icode->code[pc + 0])) 623 return -EFAULT; 624 if (put_user(snd_emu10k1_efx_read(emu, pc + 1), &icode->code[pc + 1])) 625 return -EFAULT; 626 } 627 return 0; 628 } 629 630 static struct snd_emu10k1_fx8010_ctl * 631 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, struct emu10k1_ctl_elem_id *id) 632 { 633 struct snd_emu10k1_fx8010_ctl *ctl; 634 struct snd_kcontrol *kcontrol; 635 636 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 637 kcontrol = ctl->kcontrol; 638 if (kcontrol->id.iface == id->iface && 639 !strcmp(kcontrol->id.name, id->name) && 640 kcontrol->id.index == id->index) 641 return ctl; 642 } 643 return NULL; 644 } 645 646 #define MAX_TLV_SIZE 256 647 648 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel) 649 { 650 unsigned int data[2]; 651 unsigned int *tlv; 652 653 if (!_tlv) 654 return NULL; 655 if (in_kernel) 656 memcpy(data, (__force void *)_tlv, sizeof(data)); 657 else if (copy_from_user(data, _tlv, sizeof(data))) 658 return NULL; 659 if (data[1] >= MAX_TLV_SIZE) 660 return NULL; 661 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL); 662 if (!tlv) 663 return NULL; 664 memcpy(tlv, data, sizeof(data)); 665 if (in_kernel) { 666 memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]); 667 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) { 668 kfree(tlv); 669 return NULL; 670 } 671 return tlv; 672 } 673 674 static int copy_gctl(struct snd_emu10k1 *emu, 675 struct snd_emu10k1_fx8010_control_gpr *gctl, 676 struct snd_emu10k1_fx8010_control_gpr __user *_gctl, 677 int idx, bool in_kernel) 678 { 679 struct snd_emu10k1_fx8010_control_old_gpr __user *octl; 680 681 if (emu->support_tlv) { 682 if (in_kernel) 683 memcpy(gctl, (__force void *)&_gctl[idx], sizeof(*gctl)); 684 else if (copy_from_user(gctl, &_gctl[idx], sizeof(*gctl))) 685 return -EFAULT; 686 return 0; 687 } 688 689 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl; 690 if (in_kernel) 691 memcpy(gctl, (__force void *)&octl[idx], sizeof(*octl)); 692 else if (copy_from_user(gctl, &octl[idx], sizeof(*octl))) 693 return -EFAULT; 694 gctl->tlv = NULL; 695 return 0; 696 } 697 698 static int copy_gctl_to_user(struct snd_emu10k1 *emu, 699 struct snd_emu10k1_fx8010_control_gpr __user *_gctl, 700 struct snd_emu10k1_fx8010_control_gpr *gctl, 701 int idx) 702 { 703 struct snd_emu10k1_fx8010_control_old_gpr __user *octl; 704 705 if (emu->support_tlv) 706 return copy_to_user(&_gctl[idx], gctl, sizeof(*gctl)); 707 708 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl; 709 return copy_to_user(&octl[idx], gctl, sizeof(*octl)); 710 } 711 712 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu, 713 struct snd_emu10k1_fx8010_code *icode, 714 bool in_kernel) 715 { 716 unsigned int i; 717 struct emu10k1_ctl_elem_id __user *_id; 718 struct emu10k1_ctl_elem_id id; 719 struct snd_emu10k1_fx8010_control_gpr *gctl; 720 int err; 721 722 _id = (__force struct emu10k1_ctl_elem_id __user *)icode->gpr_del_controls; 723 for (i = 0; i < icode->gpr_del_control_count; i++, _id++) { 724 if (in_kernel) 725 id = *(__force struct emu10k1_ctl_elem_id *)_id; 726 else if (copy_from_user(&id, _id, sizeof(id))) 727 return -EFAULT; 728 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL) 729 return -ENOENT; 730 } 731 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 732 if (! gctl) 733 return -ENOMEM; 734 err = 0; 735 for (i = 0; i < icode->gpr_add_control_count; i++) { 736 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 737 in_kernel)) { 738 err = -EFAULT; 739 goto __error; 740 } 741 if (snd_emu10k1_look_for_ctl(emu, &gctl->id)) 742 continue; 743 down_read(&emu->card->controls_rwsem); 744 if (snd_ctl_find_id(emu->card, 745 (struct snd_ctl_elem_id *)&gctl->id)) { 746 up_read(&emu->card->controls_rwsem); 747 err = -EEXIST; 748 goto __error; 749 } 750 up_read(&emu->card->controls_rwsem); 751 if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER && 752 gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) { 753 err = -EINVAL; 754 goto __error; 755 } 756 } 757 for (i = 0; i < icode->gpr_list_control_count; i++) { 758 /* FIXME: we need to check the WRITE access */ 759 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i, 760 in_kernel)) { 761 err = -EFAULT; 762 goto __error; 763 } 764 } 765 __error: 766 kfree(gctl); 767 return err; 768 } 769 770 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl) 771 { 772 struct snd_emu10k1_fx8010_ctl *ctl; 773 774 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value; 775 kctl->private_value = 0; 776 list_del(&ctl->list); 777 kfree(ctl); 778 kfree(kctl->tlv.p); 779 } 780 781 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu, 782 struct snd_emu10k1_fx8010_code *icode, 783 bool in_kernel) 784 { 785 unsigned int i, j; 786 struct snd_emu10k1_fx8010_control_gpr *gctl; 787 struct snd_emu10k1_fx8010_ctl *ctl, *nctl; 788 struct snd_kcontrol_new knew; 789 struct snd_kcontrol *kctl; 790 struct snd_ctl_elem_value *val; 791 int err = 0; 792 793 val = kmalloc(sizeof(*val), GFP_KERNEL); 794 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 795 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL); 796 if (!val || !gctl || !nctl) { 797 err = -ENOMEM; 798 goto __error; 799 } 800 801 for (i = 0; i < icode->gpr_add_control_count; i++) { 802 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 803 in_kernel)) { 804 err = -EFAULT; 805 goto __error; 806 } 807 if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER && 808 gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) { 809 err = -EINVAL; 810 goto __error; 811 } 812 if (! gctl->id.name[0]) { 813 err = -EINVAL; 814 goto __error; 815 } 816 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id); 817 memset(&knew, 0, sizeof(knew)); 818 knew.iface = gctl->id.iface; 819 knew.name = gctl->id.name; 820 knew.index = gctl->id.index; 821 knew.device = gctl->id.device; 822 knew.subdevice = gctl->id.subdevice; 823 knew.info = snd_emu10k1_gpr_ctl_info; 824 knew.tlv.p = copy_tlv((__force const unsigned int __user *)gctl->tlv, in_kernel); 825 if (knew.tlv.p) 826 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 827 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 828 knew.get = snd_emu10k1_gpr_ctl_get; 829 knew.put = snd_emu10k1_gpr_ctl_put; 830 memset(nctl, 0, sizeof(*nctl)); 831 nctl->vcount = gctl->vcount; 832 nctl->count = gctl->count; 833 for (j = 0; j < 32; j++) { 834 nctl->gpr[j] = gctl->gpr[j]; 835 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */ 836 val->value.integer.value[j] = gctl->value[j]; 837 } 838 nctl->min = gctl->min; 839 nctl->max = gctl->max; 840 nctl->translation = gctl->translation; 841 if (ctl == NULL) { 842 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL); 843 if (ctl == NULL) { 844 err = -ENOMEM; 845 kfree(knew.tlv.p); 846 goto __error; 847 } 848 knew.private_value = (unsigned long)ctl; 849 *ctl = *nctl; 850 if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) { 851 kfree(ctl); 852 kfree(knew.tlv.p); 853 goto __error; 854 } 855 kctl->private_free = snd_emu10k1_ctl_private_free; 856 ctl->kcontrol = kctl; 857 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl); 858 } else { 859 /* overwrite */ 860 nctl->list = ctl->list; 861 nctl->kcontrol = ctl->kcontrol; 862 *ctl = *nctl; 863 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE | 864 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id); 865 } 866 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val); 867 } 868 __error: 869 kfree(nctl); 870 kfree(gctl); 871 kfree(val); 872 return err; 873 } 874 875 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu, 876 struct snd_emu10k1_fx8010_code *icode, 877 bool in_kernel) 878 { 879 unsigned int i; 880 struct emu10k1_ctl_elem_id id; 881 struct emu10k1_ctl_elem_id __user *_id; 882 struct snd_emu10k1_fx8010_ctl *ctl; 883 struct snd_card *card = emu->card; 884 885 _id = (__force struct emu10k1_ctl_elem_id __user *)icode->gpr_del_controls; 886 887 for (i = 0; i < icode->gpr_del_control_count; i++, _id++) { 888 if (in_kernel) 889 id = *(__force struct emu10k1_ctl_elem_id *)_id; 890 else if (copy_from_user(&id, _id, sizeof(id))) 891 return -EFAULT; 892 down_write(&card->controls_rwsem); 893 ctl = snd_emu10k1_look_for_ctl(emu, &id); 894 if (ctl) 895 snd_ctl_remove(card, ctl->kcontrol); 896 up_write(&card->controls_rwsem); 897 } 898 return 0; 899 } 900 901 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu, 902 struct snd_emu10k1_fx8010_code *icode) 903 { 904 unsigned int i = 0, j; 905 unsigned int total = 0; 906 struct snd_emu10k1_fx8010_control_gpr *gctl; 907 struct snd_emu10k1_fx8010_ctl *ctl; 908 struct snd_ctl_elem_id *id; 909 910 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 911 if (! gctl) 912 return -ENOMEM; 913 914 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 915 total++; 916 if (icode->gpr_list_controls && 917 i < icode->gpr_list_control_count) { 918 memset(gctl, 0, sizeof(*gctl)); 919 id = &ctl->kcontrol->id; 920 gctl->id.iface = id->iface; 921 strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name)); 922 gctl->id.index = id->index; 923 gctl->id.device = id->device; 924 gctl->id.subdevice = id->subdevice; 925 gctl->vcount = ctl->vcount; 926 gctl->count = ctl->count; 927 for (j = 0; j < 32; j++) { 928 gctl->gpr[j] = ctl->gpr[j]; 929 gctl->value[j] = ctl->value[j]; 930 } 931 gctl->min = ctl->min; 932 gctl->max = ctl->max; 933 gctl->translation = ctl->translation; 934 if (copy_gctl_to_user(emu, icode->gpr_list_controls, 935 gctl, i)) { 936 kfree(gctl); 937 return -EFAULT; 938 } 939 i++; 940 } 941 } 942 icode->gpr_list_control_total = total; 943 kfree(gctl); 944 return 0; 945 } 946 947 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu, 948 struct snd_emu10k1_fx8010_code *icode, 949 bool in_kernel) 950 { 951 int err = 0; 952 953 mutex_lock(&emu->fx8010.lock); 954 err = snd_emu10k1_verify_controls(emu, icode, in_kernel); 955 if (err < 0) 956 goto __error; 957 strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name)); 958 /* stop FX processor - this may be dangerous, but it's better to miss 959 some samples than generate wrong ones - [jk] */ 960 if (emu->audigy) 961 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 962 else 963 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 964 /* ok, do the main job */ 965 err = snd_emu10k1_del_controls(emu, icode, in_kernel); 966 if (err < 0) 967 goto __error; 968 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel); 969 if (err < 0) 970 goto __error; 971 err = snd_emu10k1_tram_poke(emu, icode, in_kernel); 972 if (err < 0) 973 goto __error; 974 err = snd_emu10k1_code_poke(emu, icode, in_kernel); 975 if (err < 0) 976 goto __error; 977 err = snd_emu10k1_add_controls(emu, icode, in_kernel); 978 if (err < 0) 979 goto __error; 980 /* start FX processor when the DSP code is updated */ 981 if (emu->audigy) 982 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 983 else 984 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 985 __error: 986 mutex_unlock(&emu->fx8010.lock); 987 return err; 988 } 989 990 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu, 991 struct snd_emu10k1_fx8010_code *icode) 992 { 993 int err; 994 995 mutex_lock(&emu->fx8010.lock); 996 strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name)); 997 /* ok, do the main job */ 998 err = snd_emu10k1_gpr_peek(emu, icode); 999 if (err >= 0) 1000 err = snd_emu10k1_tram_peek(emu, icode); 1001 if (err >= 0) 1002 err = snd_emu10k1_code_peek(emu, icode); 1003 if (err >= 0) 1004 err = snd_emu10k1_list_controls(emu, icode); 1005 mutex_unlock(&emu->fx8010.lock); 1006 return err; 1007 } 1008 1009 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu, 1010 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1011 { 1012 unsigned int i; 1013 int err = 0; 1014 struct snd_emu10k1_fx8010_pcm *pcm; 1015 1016 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1017 return -EINVAL; 1018 ipcm->substream = array_index_nospec(ipcm->substream, 1019 EMU10K1_FX8010_PCM_COUNT); 1020 if (ipcm->channels > 32) 1021 return -EINVAL; 1022 pcm = &emu->fx8010.pcm[ipcm->substream]; 1023 mutex_lock(&emu->fx8010.lock); 1024 spin_lock_irq(&emu->reg_lock); 1025 if (pcm->opened) { 1026 err = -EBUSY; 1027 goto __error; 1028 } 1029 if (ipcm->channels == 0) { /* remove */ 1030 pcm->valid = 0; 1031 } else { 1032 /* FIXME: we need to add universal code to the PCM transfer routine */ 1033 if (ipcm->channels != 2) { 1034 err = -EINVAL; 1035 goto __error; 1036 } 1037 pcm->valid = 1; 1038 pcm->opened = 0; 1039 pcm->channels = ipcm->channels; 1040 pcm->tram_start = ipcm->tram_start; 1041 pcm->buffer_size = ipcm->buffer_size; 1042 pcm->gpr_size = ipcm->gpr_size; 1043 pcm->gpr_count = ipcm->gpr_count; 1044 pcm->gpr_tmpcount = ipcm->gpr_tmpcount; 1045 pcm->gpr_ptr = ipcm->gpr_ptr; 1046 pcm->gpr_trigger = ipcm->gpr_trigger; 1047 pcm->gpr_running = ipcm->gpr_running; 1048 for (i = 0; i < pcm->channels; i++) 1049 pcm->etram[i] = ipcm->etram[i]; 1050 } 1051 __error: 1052 spin_unlock_irq(&emu->reg_lock); 1053 mutex_unlock(&emu->fx8010.lock); 1054 return err; 1055 } 1056 1057 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu, 1058 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1059 { 1060 unsigned int i; 1061 int err = 0; 1062 struct snd_emu10k1_fx8010_pcm *pcm; 1063 1064 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1065 return -EINVAL; 1066 ipcm->substream = array_index_nospec(ipcm->substream, 1067 EMU10K1_FX8010_PCM_COUNT); 1068 pcm = &emu->fx8010.pcm[ipcm->substream]; 1069 mutex_lock(&emu->fx8010.lock); 1070 spin_lock_irq(&emu->reg_lock); 1071 ipcm->channels = pcm->channels; 1072 ipcm->tram_start = pcm->tram_start; 1073 ipcm->buffer_size = pcm->buffer_size; 1074 ipcm->gpr_size = pcm->gpr_size; 1075 ipcm->gpr_ptr = pcm->gpr_ptr; 1076 ipcm->gpr_count = pcm->gpr_count; 1077 ipcm->gpr_tmpcount = pcm->gpr_tmpcount; 1078 ipcm->gpr_trigger = pcm->gpr_trigger; 1079 ipcm->gpr_running = pcm->gpr_running; 1080 for (i = 0; i < pcm->channels; i++) 1081 ipcm->etram[i] = pcm->etram[i]; 1082 ipcm->res1 = ipcm->res2 = 0; 1083 ipcm->pad = 0; 1084 spin_unlock_irq(&emu->reg_lock); 1085 mutex_unlock(&emu->fx8010.lock); 1086 return err; 1087 } 1088 1089 #define SND_EMU10K1_GPR_CONTROLS 44 1090 #define SND_EMU10K1_INPUTS 12 1091 #define SND_EMU10K1_PLAYBACK_CHANNELS 8 1092 #define SND_EMU10K1_CAPTURE_CHANNELS 4 1093 1094 static void 1095 snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1096 const char *name, int gpr, int defval) 1097 { 1098 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1099 strcpy(ctl->id.name, name); 1100 ctl->vcount = ctl->count = 1; 1101 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1102 if (high_res_gpr_volume) { 1103 ctl->min = 0; 1104 ctl->max = 0x7fffffff; 1105 ctl->tlv = snd_emu10k1_db_linear; 1106 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE; 1107 } else { 1108 ctl->min = 0; 1109 ctl->max = 100; 1110 ctl->tlv = snd_emu10k1_db_scale1; 1111 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100; 1112 } 1113 } 1114 1115 static void 1116 snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1117 const char *name, int gpr, int defval) 1118 { 1119 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1120 strcpy(ctl->id.name, name); 1121 ctl->vcount = ctl->count = 2; 1122 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1123 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1124 if (high_res_gpr_volume) { 1125 ctl->min = 0; 1126 ctl->max = 0x7fffffff; 1127 ctl->tlv = snd_emu10k1_db_linear; 1128 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE; 1129 } else { 1130 ctl->min = 0; 1131 ctl->max = 100; 1132 ctl->tlv = snd_emu10k1_db_scale1; 1133 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100; 1134 } 1135 } 1136 1137 static void 1138 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1139 const char *name, int gpr, int defval) 1140 { 1141 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1142 strcpy(ctl->id.name, name); 1143 ctl->vcount = ctl->count = 1; 1144 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1145 ctl->min = 0; 1146 ctl->max = 1; 1147 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1148 } 1149 1150 static void 1151 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1152 const char *name, int gpr, int defval) 1153 { 1154 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1155 strcpy(ctl->id.name, name); 1156 ctl->vcount = ctl->count = 2; 1157 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1158 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1159 ctl->min = 0; 1160 ctl->max = 1; 1161 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1162 } 1163 1164 /* 1165 * Used for emu1010 - conversion from 32-bit capture inputs from HANA 1166 * to 2 x 16-bit registers in audigy - their values are read via DMA. 1167 * Conversion is performed by Audigy DSP instructions of FX8010. 1168 */ 1169 static int snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1170 struct snd_emu10k1_fx8010_code *icode, 1171 u32 *ptr, int tmp, int bit_shifter16, 1172 int reg_in, int reg_out) 1173 { 1174 A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000); 1175 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000); 1176 A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2)); 1177 A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000); 1178 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000); 1179 A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000); 1180 A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2)); 1181 A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000); 1182 return 1; 1183 } 1184 1185 /* 1186 * initial DSP configuration for Audigy 1187 */ 1188 1189 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu) 1190 { 1191 int err, i, z, gpr, nctl; 1192 int bit_shifter16; 1193 const int playback = 10; 1194 const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */ 1195 const int stereo_mix = capture + 2; 1196 const int tmp = 0x88; 1197 u32 ptr; 1198 struct snd_emu10k1_fx8010_code *icode = NULL; 1199 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1200 u32 *gpr_map; 1201 1202 err = -ENOMEM; 1203 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1204 if (!icode) 1205 return err; 1206 1207 icode->gpr_map = (u_int32_t __user *) kcalloc(512 + 256 + 256 + 2 * 1024, 1208 sizeof(u_int32_t), GFP_KERNEL); 1209 if (!icode->gpr_map) 1210 goto __err_gpr; 1211 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1212 sizeof(*controls), GFP_KERNEL); 1213 if (!controls) 1214 goto __err_ctrls; 1215 1216 gpr_map = (u32 __force *)icode->gpr_map; 1217 1218 icode->tram_data_map = icode->gpr_map + 512; 1219 icode->tram_addr_map = icode->tram_data_map + 256; 1220 icode->code = icode->tram_addr_map + 256; 1221 1222 /* clear free GPRs */ 1223 for (i = 0; i < 512; i++) 1224 set_bit(i, icode->gpr_valid); 1225 1226 /* clear TRAM data & address lines */ 1227 for (i = 0; i < 256; i++) 1228 set_bit(i, icode->tram_valid); 1229 1230 strcpy(icode->name, "Audigy DSP code for ALSA"); 1231 ptr = 0; 1232 nctl = 0; 1233 gpr = stereo_mix + 10; 1234 gpr_map[gpr++] = 0x00007fff; 1235 gpr_map[gpr++] = 0x00008000; 1236 gpr_map[gpr++] = 0x0000ffff; 1237 bit_shifter16 = gpr; 1238 1239 /* stop FX processor */ 1240 snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP); 1241 1242 #if 1 1243 /* PCM front Playback Volume (independent from stereo mix) 1244 * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31) 1245 * where gpr contains attenuation from corresponding mixer control 1246 * (snd_emu10k1_init_stereo_control) 1247 */ 1248 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT)); 1249 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT)); 1250 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100); 1251 gpr += 2; 1252 1253 /* PCM Surround Playback (independent from stereo mix) */ 1254 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR)); 1255 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR)); 1256 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100); 1257 gpr += 2; 1258 1259 /* PCM Side Playback (independent from stereo mix) */ 1260 if (emu->card_capabilities->spk71) { 1261 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE)); 1262 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE)); 1263 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100); 1264 gpr += 2; 1265 } 1266 1267 /* PCM Center Playback (independent from stereo mix) */ 1268 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER)); 1269 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100); 1270 gpr++; 1271 1272 /* PCM LFE Playback (independent from stereo mix) */ 1273 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE)); 1274 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100); 1275 gpr++; 1276 1277 /* 1278 * Stereo Mix 1279 */ 1280 /* Wave (PCM) Playback Volume (will be renamed later) */ 1281 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1282 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1283 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100); 1284 gpr += 2; 1285 1286 /* Synth Playback */ 1287 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1288 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1289 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100); 1290 gpr += 2; 1291 1292 /* Wave (PCM) Capture */ 1293 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1294 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1295 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0); 1296 gpr += 2; 1297 1298 /* Synth Capture */ 1299 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1300 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1301 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0); 1302 gpr += 2; 1303 1304 /* 1305 * inputs 1306 */ 1307 #define A_ADD_VOLUME_IN(var,vol,input) \ 1308 A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) 1309 1310 /* emu1212 DSP 0 and DSP 1 Capture */ 1311 if (emu->card_capabilities->emu_model) { 1312 if (emu->card_capabilities->ca0108_chip) { 1313 /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */ 1314 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001); 1315 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp)); 1316 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001); 1317 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp)); 1318 } else { 1319 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0)); 1320 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1)); 1321 } 1322 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0); 1323 gpr += 2; 1324 } 1325 /* AC'97 Playback Volume - used only for mic (renamed later) */ 1326 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L); 1327 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R); 1328 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0); 1329 gpr += 2; 1330 /* AC'97 Capture Volume - used only for mic */ 1331 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L); 1332 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R); 1333 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0); 1334 gpr += 2; 1335 1336 /* mic capture buffer */ 1337 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R)); 1338 1339 /* Audigy CD Playback Volume */ 1340 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L); 1341 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1342 snd_emu10k1_init_stereo_control(&controls[nctl++], 1343 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume", 1344 gpr, 0); 1345 gpr += 2; 1346 /* Audigy CD Capture Volume */ 1347 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L); 1348 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1349 snd_emu10k1_init_stereo_control(&controls[nctl++], 1350 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume", 1351 gpr, 0); 1352 gpr += 2; 1353 1354 /* Optical SPDIF Playback Volume */ 1355 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L); 1356 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1357 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0); 1358 gpr += 2; 1359 /* Optical SPDIF Capture Volume */ 1360 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L); 1361 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1362 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0); 1363 gpr += 2; 1364 1365 /* Line2 Playback Volume */ 1366 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L); 1367 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R); 1368 snd_emu10k1_init_stereo_control(&controls[nctl++], 1369 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume", 1370 gpr, 0); 1371 gpr += 2; 1372 /* Line2 Capture Volume */ 1373 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L); 1374 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R); 1375 snd_emu10k1_init_stereo_control(&controls[nctl++], 1376 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume", 1377 gpr, 0); 1378 gpr += 2; 1379 1380 /* Philips ADC Playback Volume */ 1381 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L); 1382 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R); 1383 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0); 1384 gpr += 2; 1385 /* Philips ADC Capture Volume */ 1386 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L); 1387 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R); 1388 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0); 1389 gpr += 2; 1390 1391 /* Aux2 Playback Volume */ 1392 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L); 1393 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R); 1394 snd_emu10k1_init_stereo_control(&controls[nctl++], 1395 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume", 1396 gpr, 0); 1397 gpr += 2; 1398 /* Aux2 Capture Volume */ 1399 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L); 1400 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R); 1401 snd_emu10k1_init_stereo_control(&controls[nctl++], 1402 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume", 1403 gpr, 0); 1404 gpr += 2; 1405 1406 /* Stereo Mix Front Playback Volume */ 1407 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix)); 1408 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1409 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100); 1410 gpr += 2; 1411 1412 /* Stereo Mix Surround Playback */ 1413 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix)); 1414 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1415 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0); 1416 gpr += 2; 1417 1418 /* Stereo Mix Center Playback */ 1419 /* Center = sub = Left/2 + Right/2 */ 1420 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1)); 1421 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp)); 1422 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0); 1423 gpr++; 1424 1425 /* Stereo Mix LFE Playback */ 1426 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp)); 1427 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0); 1428 gpr++; 1429 1430 if (emu->card_capabilities->spk71) { 1431 /* Stereo Mix Side Playback */ 1432 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix)); 1433 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1434 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0); 1435 gpr += 2; 1436 } 1437 1438 /* 1439 * outputs 1440 */ 1441 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src)) 1442 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \ 1443 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);} 1444 1445 #define _A_SWITCH(icode, ptr, dst, src, sw) \ 1446 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw); 1447 #define A_SWITCH(icode, ptr, dst, src, sw) \ 1448 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw)) 1449 #define _A_SWITCH_NEG(icode, ptr, dst, src) \ 1450 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001); 1451 #define A_SWITCH_NEG(icode, ptr, dst, src) \ 1452 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src)) 1453 1454 1455 /* 1456 * Process tone control 1457 */ 1458 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */ 1459 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */ 1460 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */ 1461 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */ 1462 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */ 1463 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */ 1464 if (emu->card_capabilities->spk71) { 1465 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */ 1466 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */ 1467 } 1468 1469 1470 ctl = &controls[nctl + 0]; 1471 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1472 strcpy(ctl->id.name, "Tone Control - Bass"); 1473 ctl->vcount = 2; 1474 ctl->count = 10; 1475 ctl->min = 0; 1476 ctl->max = 40; 1477 ctl->value[0] = ctl->value[1] = 20; 1478 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 1479 ctl = &controls[nctl + 1]; 1480 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1481 strcpy(ctl->id.name, "Tone Control - Treble"); 1482 ctl->vcount = 2; 1483 ctl->count = 10; 1484 ctl->min = 0; 1485 ctl->max = 40; 1486 ctl->value[0] = ctl->value[1] = 20; 1487 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 1488 1489 #define BASS_GPR 0x8c 1490 #define TREBLE_GPR 0x96 1491 1492 for (z = 0; z < 5; z++) { 1493 int j; 1494 for (j = 0; j < 2; j++) { 1495 controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j; 1496 controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j; 1497 } 1498 } 1499 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */ 1500 int j, k, l, d; 1501 for (j = 0; j < 2; j++) { /* left/right */ 1502 k = 0xb0 + (z * 8) + (j * 4); 1503 l = 0xe0 + (z * 8) + (j * 4); 1504 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j; 1505 1506 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j)); 1507 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j)); 1508 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j)); 1509 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j)); 1510 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j)); 1511 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000); 1512 1513 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j)); 1514 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j)); 1515 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j)); 1516 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j)); 1517 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j)); 1518 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010); 1519 1520 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000); 1521 1522 if (z == 2) /* center */ 1523 break; 1524 } 1525 } 1526 nctl += 2; 1527 1528 #undef BASS_GPR 1529 #undef TREBLE_GPR 1530 1531 for (z = 0; z < 8; z++) { 1532 A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0); 1533 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0); 1534 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 1535 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1536 } 1537 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0); 1538 gpr += 2; 1539 1540 /* Master volume (will be renamed later) */ 1541 A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS)); 1542 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS)); 1543 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS)); 1544 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS)); 1545 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS)); 1546 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS)); 1547 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS)); 1548 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS)); 1549 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0); 1550 gpr += 2; 1551 1552 /* analog speakers */ 1553 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); 1554 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS); 1555 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS); 1556 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS); 1557 if (emu->card_capabilities->spk71) 1558 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS); 1559 1560 /* headphone */ 1561 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); 1562 1563 /* digital outputs */ 1564 /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */ 1565 if (emu->card_capabilities->emu_model) { 1566 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */ 1567 dev_info(emu->card->dev, "EMU outputs on\n"); 1568 for (z = 0; z < 8; z++) { 1569 if (emu->card_capabilities->ca0108_chip) { 1570 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000); 1571 } else { 1572 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000); 1573 } 1574 } 1575 } 1576 1577 /* IEC958 Optical Raw Playback Switch */ 1578 gpr_map[gpr++] = 0; 1579 gpr_map[gpr++] = 0x1008; 1580 gpr_map[gpr++] = 0xffff0000; 1581 for (z = 0; z < 2; z++) { 1582 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000); 1583 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001); 1584 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2)); 1585 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000); 1586 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z); 1587 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 1588 A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1); 1589 if ((z==1) && (emu->card_capabilities->spdif_bug)) { 1590 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */ 1591 dev_info(emu->card->dev, 1592 "Installing spdif_bug patch: %s\n", 1593 emu->card_capabilities->name); 1594 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000); 1595 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1596 } else { 1597 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1598 } 1599 } 1600 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 1601 gpr += 2; 1602 1603 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS); 1604 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS); 1605 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS); 1606 1607 /* ADC buffer */ 1608 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 1609 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); 1610 #else 1611 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture); 1612 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1); 1613 #endif 1614 1615 if (emu->card_capabilities->emu_model) { 1616 if (emu->card_capabilities->ca0108_chip) { 1617 dev_info(emu->card->dev, "EMU2 inputs on\n"); 1618 for (z = 0; z < 0x10; z++) { 1619 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, 1620 bit_shifter16, 1621 A3_EMU32IN(z), 1622 A_FXBUS2(z*2) ); 1623 } 1624 } else { 1625 dev_info(emu->card->dev, "EMU inputs on\n"); 1626 /* Capture 16 (originally 8) channels of S32_LE sound */ 1627 1628 /* 1629 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n", 1630 gpr, tmp); 1631 */ 1632 /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */ 1633 /* A_P16VIN(0) is delayed by one sample, 1634 * so all other A_P16VIN channels will need to also be delayed 1635 */ 1636 /* Left ADC in. 1 of 2 */ 1637 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) ); 1638 /* Right ADC in 1 of 2 */ 1639 gpr_map[gpr++] = 0x00000000; 1640 /* Delaying by one sample: instead of copying the input 1641 * value A_P16VIN to output A_FXBUS2 as in the first channel, 1642 * we use an auxiliary register, delaying the value by one 1643 * sample 1644 */ 1645 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) ); 1646 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000); 1647 gpr_map[gpr++] = 0x00000000; 1648 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) ); 1649 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000); 1650 gpr_map[gpr++] = 0x00000000; 1651 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) ); 1652 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000); 1653 /* For 96kHz mode */ 1654 /* Left ADC in. 2 of 2 */ 1655 gpr_map[gpr++] = 0x00000000; 1656 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) ); 1657 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000); 1658 /* Right ADC in 2 of 2 */ 1659 gpr_map[gpr++] = 0x00000000; 1660 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) ); 1661 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000); 1662 gpr_map[gpr++] = 0x00000000; 1663 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) ); 1664 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000); 1665 gpr_map[gpr++] = 0x00000000; 1666 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) ); 1667 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000); 1668 /* Pavel Hofman - we still have voices, A_FXBUS2s, and 1669 * A_P16VINs available - 1670 * let's add 8 more capture channels - total of 16 1671 */ 1672 gpr_map[gpr++] = 0x00000000; 1673 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1674 bit_shifter16, 1675 A_GPR(gpr - 1), 1676 A_FXBUS2(0x10)); 1677 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8), 1678 A_C_00000000, A_C_00000000); 1679 gpr_map[gpr++] = 0x00000000; 1680 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1681 bit_shifter16, 1682 A_GPR(gpr - 1), 1683 A_FXBUS2(0x12)); 1684 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9), 1685 A_C_00000000, A_C_00000000); 1686 gpr_map[gpr++] = 0x00000000; 1687 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1688 bit_shifter16, 1689 A_GPR(gpr - 1), 1690 A_FXBUS2(0x14)); 1691 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa), 1692 A_C_00000000, A_C_00000000); 1693 gpr_map[gpr++] = 0x00000000; 1694 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1695 bit_shifter16, 1696 A_GPR(gpr - 1), 1697 A_FXBUS2(0x16)); 1698 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb), 1699 A_C_00000000, A_C_00000000); 1700 gpr_map[gpr++] = 0x00000000; 1701 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1702 bit_shifter16, 1703 A_GPR(gpr - 1), 1704 A_FXBUS2(0x18)); 1705 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc), 1706 A_C_00000000, A_C_00000000); 1707 gpr_map[gpr++] = 0x00000000; 1708 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1709 bit_shifter16, 1710 A_GPR(gpr - 1), 1711 A_FXBUS2(0x1a)); 1712 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd), 1713 A_C_00000000, A_C_00000000); 1714 gpr_map[gpr++] = 0x00000000; 1715 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1716 bit_shifter16, 1717 A_GPR(gpr - 1), 1718 A_FXBUS2(0x1c)); 1719 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe), 1720 A_C_00000000, A_C_00000000); 1721 gpr_map[gpr++] = 0x00000000; 1722 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, 1723 bit_shifter16, 1724 A_GPR(gpr - 1), 1725 A_FXBUS2(0x1e)); 1726 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf), 1727 A_C_00000000, A_C_00000000); 1728 } 1729 1730 #if 0 1731 for (z = 4; z < 8; z++) { 1732 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1733 } 1734 for (z = 0xc; z < 0x10; z++) { 1735 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1736 } 1737 #endif 1738 } else { 1739 /* EFX capture - capture the 16 EXTINs */ 1740 /* Capture 16 channels of S16_LE sound */ 1741 for (z = 0; z < 16; z++) { 1742 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z)); 1743 } 1744 } 1745 1746 #endif /* JCD test */ 1747 /* 1748 * ok, set up done.. 1749 */ 1750 1751 if (gpr > tmp) { 1752 snd_BUG(); 1753 err = -EIO; 1754 goto __err; 1755 } 1756 /* clear remaining instruction memory */ 1757 while (ptr < 0x400) 1758 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0); 1759 1760 icode->gpr_add_control_count = nctl; 1761 icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls; 1762 emu->support_tlv = 1; /* support TLV */ 1763 err = snd_emu10k1_icode_poke(emu, icode, true); 1764 emu->support_tlv = 0; /* clear again */ 1765 1766 __err: 1767 kfree(controls); 1768 __err_ctrls: 1769 kfree((void __force *)icode->gpr_map); 1770 __err_gpr: 1771 kfree(icode); 1772 return err; 1773 } 1774 1775 1776 /* 1777 * initial DSP configuration for Emu10k1 1778 */ 1779 1780 /* when volume = max, then copy only to avoid volume modification */ 1781 /* with iMAC0 (negative values) */ 1782 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1783 { 1784 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol); 1785 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1786 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001); 1787 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000); 1788 } 1789 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1790 { 1791 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1792 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1793 OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001); 1794 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001); 1795 OP(icode, ptr, iMAC0, dst, dst, src, vol); 1796 } 1797 static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1798 { 1799 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); 1800 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1801 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000); 1802 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001); 1803 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol); 1804 } 1805 1806 #define VOLUME(icode, ptr, dst, src, vol) \ 1807 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1808 #define VOLUME_IN(icode, ptr, dst, src, vol) \ 1809 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1810 #define VOLUME_ADD(icode, ptr, dst, src, vol) \ 1811 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1812 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \ 1813 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1814 #define VOLUME_OUT(icode, ptr, dst, src, vol) \ 1815 _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol)) 1816 #define _SWITCH(icode, ptr, dst, src, sw) \ 1817 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw); 1818 #define SWITCH(icode, ptr, dst, src, sw) \ 1819 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw)) 1820 #define SWITCH_IN(icode, ptr, dst, src, sw) \ 1821 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw)) 1822 #define _SWITCH_NEG(icode, ptr, dst, src) \ 1823 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001); 1824 #define SWITCH_NEG(icode, ptr, dst, src) \ 1825 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src)) 1826 1827 1828 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 1829 { 1830 int err, i, z, gpr, tmp, playback, capture; 1831 u32 ptr; 1832 struct snd_emu10k1_fx8010_code *icode; 1833 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL; 1834 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1835 u32 *gpr_map; 1836 1837 err = -ENOMEM; 1838 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1839 if (!icode) 1840 return err; 1841 1842 icode->gpr_map = (u_int32_t __user *) kcalloc(256 + 160 + 160 + 2 * 512, 1843 sizeof(u_int32_t), GFP_KERNEL); 1844 if (!icode->gpr_map) 1845 goto __err_gpr; 1846 1847 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1848 sizeof(struct snd_emu10k1_fx8010_control_gpr), 1849 GFP_KERNEL); 1850 if (!controls) 1851 goto __err_ctrls; 1852 1853 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL); 1854 if (!ipcm) 1855 goto __err_ipcm; 1856 1857 gpr_map = (u32 __force *)icode->gpr_map; 1858 1859 icode->tram_data_map = icode->gpr_map + 256; 1860 icode->tram_addr_map = icode->tram_data_map + 160; 1861 icode->code = icode->tram_addr_map + 160; 1862 1863 /* clear free GPRs */ 1864 for (i = 0; i < 256; i++) 1865 set_bit(i, icode->gpr_valid); 1866 1867 /* clear TRAM data & address lines */ 1868 for (i = 0; i < 160; i++) 1869 set_bit(i, icode->tram_valid); 1870 1871 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela"); 1872 ptr = 0; i = 0; 1873 /* we have 12 inputs */ 1874 playback = SND_EMU10K1_INPUTS; 1875 /* we have 6 playback channels and tone control doubles */ 1876 capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); 1877 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS; 1878 tmp = 0x88; /* we need 4 temporary GPR */ 1879 /* from 0x8c to 0xff is the area for tone control */ 1880 1881 /* stop FX processor */ 1882 snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP); 1883 1884 /* 1885 * Process FX Buses 1886 */ 1887 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004); 1888 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004); 1889 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004); 1890 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004); 1891 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004); 1892 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004); 1893 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004); 1894 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004); 1895 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */ 1896 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */ 1897 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004); 1898 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004); 1899 1900 /* Raw S/PDIF PCM */ 1901 ipcm->substream = 0; 1902 ipcm->channels = 2; 1903 ipcm->tram_start = 0; 1904 ipcm->buffer_size = (64 * 1024) / 2; 1905 ipcm->gpr_size = gpr++; 1906 ipcm->gpr_ptr = gpr++; 1907 ipcm->gpr_count = gpr++; 1908 ipcm->gpr_tmpcount = gpr++; 1909 ipcm->gpr_trigger = gpr++; 1910 ipcm->gpr_running = gpr++; 1911 ipcm->etram[0] = 0; 1912 ipcm->etram[1] = 1; 1913 1914 gpr_map[gpr + 0] = 0xfffff000; 1915 gpr_map[gpr + 1] = 0xffff0000; 1916 gpr_map[gpr + 2] = 0x70000000; 1917 gpr_map[gpr + 3] = 0x00000007; 1918 gpr_map[gpr + 4] = 0x001f << 11; 1919 gpr_map[gpr + 5] = 0x001c << 11; 1920 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */ 1921 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */ 1922 gpr_map[gpr + 8] = 0x2000000 + (2<<11); 1923 gpr_map[gpr + 9] = 0x4000000 + (2<<11); 1924 gpr_map[gpr + 10] = 1<<11; 1925 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */ 1926 gpr_map[gpr + 12] = 0; 1927 1928 /* if the trigger flag is not set, skip */ 1929 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000); 1930 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6)); 1931 /* if the running flag is set, we're running */ 1932 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000); 1933 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004); 1934 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */ 1935 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000); 1936 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5)); 1937 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7)); 1938 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000); 1939 1940 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001); 1941 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000); 1942 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11)); 1943 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000); 1944 1945 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000); 1946 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1947 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1948 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1949 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2)); 1950 1951 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000); 1952 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1953 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1954 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1955 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2)); 1956 1957 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000); 1958 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size)); 1959 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001); 1960 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000); 1961 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000); 1962 1963 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000); 1964 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1965 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000); 1966 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000); 1967 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000); 1968 1969 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001); 1970 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002); 1971 1972 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff); 1973 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff); 1974 1975 /* 24: */ 1976 gpr += 13; 1977 1978 /* Wave Playback Volume */ 1979 for (z = 0; z < 2; z++) 1980 VOLUME(icode, &ptr, playback + z, z, gpr + z); 1981 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100); 1982 gpr += 2; 1983 1984 /* Wave Surround Playback Volume */ 1985 for (z = 0; z < 2; z++) 1986 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z); 1987 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0); 1988 gpr += 2; 1989 1990 /* Wave Center/LFE Playback Volume */ 1991 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000); 1992 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002); 1993 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr); 1994 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0); 1995 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr); 1996 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0); 1997 1998 /* Wave Capture Volume + Switch */ 1999 for (z = 0; z < 2; z++) { 2000 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z); 2001 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z); 2002 } 2003 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0); 2004 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0); 2005 gpr += 4; 2006 2007 /* Synth Playback Volume */ 2008 for (z = 0; z < 2; z++) 2009 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z); 2010 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100); 2011 gpr += 2; 2012 2013 /* Synth Capture Volume + Switch */ 2014 for (z = 0; z < 2; z++) { 2015 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z); 2016 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2017 } 2018 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0); 2019 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0); 2020 gpr += 4; 2021 2022 /* Surround Digital Playback Volume (renamed later without Digital) */ 2023 for (z = 0; z < 2; z++) 2024 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z); 2025 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100); 2026 gpr += 2; 2027 2028 /* Surround Capture Volume + Switch */ 2029 for (z = 0; z < 2; z++) { 2030 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z); 2031 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2032 } 2033 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0); 2034 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0); 2035 gpr += 4; 2036 2037 /* Center Playback Volume (renamed later without Digital) */ 2038 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr); 2039 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100); 2040 2041 /* LFE Playback Volume + Switch (renamed later without Digital) */ 2042 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr); 2043 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100); 2044 2045 /* Front Playback Volume */ 2046 for (z = 0; z < 2; z++) 2047 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z); 2048 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100); 2049 gpr += 2; 2050 2051 /* Front Capture Volume + Switch */ 2052 for (z = 0; z < 2; z++) { 2053 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2); 2054 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2055 } 2056 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0); 2057 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0); 2058 gpr += 3; 2059 2060 /* 2061 * Process inputs 2062 */ 2063 2064 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) { 2065 /* AC'97 Playback Volume */ 2066 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++; 2067 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++; 2068 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0); 2069 /* AC'97 Capture Volume */ 2070 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++; 2071 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++; 2072 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100); 2073 } 2074 2075 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) { 2076 /* IEC958 TTL Playback Volume */ 2077 for (z = 0; z < 2; z++) 2078 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z); 2079 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0); 2080 gpr += 2; 2081 2082 /* IEC958 TTL Capture Volume + Switch */ 2083 for (z = 0; z < 2; z++) { 2084 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z); 2085 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2086 } 2087 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0); 2088 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0); 2089 gpr += 4; 2090 } 2091 2092 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) { 2093 /* Zoom Video Playback Volume */ 2094 for (z = 0; z < 2; z++) 2095 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z); 2096 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0); 2097 gpr += 2; 2098 2099 /* Zoom Video Capture Volume + Switch */ 2100 for (z = 0; z < 2; z++) { 2101 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z); 2102 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2103 } 2104 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0); 2105 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0); 2106 gpr += 4; 2107 } 2108 2109 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) { 2110 /* IEC958 Optical Playback Volume */ 2111 for (z = 0; z < 2; z++) 2112 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z); 2113 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0); 2114 gpr += 2; 2115 2116 /* IEC958 Optical Capture Volume */ 2117 for (z = 0; z < 2; z++) { 2118 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z); 2119 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2120 } 2121 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0); 2122 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0); 2123 gpr += 4; 2124 } 2125 2126 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) { 2127 /* Line LiveDrive Playback Volume */ 2128 for (z = 0; z < 2; z++) 2129 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z); 2130 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0); 2131 gpr += 2; 2132 2133 /* Line LiveDrive Capture Volume + Switch */ 2134 for (z = 0; z < 2; z++) { 2135 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z); 2136 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2137 } 2138 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0); 2139 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0); 2140 gpr += 4; 2141 } 2142 2143 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) { 2144 /* IEC958 Coax Playback Volume */ 2145 for (z = 0; z < 2; z++) 2146 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z); 2147 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0); 2148 gpr += 2; 2149 2150 /* IEC958 Coax Capture Volume + Switch */ 2151 for (z = 0; z < 2; z++) { 2152 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z); 2153 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2154 } 2155 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0); 2156 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0); 2157 gpr += 4; 2158 } 2159 2160 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) { 2161 /* Line LiveDrive Playback Volume */ 2162 for (z = 0; z < 2; z++) 2163 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z); 2164 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0); 2165 controls[i-1].id.index = 1; 2166 gpr += 2; 2167 2168 /* Line LiveDrive Capture Volume */ 2169 for (z = 0; z < 2; z++) { 2170 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z); 2171 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2172 } 2173 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0); 2174 controls[i-1].id.index = 1; 2175 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0); 2176 controls[i-1].id.index = 1; 2177 gpr += 4; 2178 } 2179 2180 /* 2181 * Process tone control 2182 */ 2183 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */ 2184 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */ 2185 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */ 2186 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */ 2187 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */ 2188 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */ 2189 2190 ctl = &controls[i + 0]; 2191 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2192 strcpy(ctl->id.name, "Tone Control - Bass"); 2193 ctl->vcount = 2; 2194 ctl->count = 10; 2195 ctl->min = 0; 2196 ctl->max = 40; 2197 ctl->value[0] = ctl->value[1] = 20; 2198 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2199 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 2200 ctl = &controls[i + 1]; 2201 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2202 strcpy(ctl->id.name, "Tone Control - Treble"); 2203 ctl->vcount = 2; 2204 ctl->count = 10; 2205 ctl->min = 0; 2206 ctl->max = 40; 2207 ctl->value[0] = ctl->value[1] = 20; 2208 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2209 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 2210 2211 #define BASS_GPR 0x8c 2212 #define TREBLE_GPR 0x96 2213 2214 for (z = 0; z < 5; z++) { 2215 int j; 2216 for (j = 0; j < 2; j++) { 2217 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j; 2218 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j; 2219 } 2220 } 2221 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */ 2222 int j, k, l, d; 2223 for (j = 0; j < 2; j++) { /* left/right */ 2224 k = 0xa0 + (z * 8) + (j * 4); 2225 l = 0xd0 + (z * 8) + (j * 4); 2226 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j; 2227 2228 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j)); 2229 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j)); 2230 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j)); 2231 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j)); 2232 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j)); 2233 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000); 2234 2235 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j)); 2236 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j)); 2237 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j)); 2238 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j)); 2239 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j)); 2240 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010); 2241 2242 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000); 2243 2244 if (z == 2) /* center */ 2245 break; 2246 } 2247 } 2248 i += 2; 2249 2250 #undef BASS_GPR 2251 #undef TREBLE_GPR 2252 2253 for (z = 0; z < 6; z++) { 2254 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0); 2255 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0); 2256 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2257 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2258 } 2259 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0); 2260 gpr += 2; 2261 2262 /* 2263 * Process outputs 2264 */ 2265 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) { 2266 /* AC'97 Playback Volume */ 2267 2268 for (z = 0; z < 2; z++) 2269 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000); 2270 } 2271 2272 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) { 2273 /* IEC958 Optical Raw Playback Switch */ 2274 2275 for (z = 0; z < 2; z++) { 2276 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z); 2277 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 2278 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1); 2279 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2280 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 2281 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2282 #endif 2283 } 2284 2285 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 2286 gpr += 2; 2287 } 2288 2289 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) { 2290 /* Headphone Playback Volume */ 2291 2292 for (z = 0; z < 2; z++) { 2293 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z); 2294 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z); 2295 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1); 2296 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2297 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z); 2298 } 2299 2300 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0); 2301 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */ 2302 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0); 2303 controls[i-1].id.index = 1; 2304 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0); 2305 controls[i-1].id.index = 1; 2306 2307 gpr += 4; 2308 } 2309 2310 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R))) 2311 for (z = 0; z < 2; z++) 2312 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000); 2313 2314 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R))) 2315 for (z = 0; z < 2; z++) 2316 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000); 2317 2318 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) { 2319 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2320 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000); 2321 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000); 2322 #else 2323 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000); 2324 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000); 2325 #endif 2326 } 2327 2328 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) { 2329 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2330 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000); 2331 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000); 2332 #else 2333 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000); 2334 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000); 2335 #endif 2336 } 2337 2338 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT 2339 for (z = 0; z < 2; z++) 2340 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000); 2341 #endif 2342 2343 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP)) 2344 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000); 2345 2346 /* EFX capture - capture the 16 EXTINS */ 2347 if (emu->card_capabilities->sblive51) { 2348 /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER 2349 * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording. 2350 * 2351 * Since only 14 of the 16 EXTINs are used, this is not a big problem. 2352 * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture 2353 * 0 and 3, then the rest of the EXTINs to the corresponding FX capture 2354 * channel. Multitrack recorders will still see the center/lfe output signal 2355 * on the second and third channels. 2356 */ 2357 OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0)); 2358 OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1)); 2359 OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2)); 2360 OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3)); 2361 for (z = 4; z < 14; z++) 2362 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2363 } else { 2364 for (z = 0; z < 16; z++) 2365 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2366 } 2367 2368 2369 if (gpr > tmp) { 2370 snd_BUG(); 2371 err = -EIO; 2372 goto __err; 2373 } 2374 if (i > SND_EMU10K1_GPR_CONTROLS) { 2375 snd_BUG(); 2376 err = -EIO; 2377 goto __err; 2378 } 2379 2380 /* clear remaining instruction memory */ 2381 while (ptr < 0x200) 2382 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000); 2383 2384 if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0) 2385 goto __err; 2386 icode->gpr_add_control_count = i; 2387 icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls; 2388 emu->support_tlv = 1; /* support TLV */ 2389 err = snd_emu10k1_icode_poke(emu, icode, true); 2390 emu->support_tlv = 0; /* clear again */ 2391 if (err >= 0) 2392 err = snd_emu10k1_ipcm_poke(emu, ipcm); 2393 __err: 2394 kfree(ipcm); 2395 __err_ipcm: 2396 kfree(controls); 2397 __err_ctrls: 2398 kfree((void __force *)icode->gpr_map); 2399 __err_gpr: 2400 kfree(icode); 2401 return err; 2402 } 2403 2404 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 2405 { 2406 spin_lock_init(&emu->fx8010.irq_lock); 2407 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl); 2408 if (emu->audigy) 2409 return _snd_emu10k1_audigy_init_efx(emu); 2410 else 2411 return _snd_emu10k1_init_efx(emu); 2412 } 2413 2414 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu) 2415 { 2416 /* stop processor */ 2417 if (emu->audigy) 2418 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP); 2419 else 2420 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP); 2421 } 2422 2423 #if 0 /* FIXME: who use them? */ 2424 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output) 2425 { 2426 if (output < 0 || output >= 6) 2427 return -EINVAL; 2428 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1); 2429 return 0; 2430 } 2431 2432 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output) 2433 { 2434 if (output < 0 || output >= 6) 2435 return -EINVAL; 2436 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0); 2437 return 0; 2438 } 2439 #endif 2440 2441 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size) 2442 { 2443 u8 size_reg = 0; 2444 2445 /* size is in samples */ 2446 if (size != 0) { 2447 size = (size - 1) >> 13; 2448 2449 while (size) { 2450 size >>= 1; 2451 size_reg++; 2452 } 2453 size = 0x2000 << size_reg; 2454 } 2455 if ((emu->fx8010.etram_pages.bytes / 2) == size) 2456 return 0; 2457 spin_lock_irq(&emu->emu_lock); 2458 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2459 spin_unlock_irq(&emu->emu_lock); 2460 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 2461 snd_emu10k1_ptr_write(emu, TCBS, 0, 0); 2462 if (emu->fx8010.etram_pages.area != NULL) { 2463 snd_dma_free_pages(&emu->fx8010.etram_pages); 2464 emu->fx8010.etram_pages.area = NULL; 2465 emu->fx8010.etram_pages.bytes = 0; 2466 } 2467 2468 if (size > 0) { 2469 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev, 2470 size * 2, &emu->fx8010.etram_pages) < 0) 2471 return -ENOMEM; 2472 memset(emu->fx8010.etram_pages.area, 0, size * 2); 2473 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2474 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2475 spin_lock_irq(&emu->emu_lock); 2476 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2477 spin_unlock_irq(&emu->emu_lock); 2478 } 2479 2480 return 0; 2481 } 2482 2483 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file) 2484 { 2485 return 0; 2486 } 2487 2488 static void copy_string(char *dst, char *src, char *null, int idx) 2489 { 2490 if (src == NULL) 2491 sprintf(dst, "%s %02X", null, idx); 2492 else 2493 strcpy(dst, src); 2494 } 2495 2496 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu, 2497 struct snd_emu10k1_fx8010_info *info) 2498 { 2499 char **fxbus, **extin, **extout; 2500 unsigned short fxbus_mask, extin_mask, extout_mask; 2501 int res; 2502 2503 info->internal_tram_size = emu->fx8010.itram_size; 2504 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2; 2505 fxbus = fxbuses; 2506 extin = emu->audigy ? audigy_ins : creative_ins; 2507 extout = emu->audigy ? audigy_outs : creative_outs; 2508 fxbus_mask = emu->fx8010.fxbus_mask; 2509 extin_mask = emu->fx8010.extin_mask; 2510 extout_mask = emu->fx8010.extout_mask; 2511 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) { 2512 copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res); 2513 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res); 2514 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2515 } 2516 for (res = 16; res < 32; res++, extout++) 2517 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2518 info->gpr_controls = emu->fx8010.gpr_count; 2519 } 2520 2521 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg) 2522 { 2523 struct snd_emu10k1 *emu = hw->private_data; 2524 struct snd_emu10k1_fx8010_info *info; 2525 struct snd_emu10k1_fx8010_code *icode; 2526 struct snd_emu10k1_fx8010_pcm_rec *ipcm; 2527 unsigned int addr; 2528 void __user *argp = (void __user *)arg; 2529 int res; 2530 2531 switch (cmd) { 2532 case SNDRV_EMU10K1_IOCTL_PVERSION: 2533 emu->support_tlv = 1; 2534 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp); 2535 case SNDRV_EMU10K1_IOCTL_INFO: 2536 info = kzalloc(sizeof(*info), GFP_KERNEL); 2537 if (!info) 2538 return -ENOMEM; 2539 snd_emu10k1_fx8010_info(emu, info); 2540 if (copy_to_user(argp, info, sizeof(*info))) { 2541 kfree(info); 2542 return -EFAULT; 2543 } 2544 kfree(info); 2545 return 0; 2546 case SNDRV_EMU10K1_IOCTL_CODE_POKE: 2547 if (!capable(CAP_SYS_ADMIN)) 2548 return -EPERM; 2549 2550 icode = memdup_user(argp, sizeof(*icode)); 2551 if (IS_ERR(icode)) 2552 return PTR_ERR(icode); 2553 res = snd_emu10k1_icode_poke(emu, icode, false); 2554 kfree(icode); 2555 return res; 2556 case SNDRV_EMU10K1_IOCTL_CODE_PEEK: 2557 icode = memdup_user(argp, sizeof(*icode)); 2558 if (IS_ERR(icode)) 2559 return PTR_ERR(icode); 2560 res = snd_emu10k1_icode_peek(emu, icode); 2561 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) { 2562 kfree(icode); 2563 return -EFAULT; 2564 } 2565 kfree(icode); 2566 return res; 2567 case SNDRV_EMU10K1_IOCTL_PCM_POKE: 2568 ipcm = memdup_user(argp, sizeof(*ipcm)); 2569 if (IS_ERR(ipcm)) 2570 return PTR_ERR(ipcm); 2571 res = snd_emu10k1_ipcm_poke(emu, ipcm); 2572 kfree(ipcm); 2573 return res; 2574 case SNDRV_EMU10K1_IOCTL_PCM_PEEK: 2575 ipcm = memdup_user(argp, sizeof(*ipcm)); 2576 if (IS_ERR(ipcm)) 2577 return PTR_ERR(ipcm); 2578 res = snd_emu10k1_ipcm_peek(emu, ipcm); 2579 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) { 2580 kfree(ipcm); 2581 return -EFAULT; 2582 } 2583 kfree(ipcm); 2584 return res; 2585 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP: 2586 if (!capable(CAP_SYS_ADMIN)) 2587 return -EPERM; 2588 if (get_user(addr, (unsigned int __user *)argp)) 2589 return -EFAULT; 2590 mutex_lock(&emu->fx8010.lock); 2591 res = snd_emu10k1_fx8010_tram_setup(emu, addr); 2592 mutex_unlock(&emu->fx8010.lock); 2593 return res; 2594 case SNDRV_EMU10K1_IOCTL_STOP: 2595 if (!capable(CAP_SYS_ADMIN)) 2596 return -EPERM; 2597 if (emu->audigy) 2598 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2599 else 2600 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2601 return 0; 2602 case SNDRV_EMU10K1_IOCTL_CONTINUE: 2603 if (!capable(CAP_SYS_ADMIN)) 2604 return -EPERM; 2605 if (emu->audigy) 2606 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0); 2607 else 2608 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0); 2609 return 0; 2610 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER: 2611 if (!capable(CAP_SYS_ADMIN)) 2612 return -EPERM; 2613 if (emu->audigy) 2614 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC); 2615 else 2616 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC); 2617 udelay(10); 2618 if (emu->audigy) 2619 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2620 else 2621 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2622 return 0; 2623 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP: 2624 if (!capable(CAP_SYS_ADMIN)) 2625 return -EPERM; 2626 if (get_user(addr, (unsigned int __user *)argp)) 2627 return -EFAULT; 2628 if (addr > 0x1ff) 2629 return -EINVAL; 2630 if (emu->audigy) 2631 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr); 2632 else 2633 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr); 2634 udelay(10); 2635 if (emu->audigy) 2636 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr); 2637 else 2638 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr); 2639 return 0; 2640 case SNDRV_EMU10K1_IOCTL_DBG_READ: 2641 if (emu->audigy) 2642 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0); 2643 else 2644 addr = snd_emu10k1_ptr_read(emu, DBG, 0); 2645 if (put_user(addr, (unsigned int __user *)argp)) 2646 return -EFAULT; 2647 return 0; 2648 } 2649 return -ENOTTY; 2650 } 2651 2652 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file) 2653 { 2654 return 0; 2655 } 2656 2657 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device) 2658 { 2659 struct snd_hwdep *hw; 2660 int err; 2661 2662 if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0) 2663 return err; 2664 strcpy(hw->name, "EMU10K1 (FX8010)"); 2665 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1; 2666 hw->ops.open = snd_emu10k1_fx8010_open; 2667 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl; 2668 hw->ops.release = snd_emu10k1_fx8010_release; 2669 hw->private_data = emu; 2670 return 0; 2671 } 2672 2673 #ifdef CONFIG_PM_SLEEP 2674 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu) 2675 { 2676 int len; 2677 2678 len = emu->audigy ? 0x200 : 0x100; 2679 emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL); 2680 if (! emu->saved_gpr) 2681 return -ENOMEM; 2682 len = emu->audigy ? 0x100 : 0xa0; 2683 emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL); 2684 emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL); 2685 if (! emu->tram_val_saved || ! emu->tram_addr_saved) 2686 return -ENOMEM; 2687 len = emu->audigy ? 2 * 1024 : 2 * 512; 2688 emu->saved_icode = vmalloc(array_size(len, 4)); 2689 if (! emu->saved_icode) 2690 return -ENOMEM; 2691 return 0; 2692 } 2693 2694 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu) 2695 { 2696 kfree(emu->saved_gpr); 2697 kfree(emu->tram_val_saved); 2698 kfree(emu->tram_addr_saved); 2699 vfree(emu->saved_icode); 2700 } 2701 2702 /* 2703 * save/restore GPR, TRAM and codes 2704 */ 2705 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu) 2706 { 2707 int i, len; 2708 2709 len = emu->audigy ? 0x200 : 0x100; 2710 for (i = 0; i < len; i++) 2711 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0); 2712 2713 len = emu->audigy ? 0x100 : 0xa0; 2714 for (i = 0; i < len; i++) { 2715 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0); 2716 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0); 2717 if (emu->audigy) { 2718 emu->tram_addr_saved[i] >>= 12; 2719 emu->tram_addr_saved[i] |= 2720 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20; 2721 } 2722 } 2723 2724 len = emu->audigy ? 2 * 1024 : 2 * 512; 2725 for (i = 0; i < len; i++) 2726 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i); 2727 } 2728 2729 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu) 2730 { 2731 int i, len; 2732 2733 /* set up TRAM */ 2734 if (emu->fx8010.etram_pages.bytes > 0) { 2735 unsigned size, size_reg = 0; 2736 size = emu->fx8010.etram_pages.bytes / 2; 2737 size = (size - 1) >> 13; 2738 while (size) { 2739 size >>= 1; 2740 size_reg++; 2741 } 2742 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2743 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2744 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2745 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2746 } 2747 2748 if (emu->audigy) 2749 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 2750 else 2751 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 2752 2753 len = emu->audigy ? 0x200 : 0x100; 2754 for (i = 0; i < len; i++) 2755 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]); 2756 2757 len = emu->audigy ? 0x100 : 0xa0; 2758 for (i = 0; i < len; i++) { 2759 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0, 2760 emu->tram_val_saved[i]); 2761 if (! emu->audigy) 2762 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2763 emu->tram_addr_saved[i]); 2764 else { 2765 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2766 emu->tram_addr_saved[i] << 12); 2767 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2768 emu->tram_addr_saved[i] >> 20); 2769 } 2770 } 2771 2772 len = emu->audigy ? 2 * 1024 : 2 * 512; 2773 for (i = 0; i < len; i++) 2774 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]); 2775 2776 /* start FX processor when the DSP code is updated */ 2777 if (emu->audigy) 2778 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2779 else 2780 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2781 } 2782 #endif 2783