1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for effect processor FX8010 6 * 7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk> 8 * Added EMU 1010 support. 9 * 10 * BUGS: 11 * -- 12 * 13 * TODO: 14 * -- 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/capability.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/vmalloc.h> 22 #include <linux/init.h> 23 #include <linux/mutex.h> 24 #include <linux/moduleparam.h> 25 #include <linux/nospec.h> 26 27 #include <sound/core.h> 28 #include <sound/tlv.h> 29 #include <sound/emu10k1.h> 30 31 #if 0 /* for testing purposes - digital out -> capture */ 32 #define EMU10K1_CAPTURE_DIGITAL_OUT 33 #endif 34 #if 0 /* for testing purposes - set S/PDIF to AC3 output */ 35 #define EMU10K1_SET_AC3_IEC958 36 #endif 37 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */ 38 #define EMU10K1_CENTER_LFE_FROM_FRONT 39 #endif 40 41 static bool high_res_gpr_volume; 42 module_param(high_res_gpr_volume, bool, 0444); 43 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range."); 44 45 /* 46 * Tables 47 */ 48 49 // Playback channel labels; corresponds with the public FXBUS_* defines. 50 // Unlike the tables below, this is not determined by the hardware. 51 const char * const snd_emu10k1_fxbus[32] = { 52 /* 0x00 */ "PCM Left", 53 /* 0x01 */ "PCM Right", 54 /* 0x02 */ "PCM Rear Left", 55 /* 0x03 */ "PCM Rear Right", 56 /* 0x04 */ "MIDI Left", 57 /* 0x05 */ "MIDI Right", 58 /* 0x06 */ "PCM Center", 59 /* 0x07 */ "PCM LFE", 60 /* 0x08 */ "PCM Front Left", 61 /* 0x09 */ "PCM Front Right", 62 /* 0x0a */ NULL, 63 /* 0x0b */ NULL, 64 /* 0x0c */ "MIDI Reverb", 65 /* 0x0d */ "MIDI Chorus", 66 /* 0x0e */ "PCM Side Left", 67 /* 0x0f */ "PCM Side Right", 68 /* 0x10 */ NULL, 69 /* 0x11 */ NULL, 70 /* 0x12 */ NULL, 71 /* 0x13 */ NULL, 72 /* 0x14 */ "Passthrough Left", 73 /* 0x15 */ "Passthrough Right", 74 /* 0x16 */ NULL, 75 /* 0x17 */ NULL, 76 /* 0x18 */ NULL, 77 /* 0x19 */ NULL, 78 /* 0x1a */ NULL, 79 /* 0x1b */ NULL, 80 /* 0x1c */ NULL, 81 /* 0x1d */ NULL, 82 /* 0x1e */ NULL, 83 /* 0x1f */ NULL 84 }; 85 86 // Physical inputs; corresponds with the public EXTIN_* defines. 87 const char * const snd_emu10k1_sblive_ins[16] = { 88 /* 0x00 */ "AC97 Left", 89 /* 0x01 */ "AC97 Right", 90 /* 0x02 */ "TTL IEC958 Left", 91 /* 0x03 */ "TTL IEC958 Right", 92 /* 0x04 */ "Zoom Video Left", 93 /* 0x05 */ "Zoom Video Right", 94 /* 0x06 */ "Optical IEC958 Left", 95 /* 0x07 */ "Optical IEC958 Right", 96 /* 0x08 */ "Line/Mic 1 Left", 97 /* 0x09 */ "Line/Mic 1 Right", 98 /* 0x0a */ "Coaxial IEC958 Left", 99 /* 0x0b */ "Coaxial IEC958 Right", 100 /* 0x0c */ "Line/Mic 2 Left", 101 /* 0x0d */ "Line/Mic 2 Right", 102 /* 0x0e */ NULL, 103 /* 0x0f */ NULL 104 }; 105 106 // Physical inputs; corresponds with the public A_EXTIN_* defines. 107 const char * const snd_emu10k1_audigy_ins[16] = { 108 /* 0x00 */ "AC97 Left", 109 /* 0x01 */ "AC97 Right", 110 /* 0x02 */ "Audigy CD Left", 111 /* 0x03 */ "Audigy CD Right", 112 /* 0x04 */ "Optical IEC958 Left", 113 /* 0x05 */ "Optical IEC958 Right", 114 /* 0x06 */ NULL, 115 /* 0x07 */ NULL, 116 /* 0x08 */ "Line/Mic 2 Left", 117 /* 0x09 */ "Line/Mic 2 Right", 118 /* 0x0a */ "SPDIF Left", 119 /* 0x0b */ "SPDIF Right", 120 /* 0x0c */ "Aux2 Left", 121 /* 0x0d */ "Aux2 Right", 122 /* 0x0e */ NULL, 123 /* 0x0f */ NULL 124 }; 125 126 // Physical outputs; corresponds with the public EXTOUT_* defines. 127 const char * const snd_emu10k1_sblive_outs[32] = { 128 /* 0x00 */ "AC97 Left", 129 /* 0x01 */ "AC97 Right", 130 /* 0x02 */ "Optical IEC958 Left", 131 /* 0x03 */ "Optical IEC958 Right", 132 /* 0x04 */ "Center", 133 /* 0x05 */ "LFE", 134 /* 0x06 */ "Headphone Left", 135 /* 0x07 */ "Headphone Right", 136 /* 0x08 */ "Surround Left", 137 /* 0x09 */ "Surround Right", 138 /* 0x0a */ "PCM Capture Left", 139 /* 0x0b */ "PCM Capture Right", 140 /* 0x0c */ "MIC Capture", 141 /* 0x0d */ "AC97 Surround Left", 142 /* 0x0e */ "AC97 Surround Right", 143 /* 0x0f */ NULL, 144 // This is actually the FXBUS2 range; SB Live! 5.1 only. 145 /* 0x10 */ NULL, 146 /* 0x11 */ "Analog Center", 147 /* 0x12 */ "Analog LFE", 148 /* 0x13 */ NULL, 149 /* 0x14 */ NULL, 150 /* 0x15 */ NULL, 151 /* 0x16 */ NULL, 152 /* 0x17 */ NULL, 153 /* 0x18 */ NULL, 154 /* 0x19 */ NULL, 155 /* 0x1a */ NULL, 156 /* 0x1b */ NULL, 157 /* 0x1c */ NULL, 158 /* 0x1d */ NULL, 159 /* 0x1e */ NULL, 160 /* 0x1f */ NULL, 161 }; 162 163 // Physical outputs; corresponds with the public A_EXTOUT_* defines. 164 const char * const snd_emu10k1_audigy_outs[32] = { 165 /* 0x00 */ "Digital Front Left", 166 /* 0x01 */ "Digital Front Right", 167 /* 0x02 */ "Digital Center", 168 /* 0x03 */ "Digital LEF", 169 /* 0x04 */ "Headphone Left", 170 /* 0x05 */ "Headphone Right", 171 /* 0x06 */ "Digital Rear Left", 172 /* 0x07 */ "Digital Rear Right", 173 /* 0x08 */ "Front Left", 174 /* 0x09 */ "Front Right", 175 /* 0x0a */ "Center", 176 /* 0x0b */ "LFE", 177 /* 0x0c */ NULL, 178 /* 0x0d */ NULL, 179 /* 0x0e */ "Rear Left", 180 /* 0x0f */ "Rear Right", 181 /* 0x10 */ "AC97 Front Left", 182 /* 0x11 */ "AC97 Front Right", 183 /* 0x12 */ "ADC Capture Left", 184 /* 0x13 */ "ADC Capture Right", 185 /* 0x14 */ NULL, 186 /* 0x15 */ NULL, 187 /* 0x16 */ NULL, 188 /* 0x17 */ NULL, 189 /* 0x18 */ NULL, 190 /* 0x19 */ NULL, 191 /* 0x1a */ NULL, 192 /* 0x1b */ NULL, 193 /* 0x1c */ NULL, 194 /* 0x1d */ NULL, 195 /* 0x1e */ NULL, 196 /* 0x1f */ NULL, 197 }; 198 199 // On the SB Live! 5.1, FXBUS2[1] and FXBUS2[2] are occupied by EXTOUT_ACENTER 200 // and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording. 201 // 202 // Since only 14 of the 16 EXTINs are used, this is not a big problem. 203 // We route AC97 to FX capture 14 and 15, SPDIF_CD to FX capture 0 and 3, 204 // and the rest of the EXTINs to the corresponding FX capture channel. 205 // Multitrack recorders will still see the center/LFE output signal 206 // on the second and third "input" channel. 207 const s8 snd_emu10k1_sblive51_fxbus2_map[16] = { 208 2, -1, -1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 1 209 }; 210 211 static const u32 bass_table[41][5] = { 212 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 }, 213 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d }, 214 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee }, 215 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c }, 216 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b }, 217 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 }, 218 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f }, 219 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 }, 220 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 }, 221 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 }, 222 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 }, 223 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be }, 224 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b }, 225 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c }, 226 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b }, 227 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 }, 228 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a }, 229 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 }, 230 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 }, 231 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e }, 232 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee }, 233 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 }, 234 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 }, 235 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 }, 236 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 }, 237 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e }, 238 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 }, 239 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 }, 240 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 }, 241 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 }, 242 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 }, 243 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca }, 244 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 }, 245 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 }, 246 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 }, 247 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 }, 248 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a }, 249 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f }, 250 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 }, 251 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 }, 252 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 } 253 }; 254 255 static const u32 treble_table[41][5] = { 256 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 }, 257 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 }, 258 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 }, 259 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca }, 260 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 }, 261 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 }, 262 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 }, 263 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 }, 264 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 }, 265 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df }, 266 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff }, 267 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 }, 268 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c }, 269 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 }, 270 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 }, 271 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 }, 272 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 }, 273 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d }, 274 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 }, 275 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 }, 276 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f }, 277 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb }, 278 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 }, 279 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 }, 280 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd }, 281 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 }, 282 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad }, 283 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 }, 284 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 }, 285 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c }, 286 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 }, 287 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 }, 288 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 }, 289 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 }, 290 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 }, 291 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 }, 292 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d }, 293 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b }, 294 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 }, 295 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd }, 296 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 } 297 }; 298 299 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */ 300 static const u32 db_table[101] = { 301 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540, 302 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8, 303 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1, 304 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0, 305 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9, 306 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb, 307 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005, 308 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d, 309 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd, 310 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8, 311 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481, 312 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333, 313 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d, 314 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6, 315 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d, 316 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf, 317 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038, 318 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a, 319 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea, 320 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272, 321 0x7fffffff, 322 }; 323 324 /* EMU10k1/EMU10k2 DSP control db gain */ 325 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1); 326 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0); 327 328 /* EMU10K1 bass/treble db gain */ 329 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0); 330 331 static const u32 onoff_table[2] = { 332 0x00000000, 0x00000001 333 }; 334 335 /* 336 * controls 337 */ 338 339 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 340 { 341 struct snd_emu10k1_fx8010_ctl *ctl = 342 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 343 344 if (ctl->min == 0 && ctl->max == 1) 345 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 346 else 347 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 348 uinfo->count = ctl->vcount; 349 uinfo->value.integer.min = ctl->min; 350 uinfo->value.integer.max = ctl->max; 351 return 0; 352 } 353 354 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 355 { 356 struct snd_emu10k1_fx8010_ctl *ctl = 357 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 358 unsigned int i; 359 360 for (i = 0; i < ctl->vcount; i++) 361 ucontrol->value.integer.value[i] = ctl->value[i]; 362 return 0; 363 } 364 365 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 366 { 367 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 368 struct snd_emu10k1_fx8010_ctl *ctl = 369 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 370 int nval, val; 371 unsigned int i, j; 372 int change = 0; 373 374 for (i = 0; i < ctl->vcount; i++) { 375 nval = ucontrol->value.integer.value[i]; 376 if (nval < ctl->min) 377 nval = ctl->min; 378 if (nval > ctl->max) 379 nval = ctl->max; 380 if (nval != ctl->value[i]) 381 change = 1; 382 val = ctl->value[i] = nval; 383 switch (ctl->translation) { 384 case EMU10K1_GPR_TRANSLATION_NONE: 385 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val); 386 break; 387 case EMU10K1_GPR_TRANSLATION_NEGATE: 388 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, ~val); 389 break; 390 case EMU10K1_GPR_TRANSLATION_TABLE100: 391 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]); 392 break; 393 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100: 394 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, 395 val == 100 ? 0x80000000 : -(int)db_table[val]); 396 break; 397 case EMU10K1_GPR_TRANSLATION_BASS: 398 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 399 change = -EIO; 400 goto __error; 401 } 402 for (j = 0; j < 5; j++) 403 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]); 404 break; 405 case EMU10K1_GPR_TRANSLATION_TREBLE: 406 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 407 change = -EIO; 408 goto __error; 409 } 410 for (j = 0; j < 5; j++) 411 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]); 412 break; 413 case EMU10K1_GPR_TRANSLATION_ONOFF: 414 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]); 415 break; 416 } 417 } 418 __error: 419 return change; 420 } 421 422 /* 423 * Interrupt handler 424 */ 425 426 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu) 427 { 428 struct snd_emu10k1_fx8010_irq *irq, *nirq; 429 430 irq = emu->fx8010.irq_handlers; 431 while (irq) { 432 nirq = irq->next; /* irq ptr can be removed from list */ 433 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) { 434 if (irq->handler) 435 irq->handler(emu, irq->private_data); 436 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1); 437 } 438 irq = nirq; 439 } 440 } 441 442 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, 443 snd_fx8010_irq_handler_t *handler, 444 unsigned char gpr_running, 445 void *private_data, 446 struct snd_emu10k1_fx8010_irq *irq) 447 { 448 unsigned long flags; 449 450 irq->handler = handler; 451 irq->gpr_running = gpr_running; 452 irq->private_data = private_data; 453 irq->next = NULL; 454 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 455 if (emu->fx8010.irq_handlers == NULL) { 456 emu->fx8010.irq_handlers = irq; 457 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt; 458 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE); 459 } else { 460 irq->next = emu->fx8010.irq_handlers; 461 emu->fx8010.irq_handlers = irq; 462 } 463 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 464 return 0; 465 } 466 467 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, 468 struct snd_emu10k1_fx8010_irq *irq) 469 { 470 struct snd_emu10k1_fx8010_irq *tmp; 471 unsigned long flags; 472 473 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 474 tmp = emu->fx8010.irq_handlers; 475 if (tmp == irq) { 476 emu->fx8010.irq_handlers = tmp->next; 477 if (emu->fx8010.irq_handlers == NULL) { 478 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE); 479 emu->dsp_interrupt = NULL; 480 } 481 } else { 482 while (tmp && tmp->next != irq) 483 tmp = tmp->next; 484 if (tmp) 485 tmp->next = tmp->next->next; 486 } 487 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 488 return 0; 489 } 490 491 /************************************************************************* 492 * EMU10K1 effect manager 493 *************************************************************************/ 494 495 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode, 496 unsigned int *ptr, 497 u32 op, u32 r, u32 a, u32 x, u32 y) 498 { 499 u_int32_t *code; 500 if (snd_BUG_ON(*ptr >= 512)) 501 return; 502 code = icode->code + (*ptr) * 2; 503 set_bit(*ptr, icode->code_valid); 504 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff); 505 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff); 506 (*ptr)++; 507 } 508 509 #define OP(icode, ptr, op, r, a, x, y) \ 510 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y) 511 512 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode, 513 unsigned int *ptr, 514 u32 op, u32 r, u32 a, u32 x, u32 y) 515 { 516 u_int32_t *code; 517 if (snd_BUG_ON(*ptr >= 1024)) 518 return; 519 code = icode->code + (*ptr) * 2; 520 set_bit(*ptr, icode->code_valid); 521 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff); 522 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff); 523 (*ptr)++; 524 } 525 526 #define A_OP(icode, ptr, op, r, a, x, y) \ 527 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y) 528 529 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data) 530 { 531 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 532 snd_emu10k1_ptr_write(emu, pc, 0, data); 533 } 534 535 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc) 536 { 537 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 538 return snd_emu10k1_ptr_read(emu, pc, 0); 539 } 540 541 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu, 542 struct snd_emu10k1_fx8010_code *icode, 543 bool in_kernel) 544 { 545 int gpr; 546 u32 val; 547 548 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 549 if (!test_bit(gpr, icode->gpr_valid)) 550 continue; 551 if (in_kernel) 552 val = icode->gpr_map[gpr]; 553 else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr])) 554 return -EFAULT; 555 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val); 556 } 557 return 0; 558 } 559 560 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu, 561 struct snd_emu10k1_fx8010_code *icode) 562 { 563 int gpr; 564 u32 val; 565 566 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 567 set_bit(gpr, icode->gpr_valid); 568 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0); 569 if (put_user(val, (__user u32 *)&icode->gpr_map[gpr])) 570 return -EFAULT; 571 } 572 return 0; 573 } 574 575 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu, 576 struct snd_emu10k1_fx8010_code *icode, 577 bool in_kernel) 578 { 579 int tram; 580 u32 addr, val; 581 582 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 583 if (!test_bit(tram, icode->tram_valid)) 584 continue; 585 if (in_kernel) { 586 val = icode->tram_data_map[tram]; 587 addr = icode->tram_addr_map[tram]; 588 } else { 589 if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) || 590 get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram])) 591 return -EFAULT; 592 } 593 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val); 594 if (!emu->audigy) { 595 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr); 596 } else { 597 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12); 598 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20); 599 } 600 } 601 return 0; 602 } 603 604 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu, 605 struct snd_emu10k1_fx8010_code *icode) 606 { 607 int tram; 608 u32 val, addr; 609 610 memset(icode->tram_valid, 0, sizeof(icode->tram_valid)); 611 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 612 set_bit(tram, icode->tram_valid); 613 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0); 614 if (!emu->audigy) { 615 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0); 616 } else { 617 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12; 618 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20; 619 } 620 if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) || 621 put_user(addr, (__user u32 *)&icode->tram_addr_map[tram])) 622 return -EFAULT; 623 } 624 return 0; 625 } 626 627 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu, 628 struct snd_emu10k1_fx8010_code *icode, 629 bool in_kernel) 630 { 631 u32 pc, lo, hi; 632 633 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 634 if (!test_bit(pc / 2, icode->code_valid)) 635 continue; 636 if (in_kernel) { 637 lo = icode->code[pc + 0]; 638 hi = icode->code[pc + 1]; 639 } else { 640 if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) || 641 get_user(hi, (__user u32 *)&icode->code[pc + 1])) 642 return -EFAULT; 643 } 644 snd_emu10k1_efx_write(emu, pc + 0, lo); 645 snd_emu10k1_efx_write(emu, pc + 1, hi); 646 } 647 return 0; 648 } 649 650 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu, 651 struct snd_emu10k1_fx8010_code *icode) 652 { 653 u32 pc; 654 655 memset(icode->code_valid, 0, sizeof(icode->code_valid)); 656 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 657 set_bit(pc / 2, icode->code_valid); 658 if (put_user(snd_emu10k1_efx_read(emu, pc + 0), 659 (__user u32 *)&icode->code[pc + 0])) 660 return -EFAULT; 661 if (put_user(snd_emu10k1_efx_read(emu, pc + 1), 662 (__user u32 *)&icode->code[pc + 1])) 663 return -EFAULT; 664 } 665 return 0; 666 } 667 668 static struct snd_emu10k1_fx8010_ctl * 669 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, 670 struct emu10k1_ctl_elem_id *_id) 671 { 672 struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id; 673 struct snd_emu10k1_fx8010_ctl *ctl; 674 struct snd_kcontrol *kcontrol; 675 676 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 677 kcontrol = ctl->kcontrol; 678 if (kcontrol->id.iface == id->iface && 679 kcontrol->id.index == id->index && 680 !strcmp(kcontrol->id.name, id->name)) 681 return ctl; 682 } 683 return NULL; 684 } 685 686 #define MAX_TLV_SIZE 256 687 688 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel) 689 { 690 unsigned int data[2]; 691 unsigned int *tlv; 692 693 if (!_tlv) 694 return NULL; 695 if (in_kernel) 696 memcpy(data, (__force void *)_tlv, sizeof(data)); 697 else if (copy_from_user(data, _tlv, sizeof(data))) 698 return NULL; 699 if (data[1] >= MAX_TLV_SIZE) 700 return NULL; 701 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL); 702 if (!tlv) 703 return NULL; 704 memcpy(tlv, data, sizeof(data)); 705 if (in_kernel) { 706 memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]); 707 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) { 708 kfree(tlv); 709 return NULL; 710 } 711 return tlv; 712 } 713 714 static int copy_gctl(struct snd_emu10k1 *emu, 715 struct snd_emu10k1_fx8010_control_gpr *dst, 716 struct snd_emu10k1_fx8010_control_gpr *src, 717 int idx, bool in_kernel) 718 { 719 struct snd_emu10k1_fx8010_control_gpr __user *_src; 720 struct snd_emu10k1_fx8010_control_old_gpr *octl; 721 struct snd_emu10k1_fx8010_control_old_gpr __user *_octl; 722 723 _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src; 724 if (emu->support_tlv) { 725 if (in_kernel) 726 *dst = src[idx]; 727 else if (copy_from_user(dst, &_src[idx], sizeof(*src))) 728 return -EFAULT; 729 return 0; 730 } 731 732 octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src; 733 _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl; 734 if (in_kernel) 735 memcpy(dst, &octl[idx], sizeof(*octl)); 736 else if (copy_from_user(dst, &_octl[idx], sizeof(*octl))) 737 return -EFAULT; 738 dst->tlv = NULL; 739 return 0; 740 } 741 742 static int copy_gctl_to_user(struct snd_emu10k1 *emu, 743 struct snd_emu10k1_fx8010_control_gpr *dst, 744 struct snd_emu10k1_fx8010_control_gpr *src, 745 int idx) 746 { 747 struct snd_emu10k1_fx8010_control_gpr __user *_dst; 748 struct snd_emu10k1_fx8010_control_old_gpr __user *octl; 749 750 _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst; 751 if (emu->support_tlv) 752 return copy_to_user(&_dst[idx], src, sizeof(*src)); 753 754 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst; 755 return copy_to_user(&octl[idx], src, sizeof(*octl)); 756 } 757 758 static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i, 759 struct emu10k1_ctl_elem_id *ret, bool in_kernel) 760 { 761 struct emu10k1_ctl_elem_id __user *_id = 762 (struct emu10k1_ctl_elem_id __user *)&list[i]; 763 764 if (in_kernel) 765 *ret = list[i]; 766 else if (copy_from_user(ret, _id, sizeof(*ret))) 767 return -EFAULT; 768 return 0; 769 } 770 771 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu, 772 struct snd_emu10k1_fx8010_code *icode, 773 bool in_kernel) 774 { 775 unsigned int i; 776 struct emu10k1_ctl_elem_id id; 777 struct snd_emu10k1_fx8010_control_gpr *gctl; 778 struct snd_ctl_elem_id *gctl_id; 779 int err; 780 781 for (i = 0; i < icode->gpr_del_control_count; i++) { 782 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id, 783 in_kernel); 784 if (err < 0) 785 return err; 786 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL) 787 return -ENOENT; 788 } 789 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 790 if (! gctl) 791 return -ENOMEM; 792 err = 0; 793 for (i = 0; i < icode->gpr_add_control_count; i++) { 794 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 795 in_kernel)) { 796 err = -EFAULT; 797 goto __error; 798 } 799 if (snd_emu10k1_look_for_ctl(emu, &gctl->id)) 800 continue; 801 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 802 if (snd_ctl_find_id(emu->card, gctl_id)) { 803 err = -EEXIST; 804 goto __error; 805 } 806 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 807 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 808 err = -EINVAL; 809 goto __error; 810 } 811 switch (gctl->translation) { 812 case EMU10K1_GPR_TRANSLATION_NONE: 813 case EMU10K1_GPR_TRANSLATION_NEGATE: 814 break; 815 case EMU10K1_GPR_TRANSLATION_TABLE100: 816 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100: 817 if (gctl->min != 0 || gctl->max != 100) { 818 err = -EINVAL; 819 goto __error; 820 } 821 break; 822 case EMU10K1_GPR_TRANSLATION_BASS: 823 case EMU10K1_GPR_TRANSLATION_TREBLE: 824 if (gctl->min != 0 || gctl->max != 40) { 825 err = -EINVAL; 826 goto __error; 827 } 828 break; 829 case EMU10K1_GPR_TRANSLATION_ONOFF: 830 if (gctl->min != 0 || gctl->max != 1) { 831 err = -EINVAL; 832 goto __error; 833 } 834 break; 835 default: 836 err = -EINVAL; 837 goto __error; 838 } 839 } 840 for (i = 0; i < icode->gpr_list_control_count; i++) { 841 /* FIXME: we need to check the WRITE access */ 842 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i, 843 in_kernel)) { 844 err = -EFAULT; 845 goto __error; 846 } 847 } 848 __error: 849 kfree(gctl); 850 return err; 851 } 852 853 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl) 854 { 855 struct snd_emu10k1_fx8010_ctl *ctl; 856 857 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value; 858 kctl->private_value = 0; 859 list_del(&ctl->list); 860 kfree(ctl); 861 kfree(kctl->tlv.p); 862 } 863 864 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu, 865 struct snd_emu10k1_fx8010_code *icode, 866 bool in_kernel) 867 { 868 unsigned int i, j; 869 struct snd_emu10k1_fx8010_control_gpr *gctl; 870 struct snd_ctl_elem_id *gctl_id; 871 struct snd_emu10k1_fx8010_ctl *ctl, *nctl; 872 struct snd_kcontrol_new knew; 873 struct snd_kcontrol *kctl; 874 struct snd_ctl_elem_value *val; 875 int err = 0; 876 877 val = kmalloc(sizeof(*val), GFP_KERNEL); 878 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 879 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL); 880 if (!val || !gctl || !nctl) { 881 err = -ENOMEM; 882 goto __error; 883 } 884 885 for (i = 0; i < icode->gpr_add_control_count; i++) { 886 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 887 in_kernel)) { 888 err = -EFAULT; 889 goto __error; 890 } 891 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 892 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 893 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 894 err = -EINVAL; 895 goto __error; 896 } 897 if (!*gctl_id->name) { 898 err = -EINVAL; 899 goto __error; 900 } 901 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id); 902 memset(&knew, 0, sizeof(knew)); 903 knew.iface = gctl_id->iface; 904 knew.name = gctl_id->name; 905 knew.index = gctl_id->index; 906 knew.device = gctl_id->device; 907 knew.subdevice = gctl_id->subdevice; 908 knew.info = snd_emu10k1_gpr_ctl_info; 909 knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel); 910 if (knew.tlv.p) 911 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 912 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 913 knew.get = snd_emu10k1_gpr_ctl_get; 914 knew.put = snd_emu10k1_gpr_ctl_put; 915 memset(nctl, 0, sizeof(*nctl)); 916 nctl->vcount = gctl->vcount; 917 nctl->count = gctl->count; 918 for (j = 0; j < 32; j++) { 919 nctl->gpr[j] = gctl->gpr[j]; 920 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */ 921 val->value.integer.value[j] = gctl->value[j]; 922 } 923 nctl->min = gctl->min; 924 nctl->max = gctl->max; 925 nctl->translation = gctl->translation; 926 if (ctl == NULL) { 927 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL); 928 if (ctl == NULL) { 929 err = -ENOMEM; 930 kfree(knew.tlv.p); 931 goto __error; 932 } 933 knew.private_value = (unsigned long)ctl; 934 *ctl = *nctl; 935 kctl = snd_ctl_new1(&knew, emu); 936 err = snd_ctl_add(emu->card, kctl); 937 if (err < 0) { 938 kfree(ctl); 939 kfree(knew.tlv.p); 940 goto __error; 941 } 942 kctl->private_free = snd_emu10k1_ctl_private_free; 943 ctl->kcontrol = kctl; 944 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl); 945 } else { 946 /* overwrite */ 947 nctl->list = ctl->list; 948 nctl->kcontrol = ctl->kcontrol; 949 *ctl = *nctl; 950 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE | 951 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id); 952 } 953 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val); 954 } 955 __error: 956 kfree(nctl); 957 kfree(gctl); 958 kfree(val); 959 return err; 960 } 961 962 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu, 963 struct snd_emu10k1_fx8010_code *icode, 964 bool in_kernel) 965 { 966 unsigned int i; 967 struct emu10k1_ctl_elem_id id; 968 struct snd_emu10k1_fx8010_ctl *ctl; 969 struct snd_card *card = emu->card; 970 int err; 971 972 for (i = 0; i < icode->gpr_del_control_count; i++) { 973 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id, 974 in_kernel); 975 if (err < 0) 976 return err; 977 ctl = snd_emu10k1_look_for_ctl(emu, &id); 978 if (ctl) 979 snd_ctl_remove(card, ctl->kcontrol); 980 } 981 return 0; 982 } 983 984 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu, 985 struct snd_emu10k1_fx8010_code *icode) 986 { 987 unsigned int i = 0, j; 988 unsigned int total = 0; 989 struct snd_emu10k1_fx8010_control_gpr *gctl; 990 struct snd_emu10k1_fx8010_ctl *ctl; 991 struct snd_ctl_elem_id *id; 992 993 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 994 if (! gctl) 995 return -ENOMEM; 996 997 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 998 total++; 999 if (icode->gpr_list_controls && 1000 i < icode->gpr_list_control_count) { 1001 memset(gctl, 0, sizeof(*gctl)); 1002 id = &ctl->kcontrol->id; 1003 gctl->id.iface = (__force int)id->iface; 1004 strscpy(gctl->id.name, id->name, sizeof(gctl->id.name)); 1005 gctl->id.index = id->index; 1006 gctl->id.device = id->device; 1007 gctl->id.subdevice = id->subdevice; 1008 gctl->vcount = ctl->vcount; 1009 gctl->count = ctl->count; 1010 for (j = 0; j < 32; j++) { 1011 gctl->gpr[j] = ctl->gpr[j]; 1012 gctl->value[j] = ctl->value[j]; 1013 } 1014 gctl->min = ctl->min; 1015 gctl->max = ctl->max; 1016 gctl->translation = ctl->translation; 1017 if (copy_gctl_to_user(emu, icode->gpr_list_controls, 1018 gctl, i)) { 1019 kfree(gctl); 1020 return -EFAULT; 1021 } 1022 i++; 1023 } 1024 } 1025 icode->gpr_list_control_total = total; 1026 kfree(gctl); 1027 return 0; 1028 } 1029 1030 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu, 1031 struct snd_emu10k1_fx8010_code *icode, 1032 bool in_kernel) 1033 { 1034 int err = 0; 1035 1036 mutex_lock(&emu->fx8010.lock); 1037 err = snd_emu10k1_verify_controls(emu, icode, in_kernel); 1038 if (err < 0) 1039 goto __error; 1040 strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name)); 1041 /* stop FX processor - this may be dangerous, but it's better to miss 1042 some samples than generate wrong ones - [jk] */ 1043 if (emu->audigy) 1044 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 1045 else 1046 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 1047 /* ok, do the main job */ 1048 err = snd_emu10k1_del_controls(emu, icode, in_kernel); 1049 if (err < 0) 1050 goto __error; 1051 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel); 1052 if (err < 0) 1053 goto __error; 1054 err = snd_emu10k1_tram_poke(emu, icode, in_kernel); 1055 if (err < 0) 1056 goto __error; 1057 err = snd_emu10k1_code_poke(emu, icode, in_kernel); 1058 if (err < 0) 1059 goto __error; 1060 err = snd_emu10k1_add_controls(emu, icode, in_kernel); 1061 if (err < 0) 1062 goto __error; 1063 /* start FX processor when the DSP code is updated */ 1064 if (emu->audigy) 1065 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 1066 else 1067 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 1068 __error: 1069 mutex_unlock(&emu->fx8010.lock); 1070 return err; 1071 } 1072 1073 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu, 1074 struct snd_emu10k1_fx8010_code *icode) 1075 { 1076 int err; 1077 1078 mutex_lock(&emu->fx8010.lock); 1079 strscpy(icode->name, emu->fx8010.name, sizeof(icode->name)); 1080 /* ok, do the main job */ 1081 err = snd_emu10k1_gpr_peek(emu, icode); 1082 if (err >= 0) 1083 err = snd_emu10k1_tram_peek(emu, icode); 1084 if (err >= 0) 1085 err = snd_emu10k1_code_peek(emu, icode); 1086 if (err >= 0) 1087 err = snd_emu10k1_list_controls(emu, icode); 1088 mutex_unlock(&emu->fx8010.lock); 1089 return err; 1090 } 1091 1092 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu, 1093 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1094 { 1095 unsigned int i; 1096 int err = 0; 1097 struct snd_emu10k1_fx8010_pcm *pcm; 1098 1099 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1100 return -EINVAL; 1101 ipcm->substream = array_index_nospec(ipcm->substream, 1102 EMU10K1_FX8010_PCM_COUNT); 1103 if (ipcm->channels > 32) 1104 return -EINVAL; 1105 pcm = &emu->fx8010.pcm[ipcm->substream]; 1106 mutex_lock(&emu->fx8010.lock); 1107 spin_lock_irq(&emu->reg_lock); 1108 if (pcm->opened) { 1109 err = -EBUSY; 1110 goto __error; 1111 } 1112 if (ipcm->channels == 0) { /* remove */ 1113 pcm->valid = 0; 1114 } else { 1115 /* FIXME: we need to add universal code to the PCM transfer routine */ 1116 if (ipcm->channels != 2) { 1117 err = -EINVAL; 1118 goto __error; 1119 } 1120 pcm->valid = 1; 1121 pcm->opened = 0; 1122 pcm->channels = ipcm->channels; 1123 pcm->tram_start = ipcm->tram_start; 1124 pcm->buffer_size = ipcm->buffer_size; 1125 pcm->gpr_size = ipcm->gpr_size; 1126 pcm->gpr_count = ipcm->gpr_count; 1127 pcm->gpr_tmpcount = ipcm->gpr_tmpcount; 1128 pcm->gpr_ptr = ipcm->gpr_ptr; 1129 pcm->gpr_trigger = ipcm->gpr_trigger; 1130 pcm->gpr_running = ipcm->gpr_running; 1131 for (i = 0; i < pcm->channels; i++) 1132 pcm->etram[i] = ipcm->etram[i]; 1133 } 1134 __error: 1135 spin_unlock_irq(&emu->reg_lock); 1136 mutex_unlock(&emu->fx8010.lock); 1137 return err; 1138 } 1139 1140 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu, 1141 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1142 { 1143 unsigned int i; 1144 int err = 0; 1145 struct snd_emu10k1_fx8010_pcm *pcm; 1146 1147 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1148 return -EINVAL; 1149 ipcm->substream = array_index_nospec(ipcm->substream, 1150 EMU10K1_FX8010_PCM_COUNT); 1151 pcm = &emu->fx8010.pcm[ipcm->substream]; 1152 mutex_lock(&emu->fx8010.lock); 1153 spin_lock_irq(&emu->reg_lock); 1154 ipcm->channels = pcm->channels; 1155 ipcm->tram_start = pcm->tram_start; 1156 ipcm->buffer_size = pcm->buffer_size; 1157 ipcm->gpr_size = pcm->gpr_size; 1158 ipcm->gpr_ptr = pcm->gpr_ptr; 1159 ipcm->gpr_count = pcm->gpr_count; 1160 ipcm->gpr_tmpcount = pcm->gpr_tmpcount; 1161 ipcm->gpr_trigger = pcm->gpr_trigger; 1162 ipcm->gpr_running = pcm->gpr_running; 1163 for (i = 0; i < pcm->channels; i++) 1164 ipcm->etram[i] = pcm->etram[i]; 1165 ipcm->res1 = ipcm->res2 = 0; 1166 ipcm->pad = 0; 1167 spin_unlock_irq(&emu->reg_lock); 1168 mutex_unlock(&emu->fx8010.lock); 1169 return err; 1170 } 1171 1172 #define SND_EMU10K1_GPR_CONTROLS 44 1173 #define SND_EMU10K1_INPUTS 12 1174 #define SND_EMU10K1_PLAYBACK_CHANNELS 8 1175 #define SND_EMU10K1_CAPTURE_CHANNELS 4 1176 1177 #define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1) 1178 1179 static void 1180 snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr *ctl, 1181 const char *name, int gpr, int defval, int defval_hr) 1182 { 1183 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1184 strcpy(ctl->id.name, name); 1185 ctl->vcount = ctl->count = 1; 1186 if (high_res_gpr_volume) { 1187 ctl->min = -1; 1188 ctl->max = 0x7fffffff; 1189 ctl->tlv = snd_emu10k1_db_linear; 1190 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE; 1191 defval = defval_hr; 1192 } else { 1193 ctl->min = 0; 1194 ctl->max = 100; 1195 ctl->tlv = snd_emu10k1_db_scale1; 1196 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100; 1197 } 1198 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1199 } 1200 #define snd_emu10k1_init_mono_control(ctl, name, gpr, defval) \ 1201 snd_emu10k1_init_mono_control2(ctl, name, gpr, defval, HR_VAL(defval)) 1202 1203 static void 1204 snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr *ctl, 1205 const char *name, int gpr, int defval, int defval_hr) 1206 { 1207 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1208 strcpy(ctl->id.name, name); 1209 ctl->vcount = ctl->count = 2; 1210 if (high_res_gpr_volume) { 1211 ctl->min = -1; 1212 ctl->max = 0x7fffffff; 1213 ctl->tlv = snd_emu10k1_db_linear; 1214 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE; 1215 defval = defval_hr; 1216 } else { 1217 ctl->min = 0; 1218 ctl->max = 100; 1219 ctl->tlv = snd_emu10k1_db_scale1; 1220 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100; 1221 } 1222 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1223 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1224 } 1225 #define snd_emu10k1_init_stereo_control(ctl, name, gpr, defval) \ 1226 snd_emu10k1_init_stereo_control2(ctl, name, gpr, defval, HR_VAL(defval)) 1227 1228 static void 1229 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1230 const char *name, int gpr, int defval) 1231 { 1232 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1233 strcpy(ctl->id.name, name); 1234 ctl->vcount = ctl->count = 1; 1235 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1236 ctl->min = 0; 1237 ctl->max = 1; 1238 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1239 } 1240 1241 static void 1242 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1243 const char *name, int gpr, int defval) 1244 { 1245 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1246 strcpy(ctl->id.name, name); 1247 ctl->vcount = ctl->count = 2; 1248 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1249 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1250 ctl->min = 0; 1251 ctl->max = 1; 1252 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1253 } 1254 1255 /* 1256 * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA 1257 * to 2 x 16-bit registers in Audigy - their values are read via DMA. 1258 * Conversion is performed by Audigy DSP instructions of FX8010. 1259 */ 1260 static void snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1261 struct snd_emu10k1_fx8010_code *icode, 1262 u32 *ptr, int tmp, int bit_shifter16, 1263 int reg_in, int reg_out) 1264 { 1265 // This leaves the low word in place, which is fine, 1266 // as the low bits are completely ignored subsequently. 1267 // reg_out[1] = reg_in 1268 A_OP(icode, ptr, iACC3, reg_out + 1, reg_in, A_C_00000000, A_C_00000000); 1269 // It is fine to read reg_in multiple times. 1270 // tmp = reg_in << 15 1271 A_OP(icode, ptr, iMACINT1, A_GPR(tmp), A_C_00000000, reg_in, A_GPR(bit_shifter16)); 1272 // Left-shift once more. This is a separate step, as the 1273 // signed multiplication would clobber the MSB. 1274 // reg_out[0] = tmp + ((tmp << 31) >> 31) 1275 A_OP(icode, ptr, iMAC3, reg_out, A_GPR(tmp), A_GPR(tmp), A_C_80000000); 1276 } 1277 1278 #define ENUM_GPR(name, size) name, name ## _dummy = name + (size) - 1 1279 1280 /* 1281 * initial DSP configuration for Audigy 1282 */ 1283 1284 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu) 1285 { 1286 int err, z, nctl; 1287 enum { 1288 ENUM_GPR(playback, SND_EMU10K1_PLAYBACK_CHANNELS), 1289 ENUM_GPR(stereo_mix, 2), 1290 ENUM_GPR(capture, 2), 1291 ENUM_GPR(bit_shifter16, 1), 1292 // The fixed allocation of these breaks the pattern, but why not. 1293 // Splitting these into left/right is questionable, as it will break 1294 // down for center/lfe. But it works for stereo/quadro, so whatever. 1295 ENUM_GPR(bass_gpr, 2 * 5), // two sides, five coefficients 1296 ENUM_GPR(treble_gpr, 2 * 5), 1297 ENUM_GPR(bass_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), // four delay stages 1298 ENUM_GPR(treble_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), 1299 ENUM_GPR(tmp, 3), 1300 num_static_gprs 1301 }; 1302 int gpr = num_static_gprs; 1303 u32 ptr, ptr_skip; 1304 struct snd_emu10k1_fx8010_code *icode = NULL; 1305 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1306 u32 *gpr_map; 1307 1308 err = -ENOMEM; 1309 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1310 if (!icode) 1311 return err; 1312 1313 icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024, 1314 sizeof(u_int32_t), GFP_KERNEL); 1315 if (!icode->gpr_map) 1316 goto __err_gpr; 1317 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1318 sizeof(*controls), GFP_KERNEL); 1319 if (!controls) 1320 goto __err_ctrls; 1321 1322 gpr_map = icode->gpr_map; 1323 1324 icode->tram_data_map = icode->gpr_map + 512; 1325 icode->tram_addr_map = icode->tram_data_map + 256; 1326 icode->code = icode->tram_addr_map + 256; 1327 1328 /* clear free GPRs */ 1329 memset(icode->gpr_valid, 0xff, 512 / 8); 1330 1331 /* clear TRAM data & address lines */ 1332 memset(icode->tram_valid, 0xff, 256 / 8); 1333 1334 strcpy(icode->name, "Audigy DSP code for ALSA"); 1335 ptr = 0; 1336 nctl = 0; 1337 gpr_map[bit_shifter16] = 0x00008000; 1338 1339 #if 1 1340 /* PCM front Playback Volume (independent from stereo mix) 1341 * playback = -gpr * FXBUS_PCM_LEFT_FRONT >> 31 1342 * where gpr contains negated attenuation from corresponding mixer control 1343 * (snd_emu10k1_init_stereo_control) 1344 */ 1345 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT)); 1346 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT)); 1347 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100); 1348 gpr += 2; 1349 1350 /* PCM Surround Playback (independent from stereo mix) */ 1351 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR)); 1352 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR)); 1353 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100); 1354 gpr += 2; 1355 1356 /* PCM Side Playback (independent from stereo mix) */ 1357 if (emu->card_capabilities->spk71) { 1358 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE)); 1359 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE)); 1360 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100); 1361 gpr += 2; 1362 } 1363 1364 /* PCM Center Playback (independent from stereo mix) */ 1365 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER)); 1366 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100); 1367 gpr++; 1368 1369 /* PCM LFE Playback (independent from stereo mix) */ 1370 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE)); 1371 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100); 1372 gpr++; 1373 1374 /* 1375 * Stereo Mix 1376 */ 1377 /* Wave (PCM) Playback Volume (will be renamed later) */ 1378 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1379 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1380 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100); 1381 gpr += 2; 1382 1383 /* Synth Playback */ 1384 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1385 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1386 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100); 1387 gpr += 2; 1388 1389 /* Wave (PCM) Capture */ 1390 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1391 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1392 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0); 1393 gpr += 2; 1394 1395 /* Synth Capture */ 1396 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1397 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1398 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0); 1399 gpr += 2; 1400 1401 // We need to double the volume, as we configure the voices for half volume, 1402 // which is necessary for bit-identical reproduction. 1403 { static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); } 1404 for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++) 1405 A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000); 1406 1407 /* 1408 * inputs 1409 */ 1410 #define A_ADD_VOLUME_IN(var,vol,input) \ 1411 A_OP(icode, &ptr, iMAC1, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) 1412 1413 if (emu->card_capabilities->emu_model) { 1414 /* EMU1010 DSP 0 and DSP 1 Capture */ 1415 // The 24 MSB hold the actual value. We implicitly discard the 16 LSB. 1416 if (emu->card_capabilities->ca0108_chip) { 1417 // For unclear reasons, the EMU32IN cannot be the Y operand! 1418 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A3_EMU32IN(0x0), A_GPR(gpr)); 1419 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels 1420 // need to be delayed as well; we use an auxiliary register for that. 1421 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1)); 1422 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A3_EMU32IN(0x1), A_C_00000000, A_C_00000000); 1423 } else { 1424 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_P16VIN(0x0), A_GPR(gpr)); 1425 // A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels 1426 // need to be delayed as well; we use an auxiliary register for that. 1427 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1)); 1428 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A_P16VIN(0x1), A_C_00000000, A_C_00000000); 1429 } 1430 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0); 1431 gpr_map[gpr + 2] = 0x00000000; 1432 gpr += 3; 1433 } else { 1434 if (emu->card_capabilities->ac97_chip) { 1435 /* AC'97 Playback Volume - used only for mic (renamed later) */ 1436 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L); 1437 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R); 1438 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0); 1439 gpr += 2; 1440 /* AC'97 Capture Volume - used only for mic */ 1441 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L); 1442 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R); 1443 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0); 1444 gpr += 2; 1445 1446 /* mic capture buffer */ 1447 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R)); 1448 } 1449 1450 /* Audigy CD Playback Volume */ 1451 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L); 1452 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1453 snd_emu10k1_init_stereo_control(&controls[nctl++], 1454 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume", 1455 gpr, 0); 1456 gpr += 2; 1457 /* Audigy CD Capture Volume */ 1458 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L); 1459 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1460 snd_emu10k1_init_stereo_control(&controls[nctl++], 1461 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume", 1462 gpr, 0); 1463 gpr += 2; 1464 1465 /* Optical SPDIF Playback Volume */ 1466 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L); 1467 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1468 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0); 1469 gpr += 2; 1470 /* Optical SPDIF Capture Volume */ 1471 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L); 1472 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1473 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0); 1474 gpr += 2; 1475 1476 /* Line2 Playback Volume */ 1477 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L); 1478 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R); 1479 snd_emu10k1_init_stereo_control(&controls[nctl++], 1480 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume", 1481 gpr, 0); 1482 gpr += 2; 1483 /* Line2 Capture Volume */ 1484 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L); 1485 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R); 1486 snd_emu10k1_init_stereo_control(&controls[nctl++], 1487 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume", 1488 gpr, 0); 1489 gpr += 2; 1490 1491 /* Philips ADC Playback Volume */ 1492 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L); 1493 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R); 1494 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0); 1495 gpr += 2; 1496 /* Philips ADC Capture Volume */ 1497 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L); 1498 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R); 1499 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0); 1500 gpr += 2; 1501 1502 /* Aux2 Playback Volume */ 1503 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L); 1504 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R); 1505 snd_emu10k1_init_stereo_control(&controls[nctl++], 1506 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume", 1507 gpr, 0); 1508 gpr += 2; 1509 /* Aux2 Capture Volume */ 1510 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L); 1511 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R); 1512 snd_emu10k1_init_stereo_control(&controls[nctl++], 1513 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume", 1514 gpr, 0); 1515 gpr += 2; 1516 } 1517 1518 /* Stereo Mix Front Playback Volume */ 1519 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix)); 1520 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1521 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100); 1522 gpr += 2; 1523 1524 /* Stereo Mix Surround Playback */ 1525 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix)); 1526 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1527 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0); 1528 gpr += 2; 1529 1530 /* Stereo Mix Center Playback */ 1531 /* Center = sub = Left/2 + Right/2 */ 1532 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1)); 1533 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp)); 1534 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0); 1535 gpr++; 1536 1537 /* Stereo Mix LFE Playback */ 1538 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp)); 1539 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0); 1540 gpr++; 1541 1542 if (emu->card_capabilities->spk71) { 1543 /* Stereo Mix Side Playback */ 1544 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix)); 1545 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1546 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0); 1547 gpr += 2; 1548 } 1549 1550 /* 1551 * outputs 1552 */ 1553 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src)) 1554 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \ 1555 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);} 1556 1557 #define _A_SWITCH(icode, ptr, dst, src, sw) \ 1558 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw); 1559 #define A_SWITCH(icode, ptr, dst, src, sw) \ 1560 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw)) 1561 #define _A_SWITCH_NEG(icode, ptr, dst, src) \ 1562 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001); 1563 #define A_SWITCH_NEG(icode, ptr, dst, src) \ 1564 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src)) 1565 1566 1567 /* 1568 * Process tone control 1569 */ 1570 ctl = &controls[nctl + 0]; 1571 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1572 strcpy(ctl->id.name, "Tone Control - Bass"); 1573 ctl->vcount = 2; 1574 ctl->count = 10; 1575 ctl->min = 0; 1576 ctl->max = 40; 1577 ctl->value[0] = ctl->value[1] = 20; 1578 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 1579 ctl = &controls[nctl + 1]; 1580 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1581 strcpy(ctl->id.name, "Tone Control - Treble"); 1582 ctl->vcount = 2; 1583 ctl->count = 10; 1584 ctl->min = 0; 1585 ctl->max = 40; 1586 ctl->value[0] = ctl->value[1] = 20; 1587 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 1588 for (z = 0; z < 5; z++) { 1589 int j; 1590 for (j = 0; j < 2; j++) { 1591 controls[nctl + 0].gpr[z * 2 + j] = bass_gpr + z * 2 + j; 1592 controls[nctl + 1].gpr[z * 2 + j] = treble_gpr + z * 2 + j; 1593 } 1594 } 1595 nctl += 2; 1596 1597 A_OP(icode, &ptr, iACC3, A_C_00000000, A_GPR(gpr), A_C_00000000, A_C_00000000); 1598 snd_emu10k1_init_mono_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0); 1599 gpr++; 1600 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_CC_REG_ZERO, A_GPR(gpr)); 1601 ptr_skip = ptr; 1602 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */ 1603 int j, k, l, d; 1604 for (j = 0; j < 2; j++) { /* left/right */ 1605 k = bass_tmp + (z * 8) + (j * 4); 1606 l = treble_tmp + (z * 8) + (j * 4); 1607 d = playback + z * 2 + j; 1608 1609 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(bass_gpr + 0 + j)); 1610 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j)); 1611 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j)); 1612 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j)); 1613 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j)); 1614 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000); 1615 1616 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j)); 1617 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(treble_gpr + 4 + j)); 1618 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j)); 1619 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(treble_gpr + 8 + j)); 1620 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(treble_gpr + 6 + j)); 1621 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010); 1622 1623 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000); 1624 1625 if (z == 2) /* center */ 1626 break; 1627 } 1628 } 1629 gpr_map[gpr++] = ptr - ptr_skip; 1630 1631 /* Master volume (will be renamed later) */ 1632 for (z = 0; z < 8; z++) 1633 A_OP(icode, &ptr, iMAC1, A_GPR(playback+z), A_C_00000000, A_GPR(gpr), A_GPR(playback+z)); 1634 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0); 1635 gpr++; 1636 1637 if (emu->card_capabilities->emu_model) { 1638 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */ 1639 dev_info(emu->card->dev, "EMU outputs on\n"); 1640 for (z = 0; z < 8; z++) { 1641 if (emu->card_capabilities->ca0108_chip) { 1642 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + z), A_C_00000000, A_C_00000000); 1643 } else { 1644 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + z), A_C_00000000, A_C_00000000); 1645 } 1646 } 1647 } else { 1648 /* analog speakers */ 1649 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback); 1650 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2); 1651 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4); 1652 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5); 1653 if (emu->card_capabilities->spk71) 1654 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6); 1655 1656 /* headphone */ 1657 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback); 1658 1659 /* IEC958 Optical Raw Playback Switch */ 1660 gpr_map[gpr++] = 0; 1661 gpr_map[gpr++] = 0x1008; 1662 gpr_map[gpr++] = 0xffff0000; 1663 for (z = 0; z < 2; z++) { 1664 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000); 1665 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001); 1666 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2)); 1667 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000); 1668 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z); 1669 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 1670 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 1671 if ((z==1) && (emu->card_capabilities->spdif_bug)) { 1672 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */ 1673 dev_info(emu->card->dev, 1674 "Installing spdif_bug patch: %s\n", 1675 emu->card_capabilities->name); 1676 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000); 1677 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1678 } else { 1679 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1680 } 1681 } 1682 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 1683 gpr += 2; 1684 1685 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2); 1686 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4); 1687 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5); 1688 } 1689 1690 /* ADC buffer */ 1691 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 1692 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback); 1693 #else 1694 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture); 1695 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1); 1696 #endif 1697 1698 if (emu->card_capabilities->emu_model) { 1699 /* Capture 16 channels of S32_LE sound. */ 1700 if (emu->card_capabilities->ca0108_chip) { 1701 dev_info(emu->card->dev, "EMU2 inputs on\n"); 1702 /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */ 1703 1704 snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1705 icode, &ptr, tmp, bit_shifter16, A3_EMU32IN(0), A_FXBUS2(0)); 1706 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels 1707 // need to be delayed as well; we use an auxiliary register for that. 1708 for (z = 1; z < 0x10; z++) { 1709 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, 1710 bit_shifter16, 1711 A_GPR(gpr), 1712 A_FXBUS2(z*2) ); 1713 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A3_EMU32IN(z), A_C_00000000, A_C_00000000); 1714 gpr_map[gpr++] = 0x00000000; 1715 } 1716 } else { 1717 dev_info(emu->card->dev, "EMU inputs on\n"); 1718 /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */ 1719 1720 /* 1721 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n", 1722 gpr, tmp); 1723 */ 1724 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) ); 1725 /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels 1726 * will need to also be delayed; we use an auxiliary register for that. */ 1727 for (z = 1; z < 0x10; z++) { 1728 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) ); 1729 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000); 1730 gpr_map[gpr++] = 0x00000000; 1731 } 1732 } 1733 1734 #if 0 1735 for (z = 4; z < 8; z++) { 1736 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1737 } 1738 for (z = 0xc; z < 0x10; z++) { 1739 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1740 } 1741 #endif 1742 } else { 1743 /* EFX capture - capture the 16 EXTINs */ 1744 /* Capture 16 channels of S16_LE sound */ 1745 for (z = 0; z < 16; z++) { 1746 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z)); 1747 } 1748 } 1749 1750 #endif /* JCD test */ 1751 /* 1752 * ok, set up done.. 1753 */ 1754 1755 if (gpr > 512) { 1756 snd_BUG(); 1757 err = -EIO; 1758 goto __err; 1759 } 1760 1761 /* clear remaining instruction memory */ 1762 while (ptr < 0x400) 1763 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0); 1764 1765 icode->gpr_add_control_count = nctl; 1766 icode->gpr_add_controls = controls; 1767 emu->support_tlv = 1; /* support TLV */ 1768 err = snd_emu10k1_icode_poke(emu, icode, true); 1769 emu->support_tlv = 0; /* clear again */ 1770 1771 __err: 1772 kfree(controls); 1773 __err_ctrls: 1774 kfree(icode->gpr_map); 1775 __err_gpr: 1776 kfree(icode); 1777 return err; 1778 } 1779 1780 1781 /* 1782 * initial DSP configuration for Emu10k1 1783 */ 1784 1785 /* Volumes are in the [-2^31, 0] range, zero being mute. */ 1786 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1787 { 1788 OP(icode, ptr, iMAC1, dst, C_00000000, src, vol); 1789 } 1790 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1791 { 1792 OP(icode, ptr, iMAC1, dst, dst, src, vol); 1793 } 1794 1795 #define VOLUME(icode, ptr, dst, src, vol) \ 1796 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1797 #define VOLUME_IN(icode, ptr, dst, src, vol) \ 1798 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1799 #define VOLUME_ADD(icode, ptr, dst, src, vol) \ 1800 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1801 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \ 1802 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1803 #define VOLUME_OUT(icode, ptr, dst, src, vol) \ 1804 _volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol)) 1805 #define _SWITCH(icode, ptr, dst, src, sw) \ 1806 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw); 1807 #define SWITCH(icode, ptr, dst, src, sw) \ 1808 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw)) 1809 #define SWITCH_IN(icode, ptr, dst, src, sw) \ 1810 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw)) 1811 #define _SWITCH_NEG(icode, ptr, dst, src) \ 1812 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001); 1813 #define SWITCH_NEG(icode, ptr, dst, src) \ 1814 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src)) 1815 1816 1817 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 1818 { 1819 int err, i, z, gpr, tmp, playback, capture; 1820 u32 ptr, ptr_skip; 1821 struct snd_emu10k1_fx8010_code *icode; 1822 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL; 1823 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1824 u32 *gpr_map; 1825 1826 err = -ENOMEM; 1827 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1828 if (!icode) 1829 return err; 1830 1831 icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512, 1832 sizeof(u_int32_t), GFP_KERNEL); 1833 if (!icode->gpr_map) 1834 goto __err_gpr; 1835 1836 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1837 sizeof(struct snd_emu10k1_fx8010_control_gpr), 1838 GFP_KERNEL); 1839 if (!controls) 1840 goto __err_ctrls; 1841 1842 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL); 1843 if (!ipcm) 1844 goto __err_ipcm; 1845 1846 gpr_map = icode->gpr_map; 1847 1848 icode->tram_data_map = icode->gpr_map + 256; 1849 icode->tram_addr_map = icode->tram_data_map + 160; 1850 icode->code = icode->tram_addr_map + 160; 1851 1852 /* clear free GPRs */ 1853 memset(icode->gpr_valid, 0xff, 256 / 8); 1854 1855 /* clear TRAM data & address lines */ 1856 memset(icode->tram_valid, 0xff, 160 / 8); 1857 1858 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela"); 1859 ptr = 0; i = 0; 1860 /* we have 12 inputs */ 1861 playback = SND_EMU10K1_INPUTS; 1862 /* we have 6 playback channels and tone control doubles */ 1863 capture = playback + SND_EMU10K1_PLAYBACK_CHANNELS; 1864 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS; 1865 tmp = 0x88; /* we need 4 temporary GPR */ 1866 /* from 0x8c to 0xff is the area for tone control */ 1867 1868 /* 1869 * Process FX Buses 1870 */ 1871 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008); 1872 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008); 1873 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000008); 1874 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000008); 1875 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000008); 1876 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000008); 1877 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000008); 1878 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000008); 1879 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */ 1880 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */ 1881 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000008); 1882 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000008); 1883 1884 /* Raw S/PDIF PCM */ 1885 ipcm->substream = 0; 1886 ipcm->channels = 2; 1887 ipcm->tram_start = 0; 1888 ipcm->buffer_size = (64 * 1024) / 2; 1889 ipcm->gpr_size = gpr++; 1890 ipcm->gpr_ptr = gpr++; 1891 ipcm->gpr_count = gpr++; 1892 ipcm->gpr_tmpcount = gpr++; 1893 ipcm->gpr_trigger = gpr++; 1894 ipcm->gpr_running = gpr++; 1895 ipcm->etram[0] = 0; 1896 ipcm->etram[1] = 1; 1897 1898 gpr_map[gpr + 0] = 0xfffff000; 1899 gpr_map[gpr + 1] = 0xffff0000; 1900 gpr_map[gpr + 2] = 0x70000000; 1901 gpr_map[gpr + 3] = 0x00000007; 1902 gpr_map[gpr + 4] = 0x001f << 11; 1903 gpr_map[gpr + 5] = 0x001c << 11; 1904 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */ 1905 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */ 1906 gpr_map[gpr + 8] = 0x2000000 + (2<<11); 1907 gpr_map[gpr + 9] = 0x4000000 + (2<<11); 1908 gpr_map[gpr + 10] = 1<<11; 1909 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */ 1910 gpr_map[gpr + 12] = 0; 1911 1912 /* if the trigger flag is not set, skip */ 1913 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000); 1914 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6)); 1915 /* if the running flag is set, we're running */ 1916 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000); 1917 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004); 1918 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */ 1919 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000); 1920 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5)); 1921 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7)); 1922 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000); 1923 1924 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001); 1925 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000); 1926 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11)); 1927 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000); 1928 1929 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000); 1930 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1931 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1932 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1933 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2)); 1934 1935 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000); 1936 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1937 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1938 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1939 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2)); 1940 1941 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000); 1942 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size)); 1943 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001); 1944 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000); 1945 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000); 1946 1947 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000); 1948 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1949 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000); 1950 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000); 1951 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000); 1952 1953 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001); 1954 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002); 1955 1956 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff); 1957 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff); 1958 1959 /* 24: */ 1960 gpr += 13; 1961 1962 /* Wave Playback Volume */ 1963 for (z = 0; z < 2; z++) 1964 VOLUME(icode, &ptr, playback + z, z, gpr + z); 1965 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100); 1966 gpr += 2; 1967 1968 /* Wave Surround Playback Volume */ 1969 for (z = 0; z < 2; z++) 1970 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z); 1971 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0); 1972 gpr += 2; 1973 1974 /* Wave Center/LFE Playback Volume */ 1975 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000); 1976 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000004); 1977 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr); 1978 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0); 1979 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr); 1980 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0); 1981 1982 /* Wave Capture Volume + Switch */ 1983 for (z = 0; z < 2; z++) { 1984 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z); 1985 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z); 1986 } 1987 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0); 1988 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0); 1989 gpr += 4; 1990 1991 /* Synth Playback Volume */ 1992 for (z = 0; z < 2; z++) 1993 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z); 1994 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100); 1995 gpr += 2; 1996 1997 /* Synth Capture Volume + Switch */ 1998 for (z = 0; z < 2; z++) { 1999 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z); 2000 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2001 } 2002 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0); 2003 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0); 2004 gpr += 4; 2005 2006 /* Surround Digital Playback Volume (renamed later without Digital) */ 2007 for (z = 0; z < 2; z++) 2008 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z); 2009 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100); 2010 gpr += 2; 2011 2012 /* Surround Capture Volume + Switch */ 2013 for (z = 0; z < 2; z++) { 2014 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z); 2015 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2016 } 2017 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0); 2018 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0); 2019 gpr += 4; 2020 2021 /* Center Playback Volume (renamed later without Digital) */ 2022 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr); 2023 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100); 2024 2025 /* LFE Playback Volume + Switch (renamed later without Digital) */ 2026 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr); 2027 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100); 2028 2029 /* Front Playback Volume */ 2030 for (z = 0; z < 2; z++) 2031 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z); 2032 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100); 2033 gpr += 2; 2034 2035 /* Front Capture Volume + Switch */ 2036 for (z = 0; z < 2; z++) { 2037 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2); 2038 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2039 } 2040 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0); 2041 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0); 2042 gpr += 3; 2043 2044 /* 2045 * Process inputs 2046 */ 2047 2048 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) { 2049 /* AC'97 Playback Volume */ 2050 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++; 2051 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++; 2052 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0); 2053 /* AC'97 Capture Volume */ 2054 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++; 2055 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++; 2056 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100); 2057 } 2058 2059 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) { 2060 /* IEC958 TTL Playback Volume */ 2061 for (z = 0; z < 2; z++) 2062 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z); 2063 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0); 2064 gpr += 2; 2065 2066 /* IEC958 TTL Capture Volume + Switch */ 2067 for (z = 0; z < 2; z++) { 2068 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z); 2069 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2070 } 2071 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0); 2072 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0); 2073 gpr += 4; 2074 } 2075 2076 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) { 2077 /* Zoom Video Playback Volume */ 2078 for (z = 0; z < 2; z++) 2079 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z); 2080 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0); 2081 gpr += 2; 2082 2083 /* Zoom Video Capture Volume + Switch */ 2084 for (z = 0; z < 2; z++) { 2085 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z); 2086 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2087 } 2088 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0); 2089 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0); 2090 gpr += 4; 2091 } 2092 2093 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) { 2094 /* IEC958 Optical Playback Volume */ 2095 for (z = 0; z < 2; z++) 2096 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z); 2097 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0); 2098 gpr += 2; 2099 2100 /* IEC958 Optical Capture Volume */ 2101 for (z = 0; z < 2; z++) { 2102 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z); 2103 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2104 } 2105 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0); 2106 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0); 2107 gpr += 4; 2108 } 2109 2110 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) { 2111 /* Line LiveDrive Playback Volume */ 2112 for (z = 0; z < 2; z++) 2113 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z); 2114 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0); 2115 gpr += 2; 2116 2117 /* Line LiveDrive Capture Volume + Switch */ 2118 for (z = 0; z < 2; z++) { 2119 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z); 2120 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2121 } 2122 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0); 2123 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0); 2124 gpr += 4; 2125 } 2126 2127 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) { 2128 /* IEC958 Coax Playback Volume */ 2129 for (z = 0; z < 2; z++) 2130 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z); 2131 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0); 2132 gpr += 2; 2133 2134 /* IEC958 Coax Capture Volume + Switch */ 2135 for (z = 0; z < 2; z++) { 2136 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z); 2137 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2138 } 2139 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0); 2140 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0); 2141 gpr += 4; 2142 } 2143 2144 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) { 2145 /* Line LiveDrive Playback Volume */ 2146 for (z = 0; z < 2; z++) 2147 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z); 2148 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0); 2149 controls[i-1].id.index = 1; 2150 gpr += 2; 2151 2152 /* Line LiveDrive Capture Volume */ 2153 for (z = 0; z < 2; z++) { 2154 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z); 2155 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2156 } 2157 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0); 2158 controls[i-1].id.index = 1; 2159 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0); 2160 controls[i-1].id.index = 1; 2161 gpr += 4; 2162 } 2163 2164 /* 2165 * Process tone control 2166 */ 2167 ctl = &controls[i + 0]; 2168 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 2169 strcpy(ctl->id.name, "Tone Control - Bass"); 2170 ctl->vcount = 2; 2171 ctl->count = 10; 2172 ctl->min = 0; 2173 ctl->max = 40; 2174 ctl->value[0] = ctl->value[1] = 20; 2175 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2176 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 2177 ctl = &controls[i + 1]; 2178 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 2179 strcpy(ctl->id.name, "Tone Control - Treble"); 2180 ctl->vcount = 2; 2181 ctl->count = 10; 2182 ctl->min = 0; 2183 ctl->max = 40; 2184 ctl->value[0] = ctl->value[1] = 20; 2185 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2186 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 2187 2188 #define BASS_GPR 0x8c 2189 #define TREBLE_GPR 0x96 2190 2191 for (z = 0; z < 5; z++) { 2192 int j; 2193 for (j = 0; j < 2; j++) { 2194 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j; 2195 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j; 2196 } 2197 } 2198 i += 2; 2199 2200 OP(icode, &ptr, iACC3, C_00000000, GPR(gpr), C_00000000, C_00000000); 2201 snd_emu10k1_init_mono_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0); 2202 gpr++; 2203 OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr)); 2204 ptr_skip = ptr; 2205 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */ 2206 int j, k, l, d; 2207 for (j = 0; j < 2; j++) { /* left/right */ 2208 k = 0xa0 + (z * 8) + (j * 4); 2209 l = 0xd0 + (z * 8) + (j * 4); 2210 d = playback + z * 2 + j; 2211 2212 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j)); 2213 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j)); 2214 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j)); 2215 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j)); 2216 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j)); 2217 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000); 2218 2219 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j)); 2220 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j)); 2221 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j)); 2222 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j)); 2223 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j)); 2224 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010); 2225 2226 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000); 2227 2228 if (z == 2) /* center */ 2229 break; 2230 } 2231 } 2232 gpr_map[gpr++] = ptr - ptr_skip; 2233 2234 #undef BASS_GPR 2235 #undef TREBLE_GPR 2236 2237 /* 2238 * Process outputs 2239 */ 2240 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) { 2241 /* AC'97 Playback Volume */ 2242 2243 for (z = 0; z < 2; z++) 2244 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + z), C_00000000, C_00000000); 2245 } 2246 2247 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) { 2248 /* IEC958 Optical Raw Playback Switch */ 2249 2250 for (z = 0; z < 2; z++) { 2251 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z); 2252 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 2253 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2254 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2255 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 2256 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2257 #endif 2258 } 2259 2260 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 2261 gpr += 2; 2262 } 2263 2264 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) { 2265 /* Headphone Playback Volume */ 2266 2267 for (z = 0; z < 2; z++) { 2268 SWITCH(icode, &ptr, tmp + 0, playback + 4 + z, gpr + 2 + z); 2269 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z); 2270 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2271 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2272 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z); 2273 } 2274 2275 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0); 2276 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */ 2277 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0); 2278 controls[i-1].id.index = 1; 2279 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0); 2280 controls[i-1].id.index = 1; 2281 2282 gpr += 4; 2283 } 2284 2285 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R))) 2286 for (z = 0; z < 2; z++) 2287 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000); 2288 2289 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R))) 2290 for (z = 0; z < 2; z++) 2291 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000); 2292 2293 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) { 2294 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2295 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 4), C_00000000, C_00000000); 2296 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 4), C_00000000, C_00000000); 2297 #else 2298 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 0), C_00000000, C_00000000); 2299 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 0), C_00000000, C_00000000); 2300 #endif 2301 } 2302 2303 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) { 2304 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2305 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 5), C_00000000, C_00000000); 2306 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 5), C_00000000, C_00000000); 2307 #else 2308 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 1), C_00000000, C_00000000); 2309 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 1), C_00000000, C_00000000); 2310 #endif 2311 } 2312 2313 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT 2314 for (z = 0; z < 2; z++) 2315 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000); 2316 #endif 2317 2318 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP)) 2319 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000); 2320 2321 /* EFX capture - capture the 16 EXTINS */ 2322 if (emu->card_capabilities->sblive51) { 2323 for (z = 0; z < 16; z++) { 2324 s8 c = snd_emu10k1_sblive51_fxbus2_map[z]; 2325 if (c != -1) 2326 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(c)); 2327 } 2328 } else { 2329 for (z = 0; z < 16; z++) 2330 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2331 } 2332 2333 2334 if (gpr > tmp) { 2335 snd_BUG(); 2336 err = -EIO; 2337 goto __err; 2338 } 2339 if (i > SND_EMU10K1_GPR_CONTROLS) { 2340 snd_BUG(); 2341 err = -EIO; 2342 goto __err; 2343 } 2344 2345 /* clear remaining instruction memory */ 2346 while (ptr < 0x200) 2347 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000); 2348 2349 err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size); 2350 if (err < 0) 2351 goto __err; 2352 icode->gpr_add_control_count = i; 2353 icode->gpr_add_controls = controls; 2354 emu->support_tlv = 1; /* support TLV */ 2355 err = snd_emu10k1_icode_poke(emu, icode, true); 2356 emu->support_tlv = 0; /* clear again */ 2357 if (err >= 0) 2358 err = snd_emu10k1_ipcm_poke(emu, ipcm); 2359 __err: 2360 kfree(ipcm); 2361 __err_ipcm: 2362 kfree(controls); 2363 __err_ctrls: 2364 kfree(icode->gpr_map); 2365 __err_gpr: 2366 kfree(icode); 2367 return err; 2368 } 2369 2370 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 2371 { 2372 spin_lock_init(&emu->fx8010.irq_lock); 2373 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl); 2374 if (emu->audigy) 2375 return _snd_emu10k1_audigy_init_efx(emu); 2376 else 2377 return _snd_emu10k1_init_efx(emu); 2378 } 2379 2380 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu) 2381 { 2382 /* stop processor */ 2383 if (emu->audigy) 2384 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP); 2385 else 2386 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP); 2387 } 2388 2389 #if 0 /* FIXME: who use them? */ 2390 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output) 2391 { 2392 if (output < 0 || output >= 6) 2393 return -EINVAL; 2394 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1); 2395 return 0; 2396 } 2397 2398 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output) 2399 { 2400 if (output < 0 || output >= 6) 2401 return -EINVAL; 2402 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0); 2403 return 0; 2404 } 2405 #endif 2406 2407 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size) 2408 { 2409 u8 size_reg = 0; 2410 2411 /* size is in samples */ 2412 if (size != 0) { 2413 size = (size - 1) >> 13; 2414 2415 while (size) { 2416 size >>= 1; 2417 size_reg++; 2418 } 2419 size = 0x2000 << size_reg; 2420 } 2421 if ((emu->fx8010.etram_pages.bytes / 2) == size) 2422 return 0; 2423 spin_lock_irq(&emu->emu_lock); 2424 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2425 spin_unlock_irq(&emu->emu_lock); 2426 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 2427 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 2428 if (emu->fx8010.etram_pages.area != NULL) { 2429 snd_dma_free_pages(&emu->fx8010.etram_pages); 2430 emu->fx8010.etram_pages.area = NULL; 2431 emu->fx8010.etram_pages.bytes = 0; 2432 } 2433 2434 if (size > 0) { 2435 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev, 2436 size * 2, &emu->fx8010.etram_pages) < 0) 2437 return -ENOMEM; 2438 memset(emu->fx8010.etram_pages.area, 0, size * 2); 2439 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2440 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2441 spin_lock_irq(&emu->emu_lock); 2442 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2443 spin_unlock_irq(&emu->emu_lock); 2444 } 2445 2446 return 0; 2447 } 2448 2449 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file) 2450 { 2451 return 0; 2452 } 2453 2454 static void copy_string(char *dst, const char *src, const char *null, int idx) 2455 { 2456 if (src == NULL) 2457 sprintf(dst, "%s %02X", null, idx); 2458 else 2459 strcpy(dst, src); 2460 } 2461 2462 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu, 2463 struct snd_emu10k1_fx8010_info *info) 2464 { 2465 const char * const *fxbus, * const *extin, * const *extout; 2466 unsigned short extin_mask, extout_mask; 2467 int res; 2468 2469 info->internal_tram_size = emu->fx8010.itram_size; 2470 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2; 2471 fxbus = snd_emu10k1_fxbus; 2472 extin = emu->audigy ? snd_emu10k1_audigy_ins : snd_emu10k1_sblive_ins; 2473 extout = emu->audigy ? snd_emu10k1_audigy_outs : snd_emu10k1_sblive_outs; 2474 extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask; 2475 extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask; 2476 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) { 2477 copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res); 2478 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res); 2479 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2480 } 2481 for (res = 16; res < 32; res++, extout++) 2482 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2483 info->gpr_controls = emu->fx8010.gpr_count; 2484 } 2485 2486 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg) 2487 { 2488 struct snd_emu10k1 *emu = hw->private_data; 2489 struct snd_emu10k1_fx8010_info *info; 2490 struct snd_emu10k1_fx8010_code *icode; 2491 struct snd_emu10k1_fx8010_pcm_rec *ipcm; 2492 unsigned int addr; 2493 void __user *argp = (void __user *)arg; 2494 int res; 2495 2496 switch (cmd) { 2497 case SNDRV_EMU10K1_IOCTL_PVERSION: 2498 emu->support_tlv = 1; 2499 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp); 2500 case SNDRV_EMU10K1_IOCTL_INFO: 2501 info = kzalloc(sizeof(*info), GFP_KERNEL); 2502 if (!info) 2503 return -ENOMEM; 2504 snd_emu10k1_fx8010_info(emu, info); 2505 if (copy_to_user(argp, info, sizeof(*info))) { 2506 kfree(info); 2507 return -EFAULT; 2508 } 2509 kfree(info); 2510 return 0; 2511 case SNDRV_EMU10K1_IOCTL_CODE_POKE: 2512 if (!capable(CAP_SYS_ADMIN)) 2513 return -EPERM; 2514 2515 icode = memdup_user(argp, sizeof(*icode)); 2516 if (IS_ERR(icode)) 2517 return PTR_ERR(icode); 2518 res = snd_emu10k1_icode_poke(emu, icode, false); 2519 kfree(icode); 2520 return res; 2521 case SNDRV_EMU10K1_IOCTL_CODE_PEEK: 2522 icode = memdup_user(argp, sizeof(*icode)); 2523 if (IS_ERR(icode)) 2524 return PTR_ERR(icode); 2525 res = snd_emu10k1_icode_peek(emu, icode); 2526 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) { 2527 kfree(icode); 2528 return -EFAULT; 2529 } 2530 kfree(icode); 2531 return res; 2532 case SNDRV_EMU10K1_IOCTL_PCM_POKE: 2533 ipcm = memdup_user(argp, sizeof(*ipcm)); 2534 if (IS_ERR(ipcm)) 2535 return PTR_ERR(ipcm); 2536 res = snd_emu10k1_ipcm_poke(emu, ipcm); 2537 kfree(ipcm); 2538 return res; 2539 case SNDRV_EMU10K1_IOCTL_PCM_PEEK: 2540 ipcm = memdup_user(argp, sizeof(*ipcm)); 2541 if (IS_ERR(ipcm)) 2542 return PTR_ERR(ipcm); 2543 res = snd_emu10k1_ipcm_peek(emu, ipcm); 2544 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) { 2545 kfree(ipcm); 2546 return -EFAULT; 2547 } 2548 kfree(ipcm); 2549 return res; 2550 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP: 2551 if (!capable(CAP_SYS_ADMIN)) 2552 return -EPERM; 2553 if (get_user(addr, (unsigned int __user *)argp)) 2554 return -EFAULT; 2555 mutex_lock(&emu->fx8010.lock); 2556 res = snd_emu10k1_fx8010_tram_setup(emu, addr); 2557 mutex_unlock(&emu->fx8010.lock); 2558 return res; 2559 case SNDRV_EMU10K1_IOCTL_STOP: 2560 if (!capable(CAP_SYS_ADMIN)) 2561 return -EPERM; 2562 if (emu->audigy) 2563 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2564 else 2565 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2566 return 0; 2567 case SNDRV_EMU10K1_IOCTL_CONTINUE: 2568 if (!capable(CAP_SYS_ADMIN)) 2569 return -EPERM; 2570 if (emu->audigy) 2571 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0); 2572 else 2573 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0); 2574 return 0; 2575 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER: 2576 if (!capable(CAP_SYS_ADMIN)) 2577 return -EPERM; 2578 if (emu->audigy) 2579 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC); 2580 else 2581 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC); 2582 udelay(10); 2583 if (emu->audigy) 2584 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2585 else 2586 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2587 return 0; 2588 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP: 2589 if (!capable(CAP_SYS_ADMIN)) 2590 return -EPERM; 2591 if (get_user(addr, (unsigned int __user *)argp)) 2592 return -EFAULT; 2593 if (emu->audigy) { 2594 if (addr > A_DBG_STEP_ADDR) 2595 return -EINVAL; 2596 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2597 udelay(10); 2598 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr); 2599 } else { 2600 if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR) 2601 return -EINVAL; 2602 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2603 udelay(10); 2604 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr); 2605 } 2606 return 0; 2607 case SNDRV_EMU10K1_IOCTL_DBG_READ: 2608 if (emu->audigy) 2609 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0); 2610 else 2611 addr = snd_emu10k1_ptr_read(emu, DBG, 0); 2612 if (put_user(addr, (unsigned int __user *)argp)) 2613 return -EFAULT; 2614 return 0; 2615 } 2616 return -ENOTTY; 2617 } 2618 2619 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file) 2620 { 2621 return 0; 2622 } 2623 2624 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device) 2625 { 2626 struct snd_hwdep *hw; 2627 int err; 2628 2629 err = snd_hwdep_new(emu->card, "FX8010", device, &hw); 2630 if (err < 0) 2631 return err; 2632 strcpy(hw->name, "EMU10K1 (FX8010)"); 2633 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1; 2634 hw->ops.open = snd_emu10k1_fx8010_open; 2635 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl; 2636 hw->ops.release = snd_emu10k1_fx8010_release; 2637 hw->private_data = emu; 2638 return 0; 2639 } 2640 2641 #ifdef CONFIG_PM_SLEEP 2642 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu) 2643 { 2644 int len; 2645 2646 len = emu->audigy ? 0x200 : 0x100; 2647 emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL); 2648 if (! emu->saved_gpr) 2649 return -ENOMEM; 2650 len = emu->audigy ? 0x100 : 0xa0; 2651 emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL); 2652 emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL); 2653 if (! emu->tram_val_saved || ! emu->tram_addr_saved) 2654 return -ENOMEM; 2655 len = emu->audigy ? 2 * 1024 : 2 * 512; 2656 emu->saved_icode = vmalloc(array_size(len, 4)); 2657 if (! emu->saved_icode) 2658 return -ENOMEM; 2659 return 0; 2660 } 2661 2662 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu) 2663 { 2664 kfree(emu->saved_gpr); 2665 kfree(emu->tram_val_saved); 2666 kfree(emu->tram_addr_saved); 2667 vfree(emu->saved_icode); 2668 } 2669 2670 /* 2671 * save/restore GPR, TRAM and codes 2672 */ 2673 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu) 2674 { 2675 int i, len; 2676 2677 len = emu->audigy ? 0x200 : 0x100; 2678 for (i = 0; i < len; i++) 2679 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0); 2680 2681 len = emu->audigy ? 0x100 : 0xa0; 2682 for (i = 0; i < len; i++) { 2683 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0); 2684 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0); 2685 if (emu->audigy) { 2686 emu->tram_addr_saved[i] >>= 12; 2687 emu->tram_addr_saved[i] |= 2688 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20; 2689 } 2690 } 2691 2692 len = emu->audigy ? 2 * 1024 : 2 * 512; 2693 for (i = 0; i < len; i++) 2694 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i); 2695 } 2696 2697 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu) 2698 { 2699 int i, len; 2700 2701 /* set up TRAM */ 2702 if (emu->fx8010.etram_pages.bytes > 0) { 2703 unsigned size, size_reg = 0; 2704 size = emu->fx8010.etram_pages.bytes / 2; 2705 size = (size - 1) >> 13; 2706 while (size) { 2707 size >>= 1; 2708 size_reg++; 2709 } 2710 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2711 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2712 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2713 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2714 } 2715 2716 if (emu->audigy) 2717 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 2718 else 2719 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 2720 2721 len = emu->audigy ? 0x200 : 0x100; 2722 for (i = 0; i < len; i++) 2723 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]); 2724 2725 len = emu->audigy ? 0x100 : 0xa0; 2726 for (i = 0; i < len; i++) { 2727 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0, 2728 emu->tram_val_saved[i]); 2729 if (! emu->audigy) 2730 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2731 emu->tram_addr_saved[i]); 2732 else { 2733 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2734 emu->tram_addr_saved[i] << 12); 2735 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2736 emu->tram_addr_saved[i] >> 20); 2737 } 2738 } 2739 2740 len = emu->audigy ? 2 * 1024 : 2 * 512; 2741 for (i = 0; i < len; i++) 2742 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]); 2743 2744 /* start FX processor when the DSP code is updated */ 2745 if (emu->audigy) 2746 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2747 else 2748 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2749 } 2750 #endif 2751