1dd7b254dSGiuliano Pochini /**************************************************************************** 2dd7b254dSGiuliano Pochini 3dd7b254dSGiuliano Pochini Copyright Echo Digital Audio Corporation (c) 1998 - 2004 4dd7b254dSGiuliano Pochini All rights reserved 5dd7b254dSGiuliano Pochini www.echoaudio.com 6dd7b254dSGiuliano Pochini 7dd7b254dSGiuliano Pochini This file is part of Echo Digital Audio's generic driver library. 8dd7b254dSGiuliano Pochini 9dd7b254dSGiuliano Pochini Echo Digital Audio's generic driver library is free software; 10dd7b254dSGiuliano Pochini you can redistribute it and/or modify it under the terms of 11dd7b254dSGiuliano Pochini the GNU General Public License as published by the Free Software 12dd7b254dSGiuliano Pochini Foundation. 13dd7b254dSGiuliano Pochini 14dd7b254dSGiuliano Pochini This program is distributed in the hope that it will be useful, 15dd7b254dSGiuliano Pochini but WITHOUT ANY WARRANTY; without even the implied warranty of 16dd7b254dSGiuliano Pochini MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17dd7b254dSGiuliano Pochini GNU General Public License for more details. 18dd7b254dSGiuliano Pochini 19dd7b254dSGiuliano Pochini You should have received a copy of the GNU General Public License 20dd7b254dSGiuliano Pochini along with this program; if not, write to the Free Software 21dd7b254dSGiuliano Pochini Foundation, Inc., 59 Temple Place - Suite 330, Boston, 22dd7b254dSGiuliano Pochini MA 02111-1307, USA. 23dd7b254dSGiuliano Pochini 24dd7b254dSGiuliano Pochini ************************************************************************* 25dd7b254dSGiuliano Pochini 26dd7b254dSGiuliano Pochini Translation from C++ and adaptation for use in ALSA-Driver 27dd7b254dSGiuliano Pochini were made by Giuliano Pochini <pochini@shiny.it> 28dd7b254dSGiuliano Pochini 29dd7b254dSGiuliano Pochini ****************************************************************************/ 30dd7b254dSGiuliano Pochini 31dd7b254dSGiuliano Pochini #ifndef _ECHO_DSP_ 32dd7b254dSGiuliano Pochini #define _ECHO_DSP_ 33dd7b254dSGiuliano Pochini 34dd7b254dSGiuliano Pochini 35dd7b254dSGiuliano Pochini /**** Echogals: Darla20, Gina20, Layla20, and Darla24 ****/ 36dd7b254dSGiuliano Pochini #if defined(ECHOGALS_FAMILY) 37dd7b254dSGiuliano Pochini 38dd7b254dSGiuliano Pochini #define NUM_ASIC_TESTS 5 39dd7b254dSGiuliano Pochini #define READ_DSP_TIMEOUT 1000000L /* one second */ 40dd7b254dSGiuliano Pochini 41dd7b254dSGiuliano Pochini /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/ 42dd7b254dSGiuliano Pochini #elif defined(ECHO24_FAMILY) 43dd7b254dSGiuliano Pochini 44dd7b254dSGiuliano Pochini #define DSP_56361 /* Some Echo24 cards use the 56361 DSP */ 45dd7b254dSGiuliano Pochini #define READ_DSP_TIMEOUT 100000L /* .1 second */ 46dd7b254dSGiuliano Pochini 47dd7b254dSGiuliano Pochini /**** 3G: Gina3G, Layla3G ****/ 48dd7b254dSGiuliano Pochini #elif defined(ECHO3G_FAMILY) 49dd7b254dSGiuliano Pochini 50dd7b254dSGiuliano Pochini #define DSP_56361 51dd7b254dSGiuliano Pochini #define READ_DSP_TIMEOUT 100000L /* .1 second */ 52dd7b254dSGiuliano Pochini #define MIN_MTC_1X_RATE 32000 53dd7b254dSGiuliano Pochini 54dd7b254dSGiuliano Pochini /**** Indigo: Indigo, Indigo IO, Indigo DJ ****/ 55dd7b254dSGiuliano Pochini #elif defined(INDIGO_FAMILY) 56dd7b254dSGiuliano Pochini 57dd7b254dSGiuliano Pochini #define DSP_56361 58dd7b254dSGiuliano Pochini #define READ_DSP_TIMEOUT 100000L /* .1 second */ 59dd7b254dSGiuliano Pochini 60dd7b254dSGiuliano Pochini #else 61dd7b254dSGiuliano Pochini 62dd7b254dSGiuliano Pochini #error No family is defined 63dd7b254dSGiuliano Pochini 64dd7b254dSGiuliano Pochini #endif 65dd7b254dSGiuliano Pochini 66dd7b254dSGiuliano Pochini 67dd7b254dSGiuliano Pochini 68dd7b254dSGiuliano Pochini /* 69dd7b254dSGiuliano Pochini * 70dd7b254dSGiuliano Pochini * Max inputs and outputs 71dd7b254dSGiuliano Pochini * 72dd7b254dSGiuliano Pochini */ 73dd7b254dSGiuliano Pochini 74dd7b254dSGiuliano Pochini #define DSP_MAXAUDIOINPUTS 16 /* Max audio input channels */ 75dd7b254dSGiuliano Pochini #define DSP_MAXAUDIOOUTPUTS 16 /* Max audio output channels */ 76dd7b254dSGiuliano Pochini #define DSP_MAXPIPES 32 /* Max total pipes (input + output) */ 77dd7b254dSGiuliano Pochini 78dd7b254dSGiuliano Pochini 79dd7b254dSGiuliano Pochini /* 80dd7b254dSGiuliano Pochini * 81dd7b254dSGiuliano Pochini * These are the offsets for the memory-mapped DSP registers; the DSP base 82dd7b254dSGiuliano Pochini * address is treated as the start of a u32 array. 83dd7b254dSGiuliano Pochini */ 84dd7b254dSGiuliano Pochini 85dd7b254dSGiuliano Pochini #define CHI32_CONTROL_REG 4 86dd7b254dSGiuliano Pochini #define CHI32_STATUS_REG 5 87dd7b254dSGiuliano Pochini #define CHI32_VECTOR_REG 6 88dd7b254dSGiuliano Pochini #define CHI32_DATA_REG 7 89dd7b254dSGiuliano Pochini 90dd7b254dSGiuliano Pochini 91dd7b254dSGiuliano Pochini /* 92dd7b254dSGiuliano Pochini * 93dd7b254dSGiuliano Pochini * Interesting bits within the DSP registers 94dd7b254dSGiuliano Pochini * 95dd7b254dSGiuliano Pochini */ 96dd7b254dSGiuliano Pochini 97dd7b254dSGiuliano Pochini #define CHI32_VECTOR_BUSY 0x00000001 98dd7b254dSGiuliano Pochini #define CHI32_STATUS_REG_HF3 0x00000008 99dd7b254dSGiuliano Pochini #define CHI32_STATUS_REG_HF4 0x00000010 100dd7b254dSGiuliano Pochini #define CHI32_STATUS_REG_HF5 0x00000020 101dd7b254dSGiuliano Pochini #define CHI32_STATUS_HOST_READ_FULL 0x00000004 102dd7b254dSGiuliano Pochini #define CHI32_STATUS_HOST_WRITE_EMPTY 0x00000002 103dd7b254dSGiuliano Pochini #define CHI32_STATUS_IRQ 0x00000040 104dd7b254dSGiuliano Pochini 105dd7b254dSGiuliano Pochini 106dd7b254dSGiuliano Pochini /* 107dd7b254dSGiuliano Pochini * 108dd7b254dSGiuliano Pochini * DSP commands sent via slave mode; these are sent to the DSP by write_dsp() 109dd7b254dSGiuliano Pochini * 110dd7b254dSGiuliano Pochini */ 111dd7b254dSGiuliano Pochini 112dd7b254dSGiuliano Pochini #define DSP_FNC_SET_COMMPAGE_ADDR 0x02 113dd7b254dSGiuliano Pochini #define DSP_FNC_LOAD_LAYLA_ASIC 0xa0 114dd7b254dSGiuliano Pochini #define DSP_FNC_LOAD_GINA24_ASIC 0xa0 115dd7b254dSGiuliano Pochini #define DSP_FNC_LOAD_MONA_PCI_CARD_ASIC 0xa0 116dd7b254dSGiuliano Pochini #define DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC 0xa0 117dd7b254dSGiuliano Pochini #define DSP_FNC_LOAD_MONA_EXTERNAL_ASIC 0xa1 118dd7b254dSGiuliano Pochini #define DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC 0xa1 119dd7b254dSGiuliano Pochini #define DSP_FNC_LOAD_3G_ASIC 0xa0 120dd7b254dSGiuliano Pochini 121dd7b254dSGiuliano Pochini 122dd7b254dSGiuliano Pochini /* 123dd7b254dSGiuliano Pochini * 124dd7b254dSGiuliano Pochini * Defines to handle the MIDI input state engine; these are used to properly 125dd7b254dSGiuliano Pochini * extract MIDI time code bytes and their timestamps from the MIDI input stream. 126dd7b254dSGiuliano Pochini * 127dd7b254dSGiuliano Pochini */ 128dd7b254dSGiuliano Pochini 129dd7b254dSGiuliano Pochini #define MIDI_IN_STATE_NORMAL 0 130dd7b254dSGiuliano Pochini #define MIDI_IN_STATE_TS_HIGH 1 131dd7b254dSGiuliano Pochini #define MIDI_IN_STATE_TS_LOW 2 132dd7b254dSGiuliano Pochini #define MIDI_IN_STATE_F1_DATA 3 133dd7b254dSGiuliano Pochini #define MIDI_IN_SKIP_DATA (-1) 134dd7b254dSGiuliano Pochini 135dd7b254dSGiuliano Pochini 136dd7b254dSGiuliano Pochini /*---------------------------------------------------------------------------- 137dd7b254dSGiuliano Pochini 138dd7b254dSGiuliano Pochini Setting the sample rates on Layla24 is somewhat schizophrenic. 139dd7b254dSGiuliano Pochini 140dd7b254dSGiuliano Pochini For standard rates, it works exactly like Mona and Gina24. That is, for 141dd7b254dSGiuliano Pochini 8, 11.025, 16, 22.05, 32, 44.1, 48, 88.2, and 96 kHz, you just set the 142dd7b254dSGiuliano Pochini appropriate bits in the control register and write the control register. 143dd7b254dSGiuliano Pochini 144dd7b254dSGiuliano Pochini In order to support MIDI time code sync (and possibly SMPTE LTC sync in 145dd7b254dSGiuliano Pochini the future), Layla24 also has "continuous sample rate mode". In this mode, 146dd7b254dSGiuliano Pochini Layla24 can generate any sample rate between 25 and 50 kHz inclusive, or 147dd7b254dSGiuliano Pochini 50 to 100 kHz inclusive for double speed mode. 148dd7b254dSGiuliano Pochini 149dd7b254dSGiuliano Pochini To use continuous mode: 150dd7b254dSGiuliano Pochini 151dd7b254dSGiuliano Pochini -Set the clock select bits in the control register to 0xe (see the #define 152dd7b254dSGiuliano Pochini below) 153dd7b254dSGiuliano Pochini 154dd7b254dSGiuliano Pochini -Set double-speed mode if you want to use sample rates above 50 kHz 155dd7b254dSGiuliano Pochini 156dd7b254dSGiuliano Pochini -Write the control register as you would normally 157dd7b254dSGiuliano Pochini 158dd7b254dSGiuliano Pochini -Now, you need to set the frequency register. First, you need to determine the 159dd7b254dSGiuliano Pochini value for the frequency register. This is given by the following formula: 160dd7b254dSGiuliano Pochini 161dd7b254dSGiuliano Pochini frequency_reg = (LAYLA24_MAGIC_NUMBER / sample_rate) - 2 162dd7b254dSGiuliano Pochini 163dd7b254dSGiuliano Pochini Note the #define below for the magic number 164dd7b254dSGiuliano Pochini 165dd7b254dSGiuliano Pochini -Wait for the DSP handshake 166dd7b254dSGiuliano Pochini -Write the frequency_reg value to the .SampleRate field of the comm page 167dd7b254dSGiuliano Pochini -Send the vector command SET_LAYLA24_FREQUENCY_REG (see vmonkey.h) 168dd7b254dSGiuliano Pochini 169dd7b254dSGiuliano Pochini Once you have set the control register up for continuous mode, you can just 170dd7b254dSGiuliano Pochini write the frequency register to change the sample rate. This could be 171dd7b254dSGiuliano Pochini used for MIDI time code sync. For MTC sync, the control register is set for 172dd7b254dSGiuliano Pochini continuous mode. The driver then just keeps writing the 173dd7b254dSGiuliano Pochini SET_LAYLA24_FREQUENCY_REG command. 174dd7b254dSGiuliano Pochini 175dd7b254dSGiuliano Pochini -----------------------------------------------------------------------------*/ 176dd7b254dSGiuliano Pochini 177dd7b254dSGiuliano Pochini #define LAYLA24_MAGIC_NUMBER 677376000 178dd7b254dSGiuliano Pochini #define LAYLA24_CONTINUOUS_CLOCK 0x000e 179dd7b254dSGiuliano Pochini 180dd7b254dSGiuliano Pochini 181dd7b254dSGiuliano Pochini /* 182dd7b254dSGiuliano Pochini * 183dd7b254dSGiuliano Pochini * DSP vector commands 184dd7b254dSGiuliano Pochini * 185dd7b254dSGiuliano Pochini */ 186dd7b254dSGiuliano Pochini 187dd7b254dSGiuliano Pochini #define DSP_VC_RESET 0x80ff 188dd7b254dSGiuliano Pochini 189dd7b254dSGiuliano Pochini #ifndef DSP_56361 190dd7b254dSGiuliano Pochini 191dd7b254dSGiuliano Pochini #define DSP_VC_ACK_INT 0x8073 192dd7b254dSGiuliano Pochini #define DSP_VC_SET_VMIXER_GAIN 0x0000 /* Not used, only for compile */ 193dd7b254dSGiuliano Pochini #define DSP_VC_START_TRANSFER 0x0075 /* Handshke rqd. */ 194dd7b254dSGiuliano Pochini #define DSP_VC_METERS_ON 0x0079 195dd7b254dSGiuliano Pochini #define DSP_VC_METERS_OFF 0x007b 196dd7b254dSGiuliano Pochini #define DSP_VC_UPDATE_OUTVOL 0x007d /* Handshke rqd. */ 197dd7b254dSGiuliano Pochini #define DSP_VC_UPDATE_INGAIN 0x007f /* Handshke rqd. */ 198dd7b254dSGiuliano Pochini #define DSP_VC_ADD_AUDIO_BUFFER 0x0081 /* Handshke rqd. */ 199dd7b254dSGiuliano Pochini #define DSP_VC_TEST_ASIC 0x00eb 200dd7b254dSGiuliano Pochini #define DSP_VC_UPDATE_CLOCKS 0x00ef /* Handshke rqd. */ 201dd7b254dSGiuliano Pochini #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00f1 /* Handshke rqd. */ 202dd7b254dSGiuliano Pochini #define DSP_VC_SET_GD_AUDIO_STATE 0x00f1 /* Handshke rqd. */ 203dd7b254dSGiuliano Pochini #define DSP_VC_WRITE_CONTROL_REG 0x00f1 /* Handshke rqd. */ 204dd7b254dSGiuliano Pochini #define DSP_VC_MIDI_WRITE 0x00f5 /* Handshke rqd. */ 205dd7b254dSGiuliano Pochini #define DSP_VC_STOP_TRANSFER 0x00f7 /* Handshke rqd. */ 206dd7b254dSGiuliano Pochini #define DSP_VC_UPDATE_FLAGS 0x00fd /* Handshke rqd. */ 207dd7b254dSGiuliano Pochini #define DSP_VC_GO_COMATOSE 0x00f9 208dd7b254dSGiuliano Pochini 209dd7b254dSGiuliano Pochini #else /* !DSP_56361 */ 210dd7b254dSGiuliano Pochini 211dd7b254dSGiuliano Pochini /* Vector commands for families that use either the 56301 or 56361 */ 212dd7b254dSGiuliano Pochini #define DSP_VC_ACK_INT 0x80F5 213dd7b254dSGiuliano Pochini #define DSP_VC_SET_VMIXER_GAIN 0x00DB /* Handshke rqd. */ 214dd7b254dSGiuliano Pochini #define DSP_VC_START_TRANSFER 0x00DD /* Handshke rqd. */ 215dd7b254dSGiuliano Pochini #define DSP_VC_METERS_ON 0x00EF 216dd7b254dSGiuliano Pochini #define DSP_VC_METERS_OFF 0x00F1 217dd7b254dSGiuliano Pochini #define DSP_VC_UPDATE_OUTVOL 0x00E3 /* Handshke rqd. */ 218dd7b254dSGiuliano Pochini #define DSP_VC_UPDATE_INGAIN 0x00E5 /* Handshke rqd. */ 219dd7b254dSGiuliano Pochini #define DSP_VC_ADD_AUDIO_BUFFER 0x00E1 /* Handshke rqd. */ 220dd7b254dSGiuliano Pochini #define DSP_VC_TEST_ASIC 0x00ED 221dd7b254dSGiuliano Pochini #define DSP_VC_UPDATE_CLOCKS 0x00E9 /* Handshke rqd. */ 222dd7b254dSGiuliano Pochini #define DSP_VC_SET_LAYLA24_FREQUENCY_REG 0x00E9 /* Handshke rqd. */ 223dd7b254dSGiuliano Pochini #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00EB /* Handshke rqd. */ 224dd7b254dSGiuliano Pochini #define DSP_VC_SET_GD_AUDIO_STATE 0x00EB /* Handshke rqd. */ 225dd7b254dSGiuliano Pochini #define DSP_VC_WRITE_CONTROL_REG 0x00EB /* Handshke rqd. */ 226dd7b254dSGiuliano Pochini #define DSP_VC_MIDI_WRITE 0x00E7 /* Handshke rqd. */ 227dd7b254dSGiuliano Pochini #define DSP_VC_STOP_TRANSFER 0x00DF /* Handshke rqd. */ 228dd7b254dSGiuliano Pochini #define DSP_VC_UPDATE_FLAGS 0x00FB /* Handshke rqd. */ 229dd7b254dSGiuliano Pochini #define DSP_VC_GO_COMATOSE 0x00d9 230dd7b254dSGiuliano Pochini 231dd7b254dSGiuliano Pochini #endif /* !DSP_56361 */ 232dd7b254dSGiuliano Pochini 233dd7b254dSGiuliano Pochini 234dd7b254dSGiuliano Pochini /* 235dd7b254dSGiuliano Pochini * 236dd7b254dSGiuliano Pochini * Timeouts 237dd7b254dSGiuliano Pochini * 238dd7b254dSGiuliano Pochini */ 239dd7b254dSGiuliano Pochini 240dd7b254dSGiuliano Pochini #define HANDSHAKE_TIMEOUT 20000 /* send_vector command timeout (20ms) */ 241dd7b254dSGiuliano Pochini #define VECTOR_BUSY_TIMEOUT 100000 /* 100ms */ 242dd7b254dSGiuliano Pochini #define MIDI_OUT_DELAY_USEC 2000 /* How long to wait after MIDI fills up */ 243dd7b254dSGiuliano Pochini 244dd7b254dSGiuliano Pochini 245dd7b254dSGiuliano Pochini /* 246dd7b254dSGiuliano Pochini * 247dd7b254dSGiuliano Pochini * Flags for .Flags field in the comm page 248dd7b254dSGiuliano Pochini * 249dd7b254dSGiuliano Pochini */ 250dd7b254dSGiuliano Pochini 251dd7b254dSGiuliano Pochini #define DSP_FLAG_MIDI_INPUT 0x0001 /* Enable MIDI input */ 252dd7b254dSGiuliano Pochini #define DSP_FLAG_SPDIF_NONAUDIO 0x0002 /* Sets the "non-audio" bit 253dd7b254dSGiuliano Pochini * in the S/PDIF out status 254dd7b254dSGiuliano Pochini * bits. Clear this flag for 255dd7b254dSGiuliano Pochini * audio data; 256dd7b254dSGiuliano Pochini * set it for AC3 or WMA or 257dd7b254dSGiuliano Pochini * some such */ 258dd7b254dSGiuliano Pochini #define DSP_FLAG_PROFESSIONAL_SPDIF 0x0008 /* 1 Professional, 0 Consumer */ 259dd7b254dSGiuliano Pochini 260dd7b254dSGiuliano Pochini 261dd7b254dSGiuliano Pochini /* 262dd7b254dSGiuliano Pochini * 263dd7b254dSGiuliano Pochini * Clock detect bits reported by the DSP for Gina20, Layla20, Darla24, and Mia 264dd7b254dSGiuliano Pochini * 265dd7b254dSGiuliano Pochini */ 266dd7b254dSGiuliano Pochini 267dd7b254dSGiuliano Pochini #define GLDM_CLOCK_DETECT_BIT_WORD 0x0002 268dd7b254dSGiuliano Pochini #define GLDM_CLOCK_DETECT_BIT_SUPER 0x0004 269dd7b254dSGiuliano Pochini #define GLDM_CLOCK_DETECT_BIT_SPDIF 0x0008 270dd7b254dSGiuliano Pochini #define GLDM_CLOCK_DETECT_BIT_ESYNC 0x0010 271dd7b254dSGiuliano Pochini 272dd7b254dSGiuliano Pochini 273dd7b254dSGiuliano Pochini /* 274dd7b254dSGiuliano Pochini * 275dd7b254dSGiuliano Pochini * Clock detect bits reported by the DSP for Gina24, Mona, and Layla24 276dd7b254dSGiuliano Pochini * 277dd7b254dSGiuliano Pochini */ 278dd7b254dSGiuliano Pochini 279dd7b254dSGiuliano Pochini #define GML_CLOCK_DETECT_BIT_WORD96 0x0002 280dd7b254dSGiuliano Pochini #define GML_CLOCK_DETECT_BIT_WORD48 0x0004 281dd7b254dSGiuliano Pochini #define GML_CLOCK_DETECT_BIT_SPDIF48 0x0008 282dd7b254dSGiuliano Pochini #define GML_CLOCK_DETECT_BIT_SPDIF96 0x0010 283dd7b254dSGiuliano Pochini #define GML_CLOCK_DETECT_BIT_WORD (GML_CLOCK_DETECT_BIT_WORD96 | GML_CLOCK_DETECT_BIT_WORD48) 284dd7b254dSGiuliano Pochini #define GML_CLOCK_DETECT_BIT_SPDIF (GML_CLOCK_DETECT_BIT_SPDIF48 | GML_CLOCK_DETECT_BIT_SPDIF96) 285dd7b254dSGiuliano Pochini #define GML_CLOCK_DETECT_BIT_ESYNC 0x0020 286dd7b254dSGiuliano Pochini #define GML_CLOCK_DETECT_BIT_ADAT 0x0040 287dd7b254dSGiuliano Pochini 288dd7b254dSGiuliano Pochini 289dd7b254dSGiuliano Pochini /* 290dd7b254dSGiuliano Pochini * 291dd7b254dSGiuliano Pochini * Layla clock numbers to send to DSP 292dd7b254dSGiuliano Pochini * 293dd7b254dSGiuliano Pochini */ 294dd7b254dSGiuliano Pochini 295dd7b254dSGiuliano Pochini #define LAYLA20_CLOCK_INTERNAL 0 296dd7b254dSGiuliano Pochini #define LAYLA20_CLOCK_SPDIF 1 297dd7b254dSGiuliano Pochini #define LAYLA20_CLOCK_WORD 2 298dd7b254dSGiuliano Pochini #define LAYLA20_CLOCK_SUPER 3 299dd7b254dSGiuliano Pochini 300dd7b254dSGiuliano Pochini 301dd7b254dSGiuliano Pochini /* 302dd7b254dSGiuliano Pochini * 303dd7b254dSGiuliano Pochini * Gina/Darla clock states 304dd7b254dSGiuliano Pochini * 305dd7b254dSGiuliano Pochini */ 306dd7b254dSGiuliano Pochini 307dd7b254dSGiuliano Pochini #define GD_CLOCK_NOCHANGE 0 308dd7b254dSGiuliano Pochini #define GD_CLOCK_44 1 309dd7b254dSGiuliano Pochini #define GD_CLOCK_48 2 310dd7b254dSGiuliano Pochini #define GD_CLOCK_SPDIFIN 3 311dd7b254dSGiuliano Pochini #define GD_CLOCK_UNDEF 0xff 312dd7b254dSGiuliano Pochini 313dd7b254dSGiuliano Pochini 314dd7b254dSGiuliano Pochini /* 315dd7b254dSGiuliano Pochini * 316dd7b254dSGiuliano Pochini * Gina/Darla S/PDIF status bits 317dd7b254dSGiuliano Pochini * 318dd7b254dSGiuliano Pochini */ 319dd7b254dSGiuliano Pochini 320dd7b254dSGiuliano Pochini #define GD_SPDIF_STATUS_NOCHANGE 0 321dd7b254dSGiuliano Pochini #define GD_SPDIF_STATUS_44 1 322dd7b254dSGiuliano Pochini #define GD_SPDIF_STATUS_48 2 323dd7b254dSGiuliano Pochini #define GD_SPDIF_STATUS_UNDEF 0xff 324dd7b254dSGiuliano Pochini 325dd7b254dSGiuliano Pochini 326dd7b254dSGiuliano Pochini /* 327dd7b254dSGiuliano Pochini * 328dd7b254dSGiuliano Pochini * Layla20 output clocks 329dd7b254dSGiuliano Pochini * 330dd7b254dSGiuliano Pochini */ 331dd7b254dSGiuliano Pochini 332dd7b254dSGiuliano Pochini #define LAYLA20_OUTPUT_CLOCK_SUPER 0 333dd7b254dSGiuliano Pochini #define LAYLA20_OUTPUT_CLOCK_WORD 1 334dd7b254dSGiuliano Pochini 335dd7b254dSGiuliano Pochini 336dd7b254dSGiuliano Pochini /**************************************************************************** 337dd7b254dSGiuliano Pochini 338dd7b254dSGiuliano Pochini Magic constants for the Darla24 hardware 339dd7b254dSGiuliano Pochini 340dd7b254dSGiuliano Pochini ****************************************************************************/ 341dd7b254dSGiuliano Pochini 342dd7b254dSGiuliano Pochini #define GD24_96000 0x0 343dd7b254dSGiuliano Pochini #define GD24_48000 0x1 344dd7b254dSGiuliano Pochini #define GD24_44100 0x2 345dd7b254dSGiuliano Pochini #define GD24_32000 0x3 346dd7b254dSGiuliano Pochini #define GD24_22050 0x4 347dd7b254dSGiuliano Pochini #define GD24_16000 0x5 348dd7b254dSGiuliano Pochini #define GD24_11025 0x6 349dd7b254dSGiuliano Pochini #define GD24_8000 0x7 350dd7b254dSGiuliano Pochini #define GD24_88200 0x8 351dd7b254dSGiuliano Pochini #define GD24_EXT_SYNC 0x9 352dd7b254dSGiuliano Pochini 353dd7b254dSGiuliano Pochini 354dd7b254dSGiuliano Pochini /* 355dd7b254dSGiuliano Pochini * 356dd7b254dSGiuliano Pochini * Return values from the DSP when ASIC is loaded 357dd7b254dSGiuliano Pochini * 358dd7b254dSGiuliano Pochini */ 359dd7b254dSGiuliano Pochini 360dd7b254dSGiuliano Pochini #define ASIC_ALREADY_LOADED 0x1 361dd7b254dSGiuliano Pochini #define ASIC_NOT_LOADED 0x0 362dd7b254dSGiuliano Pochini 363dd7b254dSGiuliano Pochini 364dd7b254dSGiuliano Pochini /* 365dd7b254dSGiuliano Pochini * 366dd7b254dSGiuliano Pochini * DSP Audio formats 367dd7b254dSGiuliano Pochini * 368dd7b254dSGiuliano Pochini * These are the audio formats that the DSP can transfer 369dd7b254dSGiuliano Pochini * via input and output pipes. LE means little-endian, 370dd7b254dSGiuliano Pochini * BE means big-endian. 371dd7b254dSGiuliano Pochini * 372dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_MS_8 373dd7b254dSGiuliano Pochini * 374dd7b254dSGiuliano Pochini * 8-bit mono unsigned samples. For playback, 375dd7b254dSGiuliano Pochini * mono data is duplicated out the left and right channels 376dd7b254dSGiuliano Pochini * of the output bus. The "MS" part of the name 377dd7b254dSGiuliano Pochini * means mono->stereo. 378dd7b254dSGiuliano Pochini * 379dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_MS_16LE 380dd7b254dSGiuliano Pochini * 381dd7b254dSGiuliano Pochini * 16-bit signed little-endian mono samples. Playback works 382dd7b254dSGiuliano Pochini * like the previous code. 383dd7b254dSGiuliano Pochini * 384dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_MS_24LE 385dd7b254dSGiuliano Pochini * 386dd7b254dSGiuliano Pochini * 24-bit signed little-endian mono samples. Data is packed 387dd7b254dSGiuliano Pochini * three bytes per sample; if you had two samples 0x112233 and 0x445566 388dd7b254dSGiuliano Pochini * they would be stored in memory like this: 33 22 11 66 55 44. 389dd7b254dSGiuliano Pochini * 390dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_MS_32LE 391dd7b254dSGiuliano Pochini * 392dd7b254dSGiuliano Pochini * 24-bit signed little-endian mono samples in a 32-bit 393dd7b254dSGiuliano Pochini * container. In other words, each sample is a 32-bit signed 394dd7b254dSGiuliano Pochini * integer, where the actual audio data is left-justified 395dd7b254dSGiuliano Pochini * in the 32 bits and only the 24 most significant bits are valid. 396dd7b254dSGiuliano Pochini * 397dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_SS_8 398dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_SS_16LE 399dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_SS_24LE 400dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_SS_32LE 401dd7b254dSGiuliano Pochini * 402dd7b254dSGiuliano Pochini * Like the previous ones, except now with stereo interleaved 403dd7b254dSGiuliano Pochini * data. "SS" means stereo->stereo. 404dd7b254dSGiuliano Pochini * 405dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_MM_32LE 406dd7b254dSGiuliano Pochini * 407dd7b254dSGiuliano Pochini * Similar to DSP_AUDIOFORM_MS_32LE, except that the mono 408dd7b254dSGiuliano Pochini * data is not duplicated out both the left and right outputs. 409dd7b254dSGiuliano Pochini * This mode is used by the ASIO driver. Here, "MM" means 410dd7b254dSGiuliano Pochini * mono->mono. 411dd7b254dSGiuliano Pochini * 412dd7b254dSGiuliano Pochini * DSP_AUDIOFORM_MM_32BE 413dd7b254dSGiuliano Pochini * 414dd7b254dSGiuliano Pochini * Just like DSP_AUDIOFORM_MM_32LE, but now the data is 415dd7b254dSGiuliano Pochini * in big-endian format. 416dd7b254dSGiuliano Pochini * 417dd7b254dSGiuliano Pochini */ 418dd7b254dSGiuliano Pochini 419dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_MS_8 0 /* 8 bit mono */ 420dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_MS_16LE 1 /* 16 bit mono */ 421dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_MS_24LE 2 /* 24 bit mono */ 422dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_MS_32LE 3 /* 32 bit mono */ 423dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_SS_8 4 /* 8 bit stereo */ 424dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_SS_16LE 5 /* 16 bit stereo */ 425dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_SS_24LE 6 /* 24 bit stereo */ 426dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_SS_32LE 7 /* 32 bit stereo */ 427dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_MM_32LE 8 /* 32 bit mono->mono little-endian */ 428dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_MM_32BE 9 /* 32 bit mono->mono big-endian */ 429dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_SS_32BE 10 /* 32 bit stereo big endian */ 430dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_INVALID 0xFF /* Invalid audio format */ 431dd7b254dSGiuliano Pochini 432dd7b254dSGiuliano Pochini 433dd7b254dSGiuliano Pochini /* 434dd7b254dSGiuliano Pochini * 435dd7b254dSGiuliano Pochini * Super-interleave is defined as interleaving by 4 or more. Darla20 and Gina20 436dd7b254dSGiuliano Pochini * do not support super interleave. 437dd7b254dSGiuliano Pochini * 438dd7b254dSGiuliano Pochini * 16 bit, 24 bit, and 32 bit little endian samples are supported for super 439dd7b254dSGiuliano Pochini * interleave. The interleave factor must be even. 16 - way interleave is the 440dd7b254dSGiuliano Pochini * current maximum, so you can interleave by 4, 6, 8, 10, 12, 14, and 16. 441dd7b254dSGiuliano Pochini * 442dd7b254dSGiuliano Pochini * The actual format code is derived by taking the define below and or-ing with 443dd7b254dSGiuliano Pochini * the interleave factor. So, 32 bit interleave by 6 is 0x86 and 444dd7b254dSGiuliano Pochini * 16 bit interleave by 16 is (0x40 | 0x10) = 0x50. 445dd7b254dSGiuliano Pochini * 446dd7b254dSGiuliano Pochini */ 447dd7b254dSGiuliano Pochini 448dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE 0x40 449dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE 0xc0 450dd7b254dSGiuliano Pochini #define DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE 0x80 451dd7b254dSGiuliano Pochini 452dd7b254dSGiuliano Pochini 453dd7b254dSGiuliano Pochini /* 454dd7b254dSGiuliano Pochini * 455dd7b254dSGiuliano Pochini * Gina24, Mona, and Layla24 control register defines 456dd7b254dSGiuliano Pochini * 457dd7b254dSGiuliano Pochini */ 458dd7b254dSGiuliano Pochini 459dd7b254dSGiuliano Pochini #define GML_CONVERTER_ENABLE 0x0010 460dd7b254dSGiuliano Pochini #define GML_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1, 461dd7b254dSGiuliano Pochini consumer == 0 */ 462dd7b254dSGiuliano Pochini #define GML_SPDIF_SAMPLE_RATE0 0x0040 463dd7b254dSGiuliano Pochini #define GML_SPDIF_SAMPLE_RATE1 0x0080 464dd7b254dSGiuliano Pochini #define GML_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels, 465dd7b254dSGiuliano Pochini 0 == one channel */ 466dd7b254dSGiuliano Pochini #define GML_SPDIF_NOT_AUDIO 0x0200 467dd7b254dSGiuliano Pochini #define GML_SPDIF_COPY_PERMIT 0x0400 468dd7b254dSGiuliano Pochini #define GML_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */ 469dd7b254dSGiuliano Pochini #define GML_ADAT_MODE 0x1000 /* 1 == ADAT mode, 0 == S/PDIF mode */ 470dd7b254dSGiuliano Pochini #define GML_SPDIF_OPTICAL_MODE 0x2000 /* 1 == optical mode, 0 == RCA mode */ 471dd7b254dSGiuliano Pochini #define GML_SPDIF_CDROM_MODE 0x3000 /* 1 == CDROM mode, 472dd7b254dSGiuliano Pochini * 0 == RCA or optical mode */ 473dd7b254dSGiuliano Pochini #define GML_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed, 474dd7b254dSGiuliano Pochini 0 == single speed */ 475dd7b254dSGiuliano Pochini 476dd7b254dSGiuliano Pochini #define GML_DIGITAL_IN_AUTO_MUTE 0x800000 477dd7b254dSGiuliano Pochini 478dd7b254dSGiuliano Pochini #define GML_96KHZ (0x0 | GML_DOUBLE_SPEED_MODE) 479dd7b254dSGiuliano Pochini #define GML_88KHZ (0x1 | GML_DOUBLE_SPEED_MODE) 480dd7b254dSGiuliano Pochini #define GML_48KHZ 0x2 481dd7b254dSGiuliano Pochini #define GML_44KHZ 0x3 482dd7b254dSGiuliano Pochini #define GML_32KHZ 0x4 483dd7b254dSGiuliano Pochini #define GML_22KHZ 0x5 484dd7b254dSGiuliano Pochini #define GML_16KHZ 0x6 485dd7b254dSGiuliano Pochini #define GML_11KHZ 0x7 486dd7b254dSGiuliano Pochini #define GML_8KHZ 0x8 487dd7b254dSGiuliano Pochini #define GML_SPDIF_CLOCK 0x9 488dd7b254dSGiuliano Pochini #define GML_ADAT_CLOCK 0xA 489dd7b254dSGiuliano Pochini #define GML_WORD_CLOCK 0xB 490dd7b254dSGiuliano Pochini #define GML_ESYNC_CLOCK 0xC 491dd7b254dSGiuliano Pochini #define GML_ESYNCx2_CLOCK 0xD 492dd7b254dSGiuliano Pochini 493dd7b254dSGiuliano Pochini #define GML_CLOCK_CLEAR_MASK 0xffffbff0 494dd7b254dSGiuliano Pochini #define GML_SPDIF_RATE_CLEAR_MASK (~(GML_SPDIF_SAMPLE_RATE0|GML_SPDIF_SAMPLE_RATE1)) 495dd7b254dSGiuliano Pochini #define GML_DIGITAL_MODE_CLEAR_MASK 0xffffcfff 496dd7b254dSGiuliano Pochini #define GML_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f 497dd7b254dSGiuliano Pochini 498dd7b254dSGiuliano Pochini 499dd7b254dSGiuliano Pochini /* 500dd7b254dSGiuliano Pochini * 501dd7b254dSGiuliano Pochini * Mia sample rate and clock setting constants 502dd7b254dSGiuliano Pochini * 503dd7b254dSGiuliano Pochini */ 504dd7b254dSGiuliano Pochini 505dd7b254dSGiuliano Pochini #define MIA_32000 0x0040 506dd7b254dSGiuliano Pochini #define MIA_44100 0x0042 507dd7b254dSGiuliano Pochini #define MIA_48000 0x0041 508dd7b254dSGiuliano Pochini #define MIA_88200 0x0142 509dd7b254dSGiuliano Pochini #define MIA_96000 0x0141 510dd7b254dSGiuliano Pochini 511dd7b254dSGiuliano Pochini #define MIA_SPDIF 0x00000044 512dd7b254dSGiuliano Pochini #define MIA_SPDIF96 0x00000144 513dd7b254dSGiuliano Pochini 514dd7b254dSGiuliano Pochini #define MIA_MIDI_REV 1 /* Must be Mia rev 1 for MIDI support */ 515dd7b254dSGiuliano Pochini 516dd7b254dSGiuliano Pochini 517dd7b254dSGiuliano Pochini /* 518dd7b254dSGiuliano Pochini * 519dd7b254dSGiuliano Pochini * 3G register bits 520dd7b254dSGiuliano Pochini * 521dd7b254dSGiuliano Pochini */ 522dd7b254dSGiuliano Pochini 523dd7b254dSGiuliano Pochini #define E3G_CONVERTER_ENABLE 0x0010 524dd7b254dSGiuliano Pochini #define E3G_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1, 525dd7b254dSGiuliano Pochini consumer == 0 */ 526dd7b254dSGiuliano Pochini #define E3G_SPDIF_SAMPLE_RATE0 0x0040 527dd7b254dSGiuliano Pochini #define E3G_SPDIF_SAMPLE_RATE1 0x0080 528dd7b254dSGiuliano Pochini #define E3G_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels, 529dd7b254dSGiuliano Pochini 0 == one channel */ 530dd7b254dSGiuliano Pochini #define E3G_SPDIF_NOT_AUDIO 0x0200 531dd7b254dSGiuliano Pochini #define E3G_SPDIF_COPY_PERMIT 0x0400 532dd7b254dSGiuliano Pochini #define E3G_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */ 533dd7b254dSGiuliano Pochini #define E3G_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed, 534dd7b254dSGiuliano Pochini 0 == single speed */ 535dd7b254dSGiuliano Pochini #define E3G_PHANTOM_POWER 0x8000 /* 1 == phantom power on, 536dd7b254dSGiuliano Pochini 0 == phantom power off */ 537dd7b254dSGiuliano Pochini 538dd7b254dSGiuliano Pochini #define E3G_96KHZ (0x0 | E3G_DOUBLE_SPEED_MODE) 539dd7b254dSGiuliano Pochini #define E3G_88KHZ (0x1 | E3G_DOUBLE_SPEED_MODE) 540dd7b254dSGiuliano Pochini #define E3G_48KHZ 0x2 541dd7b254dSGiuliano Pochini #define E3G_44KHZ 0x3 542dd7b254dSGiuliano Pochini #define E3G_32KHZ 0x4 543dd7b254dSGiuliano Pochini #define E3G_22KHZ 0x5 544dd7b254dSGiuliano Pochini #define E3G_16KHZ 0x6 545dd7b254dSGiuliano Pochini #define E3G_11KHZ 0x7 546dd7b254dSGiuliano Pochini #define E3G_8KHZ 0x8 547dd7b254dSGiuliano Pochini #define E3G_SPDIF_CLOCK 0x9 548dd7b254dSGiuliano Pochini #define E3G_ADAT_CLOCK 0xA 549dd7b254dSGiuliano Pochini #define E3G_WORD_CLOCK 0xB 550dd7b254dSGiuliano Pochini #define E3G_CONTINUOUS_CLOCK 0xE 551dd7b254dSGiuliano Pochini 552dd7b254dSGiuliano Pochini #define E3G_ADAT_MODE 0x1000 553dd7b254dSGiuliano Pochini #define E3G_SPDIF_OPTICAL_MODE 0x2000 554dd7b254dSGiuliano Pochini 555dd7b254dSGiuliano Pochini #define E3G_CLOCK_CLEAR_MASK 0xbfffbff0 556dd7b254dSGiuliano Pochini #define E3G_DIGITAL_MODE_CLEAR_MASK 0xffffcfff 557dd7b254dSGiuliano Pochini #define E3G_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f 558dd7b254dSGiuliano Pochini 559dd7b254dSGiuliano Pochini /* Clock detect bits reported by the DSP */ 560dd7b254dSGiuliano Pochini #define E3G_CLOCK_DETECT_BIT_WORD96 0x0001 561dd7b254dSGiuliano Pochini #define E3G_CLOCK_DETECT_BIT_WORD48 0x0002 562dd7b254dSGiuliano Pochini #define E3G_CLOCK_DETECT_BIT_SPDIF48 0x0004 563dd7b254dSGiuliano Pochini #define E3G_CLOCK_DETECT_BIT_ADAT 0x0004 564dd7b254dSGiuliano Pochini #define E3G_CLOCK_DETECT_BIT_SPDIF96 0x0008 565dd7b254dSGiuliano Pochini #define E3G_CLOCK_DETECT_BIT_WORD (E3G_CLOCK_DETECT_BIT_WORD96|E3G_CLOCK_DETECT_BIT_WORD48) 566dd7b254dSGiuliano Pochini #define E3G_CLOCK_DETECT_BIT_SPDIF (E3G_CLOCK_DETECT_BIT_SPDIF48|E3G_CLOCK_DETECT_BIT_SPDIF96) 567dd7b254dSGiuliano Pochini 568dd7b254dSGiuliano Pochini /* Frequency control register */ 569dd7b254dSGiuliano Pochini #define E3G_MAGIC_NUMBER 677376000 570dd7b254dSGiuliano Pochini #define E3G_FREQ_REG_DEFAULT (E3G_MAGIC_NUMBER / 48000 - 2) 571dd7b254dSGiuliano Pochini #define E3G_FREQ_REG_MAX 0xffff 572dd7b254dSGiuliano Pochini 573dd7b254dSGiuliano Pochini /* 3G external box types */ 574dd7b254dSGiuliano Pochini #define E3G_GINA3G_BOX_TYPE 0x00 575dd7b254dSGiuliano Pochini #define E3G_LAYLA3G_BOX_TYPE 0x10 576dd7b254dSGiuliano Pochini #define E3G_ASIC_NOT_LOADED 0xffff 577dd7b254dSGiuliano Pochini #define E3G_BOX_TYPE_MASK 0xf0 578dd7b254dSGiuliano Pochini 579dd7b254dSGiuliano Pochini #define EXT_3GBOX_NC 0x01 580dd7b254dSGiuliano Pochini #define EXT_3GBOX_NOT_SET 0x02 581dd7b254dSGiuliano Pochini 582dd7b254dSGiuliano Pochini 583dd7b254dSGiuliano Pochini /* 584dd7b254dSGiuliano Pochini * 585dd7b254dSGiuliano Pochini * Gina20 & Layla20 have input gain controls for the analog inputs; 586dd7b254dSGiuliano Pochini * this is the magic number for the hardware that gives you 0 dB at -10. 587dd7b254dSGiuliano Pochini * 588dd7b254dSGiuliano Pochini */ 589dd7b254dSGiuliano Pochini 590dd7b254dSGiuliano Pochini #define GL20_INPUT_GAIN_MAGIC_NUMBER 0xC8 591dd7b254dSGiuliano Pochini 592dd7b254dSGiuliano Pochini 593dd7b254dSGiuliano Pochini /* 594dd7b254dSGiuliano Pochini * 595dd7b254dSGiuliano Pochini * Defines how much time must pass between DSP load attempts 596dd7b254dSGiuliano Pochini * 597dd7b254dSGiuliano Pochini */ 598dd7b254dSGiuliano Pochini 599dd7b254dSGiuliano Pochini #define DSP_LOAD_ATTEMPT_PERIOD 1000000L /* One second */ 600dd7b254dSGiuliano Pochini 601dd7b254dSGiuliano Pochini 602dd7b254dSGiuliano Pochini /* 603dd7b254dSGiuliano Pochini * 604dd7b254dSGiuliano Pochini * Size of arrays for the comm page. MAX_PLAY_TAPS and MAX_REC_TAPS are 605dd7b254dSGiuliano Pochini * no longer used, but the sizes must still be right for the DSP to see 606dd7b254dSGiuliano Pochini * the comm page correctly. 607dd7b254dSGiuliano Pochini * 608dd7b254dSGiuliano Pochini */ 609dd7b254dSGiuliano Pochini 610dd7b254dSGiuliano Pochini #define MONITOR_ARRAY_SIZE 0x180 611dd7b254dSGiuliano Pochini #define VMIXER_ARRAY_SIZE 0x40 612dd7b254dSGiuliano Pochini #define MIDI_OUT_BUFFER_SIZE 32 613dd7b254dSGiuliano Pochini #define MIDI_IN_BUFFER_SIZE 256 614dd7b254dSGiuliano Pochini #define MAX_PLAY_TAPS 168 615dd7b254dSGiuliano Pochini #define MAX_REC_TAPS 192 616dd7b254dSGiuliano Pochini #define DSP_MIDI_OUT_FIFO_SIZE 64 617dd7b254dSGiuliano Pochini 618dd7b254dSGiuliano Pochini 619dd7b254dSGiuliano Pochini /* sg_entry is a single entry for the scatter-gather list. The array of struct 620dd7b254dSGiuliano Pochini sg_entry struct is read by the DSP, so all values must be little-endian. */ 621dd7b254dSGiuliano Pochini 622dd7b254dSGiuliano Pochini #define MAX_SGLIST_ENTRIES 512 623dd7b254dSGiuliano Pochini 624dd7b254dSGiuliano Pochini struct sg_entry { 625dd7b254dSGiuliano Pochini u32 addr; 626dd7b254dSGiuliano Pochini u32 size; 627dd7b254dSGiuliano Pochini }; 628dd7b254dSGiuliano Pochini 629dd7b254dSGiuliano Pochini 630dd7b254dSGiuliano Pochini /**************************************************************************** 631dd7b254dSGiuliano Pochini 632dd7b254dSGiuliano Pochini The comm page. This structure is read and written by the DSP; the 633dd7b254dSGiuliano Pochini DSP code is a firm believer in the byte offsets written in the comments 634dd7b254dSGiuliano Pochini at the end of each line. This structure should not be changed. 635dd7b254dSGiuliano Pochini 636dd7b254dSGiuliano Pochini Any reads from or writes to this structure should be in little-endian format. 637dd7b254dSGiuliano Pochini 638dd7b254dSGiuliano Pochini ****************************************************************************/ 639dd7b254dSGiuliano Pochini 640dd7b254dSGiuliano Pochini struct comm_page { /* Base Length*/ 641dd7b254dSGiuliano Pochini u32 comm_size; /* size of this object 0x000 4 */ 642dd7b254dSGiuliano Pochini u32 flags; /* See Appendix A below 0x004 4 */ 643dd7b254dSGiuliano Pochini u32 unused; /* Unused entry 0x008 4 */ 644dd7b254dSGiuliano Pochini u32 sample_rate; /* Card sample rate in Hz 0x00c 4 */ 645f189e14cSTakashi Iwai u32 handshake; /* DSP command handshake 0x010 4 */ 646dd7b254dSGiuliano Pochini u32 cmd_start; /* Chs. to start mask 0x014 4 */ 647dd7b254dSGiuliano Pochini u32 cmd_stop; /* Chs. to stop mask 0x018 4 */ 648dd7b254dSGiuliano Pochini u32 cmd_reset; /* Chs. to reset mask 0x01c 4 */ 649dd7b254dSGiuliano Pochini u16 audio_format[DSP_MAXPIPES]; /* Chs. audio format 0x020 32*2 */ 650dd7b254dSGiuliano Pochini struct sg_entry sglist_addr[DSP_MAXPIPES]; 651dd7b254dSGiuliano Pochini /* Chs. Physical sglist addrs 0x060 32*8 */ 652f189e14cSTakashi Iwai u32 position[DSP_MAXPIPES]; 653dd7b254dSGiuliano Pochini /* Positions for ea. ch. 0x160 32*4 */ 654f189e14cSTakashi Iwai s8 vu_meter[DSP_MAXPIPES]; 655dd7b254dSGiuliano Pochini /* VU meters 0x1e0 32*1 */ 656f189e14cSTakashi Iwai s8 peak_meter[DSP_MAXPIPES]; 657dd7b254dSGiuliano Pochini /* Peak meters 0x200 32*1 */ 658dd7b254dSGiuliano Pochini s8 line_out_level[DSP_MAXAUDIOOUTPUTS]; 659dd7b254dSGiuliano Pochini /* Output gain 0x220 16*1 */ 660dd7b254dSGiuliano Pochini s8 line_in_level[DSP_MAXAUDIOINPUTS]; 661dd7b254dSGiuliano Pochini /* Input gain 0x230 16*1 */ 662dd7b254dSGiuliano Pochini s8 monitors[MONITOR_ARRAY_SIZE]; 663dd7b254dSGiuliano Pochini /* Monitor map 0x240 0x180 */ 664dd7b254dSGiuliano Pochini u32 play_coeff[MAX_PLAY_TAPS]; 665dd7b254dSGiuliano Pochini /* Gina/Darla play filters - obsolete 0x3c0 168*4 */ 666dd7b254dSGiuliano Pochini u32 rec_coeff[MAX_REC_TAPS]; 667dd7b254dSGiuliano Pochini /* Gina/Darla record filters - obsolete 0x660 192*4 */ 668f189e14cSTakashi Iwai u16 midi_input[MIDI_IN_BUFFER_SIZE]; 669dd7b254dSGiuliano Pochini /* MIDI input data transfer buffer 0x960 256*2 */ 670dd7b254dSGiuliano Pochini u8 gd_clock_state; /* Chg Gina/Darla clock state 0xb60 1 */ 671dd7b254dSGiuliano Pochini u8 gd_spdif_status; /* Chg. Gina/Darla S/PDIF state 0xb61 1 */ 672dd7b254dSGiuliano Pochini u8 gd_resampler_state; /* Should always be 3 0xb62 1 */ 673dd7b254dSGiuliano Pochini u8 filler2; /* 0xb63 1 */ 674dd7b254dSGiuliano Pochini u32 nominal_level_mask; /* -10 level enable mask 0xb64 4 */ 675dd7b254dSGiuliano Pochini u16 input_clock; /* Chg. Input clock state 0xb68 2 */ 676dd7b254dSGiuliano Pochini u16 output_clock; /* Chg. Output clock state 0xb6a 2 */ 677f189e14cSTakashi Iwai u32 status_clocks; /* Current Input clock state 0xb6c 4 */ 678dd7b254dSGiuliano Pochini u32 ext_box_status; /* External box status 0xb70 4 */ 679dd7b254dSGiuliano Pochini u32 cmd_add_buffer; /* Pipes to add (obsolete) 0xb74 4 */ 680f189e14cSTakashi Iwai u32 midi_out_free_count; 681dd7b254dSGiuliano Pochini /* # of bytes free in MIDI output FIFO 0xb78 4 */ 682dd7b254dSGiuliano Pochini u32 unused2; /* Cyclic pipes 0xb7c 4 */ 683dd7b254dSGiuliano Pochini u32 control_register; 684dd7b254dSGiuliano Pochini /* Mona, Gina24, Layla24, 3G ctrl reg 0xb80 4 */ 685dd7b254dSGiuliano Pochini u32 e3g_frq_register; /* 3G frequency register 0xb84 4 */ 686dd7b254dSGiuliano Pochini u8 filler[24]; /* filler 0xb88 24*1 */ 687dd7b254dSGiuliano Pochini s8 vmixer[VMIXER_ARRAY_SIZE]; 688dd7b254dSGiuliano Pochini /* Vmixer levels 0xba0 64*1 */ 689dd7b254dSGiuliano Pochini u8 midi_output[MIDI_OUT_BUFFER_SIZE]; 690dd7b254dSGiuliano Pochini /* MIDI output data 0xbe0 32*1 */ 691dd7b254dSGiuliano Pochini }; 692dd7b254dSGiuliano Pochini 693dd7b254dSGiuliano Pochini #endif /* _ECHO_DSP_ */ 694