1 /**************************************************************************** 2 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004 4 All rights reserved 5 www.echoaudio.com 6 7 This file is part of Echo Digital Audio's generic driver library. 8 9 Echo Digital Audio's generic driver library is free software; 10 you can redistribute it and/or modify it under the terms of 11 the GNU General Public License as published by the Free Software 12 Foundation. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, 22 MA 02111-1307, USA. 23 24 ************************************************************************* 25 26 Translation from C++ and adaptation for use in ALSA-Driver 27 were made by Giuliano Pochini <pochini@shiny.it> 28 29 ****************************************************************************/ 30 31 32 33 /* These functions are common for all "3G" cards */ 34 35 36 static int check_asic_status(struct echoaudio *chip) 37 { 38 u32 box_status; 39 40 if (wait_handshake(chip)) 41 return -EIO; 42 43 chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED); 44 chip->asic_loaded = FALSE; 45 clear_handshake(chip); 46 send_vector(chip, DSP_VC_TEST_ASIC); 47 48 if (wait_handshake(chip)) { 49 chip->dsp_code = NULL; 50 return -EIO; 51 } 52 53 box_status = le32_to_cpu(chip->comm_page->ext_box_status); 54 DE_INIT(("box_status=%x\n", box_status)); 55 if (box_status == E3G_ASIC_NOT_LOADED) 56 return -ENODEV; 57 58 chip->asic_loaded = TRUE; 59 return box_status & E3G_BOX_TYPE_MASK; 60 } 61 62 63 64 static inline u32 get_frq_reg(struct echoaudio *chip) 65 { 66 return le32_to_cpu(chip->comm_page->e3g_frq_register); 67 } 68 69 70 71 /* Most configuration of 3G cards is accomplished by writing the control 72 register. write_control_reg sends the new control register value to the DSP. */ 73 static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq, 74 char force) 75 { 76 if (wait_handshake(chip)) 77 return -EIO; 78 79 DE_ACT(("WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq)); 80 81 ctl = cpu_to_le32(ctl); 82 frq = cpu_to_le32(frq); 83 84 if (ctl != chip->comm_page->control_register || 85 frq != chip->comm_page->e3g_frq_register || force) { 86 chip->comm_page->e3g_frq_register = frq; 87 chip->comm_page->control_register = ctl; 88 clear_handshake(chip); 89 return send_vector(chip, DSP_VC_WRITE_CONTROL_REG); 90 } 91 92 DE_ACT(("WriteControlReg: not written, no change\n")); 93 return 0; 94 } 95 96 97 98 /* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */ 99 static int set_digital_mode(struct echoaudio *chip, u8 mode) 100 { 101 u8 previous_mode; 102 int err, i, o; 103 104 /* All audio channels must be closed before changing the digital mode */ 105 if (snd_BUG_ON(chip->pipe_alloc_mask)) 106 return -EAGAIN; 107 108 if (snd_BUG_ON(!(chip->digital_modes & (1 << mode)))) 109 return -EINVAL; 110 111 previous_mode = chip->digital_mode; 112 err = dsp_set_digital_mode(chip, mode); 113 114 /* If we successfully changed the digital mode from or to ADAT, 115 * then make sure all output, input and monitor levels are 116 * updated by the DSP comm object. */ 117 if (err >= 0 && previous_mode != mode && 118 (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) { 119 spin_lock_irq(&chip->lock); 120 for (o = 0; o < num_busses_out(chip); o++) 121 for (i = 0; i < num_busses_in(chip); i++) 122 set_monitor_gain(chip, o, i, 123 chip->monitor_gain[o][i]); 124 125 #ifdef ECHOCARD_HAS_INPUT_GAIN 126 for (i = 0; i < num_busses_in(chip); i++) 127 set_input_gain(chip, i, chip->input_gain[i]); 128 update_input_line_level(chip); 129 #endif 130 131 for (o = 0; o < num_busses_out(chip); o++) 132 set_output_gain(chip, o, chip->output_gain[o]); 133 update_output_line_level(chip); 134 spin_unlock_irq(&chip->lock); 135 } 136 137 return err; 138 } 139 140 141 142 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) 143 { 144 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; 145 146 switch (rate) { 147 case 32000 : 148 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; 149 break; 150 case 44100 : 151 if (chip->professional_spdif) 152 control_reg |= E3G_SPDIF_SAMPLE_RATE0; 153 break; 154 case 48000 : 155 control_reg |= E3G_SPDIF_SAMPLE_RATE1; 156 break; 157 } 158 159 if (chip->professional_spdif) 160 control_reg |= E3G_SPDIF_PRO_MODE; 161 162 if (chip->non_audio_spdif) 163 control_reg |= E3G_SPDIF_NOT_AUDIO; 164 165 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | 166 E3G_SPDIF_COPY_PERMIT; 167 168 return control_reg; 169 } 170 171 172 173 /* Set the S/PDIF output format */ 174 static int set_professional_spdif(struct echoaudio *chip, char prof) 175 { 176 u32 control_reg; 177 178 control_reg = le32_to_cpu(chip->comm_page->control_register); 179 chip->professional_spdif = prof; 180 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate); 181 return write_control_reg(chip, control_reg, get_frq_reg(chip), 0); 182 } 183 184 185 186 /* detect_input_clocks() returns a bitmask consisting of all the input clocks 187 currently connected to the hardware; this changes as the user connects and 188 disconnects clock inputs. You should use this information to determine which 189 clocks the user is allowed to select. */ 190 static u32 detect_input_clocks(const struct echoaudio *chip) 191 { 192 u32 clocks_from_dsp, clock_bits; 193 194 /* Map the DSP clock detect bits to the generic driver clock 195 * detect bits */ 196 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); 197 198 clock_bits = ECHO_CLOCK_BIT_INTERNAL; 199 200 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD) 201 clock_bits |= ECHO_CLOCK_BIT_WORD; 202 203 switch(chip->digital_mode) { 204 case DIGITAL_MODE_SPDIF_RCA: 205 case DIGITAL_MODE_SPDIF_OPTICAL: 206 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF) 207 clock_bits |= ECHO_CLOCK_BIT_SPDIF; 208 break; 209 case DIGITAL_MODE_ADAT: 210 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT) 211 clock_bits |= ECHO_CLOCK_BIT_ADAT; 212 break; 213 } 214 215 return clock_bits; 216 } 217 218 219 220 static int load_asic(struct echoaudio *chip) 221 { 222 int box_type, err; 223 224 if (chip->asic_loaded) 225 return 0; 226 227 /* Give the DSP a few milliseconds to settle down */ 228 mdelay(2); 229 230 err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC, 231 &card_fw[FW_3G_ASIC]); 232 if (err < 0) 233 return err; 234 235 chip->asic_code = &card_fw[FW_3G_ASIC]; 236 237 /* Now give the new ASIC some time to set up */ 238 msleep(1000); 239 /* See if it worked */ 240 box_type = check_asic_status(chip); 241 242 /* Set up the control register if the load succeeded - 243 * 48 kHz, internal clock, S/PDIF RCA mode */ 244 if (box_type >= 0) { 245 err = write_control_reg(chip, E3G_48KHZ, 246 E3G_FREQ_REG_DEFAULT, TRUE); 247 if (err < 0) 248 return err; 249 } 250 251 return box_type; 252 } 253 254 255 256 static int set_sample_rate(struct echoaudio *chip, u32 rate) 257 { 258 u32 control_reg, clock, base_rate, frq_reg; 259 260 /* Only set the clock for internal mode. */ 261 if (chip->input_clock != ECHO_CLOCK_INTERNAL) { 262 DE_ACT(("set_sample_rate: Cannot set sample rate - " 263 "clock not set to CLK_CLOCKININTERNAL\n")); 264 /* Save the rate anyhow */ 265 chip->comm_page->sample_rate = cpu_to_le32(rate); 266 chip->sample_rate = rate; 267 set_input_clock(chip, chip->input_clock); 268 return 0; 269 } 270 271 if (snd_BUG_ON(rate >= 50000 && 272 chip->digital_mode == DIGITAL_MODE_ADAT)) 273 return -EINVAL; 274 275 clock = 0; 276 control_reg = le32_to_cpu(chip->comm_page->control_register); 277 control_reg &= E3G_CLOCK_CLEAR_MASK; 278 279 switch (rate) { 280 case 96000: 281 clock = E3G_96KHZ; 282 break; 283 case 88200: 284 clock = E3G_88KHZ; 285 break; 286 case 48000: 287 clock = E3G_48KHZ; 288 break; 289 case 44100: 290 clock = E3G_44KHZ; 291 break; 292 case 32000: 293 clock = E3G_32KHZ; 294 break; 295 default: 296 clock = E3G_CONTINUOUS_CLOCK; 297 if (rate > 50000) 298 clock |= E3G_DOUBLE_SPEED_MODE; 299 break; 300 } 301 302 control_reg |= clock; 303 control_reg = set_spdif_bits(chip, control_reg, rate); 304 305 base_rate = rate; 306 if (base_rate > 50000) 307 base_rate /= 2; 308 if (base_rate < 32000) 309 base_rate = 32000; 310 311 frq_reg = E3G_MAGIC_NUMBER / base_rate - 2; 312 if (frq_reg > E3G_FREQ_REG_MAX) 313 frq_reg = E3G_FREQ_REG_MAX; 314 315 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ 316 chip->sample_rate = rate; 317 DE_ACT(("SetSampleRate: %d clock %x\n", rate, control_reg)); 318 319 /* Tell the DSP about it - DSP reads both control reg & freq reg */ 320 return write_control_reg(chip, control_reg, frq_reg, 0); 321 } 322 323 324 325 /* Set the sample clock source to internal, S/PDIF, ADAT */ 326 static int set_input_clock(struct echoaudio *chip, u16 clock) 327 { 328 u32 control_reg, clocks_from_dsp; 329 330 DE_ACT(("set_input_clock:\n")); 331 332 /* Mask off the clock select bits */ 333 control_reg = le32_to_cpu(chip->comm_page->control_register) & 334 E3G_CLOCK_CLEAR_MASK; 335 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); 336 337 switch (clock) { 338 case ECHO_CLOCK_INTERNAL: 339 DE_ACT(("Set Echo3G clock to INTERNAL\n")); 340 chip->input_clock = ECHO_CLOCK_INTERNAL; 341 return set_sample_rate(chip, chip->sample_rate); 342 case ECHO_CLOCK_SPDIF: 343 if (chip->digital_mode == DIGITAL_MODE_ADAT) 344 return -EAGAIN; 345 DE_ACT(("Set Echo3G clock to SPDIF\n")); 346 control_reg |= E3G_SPDIF_CLOCK; 347 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96) 348 control_reg |= E3G_DOUBLE_SPEED_MODE; 349 else 350 control_reg &= ~E3G_DOUBLE_SPEED_MODE; 351 break; 352 case ECHO_CLOCK_ADAT: 353 if (chip->digital_mode != DIGITAL_MODE_ADAT) 354 return -EAGAIN; 355 DE_ACT(("Set Echo3G clock to ADAT\n")); 356 control_reg |= E3G_ADAT_CLOCK; 357 control_reg &= ~E3G_DOUBLE_SPEED_MODE; 358 break; 359 case ECHO_CLOCK_WORD: 360 DE_ACT(("Set Echo3G clock to WORD\n")); 361 control_reg |= E3G_WORD_CLOCK; 362 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96) 363 control_reg |= E3G_DOUBLE_SPEED_MODE; 364 else 365 control_reg &= ~E3G_DOUBLE_SPEED_MODE; 366 break; 367 default: 368 DE_ACT(("Input clock 0x%x not supported for Echo3G\n", clock)); 369 return -EINVAL; 370 } 371 372 chip->input_clock = clock; 373 return write_control_reg(chip, control_reg, get_frq_reg(chip), 1); 374 } 375 376 377 378 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode) 379 { 380 u32 control_reg; 381 int err, incompatible_clock; 382 383 /* Set clock to "internal" if it's not compatible with the new mode */ 384 incompatible_clock = FALSE; 385 switch (mode) { 386 case DIGITAL_MODE_SPDIF_OPTICAL: 387 case DIGITAL_MODE_SPDIF_RCA: 388 if (chip->input_clock == ECHO_CLOCK_ADAT) 389 incompatible_clock = TRUE; 390 break; 391 case DIGITAL_MODE_ADAT: 392 if (chip->input_clock == ECHO_CLOCK_SPDIF) 393 incompatible_clock = TRUE; 394 break; 395 default: 396 DE_ACT(("Digital mode not supported: %d\n", mode)); 397 return -EINVAL; 398 } 399 400 spin_lock_irq(&chip->lock); 401 402 if (incompatible_clock) { 403 chip->sample_rate = 48000; 404 set_input_clock(chip, ECHO_CLOCK_INTERNAL); 405 } 406 407 /* Clear the current digital mode */ 408 control_reg = le32_to_cpu(chip->comm_page->control_register); 409 control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK; 410 411 /* Tweak the control reg */ 412 switch (mode) { 413 case DIGITAL_MODE_SPDIF_OPTICAL: 414 control_reg |= E3G_SPDIF_OPTICAL_MODE; 415 break; 416 case DIGITAL_MODE_SPDIF_RCA: 417 /* E3G_SPDIF_OPTICAL_MODE bit cleared */ 418 break; 419 case DIGITAL_MODE_ADAT: 420 control_reg |= E3G_ADAT_MODE; 421 control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */ 422 break; 423 } 424 425 err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1); 426 spin_unlock_irq(&chip->lock); 427 if (err < 0) 428 return err; 429 chip->digital_mode = mode; 430 431 DE_ACT(("set_digital_mode(%d)\n", chip->digital_mode)); 432 return incompatible_clock; 433 } 434