1 /****************************************************************************
2 
3    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
4    All rights reserved
5    www.echoaudio.com
6 
7    This file is part of Echo Digital Audio's generic driver library.
8 
9    Echo Digital Audio's generic driver library is free software;
10    you can redistribute it and/or modify it under the terms of
11    the GNU General Public License as published by the Free Software
12    Foundation.
13 
14    This program is distributed in the hope that it will be useful,
15    but WITHOUT ANY WARRANTY; without even the implied warranty of
16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17    GNU General Public License for more details.
18 
19    You should have received a copy of the GNU General Public License
20    along with this program; if not, write to the Free Software
21    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22    MA  02111-1307, USA.
23 
24    *************************************************************************
25 
26  Translation from C++ and adaptation for use in ALSA-Driver
27  were made by Giuliano Pochini <pochini@shiny.it>
28 
29 ****************************************************************************/
30 
31 
32 
33 /* These functions are common for all "3G" cards */
34 
35 
36 static int check_asic_status(struct echoaudio *chip)
37 {
38 	u32 box_status;
39 
40 	if (wait_handshake(chip))
41 		return -EIO;
42 
43 	chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED);
44 	chip->asic_loaded = false;
45 	clear_handshake(chip);
46 	send_vector(chip, DSP_VC_TEST_ASIC);
47 
48 	if (wait_handshake(chip)) {
49 		chip->dsp_code = NULL;
50 		return -EIO;
51 	}
52 
53 	box_status = le32_to_cpu(chip->comm_page->ext_box_status);
54 	dev_dbg(chip->card->dev, "box_status=%x\n", box_status);
55 	if (box_status == E3G_ASIC_NOT_LOADED)
56 		return -ENODEV;
57 
58 	chip->asic_loaded = true;
59 	return box_status & E3G_BOX_TYPE_MASK;
60 }
61 
62 
63 
64 static inline u32 get_frq_reg(struct echoaudio *chip)
65 {
66 	return le32_to_cpu(chip->comm_page->e3g_frq_register);
67 }
68 
69 
70 
71 /* Most configuration of 3G cards is accomplished by writing the control
72 register. write_control_reg sends the new control register value to the DSP. */
73 static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq,
74 			     char force)
75 {
76 	if (wait_handshake(chip))
77 		return -EIO;
78 
79 	dev_dbg(chip->card->dev,
80 		"WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq);
81 
82 	ctl = cpu_to_le32(ctl);
83 	frq = cpu_to_le32(frq);
84 
85 	if (ctl != chip->comm_page->control_register ||
86 	    frq != chip->comm_page->e3g_frq_register || force) {
87 		chip->comm_page->e3g_frq_register = frq;
88 		chip->comm_page->control_register = ctl;
89 		clear_handshake(chip);
90 		return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
91 	}
92 
93 	dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n");
94 	return 0;
95 }
96 
97 
98 
99 /* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */
100 static int set_digital_mode(struct echoaudio *chip, u8 mode)
101 {
102 	u8 previous_mode;
103 	int err, i, o;
104 
105 	/* All audio channels must be closed before changing the digital mode */
106 	if (snd_BUG_ON(chip->pipe_alloc_mask))
107 		return -EAGAIN;
108 
109 	if (snd_BUG_ON(!(chip->digital_modes & (1 << mode))))
110 		return -EINVAL;
111 
112 	previous_mode = chip->digital_mode;
113 	err = dsp_set_digital_mode(chip, mode);
114 
115 	/* If we successfully changed the digital mode from or to ADAT,
116 	 * then make sure all output, input and monitor levels are
117 	 * updated by the DSP comm object. */
118 	if (err >= 0 && previous_mode != mode &&
119 	    (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) {
120 		spin_lock_irq(&chip->lock);
121 		for (o = 0; o < num_busses_out(chip); o++)
122 			for (i = 0; i < num_busses_in(chip); i++)
123 				set_monitor_gain(chip, o, i,
124 						 chip->monitor_gain[o][i]);
125 
126 #ifdef ECHOCARD_HAS_INPUT_GAIN
127 		for (i = 0; i < num_busses_in(chip); i++)
128 			set_input_gain(chip, i, chip->input_gain[i]);
129 		update_input_line_level(chip);
130 #endif
131 
132 		for (o = 0; o < num_busses_out(chip); o++)
133 			set_output_gain(chip, o, chip->output_gain[o]);
134 		update_output_line_level(chip);
135 		spin_unlock_irq(&chip->lock);
136 	}
137 
138 	return err;
139 }
140 
141 
142 
143 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
144 {
145 	control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
146 
147 	switch (rate) {
148 	case 32000 :
149 		control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
150 		break;
151 	case 44100 :
152 		if (chip->professional_spdif)
153 			control_reg |= E3G_SPDIF_SAMPLE_RATE0;
154 		break;
155 	case 48000 :
156 		control_reg |= E3G_SPDIF_SAMPLE_RATE1;
157 		break;
158 	}
159 
160 	if (chip->professional_spdif)
161 		control_reg |= E3G_SPDIF_PRO_MODE;
162 
163 	if (chip->non_audio_spdif)
164 		control_reg |= E3G_SPDIF_NOT_AUDIO;
165 
166 	control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
167 		E3G_SPDIF_COPY_PERMIT;
168 
169 	return control_reg;
170 }
171 
172 
173 
174 /* Set the S/PDIF output format */
175 static int set_professional_spdif(struct echoaudio *chip, char prof)
176 {
177 	u32 control_reg;
178 
179 	control_reg = le32_to_cpu(chip->comm_page->control_register);
180 	chip->professional_spdif = prof;
181 	control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
182 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
183 }
184 
185 
186 
187 /* detect_input_clocks() returns a bitmask consisting of all the input clocks
188 currently connected to the hardware; this changes as the user connects and
189 disconnects clock inputs. You should use this information to determine which
190 clocks the user is allowed to select. */
191 static u32 detect_input_clocks(const struct echoaudio *chip)
192 {
193 	u32 clocks_from_dsp, clock_bits;
194 
195 	/* Map the DSP clock detect bits to the generic driver clock
196 	 * detect bits */
197 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
198 
199 	clock_bits = ECHO_CLOCK_BIT_INTERNAL;
200 
201 	if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD)
202 		clock_bits |= ECHO_CLOCK_BIT_WORD;
203 
204 	switch(chip->digital_mode) {
205 	case DIGITAL_MODE_SPDIF_RCA:
206 	case DIGITAL_MODE_SPDIF_OPTICAL:
207 		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF)
208 			clock_bits |= ECHO_CLOCK_BIT_SPDIF;
209 		break;
210 	case DIGITAL_MODE_ADAT:
211 		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT)
212 			clock_bits |= ECHO_CLOCK_BIT_ADAT;
213 		break;
214 	}
215 
216 	return clock_bits;
217 }
218 
219 
220 
221 static int load_asic(struct echoaudio *chip)
222 {
223 	int box_type, err;
224 
225 	if (chip->asic_loaded)
226 		return 0;
227 
228 	/* Give the DSP a few milliseconds to settle down */
229 	mdelay(2);
230 
231 	err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC, FW_3G_ASIC);
232 	if (err < 0)
233 		return err;
234 
235 	chip->asic_code = FW_3G_ASIC;
236 
237 	/* Now give the new ASIC some time to set up */
238 	msleep(1000);
239 	/* See if it worked */
240 	box_type = check_asic_status(chip);
241 
242 	/* Set up the control register if the load succeeded -
243 	 * 48 kHz, internal clock, S/PDIF RCA mode */
244 	if (box_type >= 0) {
245 		err = write_control_reg(chip, E3G_48KHZ,
246 					E3G_FREQ_REG_DEFAULT, true);
247 		if (err < 0)
248 			return err;
249 	}
250 
251 	return box_type;
252 }
253 
254 
255 
256 static int set_sample_rate(struct echoaudio *chip, u32 rate)
257 {
258 	u32 control_reg, clock, base_rate, frq_reg;
259 
260 	/* Only set the clock for internal mode. */
261 	if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
262 		dev_warn(chip->card->dev,
263 			 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
264 		/* Save the rate anyhow */
265 		chip->comm_page->sample_rate = cpu_to_le32(rate);
266 		chip->sample_rate = rate;
267 		set_input_clock(chip, chip->input_clock);
268 		return 0;
269 	}
270 
271 	if (snd_BUG_ON(rate >= 50000 &&
272 		       chip->digital_mode == DIGITAL_MODE_ADAT))
273 		return -EINVAL;
274 
275 	clock = 0;
276 	control_reg = le32_to_cpu(chip->comm_page->control_register);
277 	control_reg &= E3G_CLOCK_CLEAR_MASK;
278 
279 	switch (rate) {
280 	case 96000:
281 		clock = E3G_96KHZ;
282 		break;
283 	case 88200:
284 		clock = E3G_88KHZ;
285 		break;
286 	case 48000:
287 		clock = E3G_48KHZ;
288 		break;
289 	case 44100:
290 		clock = E3G_44KHZ;
291 		break;
292 	case 32000:
293 		clock = E3G_32KHZ;
294 		break;
295 	default:
296 		clock = E3G_CONTINUOUS_CLOCK;
297 		if (rate > 50000)
298 			clock |= E3G_DOUBLE_SPEED_MODE;
299 		break;
300 	}
301 
302 	control_reg |= clock;
303 	control_reg = set_spdif_bits(chip, control_reg, rate);
304 
305 	base_rate = rate;
306 	if (base_rate > 50000)
307 		base_rate /= 2;
308 	if (base_rate < 32000)
309 		base_rate = 32000;
310 
311 	frq_reg = E3G_MAGIC_NUMBER / base_rate - 2;
312 	if (frq_reg > E3G_FREQ_REG_MAX)
313 		frq_reg = E3G_FREQ_REG_MAX;
314 
315 	chip->comm_page->sample_rate = cpu_to_le32(rate);	/* ignored by the DSP */
316 	chip->sample_rate = rate;
317 	dev_dbg(chip->card->dev,
318 		"SetSampleRate: %d clock %x\n", rate, control_reg);
319 
320 	/* Tell the DSP about it - DSP reads both control reg & freq reg */
321 	return write_control_reg(chip, control_reg, frq_reg, 0);
322 }
323 
324 
325 
326 /* Set the sample clock source to internal, S/PDIF, ADAT */
327 static int set_input_clock(struct echoaudio *chip, u16 clock)
328 {
329 	u32 control_reg, clocks_from_dsp;
330 
331 
332 	/* Mask off the clock select bits */
333 	control_reg = le32_to_cpu(chip->comm_page->control_register) &
334 		E3G_CLOCK_CLEAR_MASK;
335 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
336 
337 	switch (clock) {
338 	case ECHO_CLOCK_INTERNAL:
339 		chip->input_clock = ECHO_CLOCK_INTERNAL;
340 		return set_sample_rate(chip, chip->sample_rate);
341 	case ECHO_CLOCK_SPDIF:
342 		if (chip->digital_mode == DIGITAL_MODE_ADAT)
343 			return -EAGAIN;
344 		control_reg |= E3G_SPDIF_CLOCK;
345 		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96)
346 			control_reg |= E3G_DOUBLE_SPEED_MODE;
347 		else
348 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
349 		break;
350 	case ECHO_CLOCK_ADAT:
351 		if (chip->digital_mode != DIGITAL_MODE_ADAT)
352 			return -EAGAIN;
353 		control_reg |= E3G_ADAT_CLOCK;
354 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;
355 		break;
356 	case ECHO_CLOCK_WORD:
357 		control_reg |= E3G_WORD_CLOCK;
358 		if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96)
359 			control_reg |= E3G_DOUBLE_SPEED_MODE;
360 		else
361 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
362 		break;
363 	default:
364 		dev_err(chip->card->dev,
365 			"Input clock 0x%x not supported for Echo3G\n", clock);
366 		return -EINVAL;
367 	}
368 
369 	chip->input_clock = clock;
370 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
371 }
372 
373 
374 
375 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
376 {
377 	u32 control_reg;
378 	int err, incompatible_clock;
379 
380 	/* Set clock to "internal" if it's not compatible with the new mode */
381 	incompatible_clock = false;
382 	switch (mode) {
383 	case DIGITAL_MODE_SPDIF_OPTICAL:
384 	case DIGITAL_MODE_SPDIF_RCA:
385 		if (chip->input_clock == ECHO_CLOCK_ADAT)
386 			incompatible_clock = true;
387 		break;
388 	case DIGITAL_MODE_ADAT:
389 		if (chip->input_clock == ECHO_CLOCK_SPDIF)
390 			incompatible_clock = true;
391 		break;
392 	default:
393 		dev_err(chip->card->dev,
394 			"Digital mode not supported: %d\n", mode);
395 		return -EINVAL;
396 	}
397 
398 	spin_lock_irq(&chip->lock);
399 
400 	if (incompatible_clock) {
401 		chip->sample_rate = 48000;
402 		set_input_clock(chip, ECHO_CLOCK_INTERNAL);
403 	}
404 
405 	/* Clear the current digital mode */
406 	control_reg = le32_to_cpu(chip->comm_page->control_register);
407 	control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
408 
409 	/* Tweak the control reg */
410 	switch (mode) {
411 	case DIGITAL_MODE_SPDIF_OPTICAL:
412 		control_reg |= E3G_SPDIF_OPTICAL_MODE;
413 		break;
414 	case DIGITAL_MODE_SPDIF_RCA:
415 		/* E3G_SPDIF_OPTICAL_MODE bit cleared */
416 		break;
417 	case DIGITAL_MODE_ADAT:
418 		control_reg |= E3G_ADAT_MODE;
419 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;	/* @@ useless */
420 		break;
421 	}
422 
423 	err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
424 	spin_unlock_irq(&chip->lock);
425 	if (err < 0)
426 		return err;
427 	chip->digital_mode = mode;
428 
429 	dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode);
430 	return incompatible_clock;
431 }
432