1 /* 2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 3 * Abramo Bagnara <abramo@alsa-project.org> 4 * Cirrus Logic, Inc. 5 * Routines for control of Cirrus Logic CS461x chips 6 * 7 * KNOWN BUGS: 8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized 9 * and the SPDIF get somewhat "distorcionated", or/and left right channel 10 * are swapped. To get around this problem when it happens, mute and unmute 11 * the SPDIF input mixer control. 12 * - On the Hercules Game Theater XP the amplifier are sometimes turned 13 * off on inadecuate moments which causes distorcions on sound. 14 * 15 * TODO: 16 * - Secondary CODEC on some soundcards 17 * - SPDIF input support for other sample rates then 48khz 18 * - Posibility to mix the SPDIF output with analog sources. 19 * - PCM channels for Center and LFE on secondary codec 20 * 21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which 22 * is default configuration), no SPDIF, no secondary codec, no 23 * multi channel PCM. But known to work. 24 * 25 * FINALLY: A credit to the developers Tom and Jordan 26 * at Cirrus for have helping me out with the DSP, however we 27 * still don't have sufficient documentation and technical 28 * references to be able to implement all fancy feutures 29 * supported by the cs46xx DSP's. 30 * Benny <benny@hostmobility.com> 31 * 32 * This program is free software; you can redistribute it and/or modify 33 * it under the terms of the GNU General Public License as published by 34 * the Free Software Foundation; either version 2 of the License, or 35 * (at your option) any later version. 36 * 37 * This program is distributed in the hope that it will be useful, 38 * but WITHOUT ANY WARRANTY; without even the implied warranty of 39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 40 * GNU General Public License for more details. 41 * 42 * You should have received a copy of the GNU General Public License 43 * along with this program; if not, write to the Free Software 44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 45 * 46 */ 47 48 #include <linux/delay.h> 49 #include <linux/pci.h> 50 #include <linux/pm.h> 51 #include <linux/init.h> 52 #include <linux/interrupt.h> 53 #include <linux/slab.h> 54 #include <linux/gameport.h> 55 #include <linux/mutex.h> 56 57 58 #include <sound/core.h> 59 #include <sound/control.h> 60 #include <sound/info.h> 61 #include <sound/pcm.h> 62 #include <sound/pcm_params.h> 63 #include <sound/cs46xx.h> 64 65 #include <asm/io.h> 66 67 #include "cs46xx_lib.h" 68 #include "dsp_spos.h" 69 70 static void amp_voyetra(struct snd_cs46xx *chip, int change); 71 72 #ifdef CONFIG_SND_CS46XX_NEW_DSP 73 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops; 74 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; 75 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; 76 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; 77 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; 78 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; 79 #endif 80 81 static struct snd_pcm_ops snd_cs46xx_playback_ops; 82 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; 83 static struct snd_pcm_ops snd_cs46xx_capture_ops; 84 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; 85 86 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, 87 unsigned short reg, 88 int codec_index) 89 { 90 int count; 91 unsigned short result,tmp; 92 u32 offset = 0; 93 94 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 95 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 96 return -EINVAL; 97 98 chip->active_ctrl(chip, 1); 99 100 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX) 101 offset = CS46XX_SECONDARY_CODEC_OFFSET; 102 103 /* 104 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 105 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 106 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55 107 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 108 * 5. if DCV not cleared, break and return error 109 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 110 */ 111 112 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 113 114 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL); 115 if ((tmp & ACCTL_VFRM) == 0) { 116 snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp); 117 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM ); 118 msleep(50); 119 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset); 120 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM ); 121 122 } 123 124 /* 125 * Setup the AC97 control registers on the CS461x to send the 126 * appropriate command to the AC97 to perform the read. 127 * ACCAD = Command Address Register = 46Ch 128 * ACCDA = Command Data Register = 470h 129 * ACCTL = Control Register = 460h 130 * set DCV - will clear when process completed 131 * set CRW - Read command 132 * set VFRM - valid frame enabled 133 * set ESYN - ASYNC generation enabled 134 * set RSTN - ARST# inactive, AC97 codec not reset 135 */ 136 137 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg); 138 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0); 139 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 140 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW | 141 ACCTL_VFRM | ACCTL_ESYN | 142 ACCTL_RSTN); 143 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | 144 ACCTL_VFRM | ACCTL_ESYN | 145 ACCTL_RSTN); 146 } else { 147 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 148 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | 149 ACCTL_RSTN); 150 } 151 152 /* 153 * Wait for the read to occur. 154 */ 155 for (count = 0; count < 1000; count++) { 156 /* 157 * First, we want to wait for a short time. 158 */ 159 udelay(10); 160 /* 161 * Now, check to see if the read has completed. 162 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 163 */ 164 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) 165 goto ok1; 166 } 167 168 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 169 result = 0xffff; 170 goto end; 171 172 ok1: 173 /* 174 * Wait for the valid status bit to go active. 175 */ 176 for (count = 0; count < 100; count++) { 177 /* 178 * Read the AC97 status register. 179 * ACSTS = Status Register = 464h 180 * VSTS - Valid Status 181 */ 182 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS) 183 goto ok2; 184 udelay(10); 185 } 186 187 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg); 188 result = 0xffff; 189 goto end; 190 191 ok2: 192 /* 193 * Read the data returned from the AC97 register. 194 * ACSDA = Status Data Register = 474h 195 */ 196 #if 0 197 printk(KERN_DEBUG "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg, 198 snd_cs46xx_peekBA0(chip, BA0_ACSDA), 199 snd_cs46xx_peekBA0(chip, BA0_ACCAD)); 200 #endif 201 202 //snd_cs46xx_peekBA0(chip, BA0_ACCAD); 203 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 204 end: 205 chip->active_ctrl(chip, -1); 206 return result; 207 } 208 209 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97, 210 unsigned short reg) 211 { 212 struct snd_cs46xx *chip = ac97->private_data; 213 unsigned short val; 214 int codec_index = ac97->num; 215 216 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 217 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 218 return 0xffff; 219 220 val = snd_cs46xx_codec_read(chip, reg, codec_index); 221 222 return val; 223 } 224 225 226 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip, 227 unsigned short reg, 228 unsigned short val, 229 int codec_index) 230 { 231 int count; 232 233 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 234 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 235 return; 236 237 chip->active_ctrl(chip, 1); 238 239 /* 240 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 241 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 242 * 3. Write ACCTL = Control Register = 460h for initiating the write 243 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 244 * 5. if DCV not cleared, break and return error 245 */ 246 247 /* 248 * Setup the AC97 control registers on the CS461x to send the 249 * appropriate command to the AC97 to perform the read. 250 * ACCAD = Command Address Register = 46Ch 251 * ACCDA = Command Data Register = 470h 252 * ACCTL = Control Register = 460h 253 * set DCV - will clear when process completed 254 * reset CRW - Write command 255 * set VFRM - valid frame enabled 256 * set ESYN - ASYNC generation enabled 257 * set RSTN - ARST# inactive, AC97 codec not reset 258 */ 259 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg); 260 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val); 261 snd_cs46xx_peekBA0(chip, BA0_ACCTL); 262 263 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 264 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM | 265 ACCTL_ESYN | ACCTL_RSTN); 266 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | 267 ACCTL_ESYN | ACCTL_RSTN); 268 } else { 269 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 270 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 271 } 272 273 for (count = 0; count < 4000; count++) { 274 /* 275 * First, we want to wait for a short time. 276 */ 277 udelay(10); 278 /* 279 * Now, check to see if the write has completed. 280 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 281 */ 282 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) { 283 goto end; 284 } 285 } 286 snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val); 287 end: 288 chip->active_ctrl(chip, -1); 289 } 290 291 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97, 292 unsigned short reg, 293 unsigned short val) 294 { 295 struct snd_cs46xx *chip = ac97->private_data; 296 int codec_index = ac97->num; 297 298 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 299 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 300 return; 301 302 snd_cs46xx_codec_write(chip, reg, val, codec_index); 303 } 304 305 306 /* 307 * Chip initialization 308 */ 309 310 int snd_cs46xx_download(struct snd_cs46xx *chip, 311 u32 *src, 312 unsigned long offset, 313 unsigned long len) 314 { 315 void __iomem *dst; 316 unsigned int bank = offset >> 16; 317 offset = offset & 0xffff; 318 319 if (snd_BUG_ON((offset & 3) || (len & 3))) 320 return -EINVAL; 321 dst = chip->region.idx[bank+1].remap_addr + offset; 322 len /= sizeof(u32); 323 324 /* writel already converts 32-bit value to right endianess */ 325 while (len-- > 0) { 326 writel(*src++, dst); 327 dst += sizeof(u32); 328 } 329 return 0; 330 } 331 332 #ifdef CONFIG_SND_CS46XX_NEW_DSP 333 334 #include "imgs/cwc4630.h" 335 #include "imgs/cwcasync.h" 336 #include "imgs/cwcsnoop.h" 337 #include "imgs/cwcbinhack.h" 338 #include "imgs/cwcdma.h" 339 340 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, 341 unsigned long offset, 342 unsigned long len) 343 { 344 void __iomem *dst; 345 unsigned int bank = offset >> 16; 346 offset = offset & 0xffff; 347 348 if (snd_BUG_ON((offset & 3) || (len & 3))) 349 return -EINVAL; 350 dst = chip->region.idx[bank+1].remap_addr + offset; 351 len /= sizeof(u32); 352 353 /* writel already converts 32-bit value to right endianess */ 354 while (len-- > 0) { 355 writel(0, dst); 356 dst += sizeof(u32); 357 } 358 return 0; 359 } 360 361 #else /* old DSP image */ 362 363 #include "cs46xx_image.h" 364 365 int snd_cs46xx_download_image(struct snd_cs46xx *chip) 366 { 367 int idx, err; 368 unsigned long offset = 0; 369 370 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) { 371 if ((err = snd_cs46xx_download(chip, 372 &BA1Struct.map[offset], 373 BA1Struct.memory[idx].offset, 374 BA1Struct.memory[idx].size)) < 0) 375 return err; 376 offset += BA1Struct.memory[idx].size >> 2; 377 } 378 return 0; 379 } 380 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 381 382 /* 383 * Chip reset 384 */ 385 386 static void snd_cs46xx_reset(struct snd_cs46xx *chip) 387 { 388 int idx; 389 390 /* 391 * Write the reset bit of the SP control register. 392 */ 393 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP); 394 395 /* 396 * Write the control register. 397 */ 398 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN); 399 400 /* 401 * Clear the trap registers. 402 */ 403 for (idx = 0; idx < 8; idx++) { 404 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx); 405 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF); 406 } 407 snd_cs46xx_poke(chip, BA1_DREG, 0); 408 409 /* 410 * Set the frame timer to reflect the number of cycles per frame. 411 */ 412 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 413 } 414 415 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout) 416 { 417 u32 i, status = 0; 418 /* 419 * Make sure the previous FIFO write operation has completed. 420 */ 421 for(i = 0; i < 50; i++){ 422 status = snd_cs46xx_peekBA0(chip, BA0_SERBST); 423 424 if( !(status & SERBST_WBSY) ) 425 break; 426 427 mdelay(retry_timeout); 428 } 429 430 if(status & SERBST_WBSY) { 431 snd_printk(KERN_ERR "cs46xx: failure waiting for " 432 "FIFO command to complete\n"); 433 return -EINVAL; 434 } 435 436 return 0; 437 } 438 439 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip) 440 { 441 int idx, powerdown = 0; 442 unsigned int tmp; 443 444 /* 445 * See if the devices are powered down. If so, we must power them up first 446 * or they will not respond. 447 */ 448 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 449 if (!(tmp & CLKCR1_SWCE)) { 450 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 451 powerdown = 1; 452 } 453 454 /* 455 * We want to clear out the serial port FIFOs so we don't end up playing 456 * whatever random garbage happens to be in them. We fill the sample FIFOS 457 * with zero (silence). 458 */ 459 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0); 460 461 /* 462 * Fill all 256 sample FIFO locations. 463 */ 464 for (idx = 0; idx < 0xFF; idx++) { 465 /* 466 * Make sure the previous FIFO write operation has completed. 467 */ 468 if (cs46xx_wait_for_fifo(chip,1)) { 469 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx); 470 471 if (powerdown) 472 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 473 474 break; 475 } 476 /* 477 * Write the serial port FIFO index. 478 */ 479 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 480 /* 481 * Tell the serial port to load the new value into the FIFO location. 482 */ 483 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 484 } 485 /* 486 * Now, if we powered up the devices, then power them back down again. 487 * This is kinda ugly, but should never happen. 488 */ 489 if (powerdown) 490 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 491 } 492 493 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip) 494 { 495 int cnt; 496 497 /* 498 * Set the frame timer to reflect the number of cycles per frame. 499 */ 500 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 501 /* 502 * Turn on the run, run at frame, and DMA enable bits in the local copy of 503 * the SP control register. 504 */ 505 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 506 /* 507 * Wait until the run at frame bit resets itself in the SP control 508 * register. 509 */ 510 for (cnt = 0; cnt < 25; cnt++) { 511 udelay(50); 512 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)) 513 break; 514 } 515 516 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR) 517 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n"); 518 } 519 520 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip) 521 { 522 /* 523 * Turn off the run, run at frame, and DMA enable bits in the local copy of 524 * the SP control register. 525 */ 526 snd_cs46xx_poke(chip, BA1_SPCR, 0); 527 } 528 529 /* 530 * Sample rate routines 531 */ 532 533 #define GOF_PER_SEC 200 534 535 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 536 { 537 unsigned long flags; 538 unsigned int tmp1, tmp2; 539 unsigned int phiIncr; 540 unsigned int correctionPerGOF, correctionPerSec; 541 542 /* 543 * Compute the values used to drive the actual sample rate conversion. 544 * The following formulas are being computed, using inline assembly 545 * since we need to use 64 bit arithmetic to compute the values: 546 * 547 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 548 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 549 * GOF_PER_SEC) 550 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M 551 * GOF_PER_SEC * correctionPerGOF 552 * 553 * i.e. 554 * 555 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out) 556 * correctionPerGOF:correctionPerSec = 557 * dividend:remainder(ulOther / GOF_PER_SEC) 558 */ 559 tmp1 = rate << 16; 560 phiIncr = tmp1 / 48000; 561 tmp1 -= phiIncr * 48000; 562 tmp1 <<= 10; 563 phiIncr <<= 10; 564 tmp2 = tmp1 / 48000; 565 phiIncr += tmp2; 566 tmp1 -= tmp2 * 48000; 567 correctionPerGOF = tmp1 / GOF_PER_SEC; 568 tmp1 -= correctionPerGOF * GOF_PER_SEC; 569 correctionPerSec = tmp1; 570 571 /* 572 * Fill in the SampleRateConverter control block. 573 */ 574 spin_lock_irqsave(&chip->reg_lock, flags); 575 snd_cs46xx_poke(chip, BA1_PSRC, 576 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 577 snd_cs46xx_poke(chip, BA1_PPI, phiIncr); 578 spin_unlock_irqrestore(&chip->reg_lock, flags); 579 } 580 581 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 582 { 583 unsigned long flags; 584 unsigned int phiIncr, coeffIncr, tmp1, tmp2; 585 unsigned int correctionPerGOF, correctionPerSec, initialDelay; 586 unsigned int frameGroupLength, cnt; 587 588 /* 589 * We can only decimate by up to a factor of 1/9th the hardware rate. 590 * Correct the value if an attempt is made to stray outside that limit. 591 */ 592 if ((rate * 9) < 48000) 593 rate = 48000 / 9; 594 595 /* 596 * We can not capture at at rate greater than the Input Rate (48000). 597 * Return an error if an attempt is made to stray outside that limit. 598 */ 599 if (rate > 48000) 600 rate = 48000; 601 602 /* 603 * Compute the values used to drive the actual sample rate conversion. 604 * The following formulas are being computed, using inline assembly 605 * since we need to use 64 bit arithmetic to compute the values: 606 * 607 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in) 608 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 609 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 610 * GOF_PER_SEC) 611 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr - 612 * GOF_PER_SEC * correctionPerGOF 613 * initialDelay = ceil((24 * Fs,in) / Fs,out) 614 * 615 * i.e. 616 * 617 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in)) 618 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out) 619 * correctionPerGOF:correctionPerSec = 620 * dividend:remainder(ulOther / GOF_PER_SEC) 621 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out) 622 */ 623 624 tmp1 = rate << 16; 625 coeffIncr = tmp1 / 48000; 626 tmp1 -= coeffIncr * 48000; 627 tmp1 <<= 7; 628 coeffIncr <<= 7; 629 coeffIncr += tmp1 / 48000; 630 coeffIncr ^= 0xFFFFFFFF; 631 coeffIncr++; 632 tmp1 = 48000 << 16; 633 phiIncr = tmp1 / rate; 634 tmp1 -= phiIncr * rate; 635 tmp1 <<= 10; 636 phiIncr <<= 10; 637 tmp2 = tmp1 / rate; 638 phiIncr += tmp2; 639 tmp1 -= tmp2 * rate; 640 correctionPerGOF = tmp1 / GOF_PER_SEC; 641 tmp1 -= correctionPerGOF * GOF_PER_SEC; 642 correctionPerSec = tmp1; 643 initialDelay = ((48000 * 24) + rate - 1) / rate; 644 645 /* 646 * Fill in the VariDecimate control block. 647 */ 648 spin_lock_irqsave(&chip->reg_lock, flags); 649 snd_cs46xx_poke(chip, BA1_CSRC, 650 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 651 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr); 652 snd_cs46xx_poke(chip, BA1_CD, 653 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80); 654 snd_cs46xx_poke(chip, BA1_CPI, phiIncr); 655 spin_unlock_irqrestore(&chip->reg_lock, flags); 656 657 /* 658 * Figure out the frame group length for the write back task. Basically, 659 * this is just the factors of 24000 (2^6*3*5^3) that are not present in 660 * the output sample rate. 661 */ 662 frameGroupLength = 1; 663 for (cnt = 2; cnt <= 64; cnt *= 2) { 664 if (((rate / cnt) * cnt) != rate) 665 frameGroupLength *= 2; 666 } 667 if (((rate / 3) * 3) != rate) { 668 frameGroupLength *= 3; 669 } 670 for (cnt = 5; cnt <= 125; cnt *= 5) { 671 if (((rate / cnt) * cnt) != rate) 672 frameGroupLength *= 5; 673 } 674 675 /* 676 * Fill in the WriteBack control block. 677 */ 678 spin_lock_irqsave(&chip->reg_lock, flags); 679 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength); 680 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength)); 681 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF); 682 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000)); 683 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF); 684 spin_unlock_irqrestore(&chip->reg_lock, flags); 685 } 686 687 /* 688 * PCM part 689 */ 690 691 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream, 692 struct snd_pcm_indirect *rec, size_t bytes) 693 { 694 struct snd_pcm_runtime *runtime = substream->runtime; 695 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 696 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes); 697 } 698 699 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream) 700 { 701 struct snd_pcm_runtime *runtime = substream->runtime; 702 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 703 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy); 704 return 0; 705 } 706 707 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream, 708 struct snd_pcm_indirect *rec, size_t bytes) 709 { 710 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 711 struct snd_pcm_runtime *runtime = substream->runtime; 712 memcpy(runtime->dma_area + rec->sw_data, 713 chip->capt.hw_buf.area + rec->hw_data, bytes); 714 } 715 716 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream) 717 { 718 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 719 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy); 720 return 0; 721 } 722 723 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream) 724 { 725 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 726 size_t ptr; 727 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 728 729 if (snd_BUG_ON(!cpcm->pcm_channel)) 730 return -ENXIO; 731 732 #ifdef CONFIG_SND_CS46XX_NEW_DSP 733 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 734 #else 735 ptr = snd_cs46xx_peek(chip, BA1_PBA); 736 #endif 737 ptr -= cpcm->hw_buf.addr; 738 return ptr >> cpcm->shift; 739 } 740 741 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream) 742 { 743 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 744 size_t ptr; 745 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 746 747 #ifdef CONFIG_SND_CS46XX_NEW_DSP 748 if (snd_BUG_ON(!cpcm->pcm_channel)) 749 return -ENXIO; 750 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 751 #else 752 ptr = snd_cs46xx_peek(chip, BA1_PBA); 753 #endif 754 ptr -= cpcm->hw_buf.addr; 755 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr); 756 } 757 758 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream) 759 { 760 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 761 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 762 return ptr >> chip->capt.shift; 763 } 764 765 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream) 766 { 767 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 768 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 769 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr); 770 } 771 772 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream, 773 int cmd) 774 { 775 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 776 /*struct snd_pcm_runtime *runtime = substream->runtime;*/ 777 int result = 0; 778 779 #ifdef CONFIG_SND_CS46XX_NEW_DSP 780 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 781 if (! cpcm->pcm_channel) { 782 return -ENXIO; 783 } 784 #endif 785 switch (cmd) { 786 case SNDRV_PCM_TRIGGER_START: 787 case SNDRV_PCM_TRIGGER_RESUME: 788 #ifdef CONFIG_SND_CS46XX_NEW_DSP 789 /* magic value to unmute PCM stream playback volume */ 790 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 791 SCBVolumeCtrl) << 2, 0x80008000); 792 793 if (cpcm->pcm_channel->unlinked) 794 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel); 795 796 if (substream->runtime->periods != CS46XX_FRAGS) 797 snd_cs46xx_playback_transfer(substream); 798 #else 799 spin_lock(&chip->reg_lock); 800 if (substream->runtime->periods != CS46XX_FRAGS) 801 snd_cs46xx_playback_transfer(substream); 802 { unsigned int tmp; 803 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 804 tmp &= 0x0000ffff; 805 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp); 806 } 807 spin_unlock(&chip->reg_lock); 808 #endif 809 break; 810 case SNDRV_PCM_TRIGGER_STOP: 811 case SNDRV_PCM_TRIGGER_SUSPEND: 812 #ifdef CONFIG_SND_CS46XX_NEW_DSP 813 /* magic mute channel */ 814 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 815 SCBVolumeCtrl) << 2, 0xffffffff); 816 817 if (!cpcm->pcm_channel->unlinked) 818 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel); 819 #else 820 spin_lock(&chip->reg_lock); 821 { unsigned int tmp; 822 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 823 tmp &= 0x0000ffff; 824 snd_cs46xx_poke(chip, BA1_PCTL, tmp); 825 } 826 spin_unlock(&chip->reg_lock); 827 #endif 828 break; 829 default: 830 result = -EINVAL; 831 break; 832 } 833 834 return result; 835 } 836 837 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream, 838 int cmd) 839 { 840 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 841 unsigned int tmp; 842 int result = 0; 843 844 spin_lock(&chip->reg_lock); 845 switch (cmd) { 846 case SNDRV_PCM_TRIGGER_START: 847 case SNDRV_PCM_TRIGGER_RESUME: 848 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 849 tmp &= 0xffff0000; 850 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp); 851 break; 852 case SNDRV_PCM_TRIGGER_STOP: 853 case SNDRV_PCM_TRIGGER_SUSPEND: 854 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 855 tmp &= 0xffff0000; 856 snd_cs46xx_poke(chip, BA1_CCTL, tmp); 857 break; 858 default: 859 result = -EINVAL; 860 break; 861 } 862 spin_unlock(&chip->reg_lock); 863 864 return result; 865 } 866 867 #ifdef CONFIG_SND_CS46XX_NEW_DSP 868 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm, 869 int sample_rate) 870 { 871 872 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */ 873 if ( cpcm->pcm_channel == NULL) { 874 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, 875 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id); 876 if (cpcm->pcm_channel == NULL) { 877 snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n"); 878 return -ENOMEM; 879 } 880 cpcm->pcm_channel->sample_rate = sample_rate; 881 } else 882 /* if sample rate is changed */ 883 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) { 884 int unlinked = cpcm->pcm_channel->unlinked; 885 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel); 886 887 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm, 888 cpcm->hw_buf.addr, 889 cpcm->pcm_channel_id)) == NULL) { 890 snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n"); 891 return -ENOMEM; 892 } 893 894 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel); 895 cpcm->pcm_channel->sample_rate = sample_rate; 896 } 897 898 return 0; 899 } 900 #endif 901 902 903 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream, 904 struct snd_pcm_hw_params *hw_params) 905 { 906 struct snd_pcm_runtime *runtime = substream->runtime; 907 struct snd_cs46xx_pcm *cpcm; 908 int err; 909 #ifdef CONFIG_SND_CS46XX_NEW_DSP 910 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 911 int sample_rate = params_rate(hw_params); 912 int period_size = params_period_bytes(hw_params); 913 #endif 914 cpcm = runtime->private_data; 915 916 #ifdef CONFIG_SND_CS46XX_NEW_DSP 917 if (snd_BUG_ON(!sample_rate)) 918 return -ENXIO; 919 920 mutex_lock(&chip->spos_mutex); 921 922 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) { 923 mutex_unlock(&chip->spos_mutex); 924 return -ENXIO; 925 } 926 927 snd_BUG_ON(!cpcm->pcm_channel); 928 if (!cpcm->pcm_channel) { 929 mutex_unlock(&chip->spos_mutex); 930 return -ENXIO; 931 } 932 933 934 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) { 935 mutex_unlock(&chip->spos_mutex); 936 return -EINVAL; 937 } 938 939 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n", 940 period_size, params_periods(hw_params), 941 params_buffer_bytes(hw_params)); 942 #endif 943 944 if (params_periods(hw_params) == CS46XX_FRAGS) { 945 if (runtime->dma_area != cpcm->hw_buf.area) 946 snd_pcm_lib_free_pages(substream); 947 runtime->dma_area = cpcm->hw_buf.area; 948 runtime->dma_addr = cpcm->hw_buf.addr; 949 runtime->dma_bytes = cpcm->hw_buf.bytes; 950 951 952 #ifdef CONFIG_SND_CS46XX_NEW_DSP 953 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 954 substream->ops = &snd_cs46xx_playback_ops; 955 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 956 substream->ops = &snd_cs46xx_playback_rear_ops; 957 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 958 substream->ops = &snd_cs46xx_playback_clfe_ops; 959 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 960 substream->ops = &snd_cs46xx_playback_iec958_ops; 961 } else { 962 snd_BUG(); 963 } 964 #else 965 substream->ops = &snd_cs46xx_playback_ops; 966 #endif 967 968 } else { 969 if (runtime->dma_area == cpcm->hw_buf.area) { 970 runtime->dma_area = NULL; 971 runtime->dma_addr = 0; 972 runtime->dma_bytes = 0; 973 } 974 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) { 975 #ifdef CONFIG_SND_CS46XX_NEW_DSP 976 mutex_unlock(&chip->spos_mutex); 977 #endif 978 return err; 979 } 980 981 #ifdef CONFIG_SND_CS46XX_NEW_DSP 982 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 983 substream->ops = &snd_cs46xx_playback_indirect_ops; 984 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 985 substream->ops = &snd_cs46xx_playback_indirect_rear_ops; 986 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 987 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops; 988 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 989 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops; 990 } else { 991 snd_BUG(); 992 } 993 #else 994 substream->ops = &snd_cs46xx_playback_indirect_ops; 995 #endif 996 997 } 998 999 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1000 mutex_unlock(&chip->spos_mutex); 1001 #endif 1002 1003 return 0; 1004 } 1005 1006 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream) 1007 { 1008 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/ 1009 struct snd_pcm_runtime *runtime = substream->runtime; 1010 struct snd_cs46xx_pcm *cpcm; 1011 1012 cpcm = runtime->private_data; 1013 1014 /* if play_back open fails, then this function 1015 is called and cpcm can actually be NULL here */ 1016 if (!cpcm) return -ENXIO; 1017 1018 if (runtime->dma_area != cpcm->hw_buf.area) 1019 snd_pcm_lib_free_pages(substream); 1020 1021 runtime->dma_area = NULL; 1022 runtime->dma_addr = 0; 1023 runtime->dma_bytes = 0; 1024 1025 return 0; 1026 } 1027 1028 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream) 1029 { 1030 unsigned int tmp; 1031 unsigned int pfie; 1032 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1033 struct snd_pcm_runtime *runtime = substream->runtime; 1034 struct snd_cs46xx_pcm *cpcm; 1035 1036 cpcm = runtime->private_data; 1037 1038 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1039 if (snd_BUG_ON(!cpcm->pcm_channel)) 1040 return -ENXIO; 1041 1042 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 ); 1043 pfie &= ~0x0000f03f; 1044 #else 1045 /* old dsp */ 1046 pfie = snd_cs46xx_peek(chip, BA1_PFIE); 1047 pfie &= ~0x0000f03f; 1048 #endif 1049 1050 cpcm->shift = 2; 1051 /* if to convert from stereo to mono */ 1052 if (runtime->channels == 1) { 1053 cpcm->shift--; 1054 pfie |= 0x00002000; 1055 } 1056 /* if to convert from 8 bit to 16 bit */ 1057 if (snd_pcm_format_width(runtime->format) == 8) { 1058 cpcm->shift--; 1059 pfie |= 0x00001000; 1060 } 1061 /* if to convert to unsigned */ 1062 if (snd_pcm_format_unsigned(runtime->format)) 1063 pfie |= 0x00008000; 1064 1065 /* Never convert byte order when sample stream is 8 bit */ 1066 if (snd_pcm_format_width(runtime->format) != 8) { 1067 /* convert from big endian to little endian */ 1068 if (snd_pcm_format_big_endian(runtime->format)) 1069 pfie |= 0x00004000; 1070 } 1071 1072 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec)); 1073 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1074 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift; 1075 1076 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1077 1078 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2); 1079 tmp &= ~0x000003ff; 1080 tmp |= (4 << cpcm->shift) - 1; 1081 /* playback transaction count register */ 1082 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp); 1083 1084 /* playback format && interrupt enable */ 1085 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot); 1086 #else 1087 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr); 1088 tmp = snd_cs46xx_peek(chip, BA1_PDTC); 1089 tmp &= ~0x000003ff; 1090 tmp |= (4 << cpcm->shift) - 1; 1091 snd_cs46xx_poke(chip, BA1_PDTC, tmp); 1092 snd_cs46xx_poke(chip, BA1_PFIE, pfie); 1093 snd_cs46xx_set_play_sample_rate(chip, runtime->rate); 1094 #endif 1095 1096 return 0; 1097 } 1098 1099 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream, 1100 struct snd_pcm_hw_params *hw_params) 1101 { 1102 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1103 struct snd_pcm_runtime *runtime = substream->runtime; 1104 int err; 1105 1106 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1107 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params)); 1108 #endif 1109 if (runtime->periods == CS46XX_FRAGS) { 1110 if (runtime->dma_area != chip->capt.hw_buf.area) 1111 snd_pcm_lib_free_pages(substream); 1112 runtime->dma_area = chip->capt.hw_buf.area; 1113 runtime->dma_addr = chip->capt.hw_buf.addr; 1114 runtime->dma_bytes = chip->capt.hw_buf.bytes; 1115 substream->ops = &snd_cs46xx_capture_ops; 1116 } else { 1117 if (runtime->dma_area == chip->capt.hw_buf.area) { 1118 runtime->dma_area = NULL; 1119 runtime->dma_addr = 0; 1120 runtime->dma_bytes = 0; 1121 } 1122 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) 1123 return err; 1124 substream->ops = &snd_cs46xx_capture_indirect_ops; 1125 } 1126 1127 return 0; 1128 } 1129 1130 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream) 1131 { 1132 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1133 struct snd_pcm_runtime *runtime = substream->runtime; 1134 1135 if (runtime->dma_area != chip->capt.hw_buf.area) 1136 snd_pcm_lib_free_pages(substream); 1137 runtime->dma_area = NULL; 1138 runtime->dma_addr = 0; 1139 runtime->dma_bytes = 0; 1140 1141 return 0; 1142 } 1143 1144 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream) 1145 { 1146 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1147 struct snd_pcm_runtime *runtime = substream->runtime; 1148 1149 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr); 1150 chip->capt.shift = 2; 1151 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec)); 1152 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1153 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2; 1154 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate); 1155 1156 return 0; 1157 } 1158 1159 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id) 1160 { 1161 struct snd_cs46xx *chip = dev_id; 1162 u32 status1; 1163 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1164 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1165 u32 status2; 1166 int i; 1167 struct snd_cs46xx_pcm *cpcm = NULL; 1168 #endif 1169 1170 /* 1171 * Read the Interrupt Status Register to clear the interrupt 1172 */ 1173 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR); 1174 if ((status1 & 0x7fffffff) == 0) { 1175 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1176 return IRQ_NONE; 1177 } 1178 1179 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1180 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0); 1181 1182 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) { 1183 if (i <= 15) { 1184 if ( status1 & (1 << i) ) { 1185 if (i == CS46XX_DSP_CAPTURE_CHANNEL) { 1186 if (chip->capt.substream) 1187 snd_pcm_period_elapsed(chip->capt.substream); 1188 } else { 1189 if (ins->pcm_channels[i].active && 1190 ins->pcm_channels[i].private_data && 1191 !ins->pcm_channels[i].unlinked) { 1192 cpcm = ins->pcm_channels[i].private_data; 1193 snd_pcm_period_elapsed(cpcm->substream); 1194 } 1195 } 1196 } 1197 } else { 1198 if ( status2 & (1 << (i - 16))) { 1199 if (ins->pcm_channels[i].active && 1200 ins->pcm_channels[i].private_data && 1201 !ins->pcm_channels[i].unlinked) { 1202 cpcm = ins->pcm_channels[i].private_data; 1203 snd_pcm_period_elapsed(cpcm->substream); 1204 } 1205 } 1206 } 1207 } 1208 1209 #else 1210 /* old dsp */ 1211 if ((status1 & HISR_VC0) && chip->playback_pcm) { 1212 if (chip->playback_pcm->substream) 1213 snd_pcm_period_elapsed(chip->playback_pcm->substream); 1214 } 1215 if ((status1 & HISR_VC1) && chip->pcm) { 1216 if (chip->capt.substream) 1217 snd_pcm_period_elapsed(chip->capt.substream); 1218 } 1219 #endif 1220 1221 if ((status1 & HISR_MIDI) && chip->rmidi) { 1222 unsigned char c; 1223 1224 spin_lock(&chip->reg_lock); 1225 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) { 1226 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP); 1227 if ((chip->midcr & MIDCR_RIE) == 0) 1228 continue; 1229 snd_rawmidi_receive(chip->midi_input, &c, 1); 1230 } 1231 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 1232 if ((chip->midcr & MIDCR_TIE) == 0) 1233 break; 1234 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1235 chip->midcr &= ~MIDCR_TIE; 1236 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1237 break; 1238 } 1239 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c); 1240 } 1241 spin_unlock(&chip->reg_lock); 1242 } 1243 /* 1244 * EOI to the PCI part....reenables interrupts 1245 */ 1246 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1247 1248 return IRQ_HANDLED; 1249 } 1250 1251 static struct snd_pcm_hardware snd_cs46xx_playback = 1252 { 1253 .info = (SNDRV_PCM_INFO_MMAP | 1254 SNDRV_PCM_INFO_INTERLEAVED | 1255 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1256 /*SNDRV_PCM_INFO_RESUME*/), 1257 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | 1258 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 1259 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE), 1260 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1261 .rate_min = 5500, 1262 .rate_max = 48000, 1263 .channels_min = 1, 1264 .channels_max = 2, 1265 .buffer_bytes_max = (256 * 1024), 1266 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1267 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1268 .periods_min = CS46XX_FRAGS, 1269 .periods_max = 1024, 1270 .fifo_size = 0, 1271 }; 1272 1273 static struct snd_pcm_hardware snd_cs46xx_capture = 1274 { 1275 .info = (SNDRV_PCM_INFO_MMAP | 1276 SNDRV_PCM_INFO_INTERLEAVED | 1277 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1278 /*SNDRV_PCM_INFO_RESUME*/), 1279 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1280 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1281 .rate_min = 5500, 1282 .rate_max = 48000, 1283 .channels_min = 2, 1284 .channels_max = 2, 1285 .buffer_bytes_max = (256 * 1024), 1286 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1287 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1288 .periods_min = CS46XX_FRAGS, 1289 .periods_max = 1024, 1290 .fifo_size = 0, 1291 }; 1292 1293 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1294 1295 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 }; 1296 1297 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = { 1298 .count = ARRAY_SIZE(period_sizes), 1299 .list = period_sizes, 1300 .mask = 0 1301 }; 1302 1303 #endif 1304 1305 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime) 1306 { 1307 kfree(runtime->private_data); 1308 } 1309 1310 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id) 1311 { 1312 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1313 struct snd_cs46xx_pcm * cpcm; 1314 struct snd_pcm_runtime *runtime = substream->runtime; 1315 1316 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL); 1317 if (cpcm == NULL) 1318 return -ENOMEM; 1319 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1320 PAGE_SIZE, &cpcm->hw_buf) < 0) { 1321 kfree(cpcm); 1322 return -ENOMEM; 1323 } 1324 1325 runtime->hw = snd_cs46xx_playback; 1326 runtime->private_data = cpcm; 1327 runtime->private_free = snd_cs46xx_pcm_free_substream; 1328 1329 cpcm->substream = substream; 1330 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1331 mutex_lock(&chip->spos_mutex); 1332 cpcm->pcm_channel = NULL; 1333 cpcm->pcm_channel_id = pcm_channel_id; 1334 1335 1336 snd_pcm_hw_constraint_list(runtime, 0, 1337 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1338 &hw_constraints_period_sizes); 1339 1340 mutex_unlock(&chip->spos_mutex); 1341 #else 1342 chip->playback_pcm = cpcm; /* HACK */ 1343 #endif 1344 1345 if (chip->accept_valid) 1346 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1347 chip->active_ctrl(chip, 1); 1348 1349 return 0; 1350 } 1351 1352 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream) 1353 { 1354 snd_printdd("open front channel\n"); 1355 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL); 1356 } 1357 1358 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1359 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream) 1360 { 1361 snd_printdd("open rear channel\n"); 1362 1363 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL); 1364 } 1365 1366 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream) 1367 { 1368 snd_printdd("open center - LFE channel\n"); 1369 1370 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL); 1371 } 1372 1373 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream) 1374 { 1375 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1376 1377 snd_printdd("open raw iec958 channel\n"); 1378 1379 mutex_lock(&chip->spos_mutex); 1380 cs46xx_iec958_pre_open (chip); 1381 mutex_unlock(&chip->spos_mutex); 1382 1383 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL); 1384 } 1385 1386 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream); 1387 1388 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream) 1389 { 1390 int err; 1391 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1392 1393 snd_printdd("close raw iec958 channel\n"); 1394 1395 err = snd_cs46xx_playback_close(substream); 1396 1397 mutex_lock(&chip->spos_mutex); 1398 cs46xx_iec958_post_close (chip); 1399 mutex_unlock(&chip->spos_mutex); 1400 1401 return err; 1402 } 1403 #endif 1404 1405 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream) 1406 { 1407 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1408 1409 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1410 PAGE_SIZE, &chip->capt.hw_buf) < 0) 1411 return -ENOMEM; 1412 chip->capt.substream = substream; 1413 substream->runtime->hw = snd_cs46xx_capture; 1414 1415 if (chip->accept_valid) 1416 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1417 1418 chip->active_ctrl(chip, 1); 1419 1420 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1421 snd_pcm_hw_constraint_list(substream->runtime, 0, 1422 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1423 &hw_constraints_period_sizes); 1424 #endif 1425 return 0; 1426 } 1427 1428 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream) 1429 { 1430 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1431 struct snd_pcm_runtime *runtime = substream->runtime; 1432 struct snd_cs46xx_pcm * cpcm; 1433 1434 cpcm = runtime->private_data; 1435 1436 /* when playback_open fails, then cpcm can be NULL */ 1437 if (!cpcm) return -ENXIO; 1438 1439 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1440 mutex_lock(&chip->spos_mutex); 1441 if (cpcm->pcm_channel) { 1442 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel); 1443 cpcm->pcm_channel = NULL; 1444 } 1445 mutex_unlock(&chip->spos_mutex); 1446 #else 1447 chip->playback_pcm = NULL; 1448 #endif 1449 1450 cpcm->substream = NULL; 1451 snd_dma_free_pages(&cpcm->hw_buf); 1452 chip->active_ctrl(chip, -1); 1453 1454 return 0; 1455 } 1456 1457 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) 1458 { 1459 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1460 1461 chip->capt.substream = NULL; 1462 snd_dma_free_pages(&chip->capt.hw_buf); 1463 chip->active_ctrl(chip, -1); 1464 1465 return 0; 1466 } 1467 1468 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1469 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { 1470 .open = snd_cs46xx_playback_open_rear, 1471 .close = snd_cs46xx_playback_close, 1472 .ioctl = snd_pcm_lib_ioctl, 1473 .hw_params = snd_cs46xx_playback_hw_params, 1474 .hw_free = snd_cs46xx_playback_hw_free, 1475 .prepare = snd_cs46xx_playback_prepare, 1476 .trigger = snd_cs46xx_playback_trigger, 1477 .pointer = snd_cs46xx_playback_direct_pointer, 1478 }; 1479 1480 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { 1481 .open = snd_cs46xx_playback_open_rear, 1482 .close = snd_cs46xx_playback_close, 1483 .ioctl = snd_pcm_lib_ioctl, 1484 .hw_params = snd_cs46xx_playback_hw_params, 1485 .hw_free = snd_cs46xx_playback_hw_free, 1486 .prepare = snd_cs46xx_playback_prepare, 1487 .trigger = snd_cs46xx_playback_trigger, 1488 .pointer = snd_cs46xx_playback_indirect_pointer, 1489 .ack = snd_cs46xx_playback_transfer, 1490 }; 1491 1492 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { 1493 .open = snd_cs46xx_playback_open_clfe, 1494 .close = snd_cs46xx_playback_close, 1495 .ioctl = snd_pcm_lib_ioctl, 1496 .hw_params = snd_cs46xx_playback_hw_params, 1497 .hw_free = snd_cs46xx_playback_hw_free, 1498 .prepare = snd_cs46xx_playback_prepare, 1499 .trigger = snd_cs46xx_playback_trigger, 1500 .pointer = snd_cs46xx_playback_direct_pointer, 1501 }; 1502 1503 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { 1504 .open = snd_cs46xx_playback_open_clfe, 1505 .close = snd_cs46xx_playback_close, 1506 .ioctl = snd_pcm_lib_ioctl, 1507 .hw_params = snd_cs46xx_playback_hw_params, 1508 .hw_free = snd_cs46xx_playback_hw_free, 1509 .prepare = snd_cs46xx_playback_prepare, 1510 .trigger = snd_cs46xx_playback_trigger, 1511 .pointer = snd_cs46xx_playback_indirect_pointer, 1512 .ack = snd_cs46xx_playback_transfer, 1513 }; 1514 1515 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { 1516 .open = snd_cs46xx_playback_open_iec958, 1517 .close = snd_cs46xx_playback_close_iec958, 1518 .ioctl = snd_pcm_lib_ioctl, 1519 .hw_params = snd_cs46xx_playback_hw_params, 1520 .hw_free = snd_cs46xx_playback_hw_free, 1521 .prepare = snd_cs46xx_playback_prepare, 1522 .trigger = snd_cs46xx_playback_trigger, 1523 .pointer = snd_cs46xx_playback_direct_pointer, 1524 }; 1525 1526 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { 1527 .open = snd_cs46xx_playback_open_iec958, 1528 .close = snd_cs46xx_playback_close_iec958, 1529 .ioctl = snd_pcm_lib_ioctl, 1530 .hw_params = snd_cs46xx_playback_hw_params, 1531 .hw_free = snd_cs46xx_playback_hw_free, 1532 .prepare = snd_cs46xx_playback_prepare, 1533 .trigger = snd_cs46xx_playback_trigger, 1534 .pointer = snd_cs46xx_playback_indirect_pointer, 1535 .ack = snd_cs46xx_playback_transfer, 1536 }; 1537 1538 #endif 1539 1540 static struct snd_pcm_ops snd_cs46xx_playback_ops = { 1541 .open = snd_cs46xx_playback_open, 1542 .close = snd_cs46xx_playback_close, 1543 .ioctl = snd_pcm_lib_ioctl, 1544 .hw_params = snd_cs46xx_playback_hw_params, 1545 .hw_free = snd_cs46xx_playback_hw_free, 1546 .prepare = snd_cs46xx_playback_prepare, 1547 .trigger = snd_cs46xx_playback_trigger, 1548 .pointer = snd_cs46xx_playback_direct_pointer, 1549 }; 1550 1551 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { 1552 .open = snd_cs46xx_playback_open, 1553 .close = snd_cs46xx_playback_close, 1554 .ioctl = snd_pcm_lib_ioctl, 1555 .hw_params = snd_cs46xx_playback_hw_params, 1556 .hw_free = snd_cs46xx_playback_hw_free, 1557 .prepare = snd_cs46xx_playback_prepare, 1558 .trigger = snd_cs46xx_playback_trigger, 1559 .pointer = snd_cs46xx_playback_indirect_pointer, 1560 .ack = snd_cs46xx_playback_transfer, 1561 }; 1562 1563 static struct snd_pcm_ops snd_cs46xx_capture_ops = { 1564 .open = snd_cs46xx_capture_open, 1565 .close = snd_cs46xx_capture_close, 1566 .ioctl = snd_pcm_lib_ioctl, 1567 .hw_params = snd_cs46xx_capture_hw_params, 1568 .hw_free = snd_cs46xx_capture_hw_free, 1569 .prepare = snd_cs46xx_capture_prepare, 1570 .trigger = snd_cs46xx_capture_trigger, 1571 .pointer = snd_cs46xx_capture_direct_pointer, 1572 }; 1573 1574 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { 1575 .open = snd_cs46xx_capture_open, 1576 .close = snd_cs46xx_capture_close, 1577 .ioctl = snd_pcm_lib_ioctl, 1578 .hw_params = snd_cs46xx_capture_hw_params, 1579 .hw_free = snd_cs46xx_capture_hw_free, 1580 .prepare = snd_cs46xx_capture_prepare, 1581 .trigger = snd_cs46xx_capture_trigger, 1582 .pointer = snd_cs46xx_capture_indirect_pointer, 1583 .ack = snd_cs46xx_capture_transfer, 1584 }; 1585 1586 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1587 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1) 1588 #else 1589 #define MAX_PLAYBACK_CHANNELS 1 1590 #endif 1591 1592 int __devinit snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) 1593 { 1594 struct snd_pcm *pcm; 1595 int err; 1596 1597 if (rpcm) 1598 *rpcm = NULL; 1599 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0) 1600 return err; 1601 1602 pcm->private_data = chip; 1603 1604 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops); 1605 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops); 1606 1607 /* global setup */ 1608 pcm->info_flags = 0; 1609 strcpy(pcm->name, "CS46xx"); 1610 chip->pcm = pcm; 1611 1612 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1613 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1614 1615 if (rpcm) 1616 *rpcm = pcm; 1617 1618 return 0; 1619 } 1620 1621 1622 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1623 int __devinit snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) 1624 { 1625 struct snd_pcm *pcm; 1626 int err; 1627 1628 if (rpcm) 1629 *rpcm = NULL; 1630 1631 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) 1632 return err; 1633 1634 pcm->private_data = chip; 1635 1636 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops); 1637 1638 /* global setup */ 1639 pcm->info_flags = 0; 1640 strcpy(pcm->name, "CS46xx - Rear"); 1641 chip->pcm_rear = pcm; 1642 1643 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1644 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1645 1646 if (rpcm) 1647 *rpcm = pcm; 1648 1649 return 0; 1650 } 1651 1652 int __devinit snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) 1653 { 1654 struct snd_pcm *pcm; 1655 int err; 1656 1657 if (rpcm) 1658 *rpcm = NULL; 1659 1660 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) 1661 return err; 1662 1663 pcm->private_data = chip; 1664 1665 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops); 1666 1667 /* global setup */ 1668 pcm->info_flags = 0; 1669 strcpy(pcm->name, "CS46xx - Center LFE"); 1670 chip->pcm_center_lfe = pcm; 1671 1672 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1673 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1674 1675 if (rpcm) 1676 *rpcm = pcm; 1677 1678 return 0; 1679 } 1680 1681 int __devinit snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm) 1682 { 1683 struct snd_pcm *pcm; 1684 int err; 1685 1686 if (rpcm) 1687 *rpcm = NULL; 1688 1689 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0) 1690 return err; 1691 1692 pcm->private_data = chip; 1693 1694 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops); 1695 1696 /* global setup */ 1697 pcm->info_flags = 0; 1698 strcpy(pcm->name, "CS46xx - IEC958"); 1699 chip->pcm_rear = pcm; 1700 1701 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1702 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1703 1704 if (rpcm) 1705 *rpcm = pcm; 1706 1707 return 0; 1708 } 1709 #endif 1710 1711 /* 1712 * Mixer routines 1713 */ 1714 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1715 { 1716 struct snd_cs46xx *chip = bus->private_data; 1717 1718 chip->ac97_bus = NULL; 1719 } 1720 1721 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97) 1722 { 1723 struct snd_cs46xx *chip = ac97->private_data; 1724 1725 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] && 1726 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])) 1727 return; 1728 1729 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) { 1730 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL; 1731 chip->eapd_switch = NULL; 1732 } 1733 else 1734 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL; 1735 } 1736 1737 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol, 1738 struct snd_ctl_elem_info *uinfo) 1739 { 1740 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1741 uinfo->count = 2; 1742 uinfo->value.integer.min = 0; 1743 uinfo->value.integer.max = 0x7fff; 1744 return 0; 1745 } 1746 1747 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1748 { 1749 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1750 int reg = kcontrol->private_value; 1751 unsigned int val = snd_cs46xx_peek(chip, reg); 1752 ucontrol->value.integer.value[0] = 0xffff - (val >> 16); 1753 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff); 1754 return 0; 1755 } 1756 1757 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1758 { 1759 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1760 int reg = kcontrol->private_value; 1761 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | 1762 (0xffff - ucontrol->value.integer.value[1])); 1763 unsigned int old = snd_cs46xx_peek(chip, reg); 1764 int change = (old != val); 1765 1766 if (change) { 1767 snd_cs46xx_poke(chip, reg, val); 1768 } 1769 1770 return change; 1771 } 1772 1773 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1774 1775 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1776 { 1777 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1778 1779 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left; 1780 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right; 1781 1782 return 0; 1783 } 1784 1785 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1786 { 1787 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1788 int change = 0; 1789 1790 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] || 1791 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) { 1792 cs46xx_dsp_set_dac_volume(chip, 1793 ucontrol->value.integer.value[0], 1794 ucontrol->value.integer.value[1]); 1795 change = 1; 1796 } 1797 1798 return change; 1799 } 1800 1801 #if 0 1802 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1803 { 1804 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1805 1806 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left; 1807 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right; 1808 return 0; 1809 } 1810 1811 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1812 { 1813 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1814 int change = 0; 1815 1816 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] || 1817 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) { 1818 cs46xx_dsp_set_iec958_volume (chip, 1819 ucontrol->value.integer.value[0], 1820 ucontrol->value.integer.value[1]); 1821 change = 1; 1822 } 1823 1824 return change; 1825 } 1826 #endif 1827 1828 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info 1829 1830 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol, 1831 struct snd_ctl_elem_value *ucontrol) 1832 { 1833 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1834 int reg = kcontrol->private_value; 1835 1836 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT) 1837 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1838 else 1839 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in; 1840 1841 return 0; 1842 } 1843 1844 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol, 1845 struct snd_ctl_elem_value *ucontrol) 1846 { 1847 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1848 int change, res; 1849 1850 switch (kcontrol->private_value) { 1851 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT: 1852 mutex_lock(&chip->spos_mutex); 1853 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1854 if (ucontrol->value.integer.value[0] && !change) 1855 cs46xx_dsp_enable_spdif_out(chip); 1856 else if (change && !ucontrol->value.integer.value[0]) 1857 cs46xx_dsp_disable_spdif_out(chip); 1858 1859 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED)); 1860 mutex_unlock(&chip->spos_mutex); 1861 break; 1862 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT: 1863 change = chip->dsp_spos_instance->spdif_status_in; 1864 if (ucontrol->value.integer.value[0] && !change) { 1865 cs46xx_dsp_enable_spdif_in(chip); 1866 /* restore volume */ 1867 } 1868 else if (change && !ucontrol->value.integer.value[0]) 1869 cs46xx_dsp_disable_spdif_in(chip); 1870 1871 res = (change != chip->dsp_spos_instance->spdif_status_in); 1872 break; 1873 default: 1874 res = -EINVAL; 1875 snd_BUG(); /* should never happen ... */ 1876 } 1877 1878 return res; 1879 } 1880 1881 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol, 1882 struct snd_ctl_elem_value *ucontrol) 1883 { 1884 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1885 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1886 1887 if (ins->adc_input != NULL) 1888 ucontrol->value.integer.value[0] = 1; 1889 else 1890 ucontrol->value.integer.value[0] = 0; 1891 1892 return 0; 1893 } 1894 1895 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol, 1896 struct snd_ctl_elem_value *ucontrol) 1897 { 1898 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1899 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1900 int change = 0; 1901 1902 if (ucontrol->value.integer.value[0] && !ins->adc_input) { 1903 cs46xx_dsp_enable_adc_capture(chip); 1904 change = 1; 1905 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) { 1906 cs46xx_dsp_disable_adc_capture(chip); 1907 change = 1; 1908 } 1909 return change; 1910 } 1911 1912 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol, 1913 struct snd_ctl_elem_value *ucontrol) 1914 { 1915 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1916 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1917 1918 if (ins->pcm_input != NULL) 1919 ucontrol->value.integer.value[0] = 1; 1920 else 1921 ucontrol->value.integer.value[0] = 0; 1922 1923 return 0; 1924 } 1925 1926 1927 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol, 1928 struct snd_ctl_elem_value *ucontrol) 1929 { 1930 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1931 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1932 int change = 0; 1933 1934 if (ucontrol->value.integer.value[0] && !ins->pcm_input) { 1935 cs46xx_dsp_enable_pcm_capture(chip); 1936 change = 1; 1937 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) { 1938 cs46xx_dsp_disable_pcm_capture(chip); 1939 change = 1; 1940 } 1941 1942 return change; 1943 } 1944 1945 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol, 1946 struct snd_ctl_elem_value *ucontrol) 1947 { 1948 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1949 1950 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 1951 1952 if (val1 & EGPIODR_GPOE0) 1953 ucontrol->value.integer.value[0] = 1; 1954 else 1955 ucontrol->value.integer.value[0] = 0; 1956 1957 return 0; 1958 } 1959 1960 /* 1961 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial. 1962 */ 1963 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol, 1964 struct snd_ctl_elem_value *ucontrol) 1965 { 1966 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1967 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 1968 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 1969 1970 if (ucontrol->value.integer.value[0]) { 1971 /* optical is default */ 1972 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 1973 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */ 1974 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 1975 EGPIOPTR_GPPT0 | val2); /* open-drain on output */ 1976 } else { 1977 /* coaxial */ 1978 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */ 1979 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */ 1980 } 1981 1982 /* checking diff from the EGPIO direction register 1983 should be enough */ 1984 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR)); 1985 } 1986 1987 1988 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1989 { 1990 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1991 uinfo->count = 1; 1992 return 0; 1993 } 1994 1995 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol, 1996 struct snd_ctl_elem_value *ucontrol) 1997 { 1998 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1999 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2000 2001 mutex_lock(&chip->spos_mutex); 2002 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff); 2003 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff); 2004 ucontrol->value.iec958.status[2] = 0; 2005 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff); 2006 mutex_unlock(&chip->spos_mutex); 2007 2008 return 0; 2009 } 2010 2011 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol, 2012 struct snd_ctl_elem_value *ucontrol) 2013 { 2014 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2015 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2016 unsigned int val; 2017 int change; 2018 2019 mutex_lock(&chip->spos_mutex); 2020 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2021 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) | 2022 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2023 /* left and right validity bit */ 2024 (1 << 13) | (1 << 12); 2025 2026 2027 change = (unsigned int)ins->spdif_csuv_default != val; 2028 ins->spdif_csuv_default = val; 2029 2030 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) ) 2031 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2032 2033 mutex_unlock(&chip->spos_mutex); 2034 2035 return change; 2036 } 2037 2038 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol, 2039 struct snd_ctl_elem_value *ucontrol) 2040 { 2041 ucontrol->value.iec958.status[0] = 0xff; 2042 ucontrol->value.iec958.status[1] = 0xff; 2043 ucontrol->value.iec958.status[2] = 0x00; 2044 ucontrol->value.iec958.status[3] = 0xff; 2045 return 0; 2046 } 2047 2048 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol, 2049 struct snd_ctl_elem_value *ucontrol) 2050 { 2051 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2052 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2053 2054 mutex_lock(&chip->spos_mutex); 2055 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff); 2056 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff); 2057 ucontrol->value.iec958.status[2] = 0; 2058 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff); 2059 mutex_unlock(&chip->spos_mutex); 2060 2061 return 0; 2062 } 2063 2064 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol, 2065 struct snd_ctl_elem_value *ucontrol) 2066 { 2067 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2068 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2069 unsigned int val; 2070 int change; 2071 2072 mutex_lock(&chip->spos_mutex); 2073 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2074 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) | 2075 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2076 /* left and right validity bit */ 2077 (1 << 13) | (1 << 12); 2078 2079 2080 change = ins->spdif_csuv_stream != val; 2081 ins->spdif_csuv_stream = val; 2082 2083 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN ) 2084 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2085 2086 mutex_unlock(&chip->spos_mutex); 2087 2088 return change; 2089 } 2090 2091 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2092 2093 2094 static struct snd_kcontrol_new snd_cs46xx_controls[] __devinitdata = { 2095 { 2096 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2097 .name = "DAC Volume", 2098 .info = snd_cs46xx_vol_info, 2099 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2100 .get = snd_cs46xx_vol_get, 2101 .put = snd_cs46xx_vol_put, 2102 .private_value = BA1_PVOL, 2103 #else 2104 .get = snd_cs46xx_vol_dac_get, 2105 .put = snd_cs46xx_vol_dac_put, 2106 #endif 2107 }, 2108 2109 { 2110 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2111 .name = "ADC Volume", 2112 .info = snd_cs46xx_vol_info, 2113 .get = snd_cs46xx_vol_get, 2114 .put = snd_cs46xx_vol_put, 2115 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2116 .private_value = BA1_CVOL, 2117 #else 2118 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2, 2119 #endif 2120 }, 2121 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2122 { 2123 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2124 .name = "ADC Capture Switch", 2125 .info = snd_mixer_boolean_info, 2126 .get = snd_cs46xx_adc_capture_get, 2127 .put = snd_cs46xx_adc_capture_put 2128 }, 2129 { 2130 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2131 .name = "DAC Capture Switch", 2132 .info = snd_mixer_boolean_info, 2133 .get = snd_cs46xx_pcm_capture_get, 2134 .put = snd_cs46xx_pcm_capture_put 2135 }, 2136 { 2137 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2138 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), 2139 .info = snd_mixer_boolean_info, 2140 .get = snd_cs46xx_iec958_get, 2141 .put = snd_cs46xx_iec958_put, 2142 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT, 2143 }, 2144 { 2145 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2146 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH), 2147 .info = snd_mixer_boolean_info, 2148 .get = snd_cs46xx_iec958_get, 2149 .put = snd_cs46xx_iec958_put, 2150 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT, 2151 }, 2152 #if 0 2153 /* Input IEC958 volume does not work for the moment. (Benny) */ 2154 { 2155 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2156 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME), 2157 .info = snd_cs46xx_vol_info, 2158 .get = snd_cs46xx_vol_iec958_get, 2159 .put = snd_cs46xx_vol_iec958_put, 2160 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2, 2161 }, 2162 #endif 2163 { 2164 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2165 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2166 .info = snd_cs46xx_spdif_info, 2167 .get = snd_cs46xx_spdif_default_get, 2168 .put = snd_cs46xx_spdif_default_put, 2169 }, 2170 { 2171 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2172 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 2173 .info = snd_cs46xx_spdif_info, 2174 .get = snd_cs46xx_spdif_mask_get, 2175 .access = SNDRV_CTL_ELEM_ACCESS_READ 2176 }, 2177 { 2178 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2179 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2180 .info = snd_cs46xx_spdif_info, 2181 .get = snd_cs46xx_spdif_stream_get, 2182 .put = snd_cs46xx_spdif_stream_put 2183 }, 2184 2185 #endif 2186 }; 2187 2188 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2189 /* set primary cs4294 codec into Extended Audio Mode */ 2190 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol, 2191 struct snd_ctl_elem_value *ucontrol) 2192 { 2193 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2194 unsigned short val; 2195 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE); 2196 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1; 2197 return 0; 2198 } 2199 2200 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol, 2201 struct snd_ctl_elem_value *ucontrol) 2202 { 2203 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2204 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2205 AC97_CSR_ACMODE, 0x200, 2206 ucontrol->value.integer.value[0] ? 0 : 0x200); 2207 } 2208 2209 static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = { 2210 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2211 .name = "Duplicate Front", 2212 .info = snd_mixer_boolean_info, 2213 .get = snd_cs46xx_front_dup_get, 2214 .put = snd_cs46xx_front_dup_put, 2215 }; 2216 #endif 2217 2218 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2219 /* Only available on the Hercules Game Theater XP soundcard */ 2220 static struct snd_kcontrol_new snd_hercules_controls[] = { 2221 { 2222 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2223 .name = "Optical/Coaxial SPDIF Input Switch", 2224 .info = snd_mixer_boolean_info, 2225 .get = snd_herc_spdif_select_get, 2226 .put = snd_herc_spdif_select_put, 2227 }, 2228 }; 2229 2230 2231 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97) 2232 { 2233 unsigned long end_time; 2234 int err; 2235 2236 /* reset to defaults */ 2237 snd_ac97_write(ac97, AC97_RESET, 0); 2238 2239 /* set the desired CODEC mode */ 2240 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) { 2241 snd_printdd("cs46xx: CODEC1 mode %04x\n", 0x0); 2242 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0); 2243 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) { 2244 snd_printdd("cs46xx: CODEC2 mode %04x\n", 0x3); 2245 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3); 2246 } else { 2247 snd_BUG(); /* should never happen ... */ 2248 } 2249 2250 udelay(50); 2251 2252 /* it's necessary to wait awhile until registers are accessible after RESET */ 2253 /* because the PCM or MASTER volume registers can be modified, */ 2254 /* the REC_GAIN register is used for tests */ 2255 end_time = jiffies + HZ; 2256 do { 2257 unsigned short ext_mid; 2258 2259 /* use preliminary reads to settle the communication */ 2260 snd_ac97_read(ac97, AC97_RESET); 2261 snd_ac97_read(ac97, AC97_VENDOR_ID1); 2262 snd_ac97_read(ac97, AC97_VENDOR_ID2); 2263 /* modem? */ 2264 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID); 2265 if (ext_mid != 0xffff && (ext_mid & 1) != 0) 2266 return; 2267 2268 /* test if we can write to the record gain volume register */ 2269 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05); 2270 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05) 2271 return; 2272 2273 msleep(10); 2274 } while (time_after_eq(end_time, jiffies)); 2275 2276 snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n"); 2277 } 2278 #endif 2279 2280 static int __devinit cs46xx_detect_codec(struct snd_cs46xx *chip, int codec) 2281 { 2282 int idx, err; 2283 struct snd_ac97_template ac97; 2284 2285 memset(&ac97, 0, sizeof(ac97)); 2286 ac97.private_data = chip; 2287 ac97.private_free = snd_cs46xx_mixer_free_ac97; 2288 ac97.num = codec; 2289 if (chip->amplifier_ctrl == amp_voyetra) 2290 ac97.scaps = AC97_SCAP_INV_EAPD; 2291 2292 if (codec == CS46XX_SECONDARY_CODEC_INDEX) { 2293 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec); 2294 udelay(10); 2295 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) { 2296 snd_printdd("snd_cs46xx: seconadry codec not present\n"); 2297 return -ENXIO; 2298 } 2299 } 2300 2301 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec); 2302 for (idx = 0; idx < 100; ++idx) { 2303 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) { 2304 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]); 2305 return err; 2306 } 2307 msleep(10); 2308 } 2309 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec); 2310 return -ENXIO; 2311 } 2312 2313 int __devinit snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device) 2314 { 2315 struct snd_card *card = chip->card; 2316 struct snd_ctl_elem_id id; 2317 int err; 2318 unsigned int idx; 2319 static struct snd_ac97_bus_ops ops = { 2320 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2321 .reset = snd_cs46xx_codec_reset, 2322 #endif 2323 .write = snd_cs46xx_ac97_write, 2324 .read = snd_cs46xx_ac97_read, 2325 }; 2326 2327 /* detect primary codec */ 2328 chip->nr_ac97_codecs = 0; 2329 snd_printdd("snd_cs46xx: detecting primary codec\n"); 2330 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) 2331 return err; 2332 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus; 2333 2334 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0) 2335 return -ENXIO; 2336 chip->nr_ac97_codecs = 1; 2337 2338 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2339 snd_printdd("snd_cs46xx: detecting seconadry codec\n"); 2340 /* try detect a secondary codec */ 2341 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX)) 2342 chip->nr_ac97_codecs = 2; 2343 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2344 2345 /* add cs4630 mixer controls */ 2346 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) { 2347 struct snd_kcontrol *kctl; 2348 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip); 2349 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM) 2350 kctl->id.device = spdif_device; 2351 if ((err = snd_ctl_add(card, kctl)) < 0) 2352 return err; 2353 } 2354 2355 /* get EAPD mixer switch (for voyetra hack) */ 2356 memset(&id, 0, sizeof(id)); 2357 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2358 strcpy(id.name, "External Amplifier"); 2359 chip->eapd_switch = snd_ctl_find_id(chip->card, &id); 2360 2361 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2362 if (chip->nr_ac97_codecs == 1) { 2363 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff; 2364 if (id2 == 0x592b || id2 == 0x592d) { 2365 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip)); 2366 if (err < 0) 2367 return err; 2368 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2369 AC97_CSR_ACMODE, 0x200); 2370 } 2371 } 2372 /* do soundcard specific mixer setup */ 2373 if (chip->mixer_init) { 2374 snd_printdd ("calling chip->mixer_init(chip);\n"); 2375 chip->mixer_init(chip); 2376 } 2377 #endif 2378 2379 /* turn on amplifier */ 2380 chip->amplifier_ctrl(chip, 1); 2381 2382 return 0; 2383 } 2384 2385 /* 2386 * RawMIDI interface 2387 */ 2388 2389 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip) 2390 { 2391 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST); 2392 udelay(100); 2393 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2394 } 2395 2396 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream) 2397 { 2398 struct snd_cs46xx *chip = substream->rmidi->private_data; 2399 2400 chip->active_ctrl(chip, 1); 2401 spin_lock_irq(&chip->reg_lock); 2402 chip->uartm |= CS46XX_MODE_INPUT; 2403 chip->midcr |= MIDCR_RXE; 2404 chip->midi_input = substream; 2405 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2406 snd_cs46xx_midi_reset(chip); 2407 } else { 2408 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2409 } 2410 spin_unlock_irq(&chip->reg_lock); 2411 return 0; 2412 } 2413 2414 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream) 2415 { 2416 struct snd_cs46xx *chip = substream->rmidi->private_data; 2417 2418 spin_lock_irq(&chip->reg_lock); 2419 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE); 2420 chip->midi_input = NULL; 2421 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2422 snd_cs46xx_midi_reset(chip); 2423 } else { 2424 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2425 } 2426 chip->uartm &= ~CS46XX_MODE_INPUT; 2427 spin_unlock_irq(&chip->reg_lock); 2428 chip->active_ctrl(chip, -1); 2429 return 0; 2430 } 2431 2432 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream) 2433 { 2434 struct snd_cs46xx *chip = substream->rmidi->private_data; 2435 2436 chip->active_ctrl(chip, 1); 2437 2438 spin_lock_irq(&chip->reg_lock); 2439 chip->uartm |= CS46XX_MODE_OUTPUT; 2440 chip->midcr |= MIDCR_TXE; 2441 chip->midi_output = substream; 2442 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2443 snd_cs46xx_midi_reset(chip); 2444 } else { 2445 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2446 } 2447 spin_unlock_irq(&chip->reg_lock); 2448 return 0; 2449 } 2450 2451 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream) 2452 { 2453 struct snd_cs46xx *chip = substream->rmidi->private_data; 2454 2455 spin_lock_irq(&chip->reg_lock); 2456 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE); 2457 chip->midi_output = NULL; 2458 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2459 snd_cs46xx_midi_reset(chip); 2460 } else { 2461 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2462 } 2463 chip->uartm &= ~CS46XX_MODE_OUTPUT; 2464 spin_unlock_irq(&chip->reg_lock); 2465 chip->active_ctrl(chip, -1); 2466 return 0; 2467 } 2468 2469 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2470 { 2471 unsigned long flags; 2472 struct snd_cs46xx *chip = substream->rmidi->private_data; 2473 2474 spin_lock_irqsave(&chip->reg_lock, flags); 2475 if (up) { 2476 if ((chip->midcr & MIDCR_RIE) == 0) { 2477 chip->midcr |= MIDCR_RIE; 2478 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2479 } 2480 } else { 2481 if (chip->midcr & MIDCR_RIE) { 2482 chip->midcr &= ~MIDCR_RIE; 2483 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2484 } 2485 } 2486 spin_unlock_irqrestore(&chip->reg_lock, flags); 2487 } 2488 2489 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2490 { 2491 unsigned long flags; 2492 struct snd_cs46xx *chip = substream->rmidi->private_data; 2493 unsigned char byte; 2494 2495 spin_lock_irqsave(&chip->reg_lock, flags); 2496 if (up) { 2497 if ((chip->midcr & MIDCR_TIE) == 0) { 2498 chip->midcr |= MIDCR_TIE; 2499 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2500 while ((chip->midcr & MIDCR_TIE) && 2501 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 2502 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2503 chip->midcr &= ~MIDCR_TIE; 2504 } else { 2505 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte); 2506 } 2507 } 2508 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2509 } 2510 } else { 2511 if (chip->midcr & MIDCR_TIE) { 2512 chip->midcr &= ~MIDCR_TIE; 2513 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2514 } 2515 } 2516 spin_unlock_irqrestore(&chip->reg_lock, flags); 2517 } 2518 2519 static struct snd_rawmidi_ops snd_cs46xx_midi_output = 2520 { 2521 .open = snd_cs46xx_midi_output_open, 2522 .close = snd_cs46xx_midi_output_close, 2523 .trigger = snd_cs46xx_midi_output_trigger, 2524 }; 2525 2526 static struct snd_rawmidi_ops snd_cs46xx_midi_input = 2527 { 2528 .open = snd_cs46xx_midi_input_open, 2529 .close = snd_cs46xx_midi_input_close, 2530 .trigger = snd_cs46xx_midi_input_trigger, 2531 }; 2532 2533 int __devinit snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi) 2534 { 2535 struct snd_rawmidi *rmidi; 2536 int err; 2537 2538 if (rrawmidi) 2539 *rrawmidi = NULL; 2540 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0) 2541 return err; 2542 strcpy(rmidi->name, "CS46XX"); 2543 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output); 2544 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input); 2545 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 2546 rmidi->private_data = chip; 2547 chip->rmidi = rmidi; 2548 if (rrawmidi) 2549 *rrawmidi = NULL; 2550 return 0; 2551 } 2552 2553 2554 /* 2555 * gameport interface 2556 */ 2557 2558 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 2559 2560 static void snd_cs46xx_gameport_trigger(struct gameport *gameport) 2561 { 2562 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2563 2564 if (snd_BUG_ON(!chip)) 2565 return; 2566 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF); 2567 } 2568 2569 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport) 2570 { 2571 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2572 2573 if (snd_BUG_ON(!chip)) 2574 return 0; 2575 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io); 2576 } 2577 2578 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) 2579 { 2580 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2581 unsigned js1, js2, jst; 2582 2583 if (snd_BUG_ON(!chip)) 2584 return 0; 2585 2586 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1); 2587 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2); 2588 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT); 2589 2590 *buttons = (~jst >> 4) & 0x0F; 2591 2592 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 2593 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 2594 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 2595 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 2596 2597 for(jst=0;jst<4;++jst) 2598 if(axes[jst]==0xFFFF) axes[jst] = -1; 2599 return 0; 2600 } 2601 2602 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode) 2603 { 2604 switch (mode) { 2605 case GAMEPORT_MODE_COOKED: 2606 return 0; 2607 case GAMEPORT_MODE_RAW: 2608 return 0; 2609 default: 2610 return -1; 2611 } 2612 return 0; 2613 } 2614 2615 int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) 2616 { 2617 struct gameport *gp; 2618 2619 chip->gameport = gp = gameport_allocate_port(); 2620 if (!gp) { 2621 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n"); 2622 return -ENOMEM; 2623 } 2624 2625 gameport_set_name(gp, "CS46xx Gameport"); 2626 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2627 gameport_set_dev_parent(gp, &chip->pci->dev); 2628 gameport_set_port_data(gp, chip); 2629 2630 gp->open = snd_cs46xx_gameport_open; 2631 gp->read = snd_cs46xx_gameport_read; 2632 gp->trigger = snd_cs46xx_gameport_trigger; 2633 gp->cooked_read = snd_cs46xx_gameport_cooked_read; 2634 2635 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 2636 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 2637 2638 gameport_register_port(gp); 2639 2640 return 0; 2641 } 2642 2643 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) 2644 { 2645 if (chip->gameport) { 2646 gameport_unregister_port(chip->gameport); 2647 chip->gameport = NULL; 2648 } 2649 } 2650 #else 2651 int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; } 2652 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { } 2653 #endif /* CONFIG_GAMEPORT */ 2654 2655 #ifdef CONFIG_PROC_FS 2656 /* 2657 * proc interface 2658 */ 2659 2660 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry, 2661 void *file_private_data, 2662 struct file *file, char __user *buf, 2663 size_t count, loff_t pos) 2664 { 2665 struct snd_cs46xx_region *region = entry->private_data; 2666 2667 if (copy_to_user_fromio(buf, region->remap_addr + pos, count)) 2668 return -EFAULT; 2669 return count; 2670 } 2671 2672 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = { 2673 .read = snd_cs46xx_io_read, 2674 }; 2675 2676 static int __devinit snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip) 2677 { 2678 struct snd_info_entry *entry; 2679 int idx; 2680 2681 for (idx = 0; idx < 5; idx++) { 2682 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2683 if (! snd_card_proc_new(card, region->name, &entry)) { 2684 entry->content = SNDRV_INFO_CONTENT_DATA; 2685 entry->private_data = chip; 2686 entry->c.ops = &snd_cs46xx_proc_io_ops; 2687 entry->size = region->size; 2688 entry->mode = S_IFREG | S_IRUSR; 2689 } 2690 } 2691 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2692 cs46xx_dsp_proc_init(card, chip); 2693 #endif 2694 return 0; 2695 } 2696 2697 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip) 2698 { 2699 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2700 cs46xx_dsp_proc_done(chip); 2701 #endif 2702 return 0; 2703 } 2704 #else /* !CONFIG_PROC_FS */ 2705 #define snd_cs46xx_proc_init(card, chip) 2706 #define snd_cs46xx_proc_done(chip) 2707 #endif 2708 2709 /* 2710 * stop the h/w 2711 */ 2712 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip) 2713 { 2714 unsigned int tmp; 2715 2716 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 2717 tmp &= ~0x0000f03f; 2718 tmp |= 0x00000010; 2719 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */ 2720 2721 tmp = snd_cs46xx_peek(chip, BA1_CIE); 2722 tmp &= ~0x0000003f; 2723 tmp |= 0x00000011; 2724 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */ 2725 2726 /* 2727 * Stop playback DMA. 2728 */ 2729 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 2730 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 2731 2732 /* 2733 * Stop capture DMA. 2734 */ 2735 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 2736 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 2737 2738 /* 2739 * Reset the processor. 2740 */ 2741 snd_cs46xx_reset(chip); 2742 2743 snd_cs46xx_proc_stop(chip); 2744 2745 /* 2746 * Power down the PLL. 2747 */ 2748 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2749 2750 /* 2751 * Turn off the Processor by turning off the software clock enable flag in 2752 * the clock control register. 2753 */ 2754 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; 2755 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 2756 } 2757 2758 2759 static int snd_cs46xx_free(struct snd_cs46xx *chip) 2760 { 2761 int idx; 2762 2763 if (snd_BUG_ON(!chip)) 2764 return -EINVAL; 2765 2766 if (chip->active_ctrl) 2767 chip->active_ctrl(chip, 1); 2768 2769 snd_cs46xx_remove_gameport(chip); 2770 2771 if (chip->amplifier_ctrl) 2772 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */ 2773 2774 snd_cs46xx_proc_done(chip); 2775 2776 if (chip->region.idx[0].resource) 2777 snd_cs46xx_hw_stop(chip); 2778 2779 if (chip->irq >= 0) 2780 free_irq(chip->irq, chip); 2781 2782 if (chip->active_ctrl) 2783 chip->active_ctrl(chip, -chip->amplifier); 2784 2785 for (idx = 0; idx < 5; idx++) { 2786 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2787 if (region->remap_addr) 2788 iounmap(region->remap_addr); 2789 release_and_free_resource(region->resource); 2790 } 2791 2792 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2793 if (chip->dsp_spos_instance) { 2794 cs46xx_dsp_spos_destroy(chip); 2795 chip->dsp_spos_instance = NULL; 2796 } 2797 #endif 2798 2799 #ifdef CONFIG_PM 2800 kfree(chip->saved_regs); 2801 #endif 2802 2803 pci_disable_device(chip->pci); 2804 kfree(chip); 2805 return 0; 2806 } 2807 2808 static int snd_cs46xx_dev_free(struct snd_device *device) 2809 { 2810 struct snd_cs46xx *chip = device->device_data; 2811 return snd_cs46xx_free(chip); 2812 } 2813 2814 /* 2815 * initialize chip 2816 */ 2817 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip) 2818 { 2819 int timeout; 2820 2821 /* 2822 * First, blast the clock control register to zero so that the PLL starts 2823 * out in a known state, and blast the master serial port control register 2824 * to zero so that the serial ports also start out in a known state. 2825 */ 2826 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2827 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0); 2828 2829 /* 2830 * If we are in AC97 mode, then we must set the part to a host controlled 2831 * AC-link. Otherwise, we won't be able to bring up the link. 2832 */ 2833 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2834 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 | 2835 SERACC_TWO_CODECS); /* 2.00 dual codecs */ 2836 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */ 2837 #else 2838 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */ 2839 #endif 2840 2841 /* 2842 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 2843 * spec) and then drive it high. This is done for non AC97 modes since 2844 * there might be logic external to the CS461x that uses the ARST# line 2845 * for a reset. 2846 */ 2847 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0); 2848 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2849 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0); 2850 #endif 2851 udelay(50); 2852 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN); 2853 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2854 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN); 2855 #endif 2856 2857 /* 2858 * The first thing we do here is to enable sync generation. As soon 2859 * as we start receiving bit clock, we'll start producing the SYNC 2860 * signal. 2861 */ 2862 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 2863 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2864 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN); 2865 #endif 2866 2867 /* 2868 * Now wait for a short while to allow the AC97 part to start 2869 * generating bit clock (so we don't try to start the PLL without an 2870 * input clock). 2871 */ 2872 mdelay(10); 2873 2874 /* 2875 * Set the serial port timing configuration, so that 2876 * the clock control circuit gets its clock from the correct place. 2877 */ 2878 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97); 2879 2880 /* 2881 * Write the selected clock control setup to the hardware. Do not turn on 2882 * SWCE yet (if requested), so that the devices clocked by the output of 2883 * PLL are not clocked until the PLL is stable. 2884 */ 2885 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 2886 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a); 2887 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8); 2888 2889 /* 2890 * Power up the PLL. 2891 */ 2892 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP); 2893 2894 /* 2895 * Wait until the PLL has stabilized. 2896 */ 2897 msleep(100); 2898 2899 /* 2900 * Turn on clocking of the core so that we can setup the serial ports. 2901 */ 2902 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 2903 2904 /* 2905 * Enable FIFO Host Bypass 2906 */ 2907 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP); 2908 2909 /* 2910 * Fill the serial port FIFOs with silence. 2911 */ 2912 snd_cs46xx_clear_serial_FIFOs(chip); 2913 2914 /* 2915 * Set the serial port FIFO pointer to the first sample in the FIFO. 2916 */ 2917 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */ 2918 2919 /* 2920 * Write the serial port configuration to the part. The master 2921 * enable bit is not set until all other values have been written. 2922 */ 2923 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 2924 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 2925 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 2926 2927 2928 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2929 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN); 2930 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0); 2931 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0); 2932 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0); 2933 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1); 2934 #endif 2935 2936 mdelay(5); 2937 2938 2939 /* 2940 * Wait for the codec ready signal from the AC97 codec. 2941 */ 2942 timeout = 150; 2943 while (timeout-- > 0) { 2944 /* 2945 * Read the AC97 status register to see if we've seen a CODEC READY 2946 * signal from the AC97 codec. 2947 */ 2948 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) 2949 goto ok1; 2950 msleep(10); 2951 } 2952 2953 2954 snd_printk(KERN_ERR "create - never read codec ready from AC'97\n"); 2955 snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n"); 2956 return -EIO; 2957 ok1: 2958 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2959 { 2960 int count; 2961 for (count = 0; count < 150; count++) { 2962 /* First, we want to wait for a short time. */ 2963 udelay(25); 2964 2965 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY) 2966 break; 2967 } 2968 2969 /* 2970 * Make sure CODEC is READY. 2971 */ 2972 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)) 2973 snd_printdd("cs46xx: never read card ready from secondary AC'97\n"); 2974 } 2975 #endif 2976 2977 /* 2978 * Assert the vaid frame signal so that we can start sending commands 2979 * to the AC97 codec. 2980 */ 2981 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 2982 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2983 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 2984 #endif 2985 2986 2987 /* 2988 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 2989 * the codec is pumping ADC data across the AC-link. 2990 */ 2991 timeout = 150; 2992 while (timeout-- > 0) { 2993 /* 2994 * Read the input slot valid register and see if input slots 3 and 2995 * 4 are valid yet. 2996 */ 2997 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 2998 goto ok2; 2999 msleep(10); 3000 } 3001 3002 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3003 snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n"); 3004 return -EIO; 3005 #else 3006 /* This may happen on a cold boot with a Terratec SiXPack 5.1. 3007 Reloading the driver may help, if there's other soundcards 3008 with the same problem I would like to know. (Benny) */ 3009 3010 snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n"); 3011 snd_printk(KERN_ERR " Try reloading the ALSA driver, if you find something\n"); 3012 snd_printk(KERN_ERR " broken or not working on your soundcard upon\n"); 3013 snd_printk(KERN_ERR " this message please report to alsa-devel@alsa-project.org\n"); 3014 3015 return -EIO; 3016 #endif 3017 ok2: 3018 3019 /* 3020 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 3021 * commense the transfer of digital audio data to the AC97 codec. 3022 */ 3023 3024 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 3025 3026 3027 /* 3028 * Power down the DAC and ADC. We will power them up (if) when we need 3029 * them. 3030 */ 3031 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */ 3032 3033 /* 3034 * Turn off the Processor by turning off the software clock enable flag in 3035 * the clock control register. 3036 */ 3037 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */ 3038 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */ 3039 3040 return 0; 3041 } 3042 3043 /* 3044 * start and load DSP 3045 */ 3046 3047 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip) 3048 { 3049 unsigned int tmp; 3050 3051 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM); 3052 3053 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 3054 tmp &= ~0x0000f03f; 3055 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */ 3056 3057 tmp = snd_cs46xx_peek(chip, BA1_CIE); 3058 tmp &= ~0x0000003f; 3059 tmp |= 0x00000001; 3060 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */ 3061 } 3062 3063 int __devinit snd_cs46xx_start_dsp(struct snd_cs46xx *chip) 3064 { 3065 unsigned int tmp; 3066 /* 3067 * Reset the processor. 3068 */ 3069 snd_cs46xx_reset(chip); 3070 /* 3071 * Download the image to the processor. 3072 */ 3073 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3074 #if 0 3075 if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) { 3076 snd_printk(KERN_ERR "image download error\n"); 3077 return -EIO; 3078 } 3079 #endif 3080 3081 if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) { 3082 snd_printk(KERN_ERR "image download error [cwc4630]\n"); 3083 return -EIO; 3084 } 3085 3086 if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) { 3087 snd_printk(KERN_ERR "image download error [cwcasync]\n"); 3088 return -EIO; 3089 } 3090 3091 if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) { 3092 snd_printk(KERN_ERR "image download error [cwcsnoop]\n"); 3093 return -EIO; 3094 } 3095 3096 if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) { 3097 snd_printk(KERN_ERR "image download error [cwcbinhack]\n"); 3098 return -EIO; 3099 } 3100 3101 if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) { 3102 snd_printk(KERN_ERR "image download error [cwcdma]\n"); 3103 return -EIO; 3104 } 3105 3106 if (cs46xx_dsp_scb_and_task_init(chip) < 0) 3107 return -EIO; 3108 #else 3109 /* old image */ 3110 if (snd_cs46xx_download_image(chip) < 0) { 3111 snd_printk(KERN_ERR "image download error\n"); 3112 return -EIO; 3113 } 3114 3115 /* 3116 * Stop playback DMA. 3117 */ 3118 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 3119 chip->play_ctl = tmp & 0xffff0000; 3120 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 3121 #endif 3122 3123 /* 3124 * Stop capture DMA. 3125 */ 3126 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3127 chip->capt.ctl = tmp & 0x0000ffff; 3128 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3129 3130 mdelay(5); 3131 3132 snd_cs46xx_set_play_sample_rate(chip, 8000); 3133 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3134 3135 snd_cs46xx_proc_start(chip); 3136 3137 cs46xx_enable_stream_irqs(chip); 3138 3139 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3140 /* set the attenuation to 0dB */ 3141 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000); 3142 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000); 3143 #endif 3144 3145 return 0; 3146 } 3147 3148 3149 /* 3150 * AMP control - null AMP 3151 */ 3152 3153 static void amp_none(struct snd_cs46xx *chip, int change) 3154 { 3155 } 3156 3157 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3158 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip) 3159 { 3160 3161 u32 idx, valid_slots,tmp,powerdown = 0; 3162 u16 modem_power,pin_config,logic_type; 3163 3164 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n"); 3165 3166 /* 3167 * See if the devices are powered down. If so, we must power them up first 3168 * or they will not respond. 3169 */ 3170 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 3171 3172 if (!(tmp & CLKCR1_SWCE)) { 3173 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 3174 powerdown = 1; 3175 } 3176 3177 /* 3178 * Clear PRA. The Bonzo chip will be used for GPIO not for modem 3179 * stuff. 3180 */ 3181 if(chip->nr_ac97_codecs != 2) { 3182 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n"); 3183 return -EINVAL; 3184 } 3185 3186 modem_power = snd_cs46xx_codec_read (chip, 3187 AC97_EXTENDED_MSTATUS, 3188 CS46XX_SECONDARY_CODEC_INDEX); 3189 modem_power &=0xFEFF; 3190 3191 snd_cs46xx_codec_write(chip, 3192 AC97_EXTENDED_MSTATUS, modem_power, 3193 CS46XX_SECONDARY_CODEC_INDEX); 3194 3195 /* 3196 * Set GPIO pin's 7 and 8 so that they are configured for output. 3197 */ 3198 pin_config = snd_cs46xx_codec_read (chip, 3199 AC97_GPIO_CFG, 3200 CS46XX_SECONDARY_CODEC_INDEX); 3201 pin_config &=0x27F; 3202 3203 snd_cs46xx_codec_write(chip, 3204 AC97_GPIO_CFG, pin_config, 3205 CS46XX_SECONDARY_CODEC_INDEX); 3206 3207 /* 3208 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic. 3209 */ 3210 3211 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY, 3212 CS46XX_SECONDARY_CODEC_INDEX); 3213 logic_type &=0x27F; 3214 3215 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type, 3216 CS46XX_SECONDARY_CODEC_INDEX); 3217 3218 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV); 3219 valid_slots |= 0x200; 3220 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots); 3221 3222 if ( cs46xx_wait_for_fifo(chip,1) ) { 3223 snd_printdd("FIFO is busy\n"); 3224 3225 return -EINVAL; 3226 } 3227 3228 /* 3229 * Fill slots 12 with the correct value for the GPIO pins. 3230 */ 3231 for(idx = 0x90; idx <= 0x9F; idx++) { 3232 /* 3233 * Initialize the fifo so that bits 7 and 8 are on. 3234 * 3235 * Remember that the GPIO pins in bonzo are shifted by 4 bits to 3236 * the left. 0x1800 corresponds to bits 7 and 8. 3237 */ 3238 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800); 3239 3240 /* 3241 * Wait for command to complete 3242 */ 3243 if ( cs46xx_wait_for_fifo(chip,200) ) { 3244 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx); 3245 3246 return -EINVAL; 3247 } 3248 3249 /* 3250 * Write the serial port FIFO index. 3251 */ 3252 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 3253 3254 /* 3255 * Tell the serial port to load the new value into the FIFO location. 3256 */ 3257 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 3258 } 3259 3260 /* wait for last command to complete */ 3261 cs46xx_wait_for_fifo(chip,200); 3262 3263 /* 3264 * Now, if we powered up the devices, then power them back down again. 3265 * This is kinda ugly, but should never happen. 3266 */ 3267 if (powerdown) 3268 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 3269 3270 return 0; 3271 } 3272 #endif 3273 3274 /* 3275 * Crystal EAPD mode 3276 */ 3277 3278 static void amp_voyetra(struct snd_cs46xx *chip, int change) 3279 { 3280 /* Manage the EAPD bit on the Crystal 4297 3281 and the Analog AD1885 */ 3282 3283 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3284 int old = chip->amplifier; 3285 #endif 3286 int oval, val; 3287 3288 chip->amplifier += change; 3289 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN, 3290 CS46XX_PRIMARY_CODEC_INDEX); 3291 val = oval; 3292 if (chip->amplifier) { 3293 /* Turn the EAPD amp on */ 3294 val |= 0x8000; 3295 } else { 3296 /* Turn the EAPD amp off */ 3297 val &= ~0x8000; 3298 } 3299 if (val != oval) { 3300 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val, 3301 CS46XX_PRIMARY_CODEC_INDEX); 3302 if (chip->eapd_switch) 3303 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 3304 &chip->eapd_switch->id); 3305 } 3306 3307 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3308 if (chip->amplifier && !old) { 3309 voyetra_setup_eapd_slot(chip); 3310 } 3311 #endif 3312 } 3313 3314 static void hercules_init(struct snd_cs46xx *chip) 3315 { 3316 /* default: AMP off, and SPDIF input optical */ 3317 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3318 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3319 } 3320 3321 3322 /* 3323 * Game Theatre XP card - EGPIO[2] is used to enable the external amp. 3324 */ 3325 static void amp_hercules(struct snd_cs46xx *chip, int change) 3326 { 3327 int old = chip->amplifier; 3328 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 3329 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 3330 3331 chip->amplifier += change; 3332 if (chip->amplifier && !old) { 3333 snd_printdd ("Hercules amplifier ON\n"); 3334 3335 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 3336 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */ 3337 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 3338 EGPIOPTR_GPPT2 | val2); /* open-drain on output */ 3339 } else if (old && !chip->amplifier) { 3340 snd_printdd ("Hercules amplifier OFF\n"); 3341 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */ 3342 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */ 3343 } 3344 } 3345 3346 static void voyetra_mixer_init (struct snd_cs46xx *chip) 3347 { 3348 snd_printdd ("initializing Voyetra mixer\n"); 3349 3350 /* Enable SPDIF out */ 3351 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3352 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3353 } 3354 3355 static void hercules_mixer_init (struct snd_cs46xx *chip) 3356 { 3357 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3358 unsigned int idx; 3359 int err; 3360 struct snd_card *card = chip->card; 3361 #endif 3362 3363 /* set EGPIO to default */ 3364 hercules_init(chip); 3365 3366 snd_printdd ("initializing Hercules mixer\n"); 3367 3368 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3369 if (chip->in_suspend) 3370 return; 3371 3372 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) { 3373 struct snd_kcontrol *kctl; 3374 3375 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip); 3376 if ((err = snd_ctl_add(card, kctl)) < 0) { 3377 printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err); 3378 break; 3379 } 3380 } 3381 #endif 3382 } 3383 3384 3385 #if 0 3386 /* 3387 * Untested 3388 */ 3389 3390 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change) 3391 { 3392 chip->amplifier += change; 3393 3394 if (chip->amplifier) { 3395 /* Switch the GPIO pins 7 and 8 to open drain */ 3396 snd_cs46xx_codec_write(chip, 0x4C, 3397 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F); 3398 snd_cs46xx_codec_write(chip, 0x4E, 3399 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180); 3400 /* Now wake the AMP (this might be backwards) */ 3401 snd_cs46xx_codec_write(chip, 0x54, 3402 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180); 3403 } else { 3404 snd_cs46xx_codec_write(chip, 0x54, 3405 snd_cs46xx_codec_read(chip, 0x54) | 0x0180); 3406 } 3407 } 3408 #endif 3409 3410 3411 /* 3412 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support 3413 * whenever we need to beat on the chip. 3414 * 3415 * The original idea and code for this hack comes from David Kaiser at 3416 * Linuxcare. Perhaps one day Crystal will document their chips well 3417 * enough to make them useful. 3418 */ 3419 3420 static void clkrun_hack(struct snd_cs46xx *chip, int change) 3421 { 3422 u16 control, nval; 3423 3424 if (!chip->acpi_port) 3425 return; 3426 3427 chip->amplifier += change; 3428 3429 /* Read ACPI port */ 3430 nval = control = inw(chip->acpi_port + 0x10); 3431 3432 /* Flip CLKRUN off while running */ 3433 if (! chip->amplifier) 3434 nval |= 0x2000; 3435 else 3436 nval &= ~0x2000; 3437 if (nval != control) 3438 outw(nval, chip->acpi_port + 0x10); 3439 } 3440 3441 3442 /* 3443 * detect intel piix4 3444 */ 3445 static void clkrun_init(struct snd_cs46xx *chip) 3446 { 3447 struct pci_dev *pdev; 3448 u8 pp; 3449 3450 chip->acpi_port = 0; 3451 3452 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 3453 PCI_DEVICE_ID_INTEL_82371AB_3, NULL); 3454 if (pdev == NULL) 3455 return; /* Not a thinkpad thats for sure */ 3456 3457 /* Find the control port */ 3458 pci_read_config_byte(pdev, 0x41, &pp); 3459 chip->acpi_port = pp << 8; 3460 pci_dev_put(pdev); 3461 } 3462 3463 3464 /* 3465 * Card subid table 3466 */ 3467 3468 struct cs_card_type 3469 { 3470 u16 vendor; 3471 u16 id; 3472 char *name; 3473 void (*init)(struct snd_cs46xx *); 3474 void (*amp)(struct snd_cs46xx *, int); 3475 void (*active)(struct snd_cs46xx *, int); 3476 void (*mixer_init)(struct snd_cs46xx *); 3477 }; 3478 3479 static struct cs_card_type __devinitdata cards[] = { 3480 { 3481 .vendor = 0x1489, 3482 .id = 0x7001, 3483 .name = "Genius Soundmaker 128 value", 3484 /* nothing special */ 3485 }, 3486 { 3487 .vendor = 0x5053, 3488 .id = 0x3357, 3489 .name = "Voyetra", 3490 .amp = amp_voyetra, 3491 .mixer_init = voyetra_mixer_init, 3492 }, 3493 { 3494 .vendor = 0x1071, 3495 .id = 0x6003, 3496 .name = "Mitac MI6020/21", 3497 .amp = amp_voyetra, 3498 }, 3499 /* Hercules Game Theatre XP */ 3500 { 3501 .vendor = 0x14af, /* Guillemot Corporation */ 3502 .id = 0x0050, 3503 .name = "Hercules Game Theatre XP", 3504 .amp = amp_hercules, 3505 .mixer_init = hercules_mixer_init, 3506 }, 3507 { 3508 .vendor = 0x1681, 3509 .id = 0x0050, 3510 .name = "Hercules Game Theatre XP", 3511 .amp = amp_hercules, 3512 .mixer_init = hercules_mixer_init, 3513 }, 3514 { 3515 .vendor = 0x1681, 3516 .id = 0x0051, 3517 .name = "Hercules Game Theatre XP", 3518 .amp = amp_hercules, 3519 .mixer_init = hercules_mixer_init, 3520 3521 }, 3522 { 3523 .vendor = 0x1681, 3524 .id = 0x0052, 3525 .name = "Hercules Game Theatre XP", 3526 .amp = amp_hercules, 3527 .mixer_init = hercules_mixer_init, 3528 }, 3529 { 3530 .vendor = 0x1681, 3531 .id = 0x0053, 3532 .name = "Hercules Game Theatre XP", 3533 .amp = amp_hercules, 3534 .mixer_init = hercules_mixer_init, 3535 }, 3536 { 3537 .vendor = 0x1681, 3538 .id = 0x0054, 3539 .name = "Hercules Game Theatre XP", 3540 .amp = amp_hercules, 3541 .mixer_init = hercules_mixer_init, 3542 }, 3543 /* Herculess Fortissimo */ 3544 { 3545 .vendor = 0x1681, 3546 .id = 0xa010, 3547 .name = "Hercules Gamesurround Fortissimo II", 3548 }, 3549 { 3550 .vendor = 0x1681, 3551 .id = 0xa011, 3552 .name = "Hercules Gamesurround Fortissimo III 7.1", 3553 }, 3554 /* Teratec */ 3555 { 3556 .vendor = 0x153b, 3557 .id = 0x112e, 3558 .name = "Terratec DMX XFire 1024", 3559 }, 3560 { 3561 .vendor = 0x153b, 3562 .id = 0x1136, 3563 .name = "Terratec SiXPack 5.1", 3564 }, 3565 /* Not sure if the 570 needs the clkrun hack */ 3566 { 3567 .vendor = PCI_VENDOR_ID_IBM, 3568 .id = 0x0132, 3569 .name = "Thinkpad 570", 3570 .init = clkrun_init, 3571 .active = clkrun_hack, 3572 }, 3573 { 3574 .vendor = PCI_VENDOR_ID_IBM, 3575 .id = 0x0153, 3576 .name = "Thinkpad 600X/A20/T20", 3577 .init = clkrun_init, 3578 .active = clkrun_hack, 3579 }, 3580 { 3581 .vendor = PCI_VENDOR_ID_IBM, 3582 .id = 0x1010, 3583 .name = "Thinkpad 600E (unsupported)", 3584 }, 3585 {} /* terminator */ 3586 }; 3587 3588 3589 /* 3590 * APM support 3591 */ 3592 #ifdef CONFIG_PM 3593 static unsigned int saved_regs[] = { 3594 BA0_ACOSV, 3595 /*BA0_ASER_FADDR,*/ 3596 BA0_ASER_MASTER, 3597 BA1_PVOL, 3598 BA1_CVOL, 3599 }; 3600 3601 int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state) 3602 { 3603 struct snd_card *card = pci_get_drvdata(pci); 3604 struct snd_cs46xx *chip = card->private_data; 3605 int i, amp_saved; 3606 3607 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3608 chip->in_suspend = 1; 3609 snd_pcm_suspend_all(chip->pcm); 3610 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL); 3611 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE); 3612 3613 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3614 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3615 3616 /* save some registers */ 3617 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3618 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]); 3619 3620 amp_saved = chip->amplifier; 3621 /* turn off amp */ 3622 chip->amplifier_ctrl(chip, -chip->amplifier); 3623 snd_cs46xx_hw_stop(chip); 3624 /* disable CLKRUN */ 3625 chip->active_ctrl(chip, -chip->amplifier); 3626 chip->amplifier = amp_saved; /* restore the status */ 3627 3628 pci_disable_device(pci); 3629 pci_save_state(pci); 3630 pci_set_power_state(pci, pci_choose_state(pci, state)); 3631 return 0; 3632 } 3633 3634 int snd_cs46xx_resume(struct pci_dev *pci) 3635 { 3636 struct snd_card *card = pci_get_drvdata(pci); 3637 struct snd_cs46xx *chip = card->private_data; 3638 int amp_saved; 3639 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3640 int i; 3641 #endif 3642 unsigned int tmp; 3643 3644 pci_set_power_state(pci, PCI_D0); 3645 pci_restore_state(pci); 3646 if (pci_enable_device(pci) < 0) { 3647 printk(KERN_ERR "cs46xx: pci_enable_device failed, " 3648 "disabling device\n"); 3649 snd_card_disconnect(card); 3650 return -EIO; 3651 } 3652 pci_set_master(pci); 3653 3654 amp_saved = chip->amplifier; 3655 chip->amplifier = 0; 3656 chip->active_ctrl(chip, 1); /* force to on */ 3657 3658 snd_cs46xx_chip_init(chip); 3659 3660 snd_cs46xx_reset(chip); 3661 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3662 cs46xx_dsp_resume(chip); 3663 /* restore some registers */ 3664 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3665 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]); 3666 #else 3667 snd_cs46xx_download_image(chip); 3668 #endif 3669 3670 #if 0 3671 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, 3672 chip->ac97_general_purpose); 3673 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL, 3674 chip->ac97_powerdown); 3675 mdelay(10); 3676 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN, 3677 chip->ac97_powerdown); 3678 mdelay(5); 3679 #endif 3680 3681 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3682 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3683 3684 /* 3685 * Stop capture DMA. 3686 */ 3687 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3688 chip->capt.ctl = tmp & 0x0000ffff; 3689 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3690 3691 mdelay(5); 3692 3693 /* reset playback/capture */ 3694 snd_cs46xx_set_play_sample_rate(chip, 8000); 3695 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3696 snd_cs46xx_proc_start(chip); 3697 3698 cs46xx_enable_stream_irqs(chip); 3699 3700 if (amp_saved) 3701 chip->amplifier_ctrl(chip, 1); /* turn amp on */ 3702 else 3703 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3704 chip->amplifier = amp_saved; 3705 chip->in_suspend = 0; 3706 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3707 return 0; 3708 } 3709 #endif /* CONFIG_PM */ 3710 3711 3712 /* 3713 */ 3714 3715 int __devinit snd_cs46xx_create(struct snd_card *card, 3716 struct pci_dev * pci, 3717 int external_amp, int thinkpad, 3718 struct snd_cs46xx ** rchip) 3719 { 3720 struct snd_cs46xx *chip; 3721 int err, idx; 3722 struct snd_cs46xx_region *region; 3723 struct cs_card_type *cp; 3724 u16 ss_card, ss_vendor; 3725 static struct snd_device_ops ops = { 3726 .dev_free = snd_cs46xx_dev_free, 3727 }; 3728 3729 *rchip = NULL; 3730 3731 /* enable PCI device */ 3732 if ((err = pci_enable_device(pci)) < 0) 3733 return err; 3734 3735 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3736 if (chip == NULL) { 3737 pci_disable_device(pci); 3738 return -ENOMEM; 3739 } 3740 spin_lock_init(&chip->reg_lock); 3741 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3742 mutex_init(&chip->spos_mutex); 3743 #endif 3744 chip->card = card; 3745 chip->pci = pci; 3746 chip->irq = -1; 3747 chip->ba0_addr = pci_resource_start(pci, 0); 3748 chip->ba1_addr = pci_resource_start(pci, 1); 3749 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 || 3750 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) { 3751 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", 3752 chip->ba0_addr, chip->ba1_addr); 3753 snd_cs46xx_free(chip); 3754 return -ENOMEM; 3755 } 3756 3757 region = &chip->region.name.ba0; 3758 strcpy(region->name, "CS46xx_BA0"); 3759 region->base = chip->ba0_addr; 3760 region->size = CS46XX_BA0_SIZE; 3761 3762 region = &chip->region.name.data0; 3763 strcpy(region->name, "CS46xx_BA1_data0"); 3764 region->base = chip->ba1_addr + BA1_SP_DMEM0; 3765 region->size = CS46XX_BA1_DATA0_SIZE; 3766 3767 region = &chip->region.name.data1; 3768 strcpy(region->name, "CS46xx_BA1_data1"); 3769 region->base = chip->ba1_addr + BA1_SP_DMEM1; 3770 region->size = CS46XX_BA1_DATA1_SIZE; 3771 3772 region = &chip->region.name.pmem; 3773 strcpy(region->name, "CS46xx_BA1_pmem"); 3774 region->base = chip->ba1_addr + BA1_SP_PMEM; 3775 region->size = CS46XX_BA1_PRG_SIZE; 3776 3777 region = &chip->region.name.reg; 3778 strcpy(region->name, "CS46xx_BA1_reg"); 3779 region->base = chip->ba1_addr + BA1_SP_REG; 3780 region->size = CS46XX_BA1_REG_SIZE; 3781 3782 /* set up amp and clkrun hack */ 3783 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor); 3784 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card); 3785 3786 for (cp = &cards[0]; cp->name; cp++) { 3787 if (cp->vendor == ss_vendor && cp->id == ss_card) { 3788 snd_printdd ("hack for %s enabled\n", cp->name); 3789 3790 chip->amplifier_ctrl = cp->amp; 3791 chip->active_ctrl = cp->active; 3792 chip->mixer_init = cp->mixer_init; 3793 3794 if (cp->init) 3795 cp->init(chip); 3796 break; 3797 } 3798 } 3799 3800 if (external_amp) { 3801 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n"); 3802 chip->amplifier_ctrl = amp_voyetra; 3803 } 3804 3805 if (thinkpad) { 3806 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n"); 3807 chip->active_ctrl = clkrun_hack; 3808 clkrun_init(chip); 3809 } 3810 3811 if (chip->amplifier_ctrl == NULL) 3812 chip->amplifier_ctrl = amp_none; 3813 if (chip->active_ctrl == NULL) 3814 chip->active_ctrl = amp_none; 3815 3816 chip->active_ctrl(chip, 1); /* enable CLKRUN */ 3817 3818 pci_set_master(pci); 3819 3820 for (idx = 0; idx < 5; idx++) { 3821 region = &chip->region.idx[idx]; 3822 if ((region->resource = request_mem_region(region->base, region->size, 3823 region->name)) == NULL) { 3824 snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n", 3825 region->base, region->base + region->size - 1); 3826 snd_cs46xx_free(chip); 3827 return -EBUSY; 3828 } 3829 region->remap_addr = ioremap_nocache(region->base, region->size); 3830 if (region->remap_addr == NULL) { 3831 snd_printk(KERN_ERR "%s ioremap problem\n", region->name); 3832 snd_cs46xx_free(chip); 3833 return -ENOMEM; 3834 } 3835 } 3836 3837 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED, 3838 KBUILD_MODNAME, chip)) { 3839 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 3840 snd_cs46xx_free(chip); 3841 return -EBUSY; 3842 } 3843 chip->irq = pci->irq; 3844 3845 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3846 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip); 3847 if (chip->dsp_spos_instance == NULL) { 3848 snd_cs46xx_free(chip); 3849 return -ENOMEM; 3850 } 3851 #endif 3852 3853 err = snd_cs46xx_chip_init(chip); 3854 if (err < 0) { 3855 snd_cs46xx_free(chip); 3856 return err; 3857 } 3858 3859 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 3860 snd_cs46xx_free(chip); 3861 return err; 3862 } 3863 3864 snd_cs46xx_proc_init(card, chip); 3865 3866 #ifdef CONFIG_PM 3867 chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) * 3868 ARRAY_SIZE(saved_regs), GFP_KERNEL); 3869 if (!chip->saved_regs) { 3870 snd_cs46xx_free(chip); 3871 return -ENOMEM; 3872 } 3873 #endif 3874 3875 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3876 3877 snd_card_set_dev(card, &pci->dev); 3878 3879 *rchip = chip; 3880 return 0; 3881 } 3882