1 /* 2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 3 * Abramo Bagnara <abramo@alsa-project.org> 4 * Cirrus Logic, Inc. 5 * Routines for control of Cirrus Logic CS461x chips 6 * 7 * KNOWN BUGS: 8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized 9 * and the SPDIF get somewhat "distorcionated", or/and left right channel 10 * are swapped. To get around this problem when it happens, mute and unmute 11 * the SPDIF input mixer control. 12 * - On the Hercules Game Theater XP the amplifier are sometimes turned 13 * off on inadecuate moments which causes distorcions on sound. 14 * 15 * TODO: 16 * - Secondary CODEC on some soundcards 17 * - SPDIF input support for other sample rates then 48khz 18 * - Posibility to mix the SPDIF output with analog sources. 19 * - PCM channels for Center and LFE on secondary codec 20 * 21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which 22 * is default configuration), no SPDIF, no secondary codec, no 23 * multi channel PCM. But known to work. 24 * 25 * FINALLY: A credit to the developers Tom and Jordan 26 * at Cirrus for have helping me out with the DSP, however we 27 * still don't have sufficient documentation and technical 28 * references to be able to implement all fancy feutures 29 * supported by the cs46xx DSP's. 30 * Benny <benny@hostmobility.com> 31 * 32 * This program is free software; you can redistribute it and/or modify 33 * it under the terms of the GNU General Public License as published by 34 * the Free Software Foundation; either version 2 of the License, or 35 * (at your option) any later version. 36 * 37 * This program is distributed in the hope that it will be useful, 38 * but WITHOUT ANY WARRANTY; without even the implied warranty of 39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 40 * GNU General Public License for more details. 41 * 42 * You should have received a copy of the GNU General Public License 43 * along with this program; if not, write to the Free Software 44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 45 * 46 */ 47 48 #include <linux/delay.h> 49 #include <linux/pci.h> 50 #include <linux/pm.h> 51 #include <linux/init.h> 52 #include <linux/interrupt.h> 53 #include <linux/slab.h> 54 #include <linux/gameport.h> 55 #include <linux/mutex.h> 56 #include <linux/export.h> 57 58 59 #include <sound/core.h> 60 #include <sound/control.h> 61 #include <sound/info.h> 62 #include <sound/pcm.h> 63 #include <sound/pcm_params.h> 64 #include "cs46xx.h" 65 66 #include <asm/io.h> 67 68 #include "cs46xx_lib.h" 69 #include "dsp_spos.h" 70 71 static void amp_voyetra(struct snd_cs46xx *chip, int change); 72 73 #ifdef CONFIG_SND_CS46XX_NEW_DSP 74 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops; 75 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; 76 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; 77 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; 78 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; 79 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; 80 #endif 81 82 static struct snd_pcm_ops snd_cs46xx_playback_ops; 83 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; 84 static struct snd_pcm_ops snd_cs46xx_capture_ops; 85 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; 86 87 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, 88 unsigned short reg, 89 int codec_index) 90 { 91 int count; 92 unsigned short result,tmp; 93 u32 offset = 0; 94 95 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 96 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 97 return 0xffff; 98 99 chip->active_ctrl(chip, 1); 100 101 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX) 102 offset = CS46XX_SECONDARY_CODEC_OFFSET; 103 104 /* 105 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 106 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 107 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55 108 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 109 * 5. if DCV not cleared, break and return error 110 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 111 */ 112 113 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 114 115 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL); 116 if ((tmp & ACCTL_VFRM) == 0) { 117 snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp); 118 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM ); 119 msleep(50); 120 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset); 121 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM ); 122 123 } 124 125 /* 126 * Setup the AC97 control registers on the CS461x to send the 127 * appropriate command to the AC97 to perform the read. 128 * ACCAD = Command Address Register = 46Ch 129 * ACCDA = Command Data Register = 470h 130 * ACCTL = Control Register = 460h 131 * set DCV - will clear when process completed 132 * set CRW - Read command 133 * set VFRM - valid frame enabled 134 * set ESYN - ASYNC generation enabled 135 * set RSTN - ARST# inactive, AC97 codec not reset 136 */ 137 138 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg); 139 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0); 140 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 141 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW | 142 ACCTL_VFRM | ACCTL_ESYN | 143 ACCTL_RSTN); 144 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | 145 ACCTL_VFRM | ACCTL_ESYN | 146 ACCTL_RSTN); 147 } else { 148 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 149 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | 150 ACCTL_RSTN); 151 } 152 153 /* 154 * Wait for the read to occur. 155 */ 156 for (count = 0; count < 1000; count++) { 157 /* 158 * First, we want to wait for a short time. 159 */ 160 udelay(10); 161 /* 162 * Now, check to see if the read has completed. 163 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 164 */ 165 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) 166 goto ok1; 167 } 168 169 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 170 result = 0xffff; 171 goto end; 172 173 ok1: 174 /* 175 * Wait for the valid status bit to go active. 176 */ 177 for (count = 0; count < 100; count++) { 178 /* 179 * Read the AC97 status register. 180 * ACSTS = Status Register = 464h 181 * VSTS - Valid Status 182 */ 183 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS) 184 goto ok2; 185 udelay(10); 186 } 187 188 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg); 189 result = 0xffff; 190 goto end; 191 192 ok2: 193 /* 194 * Read the data returned from the AC97 register. 195 * ACSDA = Status Data Register = 474h 196 */ 197 #if 0 198 printk(KERN_DEBUG "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg, 199 snd_cs46xx_peekBA0(chip, BA0_ACSDA), 200 snd_cs46xx_peekBA0(chip, BA0_ACCAD)); 201 #endif 202 203 //snd_cs46xx_peekBA0(chip, BA0_ACCAD); 204 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 205 end: 206 chip->active_ctrl(chip, -1); 207 return result; 208 } 209 210 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97, 211 unsigned short reg) 212 { 213 struct snd_cs46xx *chip = ac97->private_data; 214 unsigned short val; 215 int codec_index = ac97->num; 216 217 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 218 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 219 return 0xffff; 220 221 val = snd_cs46xx_codec_read(chip, reg, codec_index); 222 223 return val; 224 } 225 226 227 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip, 228 unsigned short reg, 229 unsigned short val, 230 int codec_index) 231 { 232 int count; 233 234 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 235 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 236 return; 237 238 chip->active_ctrl(chip, 1); 239 240 /* 241 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 242 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 243 * 3. Write ACCTL = Control Register = 460h for initiating the write 244 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 245 * 5. if DCV not cleared, break and return error 246 */ 247 248 /* 249 * Setup the AC97 control registers on the CS461x to send the 250 * appropriate command to the AC97 to perform the read. 251 * ACCAD = Command Address Register = 46Ch 252 * ACCDA = Command Data Register = 470h 253 * ACCTL = Control Register = 460h 254 * set DCV - will clear when process completed 255 * reset CRW - Write command 256 * set VFRM - valid frame enabled 257 * set ESYN - ASYNC generation enabled 258 * set RSTN - ARST# inactive, AC97 codec not reset 259 */ 260 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg); 261 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val); 262 snd_cs46xx_peekBA0(chip, BA0_ACCTL); 263 264 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 265 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM | 266 ACCTL_ESYN | ACCTL_RSTN); 267 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | 268 ACCTL_ESYN | ACCTL_RSTN); 269 } else { 270 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 271 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 272 } 273 274 for (count = 0; count < 4000; count++) { 275 /* 276 * First, we want to wait for a short time. 277 */ 278 udelay(10); 279 /* 280 * Now, check to see if the write has completed. 281 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 282 */ 283 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) { 284 goto end; 285 } 286 } 287 snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val); 288 end: 289 chip->active_ctrl(chip, -1); 290 } 291 292 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97, 293 unsigned short reg, 294 unsigned short val) 295 { 296 struct snd_cs46xx *chip = ac97->private_data; 297 int codec_index = ac97->num; 298 299 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 300 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 301 return; 302 303 snd_cs46xx_codec_write(chip, reg, val, codec_index); 304 } 305 306 307 /* 308 * Chip initialization 309 */ 310 311 int snd_cs46xx_download(struct snd_cs46xx *chip, 312 u32 *src, 313 unsigned long offset, 314 unsigned long len) 315 { 316 void __iomem *dst; 317 unsigned int bank = offset >> 16; 318 offset = offset & 0xffff; 319 320 if (snd_BUG_ON((offset & 3) || (len & 3))) 321 return -EINVAL; 322 dst = chip->region.idx[bank+1].remap_addr + offset; 323 len /= sizeof(u32); 324 325 /* writel already converts 32-bit value to right endianess */ 326 while (len-- > 0) { 327 writel(*src++, dst); 328 dst += sizeof(u32); 329 } 330 return 0; 331 } 332 333 #ifdef CONFIG_SND_CS46XX_NEW_DSP 334 335 #include "imgs/cwc4630.h" 336 #include "imgs/cwcasync.h" 337 #include "imgs/cwcsnoop.h" 338 #include "imgs/cwcbinhack.h" 339 #include "imgs/cwcdma.h" 340 341 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, 342 unsigned long offset, 343 unsigned long len) 344 { 345 void __iomem *dst; 346 unsigned int bank = offset >> 16; 347 offset = offset & 0xffff; 348 349 if (snd_BUG_ON((offset & 3) || (len & 3))) 350 return -EINVAL; 351 dst = chip->region.idx[bank+1].remap_addr + offset; 352 len /= sizeof(u32); 353 354 /* writel already converts 32-bit value to right endianess */ 355 while (len-- > 0) { 356 writel(0, dst); 357 dst += sizeof(u32); 358 } 359 return 0; 360 } 361 362 #else /* old DSP image */ 363 364 #include "cs46xx_image.h" 365 366 int snd_cs46xx_download_image(struct snd_cs46xx *chip) 367 { 368 int idx, err; 369 unsigned long offset = 0; 370 371 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) { 372 if ((err = snd_cs46xx_download(chip, 373 &BA1Struct.map[offset], 374 BA1Struct.memory[idx].offset, 375 BA1Struct.memory[idx].size)) < 0) 376 return err; 377 offset += BA1Struct.memory[idx].size >> 2; 378 } 379 return 0; 380 } 381 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 382 383 /* 384 * Chip reset 385 */ 386 387 static void snd_cs46xx_reset(struct snd_cs46xx *chip) 388 { 389 int idx; 390 391 /* 392 * Write the reset bit of the SP control register. 393 */ 394 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP); 395 396 /* 397 * Write the control register. 398 */ 399 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN); 400 401 /* 402 * Clear the trap registers. 403 */ 404 for (idx = 0; idx < 8; idx++) { 405 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx); 406 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF); 407 } 408 snd_cs46xx_poke(chip, BA1_DREG, 0); 409 410 /* 411 * Set the frame timer to reflect the number of cycles per frame. 412 */ 413 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 414 } 415 416 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout) 417 { 418 u32 i, status = 0; 419 /* 420 * Make sure the previous FIFO write operation has completed. 421 */ 422 for(i = 0; i < 50; i++){ 423 status = snd_cs46xx_peekBA0(chip, BA0_SERBST); 424 425 if( !(status & SERBST_WBSY) ) 426 break; 427 428 mdelay(retry_timeout); 429 } 430 431 if(status & SERBST_WBSY) { 432 snd_printk(KERN_ERR "cs46xx: failure waiting for " 433 "FIFO command to complete\n"); 434 return -EINVAL; 435 } 436 437 return 0; 438 } 439 440 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip) 441 { 442 int idx, powerdown = 0; 443 unsigned int tmp; 444 445 /* 446 * See if the devices are powered down. If so, we must power them up first 447 * or they will not respond. 448 */ 449 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 450 if (!(tmp & CLKCR1_SWCE)) { 451 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 452 powerdown = 1; 453 } 454 455 /* 456 * We want to clear out the serial port FIFOs so we don't end up playing 457 * whatever random garbage happens to be in them. We fill the sample FIFOS 458 * with zero (silence). 459 */ 460 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0); 461 462 /* 463 * Fill all 256 sample FIFO locations. 464 */ 465 for (idx = 0; idx < 0xFF; idx++) { 466 /* 467 * Make sure the previous FIFO write operation has completed. 468 */ 469 if (cs46xx_wait_for_fifo(chip,1)) { 470 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx); 471 472 if (powerdown) 473 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 474 475 break; 476 } 477 /* 478 * Write the serial port FIFO index. 479 */ 480 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 481 /* 482 * Tell the serial port to load the new value into the FIFO location. 483 */ 484 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 485 } 486 /* 487 * Now, if we powered up the devices, then power them back down again. 488 * This is kinda ugly, but should never happen. 489 */ 490 if (powerdown) 491 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 492 } 493 494 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip) 495 { 496 int cnt; 497 498 /* 499 * Set the frame timer to reflect the number of cycles per frame. 500 */ 501 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 502 /* 503 * Turn on the run, run at frame, and DMA enable bits in the local copy of 504 * the SP control register. 505 */ 506 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 507 /* 508 * Wait until the run at frame bit resets itself in the SP control 509 * register. 510 */ 511 for (cnt = 0; cnt < 25; cnt++) { 512 udelay(50); 513 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)) 514 break; 515 } 516 517 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR) 518 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n"); 519 } 520 521 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip) 522 { 523 /* 524 * Turn off the run, run at frame, and DMA enable bits in the local copy of 525 * the SP control register. 526 */ 527 snd_cs46xx_poke(chip, BA1_SPCR, 0); 528 } 529 530 /* 531 * Sample rate routines 532 */ 533 534 #define GOF_PER_SEC 200 535 536 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 537 { 538 unsigned long flags; 539 unsigned int tmp1, tmp2; 540 unsigned int phiIncr; 541 unsigned int correctionPerGOF, correctionPerSec; 542 543 /* 544 * Compute the values used to drive the actual sample rate conversion. 545 * The following formulas are being computed, using inline assembly 546 * since we need to use 64 bit arithmetic to compute the values: 547 * 548 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 549 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 550 * GOF_PER_SEC) 551 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M 552 * GOF_PER_SEC * correctionPerGOF 553 * 554 * i.e. 555 * 556 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out) 557 * correctionPerGOF:correctionPerSec = 558 * dividend:remainder(ulOther / GOF_PER_SEC) 559 */ 560 tmp1 = rate << 16; 561 phiIncr = tmp1 / 48000; 562 tmp1 -= phiIncr * 48000; 563 tmp1 <<= 10; 564 phiIncr <<= 10; 565 tmp2 = tmp1 / 48000; 566 phiIncr += tmp2; 567 tmp1 -= tmp2 * 48000; 568 correctionPerGOF = tmp1 / GOF_PER_SEC; 569 tmp1 -= correctionPerGOF * GOF_PER_SEC; 570 correctionPerSec = tmp1; 571 572 /* 573 * Fill in the SampleRateConverter control block. 574 */ 575 spin_lock_irqsave(&chip->reg_lock, flags); 576 snd_cs46xx_poke(chip, BA1_PSRC, 577 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 578 snd_cs46xx_poke(chip, BA1_PPI, phiIncr); 579 spin_unlock_irqrestore(&chip->reg_lock, flags); 580 } 581 582 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 583 { 584 unsigned long flags; 585 unsigned int phiIncr, coeffIncr, tmp1, tmp2; 586 unsigned int correctionPerGOF, correctionPerSec, initialDelay; 587 unsigned int frameGroupLength, cnt; 588 589 /* 590 * We can only decimate by up to a factor of 1/9th the hardware rate. 591 * Correct the value if an attempt is made to stray outside that limit. 592 */ 593 if ((rate * 9) < 48000) 594 rate = 48000 / 9; 595 596 /* 597 * We can not capture at at rate greater than the Input Rate (48000). 598 * Return an error if an attempt is made to stray outside that limit. 599 */ 600 if (rate > 48000) 601 rate = 48000; 602 603 /* 604 * Compute the values used to drive the actual sample rate conversion. 605 * The following formulas are being computed, using inline assembly 606 * since we need to use 64 bit arithmetic to compute the values: 607 * 608 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in) 609 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 610 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 611 * GOF_PER_SEC) 612 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr - 613 * GOF_PER_SEC * correctionPerGOF 614 * initialDelay = ceil((24 * Fs,in) / Fs,out) 615 * 616 * i.e. 617 * 618 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in)) 619 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out) 620 * correctionPerGOF:correctionPerSec = 621 * dividend:remainder(ulOther / GOF_PER_SEC) 622 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out) 623 */ 624 625 tmp1 = rate << 16; 626 coeffIncr = tmp1 / 48000; 627 tmp1 -= coeffIncr * 48000; 628 tmp1 <<= 7; 629 coeffIncr <<= 7; 630 coeffIncr += tmp1 / 48000; 631 coeffIncr ^= 0xFFFFFFFF; 632 coeffIncr++; 633 tmp1 = 48000 << 16; 634 phiIncr = tmp1 / rate; 635 tmp1 -= phiIncr * rate; 636 tmp1 <<= 10; 637 phiIncr <<= 10; 638 tmp2 = tmp1 / rate; 639 phiIncr += tmp2; 640 tmp1 -= tmp2 * rate; 641 correctionPerGOF = tmp1 / GOF_PER_SEC; 642 tmp1 -= correctionPerGOF * GOF_PER_SEC; 643 correctionPerSec = tmp1; 644 initialDelay = ((48000 * 24) + rate - 1) / rate; 645 646 /* 647 * Fill in the VariDecimate control block. 648 */ 649 spin_lock_irqsave(&chip->reg_lock, flags); 650 snd_cs46xx_poke(chip, BA1_CSRC, 651 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 652 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr); 653 snd_cs46xx_poke(chip, BA1_CD, 654 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80); 655 snd_cs46xx_poke(chip, BA1_CPI, phiIncr); 656 spin_unlock_irqrestore(&chip->reg_lock, flags); 657 658 /* 659 * Figure out the frame group length for the write back task. Basically, 660 * this is just the factors of 24000 (2^6*3*5^3) that are not present in 661 * the output sample rate. 662 */ 663 frameGroupLength = 1; 664 for (cnt = 2; cnt <= 64; cnt *= 2) { 665 if (((rate / cnt) * cnt) != rate) 666 frameGroupLength *= 2; 667 } 668 if (((rate / 3) * 3) != rate) { 669 frameGroupLength *= 3; 670 } 671 for (cnt = 5; cnt <= 125; cnt *= 5) { 672 if (((rate / cnt) * cnt) != rate) 673 frameGroupLength *= 5; 674 } 675 676 /* 677 * Fill in the WriteBack control block. 678 */ 679 spin_lock_irqsave(&chip->reg_lock, flags); 680 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength); 681 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength)); 682 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF); 683 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000)); 684 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF); 685 spin_unlock_irqrestore(&chip->reg_lock, flags); 686 } 687 688 /* 689 * PCM part 690 */ 691 692 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream, 693 struct snd_pcm_indirect *rec, size_t bytes) 694 { 695 struct snd_pcm_runtime *runtime = substream->runtime; 696 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 697 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes); 698 } 699 700 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream) 701 { 702 struct snd_pcm_runtime *runtime = substream->runtime; 703 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 704 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy); 705 return 0; 706 } 707 708 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream, 709 struct snd_pcm_indirect *rec, size_t bytes) 710 { 711 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 712 struct snd_pcm_runtime *runtime = substream->runtime; 713 memcpy(runtime->dma_area + rec->sw_data, 714 chip->capt.hw_buf.area + rec->hw_data, bytes); 715 } 716 717 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream) 718 { 719 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 720 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy); 721 return 0; 722 } 723 724 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream) 725 { 726 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 727 size_t ptr; 728 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 729 730 if (snd_BUG_ON(!cpcm->pcm_channel)) 731 return -ENXIO; 732 733 #ifdef CONFIG_SND_CS46XX_NEW_DSP 734 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 735 #else 736 ptr = snd_cs46xx_peek(chip, BA1_PBA); 737 #endif 738 ptr -= cpcm->hw_buf.addr; 739 return ptr >> cpcm->shift; 740 } 741 742 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream) 743 { 744 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 745 size_t ptr; 746 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 747 748 #ifdef CONFIG_SND_CS46XX_NEW_DSP 749 if (snd_BUG_ON(!cpcm->pcm_channel)) 750 return -ENXIO; 751 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 752 #else 753 ptr = snd_cs46xx_peek(chip, BA1_PBA); 754 #endif 755 ptr -= cpcm->hw_buf.addr; 756 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr); 757 } 758 759 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream) 760 { 761 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 762 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 763 return ptr >> chip->capt.shift; 764 } 765 766 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream) 767 { 768 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 769 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 770 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr); 771 } 772 773 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream, 774 int cmd) 775 { 776 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 777 /*struct snd_pcm_runtime *runtime = substream->runtime;*/ 778 int result = 0; 779 780 #ifdef CONFIG_SND_CS46XX_NEW_DSP 781 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 782 if (! cpcm->pcm_channel) { 783 return -ENXIO; 784 } 785 #endif 786 switch (cmd) { 787 case SNDRV_PCM_TRIGGER_START: 788 case SNDRV_PCM_TRIGGER_RESUME: 789 #ifdef CONFIG_SND_CS46XX_NEW_DSP 790 /* magic value to unmute PCM stream playback volume */ 791 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 792 SCBVolumeCtrl) << 2, 0x80008000); 793 794 if (cpcm->pcm_channel->unlinked) 795 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel); 796 797 if (substream->runtime->periods != CS46XX_FRAGS) 798 snd_cs46xx_playback_transfer(substream); 799 #else 800 spin_lock(&chip->reg_lock); 801 if (substream->runtime->periods != CS46XX_FRAGS) 802 snd_cs46xx_playback_transfer(substream); 803 { unsigned int tmp; 804 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 805 tmp &= 0x0000ffff; 806 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp); 807 } 808 spin_unlock(&chip->reg_lock); 809 #endif 810 break; 811 case SNDRV_PCM_TRIGGER_STOP: 812 case SNDRV_PCM_TRIGGER_SUSPEND: 813 #ifdef CONFIG_SND_CS46XX_NEW_DSP 814 /* magic mute channel */ 815 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 816 SCBVolumeCtrl) << 2, 0xffffffff); 817 818 if (!cpcm->pcm_channel->unlinked) 819 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel); 820 #else 821 spin_lock(&chip->reg_lock); 822 { unsigned int tmp; 823 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 824 tmp &= 0x0000ffff; 825 snd_cs46xx_poke(chip, BA1_PCTL, tmp); 826 } 827 spin_unlock(&chip->reg_lock); 828 #endif 829 break; 830 default: 831 result = -EINVAL; 832 break; 833 } 834 835 return result; 836 } 837 838 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream, 839 int cmd) 840 { 841 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 842 unsigned int tmp; 843 int result = 0; 844 845 spin_lock(&chip->reg_lock); 846 switch (cmd) { 847 case SNDRV_PCM_TRIGGER_START: 848 case SNDRV_PCM_TRIGGER_RESUME: 849 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 850 tmp &= 0xffff0000; 851 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp); 852 break; 853 case SNDRV_PCM_TRIGGER_STOP: 854 case SNDRV_PCM_TRIGGER_SUSPEND: 855 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 856 tmp &= 0xffff0000; 857 snd_cs46xx_poke(chip, BA1_CCTL, tmp); 858 break; 859 default: 860 result = -EINVAL; 861 break; 862 } 863 spin_unlock(&chip->reg_lock); 864 865 return result; 866 } 867 868 #ifdef CONFIG_SND_CS46XX_NEW_DSP 869 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm, 870 int sample_rate) 871 { 872 873 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */ 874 if ( cpcm->pcm_channel == NULL) { 875 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, 876 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id); 877 if (cpcm->pcm_channel == NULL) { 878 snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n"); 879 return -ENOMEM; 880 } 881 cpcm->pcm_channel->sample_rate = sample_rate; 882 } else 883 /* if sample rate is changed */ 884 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) { 885 int unlinked = cpcm->pcm_channel->unlinked; 886 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel); 887 888 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm, 889 cpcm->hw_buf.addr, 890 cpcm->pcm_channel_id)) == NULL) { 891 snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n"); 892 return -ENOMEM; 893 } 894 895 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel); 896 cpcm->pcm_channel->sample_rate = sample_rate; 897 } 898 899 return 0; 900 } 901 #endif 902 903 904 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream, 905 struct snd_pcm_hw_params *hw_params) 906 { 907 struct snd_pcm_runtime *runtime = substream->runtime; 908 struct snd_cs46xx_pcm *cpcm; 909 int err; 910 #ifdef CONFIG_SND_CS46XX_NEW_DSP 911 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 912 int sample_rate = params_rate(hw_params); 913 int period_size = params_period_bytes(hw_params); 914 #endif 915 cpcm = runtime->private_data; 916 917 #ifdef CONFIG_SND_CS46XX_NEW_DSP 918 if (snd_BUG_ON(!sample_rate)) 919 return -ENXIO; 920 921 mutex_lock(&chip->spos_mutex); 922 923 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) { 924 mutex_unlock(&chip->spos_mutex); 925 return -ENXIO; 926 } 927 928 snd_BUG_ON(!cpcm->pcm_channel); 929 if (!cpcm->pcm_channel) { 930 mutex_unlock(&chip->spos_mutex); 931 return -ENXIO; 932 } 933 934 935 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) { 936 mutex_unlock(&chip->spos_mutex); 937 return -EINVAL; 938 } 939 940 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n", 941 period_size, params_periods(hw_params), 942 params_buffer_bytes(hw_params)); 943 #endif 944 945 if (params_periods(hw_params) == CS46XX_FRAGS) { 946 if (runtime->dma_area != cpcm->hw_buf.area) 947 snd_pcm_lib_free_pages(substream); 948 runtime->dma_area = cpcm->hw_buf.area; 949 runtime->dma_addr = cpcm->hw_buf.addr; 950 runtime->dma_bytes = cpcm->hw_buf.bytes; 951 952 953 #ifdef CONFIG_SND_CS46XX_NEW_DSP 954 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 955 substream->ops = &snd_cs46xx_playback_ops; 956 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 957 substream->ops = &snd_cs46xx_playback_rear_ops; 958 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 959 substream->ops = &snd_cs46xx_playback_clfe_ops; 960 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 961 substream->ops = &snd_cs46xx_playback_iec958_ops; 962 } else { 963 snd_BUG(); 964 } 965 #else 966 substream->ops = &snd_cs46xx_playback_ops; 967 #endif 968 969 } else { 970 if (runtime->dma_area == cpcm->hw_buf.area) { 971 runtime->dma_area = NULL; 972 runtime->dma_addr = 0; 973 runtime->dma_bytes = 0; 974 } 975 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) { 976 #ifdef CONFIG_SND_CS46XX_NEW_DSP 977 mutex_unlock(&chip->spos_mutex); 978 #endif 979 return err; 980 } 981 982 #ifdef CONFIG_SND_CS46XX_NEW_DSP 983 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 984 substream->ops = &snd_cs46xx_playback_indirect_ops; 985 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 986 substream->ops = &snd_cs46xx_playback_indirect_rear_ops; 987 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 988 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops; 989 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 990 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops; 991 } else { 992 snd_BUG(); 993 } 994 #else 995 substream->ops = &snd_cs46xx_playback_indirect_ops; 996 #endif 997 998 } 999 1000 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1001 mutex_unlock(&chip->spos_mutex); 1002 #endif 1003 1004 return 0; 1005 } 1006 1007 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream) 1008 { 1009 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/ 1010 struct snd_pcm_runtime *runtime = substream->runtime; 1011 struct snd_cs46xx_pcm *cpcm; 1012 1013 cpcm = runtime->private_data; 1014 1015 /* if play_back open fails, then this function 1016 is called and cpcm can actually be NULL here */ 1017 if (!cpcm) return -ENXIO; 1018 1019 if (runtime->dma_area != cpcm->hw_buf.area) 1020 snd_pcm_lib_free_pages(substream); 1021 1022 runtime->dma_area = NULL; 1023 runtime->dma_addr = 0; 1024 runtime->dma_bytes = 0; 1025 1026 return 0; 1027 } 1028 1029 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream) 1030 { 1031 unsigned int tmp; 1032 unsigned int pfie; 1033 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1034 struct snd_pcm_runtime *runtime = substream->runtime; 1035 struct snd_cs46xx_pcm *cpcm; 1036 1037 cpcm = runtime->private_data; 1038 1039 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1040 if (snd_BUG_ON(!cpcm->pcm_channel)) 1041 return -ENXIO; 1042 1043 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 ); 1044 pfie &= ~0x0000f03f; 1045 #else 1046 /* old dsp */ 1047 pfie = snd_cs46xx_peek(chip, BA1_PFIE); 1048 pfie &= ~0x0000f03f; 1049 #endif 1050 1051 cpcm->shift = 2; 1052 /* if to convert from stereo to mono */ 1053 if (runtime->channels == 1) { 1054 cpcm->shift--; 1055 pfie |= 0x00002000; 1056 } 1057 /* if to convert from 8 bit to 16 bit */ 1058 if (snd_pcm_format_width(runtime->format) == 8) { 1059 cpcm->shift--; 1060 pfie |= 0x00001000; 1061 } 1062 /* if to convert to unsigned */ 1063 if (snd_pcm_format_unsigned(runtime->format)) 1064 pfie |= 0x00008000; 1065 1066 /* Never convert byte order when sample stream is 8 bit */ 1067 if (snd_pcm_format_width(runtime->format) != 8) { 1068 /* convert from big endian to little endian */ 1069 if (snd_pcm_format_big_endian(runtime->format)) 1070 pfie |= 0x00004000; 1071 } 1072 1073 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec)); 1074 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1075 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift; 1076 1077 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1078 1079 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2); 1080 tmp &= ~0x000003ff; 1081 tmp |= (4 << cpcm->shift) - 1; 1082 /* playback transaction count register */ 1083 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp); 1084 1085 /* playback format && interrupt enable */ 1086 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot); 1087 #else 1088 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr); 1089 tmp = snd_cs46xx_peek(chip, BA1_PDTC); 1090 tmp &= ~0x000003ff; 1091 tmp |= (4 << cpcm->shift) - 1; 1092 snd_cs46xx_poke(chip, BA1_PDTC, tmp); 1093 snd_cs46xx_poke(chip, BA1_PFIE, pfie); 1094 snd_cs46xx_set_play_sample_rate(chip, runtime->rate); 1095 #endif 1096 1097 return 0; 1098 } 1099 1100 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream, 1101 struct snd_pcm_hw_params *hw_params) 1102 { 1103 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1104 struct snd_pcm_runtime *runtime = substream->runtime; 1105 int err; 1106 1107 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1108 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params)); 1109 #endif 1110 if (runtime->periods == CS46XX_FRAGS) { 1111 if (runtime->dma_area != chip->capt.hw_buf.area) 1112 snd_pcm_lib_free_pages(substream); 1113 runtime->dma_area = chip->capt.hw_buf.area; 1114 runtime->dma_addr = chip->capt.hw_buf.addr; 1115 runtime->dma_bytes = chip->capt.hw_buf.bytes; 1116 substream->ops = &snd_cs46xx_capture_ops; 1117 } else { 1118 if (runtime->dma_area == chip->capt.hw_buf.area) { 1119 runtime->dma_area = NULL; 1120 runtime->dma_addr = 0; 1121 runtime->dma_bytes = 0; 1122 } 1123 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) 1124 return err; 1125 substream->ops = &snd_cs46xx_capture_indirect_ops; 1126 } 1127 1128 return 0; 1129 } 1130 1131 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream) 1132 { 1133 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1134 struct snd_pcm_runtime *runtime = substream->runtime; 1135 1136 if (runtime->dma_area != chip->capt.hw_buf.area) 1137 snd_pcm_lib_free_pages(substream); 1138 runtime->dma_area = NULL; 1139 runtime->dma_addr = 0; 1140 runtime->dma_bytes = 0; 1141 1142 return 0; 1143 } 1144 1145 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream) 1146 { 1147 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1148 struct snd_pcm_runtime *runtime = substream->runtime; 1149 1150 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr); 1151 chip->capt.shift = 2; 1152 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec)); 1153 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1154 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2; 1155 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate); 1156 1157 return 0; 1158 } 1159 1160 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id) 1161 { 1162 struct snd_cs46xx *chip = dev_id; 1163 u32 status1; 1164 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1165 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1166 u32 status2; 1167 int i; 1168 struct snd_cs46xx_pcm *cpcm = NULL; 1169 #endif 1170 1171 /* 1172 * Read the Interrupt Status Register to clear the interrupt 1173 */ 1174 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR); 1175 if ((status1 & 0x7fffffff) == 0) { 1176 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1177 return IRQ_NONE; 1178 } 1179 1180 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1181 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0); 1182 1183 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) { 1184 if (i <= 15) { 1185 if ( status1 & (1 << i) ) { 1186 if (i == CS46XX_DSP_CAPTURE_CHANNEL) { 1187 if (chip->capt.substream) 1188 snd_pcm_period_elapsed(chip->capt.substream); 1189 } else { 1190 if (ins->pcm_channels[i].active && 1191 ins->pcm_channels[i].private_data && 1192 !ins->pcm_channels[i].unlinked) { 1193 cpcm = ins->pcm_channels[i].private_data; 1194 snd_pcm_period_elapsed(cpcm->substream); 1195 } 1196 } 1197 } 1198 } else { 1199 if ( status2 & (1 << (i - 16))) { 1200 if (ins->pcm_channels[i].active && 1201 ins->pcm_channels[i].private_data && 1202 !ins->pcm_channels[i].unlinked) { 1203 cpcm = ins->pcm_channels[i].private_data; 1204 snd_pcm_period_elapsed(cpcm->substream); 1205 } 1206 } 1207 } 1208 } 1209 1210 #else 1211 /* old dsp */ 1212 if ((status1 & HISR_VC0) && chip->playback_pcm) { 1213 if (chip->playback_pcm->substream) 1214 snd_pcm_period_elapsed(chip->playback_pcm->substream); 1215 } 1216 if ((status1 & HISR_VC1) && chip->pcm) { 1217 if (chip->capt.substream) 1218 snd_pcm_period_elapsed(chip->capt.substream); 1219 } 1220 #endif 1221 1222 if ((status1 & HISR_MIDI) && chip->rmidi) { 1223 unsigned char c; 1224 1225 spin_lock(&chip->reg_lock); 1226 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) { 1227 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP); 1228 if ((chip->midcr & MIDCR_RIE) == 0) 1229 continue; 1230 snd_rawmidi_receive(chip->midi_input, &c, 1); 1231 } 1232 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 1233 if ((chip->midcr & MIDCR_TIE) == 0) 1234 break; 1235 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1236 chip->midcr &= ~MIDCR_TIE; 1237 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1238 break; 1239 } 1240 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c); 1241 } 1242 spin_unlock(&chip->reg_lock); 1243 } 1244 /* 1245 * EOI to the PCI part....reenables interrupts 1246 */ 1247 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1248 1249 return IRQ_HANDLED; 1250 } 1251 1252 static struct snd_pcm_hardware snd_cs46xx_playback = 1253 { 1254 .info = (SNDRV_PCM_INFO_MMAP | 1255 SNDRV_PCM_INFO_INTERLEAVED | 1256 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1257 /*SNDRV_PCM_INFO_RESUME*/), 1258 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | 1259 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 1260 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE), 1261 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1262 .rate_min = 5500, 1263 .rate_max = 48000, 1264 .channels_min = 1, 1265 .channels_max = 2, 1266 .buffer_bytes_max = (256 * 1024), 1267 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1268 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1269 .periods_min = CS46XX_FRAGS, 1270 .periods_max = 1024, 1271 .fifo_size = 0, 1272 }; 1273 1274 static struct snd_pcm_hardware snd_cs46xx_capture = 1275 { 1276 .info = (SNDRV_PCM_INFO_MMAP | 1277 SNDRV_PCM_INFO_INTERLEAVED | 1278 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1279 /*SNDRV_PCM_INFO_RESUME*/), 1280 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1281 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1282 .rate_min = 5500, 1283 .rate_max = 48000, 1284 .channels_min = 2, 1285 .channels_max = 2, 1286 .buffer_bytes_max = (256 * 1024), 1287 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1288 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1289 .periods_min = CS46XX_FRAGS, 1290 .periods_max = 1024, 1291 .fifo_size = 0, 1292 }; 1293 1294 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1295 1296 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 }; 1297 1298 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = { 1299 .count = ARRAY_SIZE(period_sizes), 1300 .list = period_sizes, 1301 .mask = 0 1302 }; 1303 1304 #endif 1305 1306 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime) 1307 { 1308 kfree(runtime->private_data); 1309 } 1310 1311 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id) 1312 { 1313 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1314 struct snd_cs46xx_pcm * cpcm; 1315 struct snd_pcm_runtime *runtime = substream->runtime; 1316 1317 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL); 1318 if (cpcm == NULL) 1319 return -ENOMEM; 1320 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1321 PAGE_SIZE, &cpcm->hw_buf) < 0) { 1322 kfree(cpcm); 1323 return -ENOMEM; 1324 } 1325 1326 runtime->hw = snd_cs46xx_playback; 1327 runtime->private_data = cpcm; 1328 runtime->private_free = snd_cs46xx_pcm_free_substream; 1329 1330 cpcm->substream = substream; 1331 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1332 mutex_lock(&chip->spos_mutex); 1333 cpcm->pcm_channel = NULL; 1334 cpcm->pcm_channel_id = pcm_channel_id; 1335 1336 1337 snd_pcm_hw_constraint_list(runtime, 0, 1338 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1339 &hw_constraints_period_sizes); 1340 1341 mutex_unlock(&chip->spos_mutex); 1342 #else 1343 chip->playback_pcm = cpcm; /* HACK */ 1344 #endif 1345 1346 if (chip->accept_valid) 1347 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1348 chip->active_ctrl(chip, 1); 1349 1350 return 0; 1351 } 1352 1353 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream) 1354 { 1355 snd_printdd("open front channel\n"); 1356 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL); 1357 } 1358 1359 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1360 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream) 1361 { 1362 snd_printdd("open rear channel\n"); 1363 1364 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL); 1365 } 1366 1367 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream) 1368 { 1369 snd_printdd("open center - LFE channel\n"); 1370 1371 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL); 1372 } 1373 1374 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream) 1375 { 1376 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1377 1378 snd_printdd("open raw iec958 channel\n"); 1379 1380 mutex_lock(&chip->spos_mutex); 1381 cs46xx_iec958_pre_open (chip); 1382 mutex_unlock(&chip->spos_mutex); 1383 1384 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL); 1385 } 1386 1387 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream); 1388 1389 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream) 1390 { 1391 int err; 1392 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1393 1394 snd_printdd("close raw iec958 channel\n"); 1395 1396 err = snd_cs46xx_playback_close(substream); 1397 1398 mutex_lock(&chip->spos_mutex); 1399 cs46xx_iec958_post_close (chip); 1400 mutex_unlock(&chip->spos_mutex); 1401 1402 return err; 1403 } 1404 #endif 1405 1406 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream) 1407 { 1408 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1409 1410 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1411 PAGE_SIZE, &chip->capt.hw_buf) < 0) 1412 return -ENOMEM; 1413 chip->capt.substream = substream; 1414 substream->runtime->hw = snd_cs46xx_capture; 1415 1416 if (chip->accept_valid) 1417 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1418 1419 chip->active_ctrl(chip, 1); 1420 1421 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1422 snd_pcm_hw_constraint_list(substream->runtime, 0, 1423 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1424 &hw_constraints_period_sizes); 1425 #endif 1426 return 0; 1427 } 1428 1429 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream) 1430 { 1431 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1432 struct snd_pcm_runtime *runtime = substream->runtime; 1433 struct snd_cs46xx_pcm * cpcm; 1434 1435 cpcm = runtime->private_data; 1436 1437 /* when playback_open fails, then cpcm can be NULL */ 1438 if (!cpcm) return -ENXIO; 1439 1440 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1441 mutex_lock(&chip->spos_mutex); 1442 if (cpcm->pcm_channel) { 1443 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel); 1444 cpcm->pcm_channel = NULL; 1445 } 1446 mutex_unlock(&chip->spos_mutex); 1447 #else 1448 chip->playback_pcm = NULL; 1449 #endif 1450 1451 cpcm->substream = NULL; 1452 snd_dma_free_pages(&cpcm->hw_buf); 1453 chip->active_ctrl(chip, -1); 1454 1455 return 0; 1456 } 1457 1458 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) 1459 { 1460 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1461 1462 chip->capt.substream = NULL; 1463 snd_dma_free_pages(&chip->capt.hw_buf); 1464 chip->active_ctrl(chip, -1); 1465 1466 return 0; 1467 } 1468 1469 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1470 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { 1471 .open = snd_cs46xx_playback_open_rear, 1472 .close = snd_cs46xx_playback_close, 1473 .ioctl = snd_pcm_lib_ioctl, 1474 .hw_params = snd_cs46xx_playback_hw_params, 1475 .hw_free = snd_cs46xx_playback_hw_free, 1476 .prepare = snd_cs46xx_playback_prepare, 1477 .trigger = snd_cs46xx_playback_trigger, 1478 .pointer = snd_cs46xx_playback_direct_pointer, 1479 }; 1480 1481 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { 1482 .open = snd_cs46xx_playback_open_rear, 1483 .close = snd_cs46xx_playback_close, 1484 .ioctl = snd_pcm_lib_ioctl, 1485 .hw_params = snd_cs46xx_playback_hw_params, 1486 .hw_free = snd_cs46xx_playback_hw_free, 1487 .prepare = snd_cs46xx_playback_prepare, 1488 .trigger = snd_cs46xx_playback_trigger, 1489 .pointer = snd_cs46xx_playback_indirect_pointer, 1490 .ack = snd_cs46xx_playback_transfer, 1491 }; 1492 1493 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { 1494 .open = snd_cs46xx_playback_open_clfe, 1495 .close = snd_cs46xx_playback_close, 1496 .ioctl = snd_pcm_lib_ioctl, 1497 .hw_params = snd_cs46xx_playback_hw_params, 1498 .hw_free = snd_cs46xx_playback_hw_free, 1499 .prepare = snd_cs46xx_playback_prepare, 1500 .trigger = snd_cs46xx_playback_trigger, 1501 .pointer = snd_cs46xx_playback_direct_pointer, 1502 }; 1503 1504 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { 1505 .open = snd_cs46xx_playback_open_clfe, 1506 .close = snd_cs46xx_playback_close, 1507 .ioctl = snd_pcm_lib_ioctl, 1508 .hw_params = snd_cs46xx_playback_hw_params, 1509 .hw_free = snd_cs46xx_playback_hw_free, 1510 .prepare = snd_cs46xx_playback_prepare, 1511 .trigger = snd_cs46xx_playback_trigger, 1512 .pointer = snd_cs46xx_playback_indirect_pointer, 1513 .ack = snd_cs46xx_playback_transfer, 1514 }; 1515 1516 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { 1517 .open = snd_cs46xx_playback_open_iec958, 1518 .close = snd_cs46xx_playback_close_iec958, 1519 .ioctl = snd_pcm_lib_ioctl, 1520 .hw_params = snd_cs46xx_playback_hw_params, 1521 .hw_free = snd_cs46xx_playback_hw_free, 1522 .prepare = snd_cs46xx_playback_prepare, 1523 .trigger = snd_cs46xx_playback_trigger, 1524 .pointer = snd_cs46xx_playback_direct_pointer, 1525 }; 1526 1527 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { 1528 .open = snd_cs46xx_playback_open_iec958, 1529 .close = snd_cs46xx_playback_close_iec958, 1530 .ioctl = snd_pcm_lib_ioctl, 1531 .hw_params = snd_cs46xx_playback_hw_params, 1532 .hw_free = snd_cs46xx_playback_hw_free, 1533 .prepare = snd_cs46xx_playback_prepare, 1534 .trigger = snd_cs46xx_playback_trigger, 1535 .pointer = snd_cs46xx_playback_indirect_pointer, 1536 .ack = snd_cs46xx_playback_transfer, 1537 }; 1538 1539 #endif 1540 1541 static struct snd_pcm_ops snd_cs46xx_playback_ops = { 1542 .open = snd_cs46xx_playback_open, 1543 .close = snd_cs46xx_playback_close, 1544 .ioctl = snd_pcm_lib_ioctl, 1545 .hw_params = snd_cs46xx_playback_hw_params, 1546 .hw_free = snd_cs46xx_playback_hw_free, 1547 .prepare = snd_cs46xx_playback_prepare, 1548 .trigger = snd_cs46xx_playback_trigger, 1549 .pointer = snd_cs46xx_playback_direct_pointer, 1550 }; 1551 1552 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { 1553 .open = snd_cs46xx_playback_open, 1554 .close = snd_cs46xx_playback_close, 1555 .ioctl = snd_pcm_lib_ioctl, 1556 .hw_params = snd_cs46xx_playback_hw_params, 1557 .hw_free = snd_cs46xx_playback_hw_free, 1558 .prepare = snd_cs46xx_playback_prepare, 1559 .trigger = snd_cs46xx_playback_trigger, 1560 .pointer = snd_cs46xx_playback_indirect_pointer, 1561 .ack = snd_cs46xx_playback_transfer, 1562 }; 1563 1564 static struct snd_pcm_ops snd_cs46xx_capture_ops = { 1565 .open = snd_cs46xx_capture_open, 1566 .close = snd_cs46xx_capture_close, 1567 .ioctl = snd_pcm_lib_ioctl, 1568 .hw_params = snd_cs46xx_capture_hw_params, 1569 .hw_free = snd_cs46xx_capture_hw_free, 1570 .prepare = snd_cs46xx_capture_prepare, 1571 .trigger = snd_cs46xx_capture_trigger, 1572 .pointer = snd_cs46xx_capture_direct_pointer, 1573 }; 1574 1575 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { 1576 .open = snd_cs46xx_capture_open, 1577 .close = snd_cs46xx_capture_close, 1578 .ioctl = snd_pcm_lib_ioctl, 1579 .hw_params = snd_cs46xx_capture_hw_params, 1580 .hw_free = snd_cs46xx_capture_hw_free, 1581 .prepare = snd_cs46xx_capture_prepare, 1582 .trigger = snd_cs46xx_capture_trigger, 1583 .pointer = snd_cs46xx_capture_indirect_pointer, 1584 .ack = snd_cs46xx_capture_transfer, 1585 }; 1586 1587 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1588 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1) 1589 #else 1590 #define MAX_PLAYBACK_CHANNELS 1 1591 #endif 1592 1593 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm) 1594 { 1595 struct snd_pcm *pcm; 1596 int err; 1597 1598 if (rpcm) 1599 *rpcm = NULL; 1600 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0) 1601 return err; 1602 1603 pcm->private_data = chip; 1604 1605 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops); 1606 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops); 1607 1608 /* global setup */ 1609 pcm->info_flags = 0; 1610 strcpy(pcm->name, "CS46xx"); 1611 chip->pcm = pcm; 1612 1613 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1614 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1615 1616 if (rpcm) 1617 *rpcm = pcm; 1618 1619 return 0; 1620 } 1621 1622 1623 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1624 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, 1625 struct snd_pcm **rpcm) 1626 { 1627 struct snd_pcm *pcm; 1628 int err; 1629 1630 if (rpcm) 1631 *rpcm = NULL; 1632 1633 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) 1634 return err; 1635 1636 pcm->private_data = chip; 1637 1638 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops); 1639 1640 /* global setup */ 1641 pcm->info_flags = 0; 1642 strcpy(pcm->name, "CS46xx - Rear"); 1643 chip->pcm_rear = pcm; 1644 1645 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1646 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1647 1648 if (rpcm) 1649 *rpcm = pcm; 1650 1651 return 0; 1652 } 1653 1654 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, 1655 struct snd_pcm **rpcm) 1656 { 1657 struct snd_pcm *pcm; 1658 int err; 1659 1660 if (rpcm) 1661 *rpcm = NULL; 1662 1663 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) 1664 return err; 1665 1666 pcm->private_data = chip; 1667 1668 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops); 1669 1670 /* global setup */ 1671 pcm->info_flags = 0; 1672 strcpy(pcm->name, "CS46xx - Center LFE"); 1673 chip->pcm_center_lfe = pcm; 1674 1675 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1676 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1677 1678 if (rpcm) 1679 *rpcm = pcm; 1680 1681 return 0; 1682 } 1683 1684 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, 1685 struct snd_pcm **rpcm) 1686 { 1687 struct snd_pcm *pcm; 1688 int err; 1689 1690 if (rpcm) 1691 *rpcm = NULL; 1692 1693 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0) 1694 return err; 1695 1696 pcm->private_data = chip; 1697 1698 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops); 1699 1700 /* global setup */ 1701 pcm->info_flags = 0; 1702 strcpy(pcm->name, "CS46xx - IEC958"); 1703 chip->pcm_rear = pcm; 1704 1705 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1706 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1707 1708 if (rpcm) 1709 *rpcm = pcm; 1710 1711 return 0; 1712 } 1713 #endif 1714 1715 /* 1716 * Mixer routines 1717 */ 1718 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1719 { 1720 struct snd_cs46xx *chip = bus->private_data; 1721 1722 chip->ac97_bus = NULL; 1723 } 1724 1725 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97) 1726 { 1727 struct snd_cs46xx *chip = ac97->private_data; 1728 1729 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] && 1730 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])) 1731 return; 1732 1733 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) { 1734 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL; 1735 chip->eapd_switch = NULL; 1736 } 1737 else 1738 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL; 1739 } 1740 1741 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol, 1742 struct snd_ctl_elem_info *uinfo) 1743 { 1744 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1745 uinfo->count = 2; 1746 uinfo->value.integer.min = 0; 1747 uinfo->value.integer.max = 0x7fff; 1748 return 0; 1749 } 1750 1751 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1752 { 1753 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1754 int reg = kcontrol->private_value; 1755 unsigned int val = snd_cs46xx_peek(chip, reg); 1756 ucontrol->value.integer.value[0] = 0xffff - (val >> 16); 1757 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff); 1758 return 0; 1759 } 1760 1761 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1762 { 1763 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1764 int reg = kcontrol->private_value; 1765 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | 1766 (0xffff - ucontrol->value.integer.value[1])); 1767 unsigned int old = snd_cs46xx_peek(chip, reg); 1768 int change = (old != val); 1769 1770 if (change) { 1771 snd_cs46xx_poke(chip, reg, val); 1772 } 1773 1774 return change; 1775 } 1776 1777 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1778 1779 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1780 { 1781 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1782 1783 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left; 1784 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right; 1785 1786 return 0; 1787 } 1788 1789 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1790 { 1791 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1792 int change = 0; 1793 1794 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] || 1795 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) { 1796 cs46xx_dsp_set_dac_volume(chip, 1797 ucontrol->value.integer.value[0], 1798 ucontrol->value.integer.value[1]); 1799 change = 1; 1800 } 1801 1802 return change; 1803 } 1804 1805 #if 0 1806 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1807 { 1808 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1809 1810 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left; 1811 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right; 1812 return 0; 1813 } 1814 1815 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1816 { 1817 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1818 int change = 0; 1819 1820 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] || 1821 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) { 1822 cs46xx_dsp_set_iec958_volume (chip, 1823 ucontrol->value.integer.value[0], 1824 ucontrol->value.integer.value[1]); 1825 change = 1; 1826 } 1827 1828 return change; 1829 } 1830 #endif 1831 1832 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info 1833 1834 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol, 1835 struct snd_ctl_elem_value *ucontrol) 1836 { 1837 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1838 int reg = kcontrol->private_value; 1839 1840 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT) 1841 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1842 else 1843 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in; 1844 1845 return 0; 1846 } 1847 1848 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol, 1849 struct snd_ctl_elem_value *ucontrol) 1850 { 1851 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1852 int change, res; 1853 1854 switch (kcontrol->private_value) { 1855 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT: 1856 mutex_lock(&chip->spos_mutex); 1857 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1858 if (ucontrol->value.integer.value[0] && !change) 1859 cs46xx_dsp_enable_spdif_out(chip); 1860 else if (change && !ucontrol->value.integer.value[0]) 1861 cs46xx_dsp_disable_spdif_out(chip); 1862 1863 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED)); 1864 mutex_unlock(&chip->spos_mutex); 1865 break; 1866 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT: 1867 change = chip->dsp_spos_instance->spdif_status_in; 1868 if (ucontrol->value.integer.value[0] && !change) { 1869 cs46xx_dsp_enable_spdif_in(chip); 1870 /* restore volume */ 1871 } 1872 else if (change && !ucontrol->value.integer.value[0]) 1873 cs46xx_dsp_disable_spdif_in(chip); 1874 1875 res = (change != chip->dsp_spos_instance->spdif_status_in); 1876 break; 1877 default: 1878 res = -EINVAL; 1879 snd_BUG(); /* should never happen ... */ 1880 } 1881 1882 return res; 1883 } 1884 1885 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol, 1886 struct snd_ctl_elem_value *ucontrol) 1887 { 1888 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1889 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1890 1891 if (ins->adc_input != NULL) 1892 ucontrol->value.integer.value[0] = 1; 1893 else 1894 ucontrol->value.integer.value[0] = 0; 1895 1896 return 0; 1897 } 1898 1899 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol, 1900 struct snd_ctl_elem_value *ucontrol) 1901 { 1902 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1903 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1904 int change = 0; 1905 1906 if (ucontrol->value.integer.value[0] && !ins->adc_input) { 1907 cs46xx_dsp_enable_adc_capture(chip); 1908 change = 1; 1909 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) { 1910 cs46xx_dsp_disable_adc_capture(chip); 1911 change = 1; 1912 } 1913 return change; 1914 } 1915 1916 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol, 1917 struct snd_ctl_elem_value *ucontrol) 1918 { 1919 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1920 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1921 1922 if (ins->pcm_input != NULL) 1923 ucontrol->value.integer.value[0] = 1; 1924 else 1925 ucontrol->value.integer.value[0] = 0; 1926 1927 return 0; 1928 } 1929 1930 1931 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol, 1932 struct snd_ctl_elem_value *ucontrol) 1933 { 1934 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1935 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1936 int change = 0; 1937 1938 if (ucontrol->value.integer.value[0] && !ins->pcm_input) { 1939 cs46xx_dsp_enable_pcm_capture(chip); 1940 change = 1; 1941 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) { 1942 cs46xx_dsp_disable_pcm_capture(chip); 1943 change = 1; 1944 } 1945 1946 return change; 1947 } 1948 1949 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol, 1950 struct snd_ctl_elem_value *ucontrol) 1951 { 1952 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1953 1954 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 1955 1956 if (val1 & EGPIODR_GPOE0) 1957 ucontrol->value.integer.value[0] = 1; 1958 else 1959 ucontrol->value.integer.value[0] = 0; 1960 1961 return 0; 1962 } 1963 1964 /* 1965 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial. 1966 */ 1967 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol, 1968 struct snd_ctl_elem_value *ucontrol) 1969 { 1970 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1971 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 1972 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 1973 1974 if (ucontrol->value.integer.value[0]) { 1975 /* optical is default */ 1976 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 1977 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */ 1978 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 1979 EGPIOPTR_GPPT0 | val2); /* open-drain on output */ 1980 } else { 1981 /* coaxial */ 1982 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */ 1983 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */ 1984 } 1985 1986 /* checking diff from the EGPIO direction register 1987 should be enough */ 1988 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR)); 1989 } 1990 1991 1992 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1993 { 1994 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1995 uinfo->count = 1; 1996 return 0; 1997 } 1998 1999 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol, 2000 struct snd_ctl_elem_value *ucontrol) 2001 { 2002 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2003 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2004 2005 mutex_lock(&chip->spos_mutex); 2006 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff); 2007 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff); 2008 ucontrol->value.iec958.status[2] = 0; 2009 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff); 2010 mutex_unlock(&chip->spos_mutex); 2011 2012 return 0; 2013 } 2014 2015 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol, 2016 struct snd_ctl_elem_value *ucontrol) 2017 { 2018 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2019 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2020 unsigned int val; 2021 int change; 2022 2023 mutex_lock(&chip->spos_mutex); 2024 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2025 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) | 2026 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2027 /* left and right validity bit */ 2028 (1 << 13) | (1 << 12); 2029 2030 2031 change = (unsigned int)ins->spdif_csuv_default != val; 2032 ins->spdif_csuv_default = val; 2033 2034 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) ) 2035 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2036 2037 mutex_unlock(&chip->spos_mutex); 2038 2039 return change; 2040 } 2041 2042 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol, 2043 struct snd_ctl_elem_value *ucontrol) 2044 { 2045 ucontrol->value.iec958.status[0] = 0xff; 2046 ucontrol->value.iec958.status[1] = 0xff; 2047 ucontrol->value.iec958.status[2] = 0x00; 2048 ucontrol->value.iec958.status[3] = 0xff; 2049 return 0; 2050 } 2051 2052 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol, 2053 struct snd_ctl_elem_value *ucontrol) 2054 { 2055 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2056 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2057 2058 mutex_lock(&chip->spos_mutex); 2059 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff); 2060 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff); 2061 ucontrol->value.iec958.status[2] = 0; 2062 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff); 2063 mutex_unlock(&chip->spos_mutex); 2064 2065 return 0; 2066 } 2067 2068 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol, 2069 struct snd_ctl_elem_value *ucontrol) 2070 { 2071 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2072 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2073 unsigned int val; 2074 int change; 2075 2076 mutex_lock(&chip->spos_mutex); 2077 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2078 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) | 2079 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2080 /* left and right validity bit */ 2081 (1 << 13) | (1 << 12); 2082 2083 2084 change = ins->spdif_csuv_stream != val; 2085 ins->spdif_csuv_stream = val; 2086 2087 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN ) 2088 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2089 2090 mutex_unlock(&chip->spos_mutex); 2091 2092 return change; 2093 } 2094 2095 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2096 2097 2098 static struct snd_kcontrol_new snd_cs46xx_controls[] = { 2099 { 2100 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2101 .name = "DAC Volume", 2102 .info = snd_cs46xx_vol_info, 2103 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2104 .get = snd_cs46xx_vol_get, 2105 .put = snd_cs46xx_vol_put, 2106 .private_value = BA1_PVOL, 2107 #else 2108 .get = snd_cs46xx_vol_dac_get, 2109 .put = snd_cs46xx_vol_dac_put, 2110 #endif 2111 }, 2112 2113 { 2114 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2115 .name = "ADC Volume", 2116 .info = snd_cs46xx_vol_info, 2117 .get = snd_cs46xx_vol_get, 2118 .put = snd_cs46xx_vol_put, 2119 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2120 .private_value = BA1_CVOL, 2121 #else 2122 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2, 2123 #endif 2124 }, 2125 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2126 { 2127 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2128 .name = "ADC Capture Switch", 2129 .info = snd_mixer_boolean_info, 2130 .get = snd_cs46xx_adc_capture_get, 2131 .put = snd_cs46xx_adc_capture_put 2132 }, 2133 { 2134 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2135 .name = "DAC Capture Switch", 2136 .info = snd_mixer_boolean_info, 2137 .get = snd_cs46xx_pcm_capture_get, 2138 .put = snd_cs46xx_pcm_capture_put 2139 }, 2140 { 2141 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2142 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), 2143 .info = snd_mixer_boolean_info, 2144 .get = snd_cs46xx_iec958_get, 2145 .put = snd_cs46xx_iec958_put, 2146 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT, 2147 }, 2148 { 2149 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2150 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH), 2151 .info = snd_mixer_boolean_info, 2152 .get = snd_cs46xx_iec958_get, 2153 .put = snd_cs46xx_iec958_put, 2154 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT, 2155 }, 2156 #if 0 2157 /* Input IEC958 volume does not work for the moment. (Benny) */ 2158 { 2159 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2160 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME), 2161 .info = snd_cs46xx_vol_info, 2162 .get = snd_cs46xx_vol_iec958_get, 2163 .put = snd_cs46xx_vol_iec958_put, 2164 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2, 2165 }, 2166 #endif 2167 { 2168 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2169 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2170 .info = snd_cs46xx_spdif_info, 2171 .get = snd_cs46xx_spdif_default_get, 2172 .put = snd_cs46xx_spdif_default_put, 2173 }, 2174 { 2175 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2176 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 2177 .info = snd_cs46xx_spdif_info, 2178 .get = snd_cs46xx_spdif_mask_get, 2179 .access = SNDRV_CTL_ELEM_ACCESS_READ 2180 }, 2181 { 2182 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2183 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2184 .info = snd_cs46xx_spdif_info, 2185 .get = snd_cs46xx_spdif_stream_get, 2186 .put = snd_cs46xx_spdif_stream_put 2187 }, 2188 2189 #endif 2190 }; 2191 2192 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2193 /* set primary cs4294 codec into Extended Audio Mode */ 2194 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol, 2195 struct snd_ctl_elem_value *ucontrol) 2196 { 2197 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2198 unsigned short val; 2199 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE); 2200 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1; 2201 return 0; 2202 } 2203 2204 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol, 2205 struct snd_ctl_elem_value *ucontrol) 2206 { 2207 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2208 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2209 AC97_CSR_ACMODE, 0x200, 2210 ucontrol->value.integer.value[0] ? 0 : 0x200); 2211 } 2212 2213 static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = { 2214 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2215 .name = "Duplicate Front", 2216 .info = snd_mixer_boolean_info, 2217 .get = snd_cs46xx_front_dup_get, 2218 .put = snd_cs46xx_front_dup_put, 2219 }; 2220 #endif 2221 2222 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2223 /* Only available on the Hercules Game Theater XP soundcard */ 2224 static struct snd_kcontrol_new snd_hercules_controls[] = { 2225 { 2226 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2227 .name = "Optical/Coaxial SPDIF Input Switch", 2228 .info = snd_mixer_boolean_info, 2229 .get = snd_herc_spdif_select_get, 2230 .put = snd_herc_spdif_select_put, 2231 }, 2232 }; 2233 2234 2235 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97) 2236 { 2237 unsigned long end_time; 2238 int err; 2239 2240 /* reset to defaults */ 2241 snd_ac97_write(ac97, AC97_RESET, 0); 2242 2243 /* set the desired CODEC mode */ 2244 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) { 2245 snd_printdd("cs46xx: CODEC1 mode %04x\n", 0x0); 2246 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0); 2247 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) { 2248 snd_printdd("cs46xx: CODEC2 mode %04x\n", 0x3); 2249 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3); 2250 } else { 2251 snd_BUG(); /* should never happen ... */ 2252 } 2253 2254 udelay(50); 2255 2256 /* it's necessary to wait awhile until registers are accessible after RESET */ 2257 /* because the PCM or MASTER volume registers can be modified, */ 2258 /* the REC_GAIN register is used for tests */ 2259 end_time = jiffies + HZ; 2260 do { 2261 unsigned short ext_mid; 2262 2263 /* use preliminary reads to settle the communication */ 2264 snd_ac97_read(ac97, AC97_RESET); 2265 snd_ac97_read(ac97, AC97_VENDOR_ID1); 2266 snd_ac97_read(ac97, AC97_VENDOR_ID2); 2267 /* modem? */ 2268 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID); 2269 if (ext_mid != 0xffff && (ext_mid & 1) != 0) 2270 return; 2271 2272 /* test if we can write to the record gain volume register */ 2273 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05); 2274 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05) 2275 return; 2276 2277 msleep(10); 2278 } while (time_after_eq(end_time, jiffies)); 2279 2280 snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n"); 2281 } 2282 #endif 2283 2284 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec) 2285 { 2286 int idx, err; 2287 struct snd_ac97_template ac97; 2288 2289 memset(&ac97, 0, sizeof(ac97)); 2290 ac97.private_data = chip; 2291 ac97.private_free = snd_cs46xx_mixer_free_ac97; 2292 ac97.num = codec; 2293 if (chip->amplifier_ctrl == amp_voyetra) 2294 ac97.scaps = AC97_SCAP_INV_EAPD; 2295 2296 if (codec == CS46XX_SECONDARY_CODEC_INDEX) { 2297 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec); 2298 udelay(10); 2299 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) { 2300 snd_printdd("snd_cs46xx: seconadry codec not present\n"); 2301 return -ENXIO; 2302 } 2303 } 2304 2305 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec); 2306 for (idx = 0; idx < 100; ++idx) { 2307 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) { 2308 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]); 2309 return err; 2310 } 2311 msleep(10); 2312 } 2313 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec); 2314 return -ENXIO; 2315 } 2316 2317 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device) 2318 { 2319 struct snd_card *card = chip->card; 2320 struct snd_ctl_elem_id id; 2321 int err; 2322 unsigned int idx; 2323 static struct snd_ac97_bus_ops ops = { 2324 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2325 .reset = snd_cs46xx_codec_reset, 2326 #endif 2327 .write = snd_cs46xx_ac97_write, 2328 .read = snd_cs46xx_ac97_read, 2329 }; 2330 2331 /* detect primary codec */ 2332 chip->nr_ac97_codecs = 0; 2333 snd_printdd("snd_cs46xx: detecting primary codec\n"); 2334 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) 2335 return err; 2336 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus; 2337 2338 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0) 2339 return -ENXIO; 2340 chip->nr_ac97_codecs = 1; 2341 2342 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2343 snd_printdd("snd_cs46xx: detecting seconadry codec\n"); 2344 /* try detect a secondary codec */ 2345 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX)) 2346 chip->nr_ac97_codecs = 2; 2347 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2348 2349 /* add cs4630 mixer controls */ 2350 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) { 2351 struct snd_kcontrol *kctl; 2352 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip); 2353 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM) 2354 kctl->id.device = spdif_device; 2355 if ((err = snd_ctl_add(card, kctl)) < 0) 2356 return err; 2357 } 2358 2359 /* get EAPD mixer switch (for voyetra hack) */ 2360 memset(&id, 0, sizeof(id)); 2361 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2362 strcpy(id.name, "External Amplifier"); 2363 chip->eapd_switch = snd_ctl_find_id(chip->card, &id); 2364 2365 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2366 if (chip->nr_ac97_codecs == 1) { 2367 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff; 2368 if (id2 == 0x592b || id2 == 0x592d) { 2369 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip)); 2370 if (err < 0) 2371 return err; 2372 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2373 AC97_CSR_ACMODE, 0x200); 2374 } 2375 } 2376 /* do soundcard specific mixer setup */ 2377 if (chip->mixer_init) { 2378 snd_printdd ("calling chip->mixer_init(chip);\n"); 2379 chip->mixer_init(chip); 2380 } 2381 #endif 2382 2383 /* turn on amplifier */ 2384 chip->amplifier_ctrl(chip, 1); 2385 2386 return 0; 2387 } 2388 2389 /* 2390 * RawMIDI interface 2391 */ 2392 2393 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip) 2394 { 2395 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST); 2396 udelay(100); 2397 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2398 } 2399 2400 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream) 2401 { 2402 struct snd_cs46xx *chip = substream->rmidi->private_data; 2403 2404 chip->active_ctrl(chip, 1); 2405 spin_lock_irq(&chip->reg_lock); 2406 chip->uartm |= CS46XX_MODE_INPUT; 2407 chip->midcr |= MIDCR_RXE; 2408 chip->midi_input = substream; 2409 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2410 snd_cs46xx_midi_reset(chip); 2411 } else { 2412 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2413 } 2414 spin_unlock_irq(&chip->reg_lock); 2415 return 0; 2416 } 2417 2418 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream) 2419 { 2420 struct snd_cs46xx *chip = substream->rmidi->private_data; 2421 2422 spin_lock_irq(&chip->reg_lock); 2423 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE); 2424 chip->midi_input = NULL; 2425 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2426 snd_cs46xx_midi_reset(chip); 2427 } else { 2428 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2429 } 2430 chip->uartm &= ~CS46XX_MODE_INPUT; 2431 spin_unlock_irq(&chip->reg_lock); 2432 chip->active_ctrl(chip, -1); 2433 return 0; 2434 } 2435 2436 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream) 2437 { 2438 struct snd_cs46xx *chip = substream->rmidi->private_data; 2439 2440 chip->active_ctrl(chip, 1); 2441 2442 spin_lock_irq(&chip->reg_lock); 2443 chip->uartm |= CS46XX_MODE_OUTPUT; 2444 chip->midcr |= MIDCR_TXE; 2445 chip->midi_output = substream; 2446 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2447 snd_cs46xx_midi_reset(chip); 2448 } else { 2449 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2450 } 2451 spin_unlock_irq(&chip->reg_lock); 2452 return 0; 2453 } 2454 2455 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream) 2456 { 2457 struct snd_cs46xx *chip = substream->rmidi->private_data; 2458 2459 spin_lock_irq(&chip->reg_lock); 2460 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE); 2461 chip->midi_output = NULL; 2462 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2463 snd_cs46xx_midi_reset(chip); 2464 } else { 2465 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2466 } 2467 chip->uartm &= ~CS46XX_MODE_OUTPUT; 2468 spin_unlock_irq(&chip->reg_lock); 2469 chip->active_ctrl(chip, -1); 2470 return 0; 2471 } 2472 2473 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2474 { 2475 unsigned long flags; 2476 struct snd_cs46xx *chip = substream->rmidi->private_data; 2477 2478 spin_lock_irqsave(&chip->reg_lock, flags); 2479 if (up) { 2480 if ((chip->midcr & MIDCR_RIE) == 0) { 2481 chip->midcr |= MIDCR_RIE; 2482 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2483 } 2484 } else { 2485 if (chip->midcr & MIDCR_RIE) { 2486 chip->midcr &= ~MIDCR_RIE; 2487 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2488 } 2489 } 2490 spin_unlock_irqrestore(&chip->reg_lock, flags); 2491 } 2492 2493 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2494 { 2495 unsigned long flags; 2496 struct snd_cs46xx *chip = substream->rmidi->private_data; 2497 unsigned char byte; 2498 2499 spin_lock_irqsave(&chip->reg_lock, flags); 2500 if (up) { 2501 if ((chip->midcr & MIDCR_TIE) == 0) { 2502 chip->midcr |= MIDCR_TIE; 2503 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2504 while ((chip->midcr & MIDCR_TIE) && 2505 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 2506 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2507 chip->midcr &= ~MIDCR_TIE; 2508 } else { 2509 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte); 2510 } 2511 } 2512 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2513 } 2514 } else { 2515 if (chip->midcr & MIDCR_TIE) { 2516 chip->midcr &= ~MIDCR_TIE; 2517 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2518 } 2519 } 2520 spin_unlock_irqrestore(&chip->reg_lock, flags); 2521 } 2522 2523 static struct snd_rawmidi_ops snd_cs46xx_midi_output = 2524 { 2525 .open = snd_cs46xx_midi_output_open, 2526 .close = snd_cs46xx_midi_output_close, 2527 .trigger = snd_cs46xx_midi_output_trigger, 2528 }; 2529 2530 static struct snd_rawmidi_ops snd_cs46xx_midi_input = 2531 { 2532 .open = snd_cs46xx_midi_input_open, 2533 .close = snd_cs46xx_midi_input_close, 2534 .trigger = snd_cs46xx_midi_input_trigger, 2535 }; 2536 2537 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi) 2538 { 2539 struct snd_rawmidi *rmidi; 2540 int err; 2541 2542 if (rrawmidi) 2543 *rrawmidi = NULL; 2544 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0) 2545 return err; 2546 strcpy(rmidi->name, "CS46XX"); 2547 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output); 2548 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input); 2549 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 2550 rmidi->private_data = chip; 2551 chip->rmidi = rmidi; 2552 if (rrawmidi) 2553 *rrawmidi = NULL; 2554 return 0; 2555 } 2556 2557 2558 /* 2559 * gameport interface 2560 */ 2561 2562 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 2563 2564 static void snd_cs46xx_gameport_trigger(struct gameport *gameport) 2565 { 2566 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2567 2568 if (snd_BUG_ON(!chip)) 2569 return; 2570 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF); 2571 } 2572 2573 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport) 2574 { 2575 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2576 2577 if (snd_BUG_ON(!chip)) 2578 return 0; 2579 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io); 2580 } 2581 2582 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) 2583 { 2584 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2585 unsigned js1, js2, jst; 2586 2587 if (snd_BUG_ON(!chip)) 2588 return 0; 2589 2590 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1); 2591 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2); 2592 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT); 2593 2594 *buttons = (~jst >> 4) & 0x0F; 2595 2596 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 2597 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 2598 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 2599 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 2600 2601 for(jst=0;jst<4;++jst) 2602 if(axes[jst]==0xFFFF) axes[jst] = -1; 2603 return 0; 2604 } 2605 2606 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode) 2607 { 2608 switch (mode) { 2609 case GAMEPORT_MODE_COOKED: 2610 return 0; 2611 case GAMEPORT_MODE_RAW: 2612 return 0; 2613 default: 2614 return -1; 2615 } 2616 return 0; 2617 } 2618 2619 int snd_cs46xx_gameport(struct snd_cs46xx *chip) 2620 { 2621 struct gameport *gp; 2622 2623 chip->gameport = gp = gameport_allocate_port(); 2624 if (!gp) { 2625 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n"); 2626 return -ENOMEM; 2627 } 2628 2629 gameport_set_name(gp, "CS46xx Gameport"); 2630 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2631 gameport_set_dev_parent(gp, &chip->pci->dev); 2632 gameport_set_port_data(gp, chip); 2633 2634 gp->open = snd_cs46xx_gameport_open; 2635 gp->read = snd_cs46xx_gameport_read; 2636 gp->trigger = snd_cs46xx_gameport_trigger; 2637 gp->cooked_read = snd_cs46xx_gameport_cooked_read; 2638 2639 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 2640 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 2641 2642 gameport_register_port(gp); 2643 2644 return 0; 2645 } 2646 2647 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) 2648 { 2649 if (chip->gameport) { 2650 gameport_unregister_port(chip->gameport); 2651 chip->gameport = NULL; 2652 } 2653 } 2654 #else 2655 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; } 2656 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { } 2657 #endif /* CONFIG_GAMEPORT */ 2658 2659 #ifdef CONFIG_PROC_FS 2660 /* 2661 * proc interface 2662 */ 2663 2664 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry, 2665 void *file_private_data, 2666 struct file *file, char __user *buf, 2667 size_t count, loff_t pos) 2668 { 2669 struct snd_cs46xx_region *region = entry->private_data; 2670 2671 if (copy_to_user_fromio(buf, region->remap_addr + pos, count)) 2672 return -EFAULT; 2673 return count; 2674 } 2675 2676 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = { 2677 .read = snd_cs46xx_io_read, 2678 }; 2679 2680 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip) 2681 { 2682 struct snd_info_entry *entry; 2683 int idx; 2684 2685 for (idx = 0; idx < 5; idx++) { 2686 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2687 if (! snd_card_proc_new(card, region->name, &entry)) { 2688 entry->content = SNDRV_INFO_CONTENT_DATA; 2689 entry->private_data = chip; 2690 entry->c.ops = &snd_cs46xx_proc_io_ops; 2691 entry->size = region->size; 2692 entry->mode = S_IFREG | S_IRUSR; 2693 } 2694 } 2695 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2696 cs46xx_dsp_proc_init(card, chip); 2697 #endif 2698 return 0; 2699 } 2700 2701 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip) 2702 { 2703 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2704 cs46xx_dsp_proc_done(chip); 2705 #endif 2706 return 0; 2707 } 2708 #else /* !CONFIG_PROC_FS */ 2709 #define snd_cs46xx_proc_init(card, chip) 2710 #define snd_cs46xx_proc_done(chip) 2711 #endif 2712 2713 /* 2714 * stop the h/w 2715 */ 2716 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip) 2717 { 2718 unsigned int tmp; 2719 2720 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 2721 tmp &= ~0x0000f03f; 2722 tmp |= 0x00000010; 2723 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */ 2724 2725 tmp = snd_cs46xx_peek(chip, BA1_CIE); 2726 tmp &= ~0x0000003f; 2727 tmp |= 0x00000011; 2728 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */ 2729 2730 /* 2731 * Stop playback DMA. 2732 */ 2733 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 2734 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 2735 2736 /* 2737 * Stop capture DMA. 2738 */ 2739 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 2740 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 2741 2742 /* 2743 * Reset the processor. 2744 */ 2745 snd_cs46xx_reset(chip); 2746 2747 snd_cs46xx_proc_stop(chip); 2748 2749 /* 2750 * Power down the PLL. 2751 */ 2752 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2753 2754 /* 2755 * Turn off the Processor by turning off the software clock enable flag in 2756 * the clock control register. 2757 */ 2758 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; 2759 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 2760 } 2761 2762 2763 static int snd_cs46xx_free(struct snd_cs46xx *chip) 2764 { 2765 int idx; 2766 2767 if (snd_BUG_ON(!chip)) 2768 return -EINVAL; 2769 2770 if (chip->active_ctrl) 2771 chip->active_ctrl(chip, 1); 2772 2773 snd_cs46xx_remove_gameport(chip); 2774 2775 if (chip->amplifier_ctrl) 2776 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */ 2777 2778 snd_cs46xx_proc_done(chip); 2779 2780 if (chip->region.idx[0].resource) 2781 snd_cs46xx_hw_stop(chip); 2782 2783 if (chip->irq >= 0) 2784 free_irq(chip->irq, chip); 2785 2786 if (chip->active_ctrl) 2787 chip->active_ctrl(chip, -chip->amplifier); 2788 2789 for (idx = 0; idx < 5; idx++) { 2790 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2791 if (region->remap_addr) 2792 iounmap(region->remap_addr); 2793 release_and_free_resource(region->resource); 2794 } 2795 2796 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2797 if (chip->dsp_spos_instance) { 2798 cs46xx_dsp_spos_destroy(chip); 2799 chip->dsp_spos_instance = NULL; 2800 } 2801 #endif 2802 2803 #ifdef CONFIG_PM_SLEEP 2804 kfree(chip->saved_regs); 2805 #endif 2806 2807 pci_disable_device(chip->pci); 2808 kfree(chip); 2809 return 0; 2810 } 2811 2812 static int snd_cs46xx_dev_free(struct snd_device *device) 2813 { 2814 struct snd_cs46xx *chip = device->device_data; 2815 return snd_cs46xx_free(chip); 2816 } 2817 2818 /* 2819 * initialize chip 2820 */ 2821 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip) 2822 { 2823 int timeout; 2824 2825 /* 2826 * First, blast the clock control register to zero so that the PLL starts 2827 * out in a known state, and blast the master serial port control register 2828 * to zero so that the serial ports also start out in a known state. 2829 */ 2830 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2831 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0); 2832 2833 /* 2834 * If we are in AC97 mode, then we must set the part to a host controlled 2835 * AC-link. Otherwise, we won't be able to bring up the link. 2836 */ 2837 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2838 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 | 2839 SERACC_TWO_CODECS); /* 2.00 dual codecs */ 2840 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */ 2841 #else 2842 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */ 2843 #endif 2844 2845 /* 2846 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 2847 * spec) and then drive it high. This is done for non AC97 modes since 2848 * there might be logic external to the CS461x that uses the ARST# line 2849 * for a reset. 2850 */ 2851 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0); 2852 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2853 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0); 2854 #endif 2855 udelay(50); 2856 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN); 2857 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2858 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN); 2859 #endif 2860 2861 /* 2862 * The first thing we do here is to enable sync generation. As soon 2863 * as we start receiving bit clock, we'll start producing the SYNC 2864 * signal. 2865 */ 2866 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 2867 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2868 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN); 2869 #endif 2870 2871 /* 2872 * Now wait for a short while to allow the AC97 part to start 2873 * generating bit clock (so we don't try to start the PLL without an 2874 * input clock). 2875 */ 2876 mdelay(10); 2877 2878 /* 2879 * Set the serial port timing configuration, so that 2880 * the clock control circuit gets its clock from the correct place. 2881 */ 2882 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97); 2883 2884 /* 2885 * Write the selected clock control setup to the hardware. Do not turn on 2886 * SWCE yet (if requested), so that the devices clocked by the output of 2887 * PLL are not clocked until the PLL is stable. 2888 */ 2889 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 2890 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a); 2891 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8); 2892 2893 /* 2894 * Power up the PLL. 2895 */ 2896 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP); 2897 2898 /* 2899 * Wait until the PLL has stabilized. 2900 */ 2901 msleep(100); 2902 2903 /* 2904 * Turn on clocking of the core so that we can setup the serial ports. 2905 */ 2906 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 2907 2908 /* 2909 * Enable FIFO Host Bypass 2910 */ 2911 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP); 2912 2913 /* 2914 * Fill the serial port FIFOs with silence. 2915 */ 2916 snd_cs46xx_clear_serial_FIFOs(chip); 2917 2918 /* 2919 * Set the serial port FIFO pointer to the first sample in the FIFO. 2920 */ 2921 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */ 2922 2923 /* 2924 * Write the serial port configuration to the part. The master 2925 * enable bit is not set until all other values have been written. 2926 */ 2927 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 2928 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 2929 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 2930 2931 2932 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2933 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN); 2934 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0); 2935 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0); 2936 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0); 2937 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1); 2938 #endif 2939 2940 mdelay(5); 2941 2942 2943 /* 2944 * Wait for the codec ready signal from the AC97 codec. 2945 */ 2946 timeout = 150; 2947 while (timeout-- > 0) { 2948 /* 2949 * Read the AC97 status register to see if we've seen a CODEC READY 2950 * signal from the AC97 codec. 2951 */ 2952 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) 2953 goto ok1; 2954 msleep(10); 2955 } 2956 2957 2958 snd_printk(KERN_ERR "create - never read codec ready from AC'97\n"); 2959 snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n"); 2960 return -EIO; 2961 ok1: 2962 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2963 { 2964 int count; 2965 for (count = 0; count < 150; count++) { 2966 /* First, we want to wait for a short time. */ 2967 udelay(25); 2968 2969 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY) 2970 break; 2971 } 2972 2973 /* 2974 * Make sure CODEC is READY. 2975 */ 2976 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)) 2977 snd_printdd("cs46xx: never read card ready from secondary AC'97\n"); 2978 } 2979 #endif 2980 2981 /* 2982 * Assert the vaid frame signal so that we can start sending commands 2983 * to the AC97 codec. 2984 */ 2985 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 2986 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2987 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 2988 #endif 2989 2990 2991 /* 2992 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 2993 * the codec is pumping ADC data across the AC-link. 2994 */ 2995 timeout = 150; 2996 while (timeout-- > 0) { 2997 /* 2998 * Read the input slot valid register and see if input slots 3 and 2999 * 4 are valid yet. 3000 */ 3001 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 3002 goto ok2; 3003 msleep(10); 3004 } 3005 3006 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3007 snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n"); 3008 return -EIO; 3009 #else 3010 /* This may happen on a cold boot with a Terratec SiXPack 5.1. 3011 Reloading the driver may help, if there's other soundcards 3012 with the same problem I would like to know. (Benny) */ 3013 3014 snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n"); 3015 snd_printk(KERN_ERR " Try reloading the ALSA driver, if you find something\n"); 3016 snd_printk(KERN_ERR " broken or not working on your soundcard upon\n"); 3017 snd_printk(KERN_ERR " this message please report to alsa-devel@alsa-project.org\n"); 3018 3019 return -EIO; 3020 #endif 3021 ok2: 3022 3023 /* 3024 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 3025 * commense the transfer of digital audio data to the AC97 codec. 3026 */ 3027 3028 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 3029 3030 3031 /* 3032 * Power down the DAC and ADC. We will power them up (if) when we need 3033 * them. 3034 */ 3035 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */ 3036 3037 /* 3038 * Turn off the Processor by turning off the software clock enable flag in 3039 * the clock control register. 3040 */ 3041 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */ 3042 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */ 3043 3044 return 0; 3045 } 3046 3047 /* 3048 * start and load DSP 3049 */ 3050 3051 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip) 3052 { 3053 unsigned int tmp; 3054 3055 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM); 3056 3057 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 3058 tmp &= ~0x0000f03f; 3059 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */ 3060 3061 tmp = snd_cs46xx_peek(chip, BA1_CIE); 3062 tmp &= ~0x0000003f; 3063 tmp |= 0x00000001; 3064 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */ 3065 } 3066 3067 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip) 3068 { 3069 unsigned int tmp; 3070 /* 3071 * Reset the processor. 3072 */ 3073 snd_cs46xx_reset(chip); 3074 /* 3075 * Download the image to the processor. 3076 */ 3077 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3078 #if 0 3079 if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) { 3080 snd_printk(KERN_ERR "image download error\n"); 3081 return -EIO; 3082 } 3083 #endif 3084 3085 if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) { 3086 snd_printk(KERN_ERR "image download error [cwc4630]\n"); 3087 return -EIO; 3088 } 3089 3090 if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) { 3091 snd_printk(KERN_ERR "image download error [cwcasync]\n"); 3092 return -EIO; 3093 } 3094 3095 if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) { 3096 snd_printk(KERN_ERR "image download error [cwcsnoop]\n"); 3097 return -EIO; 3098 } 3099 3100 if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) { 3101 snd_printk(KERN_ERR "image download error [cwcbinhack]\n"); 3102 return -EIO; 3103 } 3104 3105 if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) { 3106 snd_printk(KERN_ERR "image download error [cwcdma]\n"); 3107 return -EIO; 3108 } 3109 3110 if (cs46xx_dsp_scb_and_task_init(chip) < 0) 3111 return -EIO; 3112 #else 3113 /* old image */ 3114 if (snd_cs46xx_download_image(chip) < 0) { 3115 snd_printk(KERN_ERR "image download error\n"); 3116 return -EIO; 3117 } 3118 3119 /* 3120 * Stop playback DMA. 3121 */ 3122 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 3123 chip->play_ctl = tmp & 0xffff0000; 3124 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 3125 #endif 3126 3127 /* 3128 * Stop capture DMA. 3129 */ 3130 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3131 chip->capt.ctl = tmp & 0x0000ffff; 3132 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3133 3134 mdelay(5); 3135 3136 snd_cs46xx_set_play_sample_rate(chip, 8000); 3137 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3138 3139 snd_cs46xx_proc_start(chip); 3140 3141 cs46xx_enable_stream_irqs(chip); 3142 3143 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3144 /* set the attenuation to 0dB */ 3145 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000); 3146 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000); 3147 #endif 3148 3149 return 0; 3150 } 3151 3152 3153 /* 3154 * AMP control - null AMP 3155 */ 3156 3157 static void amp_none(struct snd_cs46xx *chip, int change) 3158 { 3159 } 3160 3161 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3162 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip) 3163 { 3164 3165 u32 idx, valid_slots,tmp,powerdown = 0; 3166 u16 modem_power,pin_config,logic_type; 3167 3168 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n"); 3169 3170 /* 3171 * See if the devices are powered down. If so, we must power them up first 3172 * or they will not respond. 3173 */ 3174 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 3175 3176 if (!(tmp & CLKCR1_SWCE)) { 3177 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 3178 powerdown = 1; 3179 } 3180 3181 /* 3182 * Clear PRA. The Bonzo chip will be used for GPIO not for modem 3183 * stuff. 3184 */ 3185 if(chip->nr_ac97_codecs != 2) { 3186 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n"); 3187 return -EINVAL; 3188 } 3189 3190 modem_power = snd_cs46xx_codec_read (chip, 3191 AC97_EXTENDED_MSTATUS, 3192 CS46XX_SECONDARY_CODEC_INDEX); 3193 modem_power &=0xFEFF; 3194 3195 snd_cs46xx_codec_write(chip, 3196 AC97_EXTENDED_MSTATUS, modem_power, 3197 CS46XX_SECONDARY_CODEC_INDEX); 3198 3199 /* 3200 * Set GPIO pin's 7 and 8 so that they are configured for output. 3201 */ 3202 pin_config = snd_cs46xx_codec_read (chip, 3203 AC97_GPIO_CFG, 3204 CS46XX_SECONDARY_CODEC_INDEX); 3205 pin_config &=0x27F; 3206 3207 snd_cs46xx_codec_write(chip, 3208 AC97_GPIO_CFG, pin_config, 3209 CS46XX_SECONDARY_CODEC_INDEX); 3210 3211 /* 3212 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic. 3213 */ 3214 3215 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY, 3216 CS46XX_SECONDARY_CODEC_INDEX); 3217 logic_type &=0x27F; 3218 3219 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type, 3220 CS46XX_SECONDARY_CODEC_INDEX); 3221 3222 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV); 3223 valid_slots |= 0x200; 3224 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots); 3225 3226 if ( cs46xx_wait_for_fifo(chip,1) ) { 3227 snd_printdd("FIFO is busy\n"); 3228 3229 return -EINVAL; 3230 } 3231 3232 /* 3233 * Fill slots 12 with the correct value for the GPIO pins. 3234 */ 3235 for(idx = 0x90; idx <= 0x9F; idx++) { 3236 /* 3237 * Initialize the fifo so that bits 7 and 8 are on. 3238 * 3239 * Remember that the GPIO pins in bonzo are shifted by 4 bits to 3240 * the left. 0x1800 corresponds to bits 7 and 8. 3241 */ 3242 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800); 3243 3244 /* 3245 * Wait for command to complete 3246 */ 3247 if ( cs46xx_wait_for_fifo(chip,200) ) { 3248 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx); 3249 3250 return -EINVAL; 3251 } 3252 3253 /* 3254 * Write the serial port FIFO index. 3255 */ 3256 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 3257 3258 /* 3259 * Tell the serial port to load the new value into the FIFO location. 3260 */ 3261 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 3262 } 3263 3264 /* wait for last command to complete */ 3265 cs46xx_wait_for_fifo(chip,200); 3266 3267 /* 3268 * Now, if we powered up the devices, then power them back down again. 3269 * This is kinda ugly, but should never happen. 3270 */ 3271 if (powerdown) 3272 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 3273 3274 return 0; 3275 } 3276 #endif 3277 3278 /* 3279 * Crystal EAPD mode 3280 */ 3281 3282 static void amp_voyetra(struct snd_cs46xx *chip, int change) 3283 { 3284 /* Manage the EAPD bit on the Crystal 4297 3285 and the Analog AD1885 */ 3286 3287 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3288 int old = chip->amplifier; 3289 #endif 3290 int oval, val; 3291 3292 chip->amplifier += change; 3293 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN, 3294 CS46XX_PRIMARY_CODEC_INDEX); 3295 val = oval; 3296 if (chip->amplifier) { 3297 /* Turn the EAPD amp on */ 3298 val |= 0x8000; 3299 } else { 3300 /* Turn the EAPD amp off */ 3301 val &= ~0x8000; 3302 } 3303 if (val != oval) { 3304 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val, 3305 CS46XX_PRIMARY_CODEC_INDEX); 3306 if (chip->eapd_switch) 3307 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 3308 &chip->eapd_switch->id); 3309 } 3310 3311 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3312 if (chip->amplifier && !old) { 3313 voyetra_setup_eapd_slot(chip); 3314 } 3315 #endif 3316 } 3317 3318 static void hercules_init(struct snd_cs46xx *chip) 3319 { 3320 /* default: AMP off, and SPDIF input optical */ 3321 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3322 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3323 } 3324 3325 3326 /* 3327 * Game Theatre XP card - EGPIO[2] is used to enable the external amp. 3328 */ 3329 static void amp_hercules(struct snd_cs46xx *chip, int change) 3330 { 3331 int old = chip->amplifier; 3332 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 3333 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 3334 3335 chip->amplifier += change; 3336 if (chip->amplifier && !old) { 3337 snd_printdd ("Hercules amplifier ON\n"); 3338 3339 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 3340 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */ 3341 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 3342 EGPIOPTR_GPPT2 | val2); /* open-drain on output */ 3343 } else if (old && !chip->amplifier) { 3344 snd_printdd ("Hercules amplifier OFF\n"); 3345 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */ 3346 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */ 3347 } 3348 } 3349 3350 static void voyetra_mixer_init (struct snd_cs46xx *chip) 3351 { 3352 snd_printdd ("initializing Voyetra mixer\n"); 3353 3354 /* Enable SPDIF out */ 3355 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3356 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3357 } 3358 3359 static void hercules_mixer_init (struct snd_cs46xx *chip) 3360 { 3361 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3362 unsigned int idx; 3363 int err; 3364 struct snd_card *card = chip->card; 3365 #endif 3366 3367 /* set EGPIO to default */ 3368 hercules_init(chip); 3369 3370 snd_printdd ("initializing Hercules mixer\n"); 3371 3372 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3373 if (chip->in_suspend) 3374 return; 3375 3376 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) { 3377 struct snd_kcontrol *kctl; 3378 3379 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip); 3380 if ((err = snd_ctl_add(card, kctl)) < 0) { 3381 printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err); 3382 break; 3383 } 3384 } 3385 #endif 3386 } 3387 3388 3389 #if 0 3390 /* 3391 * Untested 3392 */ 3393 3394 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change) 3395 { 3396 chip->amplifier += change; 3397 3398 if (chip->amplifier) { 3399 /* Switch the GPIO pins 7 and 8 to open drain */ 3400 snd_cs46xx_codec_write(chip, 0x4C, 3401 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F); 3402 snd_cs46xx_codec_write(chip, 0x4E, 3403 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180); 3404 /* Now wake the AMP (this might be backwards) */ 3405 snd_cs46xx_codec_write(chip, 0x54, 3406 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180); 3407 } else { 3408 snd_cs46xx_codec_write(chip, 0x54, 3409 snd_cs46xx_codec_read(chip, 0x54) | 0x0180); 3410 } 3411 } 3412 #endif 3413 3414 3415 /* 3416 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support 3417 * whenever we need to beat on the chip. 3418 * 3419 * The original idea and code for this hack comes from David Kaiser at 3420 * Linuxcare. Perhaps one day Crystal will document their chips well 3421 * enough to make them useful. 3422 */ 3423 3424 static void clkrun_hack(struct snd_cs46xx *chip, int change) 3425 { 3426 u16 control, nval; 3427 3428 if (!chip->acpi_port) 3429 return; 3430 3431 chip->amplifier += change; 3432 3433 /* Read ACPI port */ 3434 nval = control = inw(chip->acpi_port + 0x10); 3435 3436 /* Flip CLKRUN off while running */ 3437 if (! chip->amplifier) 3438 nval |= 0x2000; 3439 else 3440 nval &= ~0x2000; 3441 if (nval != control) 3442 outw(nval, chip->acpi_port + 0x10); 3443 } 3444 3445 3446 /* 3447 * detect intel piix4 3448 */ 3449 static void clkrun_init(struct snd_cs46xx *chip) 3450 { 3451 struct pci_dev *pdev; 3452 u8 pp; 3453 3454 chip->acpi_port = 0; 3455 3456 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 3457 PCI_DEVICE_ID_INTEL_82371AB_3, NULL); 3458 if (pdev == NULL) 3459 return; /* Not a thinkpad thats for sure */ 3460 3461 /* Find the control port */ 3462 pci_read_config_byte(pdev, 0x41, &pp); 3463 chip->acpi_port = pp << 8; 3464 pci_dev_put(pdev); 3465 } 3466 3467 3468 /* 3469 * Card subid table 3470 */ 3471 3472 struct cs_card_type 3473 { 3474 u16 vendor; 3475 u16 id; 3476 char *name; 3477 void (*init)(struct snd_cs46xx *); 3478 void (*amp)(struct snd_cs46xx *, int); 3479 void (*active)(struct snd_cs46xx *, int); 3480 void (*mixer_init)(struct snd_cs46xx *); 3481 }; 3482 3483 static struct cs_card_type cards[] = { 3484 { 3485 .vendor = 0x1489, 3486 .id = 0x7001, 3487 .name = "Genius Soundmaker 128 value", 3488 /* nothing special */ 3489 }, 3490 { 3491 .vendor = 0x5053, 3492 .id = 0x3357, 3493 .name = "Voyetra", 3494 .amp = amp_voyetra, 3495 .mixer_init = voyetra_mixer_init, 3496 }, 3497 { 3498 .vendor = 0x1071, 3499 .id = 0x6003, 3500 .name = "Mitac MI6020/21", 3501 .amp = amp_voyetra, 3502 }, 3503 /* Hercules Game Theatre XP */ 3504 { 3505 .vendor = 0x14af, /* Guillemot Corporation */ 3506 .id = 0x0050, 3507 .name = "Hercules Game Theatre XP", 3508 .amp = amp_hercules, 3509 .mixer_init = hercules_mixer_init, 3510 }, 3511 { 3512 .vendor = 0x1681, 3513 .id = 0x0050, 3514 .name = "Hercules Game Theatre XP", 3515 .amp = amp_hercules, 3516 .mixer_init = hercules_mixer_init, 3517 }, 3518 { 3519 .vendor = 0x1681, 3520 .id = 0x0051, 3521 .name = "Hercules Game Theatre XP", 3522 .amp = amp_hercules, 3523 .mixer_init = hercules_mixer_init, 3524 3525 }, 3526 { 3527 .vendor = 0x1681, 3528 .id = 0x0052, 3529 .name = "Hercules Game Theatre XP", 3530 .amp = amp_hercules, 3531 .mixer_init = hercules_mixer_init, 3532 }, 3533 { 3534 .vendor = 0x1681, 3535 .id = 0x0053, 3536 .name = "Hercules Game Theatre XP", 3537 .amp = amp_hercules, 3538 .mixer_init = hercules_mixer_init, 3539 }, 3540 { 3541 .vendor = 0x1681, 3542 .id = 0x0054, 3543 .name = "Hercules Game Theatre XP", 3544 .amp = amp_hercules, 3545 .mixer_init = hercules_mixer_init, 3546 }, 3547 /* Herculess Fortissimo */ 3548 { 3549 .vendor = 0x1681, 3550 .id = 0xa010, 3551 .name = "Hercules Gamesurround Fortissimo II", 3552 }, 3553 { 3554 .vendor = 0x1681, 3555 .id = 0xa011, 3556 .name = "Hercules Gamesurround Fortissimo III 7.1", 3557 }, 3558 /* Teratec */ 3559 { 3560 .vendor = 0x153b, 3561 .id = 0x112e, 3562 .name = "Terratec DMX XFire 1024", 3563 }, 3564 { 3565 .vendor = 0x153b, 3566 .id = 0x1136, 3567 .name = "Terratec SiXPack 5.1", 3568 }, 3569 /* Not sure if the 570 needs the clkrun hack */ 3570 { 3571 .vendor = PCI_VENDOR_ID_IBM, 3572 .id = 0x0132, 3573 .name = "Thinkpad 570", 3574 .init = clkrun_init, 3575 .active = clkrun_hack, 3576 }, 3577 { 3578 .vendor = PCI_VENDOR_ID_IBM, 3579 .id = 0x0153, 3580 .name = "Thinkpad 600X/A20/T20", 3581 .init = clkrun_init, 3582 .active = clkrun_hack, 3583 }, 3584 { 3585 .vendor = PCI_VENDOR_ID_IBM, 3586 .id = 0x1010, 3587 .name = "Thinkpad 600E (unsupported)", 3588 }, 3589 {} /* terminator */ 3590 }; 3591 3592 3593 /* 3594 * APM support 3595 */ 3596 #ifdef CONFIG_PM_SLEEP 3597 static unsigned int saved_regs[] = { 3598 BA0_ACOSV, 3599 /*BA0_ASER_FADDR,*/ 3600 BA0_ASER_MASTER, 3601 BA1_PVOL, 3602 BA1_CVOL, 3603 }; 3604 3605 static int snd_cs46xx_suspend(struct device *dev) 3606 { 3607 struct pci_dev *pci = to_pci_dev(dev); 3608 struct snd_card *card = dev_get_drvdata(dev); 3609 struct snd_cs46xx *chip = card->private_data; 3610 int i, amp_saved; 3611 3612 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3613 chip->in_suspend = 1; 3614 snd_pcm_suspend_all(chip->pcm); 3615 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL); 3616 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE); 3617 3618 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3619 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3620 3621 /* save some registers */ 3622 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3623 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]); 3624 3625 amp_saved = chip->amplifier; 3626 /* turn off amp */ 3627 chip->amplifier_ctrl(chip, -chip->amplifier); 3628 snd_cs46xx_hw_stop(chip); 3629 /* disable CLKRUN */ 3630 chip->active_ctrl(chip, -chip->amplifier); 3631 chip->amplifier = amp_saved; /* restore the status */ 3632 3633 pci_disable_device(pci); 3634 pci_save_state(pci); 3635 pci_set_power_state(pci, PCI_D3hot); 3636 return 0; 3637 } 3638 3639 static int snd_cs46xx_resume(struct device *dev) 3640 { 3641 struct pci_dev *pci = to_pci_dev(dev); 3642 struct snd_card *card = dev_get_drvdata(dev); 3643 struct snd_cs46xx *chip = card->private_data; 3644 int amp_saved; 3645 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3646 int i; 3647 #endif 3648 unsigned int tmp; 3649 3650 pci_set_power_state(pci, PCI_D0); 3651 pci_restore_state(pci); 3652 if (pci_enable_device(pci) < 0) { 3653 printk(KERN_ERR "cs46xx: pci_enable_device failed, " 3654 "disabling device\n"); 3655 snd_card_disconnect(card); 3656 return -EIO; 3657 } 3658 pci_set_master(pci); 3659 3660 amp_saved = chip->amplifier; 3661 chip->amplifier = 0; 3662 chip->active_ctrl(chip, 1); /* force to on */ 3663 3664 snd_cs46xx_chip_init(chip); 3665 3666 snd_cs46xx_reset(chip); 3667 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3668 cs46xx_dsp_resume(chip); 3669 /* restore some registers */ 3670 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3671 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]); 3672 #else 3673 snd_cs46xx_download_image(chip); 3674 #endif 3675 3676 #if 0 3677 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, 3678 chip->ac97_general_purpose); 3679 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL, 3680 chip->ac97_powerdown); 3681 mdelay(10); 3682 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN, 3683 chip->ac97_powerdown); 3684 mdelay(5); 3685 #endif 3686 3687 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3688 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3689 3690 /* 3691 * Stop capture DMA. 3692 */ 3693 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3694 chip->capt.ctl = tmp & 0x0000ffff; 3695 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3696 3697 mdelay(5); 3698 3699 /* reset playback/capture */ 3700 snd_cs46xx_set_play_sample_rate(chip, 8000); 3701 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3702 snd_cs46xx_proc_start(chip); 3703 3704 cs46xx_enable_stream_irqs(chip); 3705 3706 if (amp_saved) 3707 chip->amplifier_ctrl(chip, 1); /* turn amp on */ 3708 else 3709 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3710 chip->amplifier = amp_saved; 3711 chip->in_suspend = 0; 3712 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3713 return 0; 3714 } 3715 3716 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume); 3717 #endif /* CONFIG_PM_SLEEP */ 3718 3719 3720 /* 3721 */ 3722 3723 int snd_cs46xx_create(struct snd_card *card, 3724 struct pci_dev *pci, 3725 int external_amp, int thinkpad, 3726 struct snd_cs46xx **rchip) 3727 { 3728 struct snd_cs46xx *chip; 3729 int err, idx; 3730 struct snd_cs46xx_region *region; 3731 struct cs_card_type *cp; 3732 u16 ss_card, ss_vendor; 3733 static struct snd_device_ops ops = { 3734 .dev_free = snd_cs46xx_dev_free, 3735 }; 3736 3737 *rchip = NULL; 3738 3739 /* enable PCI device */ 3740 if ((err = pci_enable_device(pci)) < 0) 3741 return err; 3742 3743 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3744 if (chip == NULL) { 3745 pci_disable_device(pci); 3746 return -ENOMEM; 3747 } 3748 spin_lock_init(&chip->reg_lock); 3749 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3750 mutex_init(&chip->spos_mutex); 3751 #endif 3752 chip->card = card; 3753 chip->pci = pci; 3754 chip->irq = -1; 3755 chip->ba0_addr = pci_resource_start(pci, 0); 3756 chip->ba1_addr = pci_resource_start(pci, 1); 3757 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 || 3758 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) { 3759 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", 3760 chip->ba0_addr, chip->ba1_addr); 3761 snd_cs46xx_free(chip); 3762 return -ENOMEM; 3763 } 3764 3765 region = &chip->region.name.ba0; 3766 strcpy(region->name, "CS46xx_BA0"); 3767 region->base = chip->ba0_addr; 3768 region->size = CS46XX_BA0_SIZE; 3769 3770 region = &chip->region.name.data0; 3771 strcpy(region->name, "CS46xx_BA1_data0"); 3772 region->base = chip->ba1_addr + BA1_SP_DMEM0; 3773 region->size = CS46XX_BA1_DATA0_SIZE; 3774 3775 region = &chip->region.name.data1; 3776 strcpy(region->name, "CS46xx_BA1_data1"); 3777 region->base = chip->ba1_addr + BA1_SP_DMEM1; 3778 region->size = CS46XX_BA1_DATA1_SIZE; 3779 3780 region = &chip->region.name.pmem; 3781 strcpy(region->name, "CS46xx_BA1_pmem"); 3782 region->base = chip->ba1_addr + BA1_SP_PMEM; 3783 region->size = CS46XX_BA1_PRG_SIZE; 3784 3785 region = &chip->region.name.reg; 3786 strcpy(region->name, "CS46xx_BA1_reg"); 3787 region->base = chip->ba1_addr + BA1_SP_REG; 3788 region->size = CS46XX_BA1_REG_SIZE; 3789 3790 /* set up amp and clkrun hack */ 3791 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor); 3792 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card); 3793 3794 for (cp = &cards[0]; cp->name; cp++) { 3795 if (cp->vendor == ss_vendor && cp->id == ss_card) { 3796 snd_printdd ("hack for %s enabled\n", cp->name); 3797 3798 chip->amplifier_ctrl = cp->amp; 3799 chip->active_ctrl = cp->active; 3800 chip->mixer_init = cp->mixer_init; 3801 3802 if (cp->init) 3803 cp->init(chip); 3804 break; 3805 } 3806 } 3807 3808 if (external_amp) { 3809 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n"); 3810 chip->amplifier_ctrl = amp_voyetra; 3811 } 3812 3813 if (thinkpad) { 3814 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n"); 3815 chip->active_ctrl = clkrun_hack; 3816 clkrun_init(chip); 3817 } 3818 3819 if (chip->amplifier_ctrl == NULL) 3820 chip->amplifier_ctrl = amp_none; 3821 if (chip->active_ctrl == NULL) 3822 chip->active_ctrl = amp_none; 3823 3824 chip->active_ctrl(chip, 1); /* enable CLKRUN */ 3825 3826 pci_set_master(pci); 3827 3828 for (idx = 0; idx < 5; idx++) { 3829 region = &chip->region.idx[idx]; 3830 if ((region->resource = request_mem_region(region->base, region->size, 3831 region->name)) == NULL) { 3832 snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n", 3833 region->base, region->base + region->size - 1); 3834 snd_cs46xx_free(chip); 3835 return -EBUSY; 3836 } 3837 region->remap_addr = ioremap_nocache(region->base, region->size); 3838 if (region->remap_addr == NULL) { 3839 snd_printk(KERN_ERR "%s ioremap problem\n", region->name); 3840 snd_cs46xx_free(chip); 3841 return -ENOMEM; 3842 } 3843 } 3844 3845 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED, 3846 KBUILD_MODNAME, chip)) { 3847 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 3848 snd_cs46xx_free(chip); 3849 return -EBUSY; 3850 } 3851 chip->irq = pci->irq; 3852 3853 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3854 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip); 3855 if (chip->dsp_spos_instance == NULL) { 3856 snd_cs46xx_free(chip); 3857 return -ENOMEM; 3858 } 3859 #endif 3860 3861 err = snd_cs46xx_chip_init(chip); 3862 if (err < 0) { 3863 snd_cs46xx_free(chip); 3864 return err; 3865 } 3866 3867 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 3868 snd_cs46xx_free(chip); 3869 return err; 3870 } 3871 3872 snd_cs46xx_proc_init(card, chip); 3873 3874 #ifdef CONFIG_PM_SLEEP 3875 chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) * 3876 ARRAY_SIZE(saved_regs), GFP_KERNEL); 3877 if (!chip->saved_regs) { 3878 snd_cs46xx_free(chip); 3879 return -ENOMEM; 3880 } 3881 #endif 3882 3883 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3884 3885 snd_card_set_dev(card, &pci->dev); 3886 3887 *rchip = chip; 3888 return 0; 3889 } 3890