1 /* 2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 3 * Abramo Bagnara <abramo@alsa-project.org> 4 * Cirrus Logic, Inc. 5 * Routines for control of Cirrus Logic CS461x chips 6 * 7 * KNOWN BUGS: 8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized 9 * and the SPDIF get somewhat "distorcionated", or/and left right channel 10 * are swapped. To get around this problem when it happens, mute and unmute 11 * the SPDIF input mixer control. 12 * - On the Hercules Game Theater XP the amplifier are sometimes turned 13 * off on inadecuate moments which causes distorcions on sound. 14 * 15 * TODO: 16 * - Secondary CODEC on some soundcards 17 * - SPDIF input support for other sample rates then 48khz 18 * - Posibility to mix the SPDIF output with analog sources. 19 * - PCM channels for Center and LFE on secondary codec 20 * 21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which 22 * is default configuration), no SPDIF, no secondary codec, no 23 * multi channel PCM. But known to work. 24 * 25 * FINALLY: A credit to the developers Tom and Jordan 26 * at Cirrus for have helping me out with the DSP, however we 27 * still don't have sufficient documentation and technical 28 * references to be able to implement all fancy feutures 29 * supported by the cs46xx DSP's. 30 * Benny <benny@hostmobility.com> 31 * 32 * This program is free software; you can redistribute it and/or modify 33 * it under the terms of the GNU General Public License as published by 34 * the Free Software Foundation; either version 2 of the License, or 35 * (at your option) any later version. 36 * 37 * This program is distributed in the hope that it will be useful, 38 * but WITHOUT ANY WARRANTY; without even the implied warranty of 39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 40 * GNU General Public License for more details. 41 * 42 * You should have received a copy of the GNU General Public License 43 * along with this program; if not, write to the Free Software 44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 45 * 46 */ 47 48 #include <linux/delay.h> 49 #include <linux/pci.h> 50 #include <linux/pm.h> 51 #include <linux/init.h> 52 #include <linux/interrupt.h> 53 #include <linux/slab.h> 54 #include <linux/gameport.h> 55 #include <linux/mutex.h> 56 #include <linux/export.h> 57 #include <linux/module.h> 58 #include <linux/firmware.h> 59 #include <linux/vmalloc.h> 60 61 #include <sound/core.h> 62 #include <sound/control.h> 63 #include <sound/info.h> 64 #include <sound/pcm.h> 65 #include <sound/pcm_params.h> 66 #include "cs46xx.h" 67 68 #include <asm/io.h> 69 70 #include "cs46xx_lib.h" 71 #include "dsp_spos.h" 72 73 static void amp_voyetra(struct snd_cs46xx *chip, int change); 74 75 #ifdef CONFIG_SND_CS46XX_NEW_DSP 76 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops; 77 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; 78 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; 79 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; 80 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; 81 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; 82 #endif 83 84 static struct snd_pcm_ops snd_cs46xx_playback_ops; 85 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; 86 static struct snd_pcm_ops snd_cs46xx_capture_ops; 87 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; 88 89 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, 90 unsigned short reg, 91 int codec_index) 92 { 93 int count; 94 unsigned short result,tmp; 95 u32 offset = 0; 96 97 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 98 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 99 return 0xffff; 100 101 chip->active_ctrl(chip, 1); 102 103 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX) 104 offset = CS46XX_SECONDARY_CODEC_OFFSET; 105 106 /* 107 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 108 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 109 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55 110 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 111 * 5. if DCV not cleared, break and return error 112 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 113 */ 114 115 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 116 117 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL); 118 if ((tmp & ACCTL_VFRM) == 0) { 119 snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp); 120 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM ); 121 msleep(50); 122 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset); 123 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM ); 124 125 } 126 127 /* 128 * Setup the AC97 control registers on the CS461x to send the 129 * appropriate command to the AC97 to perform the read. 130 * ACCAD = Command Address Register = 46Ch 131 * ACCDA = Command Data Register = 470h 132 * ACCTL = Control Register = 460h 133 * set DCV - will clear when process completed 134 * set CRW - Read command 135 * set VFRM - valid frame enabled 136 * set ESYN - ASYNC generation enabled 137 * set RSTN - ARST# inactive, AC97 codec not reset 138 */ 139 140 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg); 141 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0); 142 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 143 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW | 144 ACCTL_VFRM | ACCTL_ESYN | 145 ACCTL_RSTN); 146 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | 147 ACCTL_VFRM | ACCTL_ESYN | 148 ACCTL_RSTN); 149 } else { 150 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 151 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | 152 ACCTL_RSTN); 153 } 154 155 /* 156 * Wait for the read to occur. 157 */ 158 for (count = 0; count < 1000; count++) { 159 /* 160 * First, we want to wait for a short time. 161 */ 162 udelay(10); 163 /* 164 * Now, check to see if the read has completed. 165 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 166 */ 167 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) 168 goto ok1; 169 } 170 171 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 172 result = 0xffff; 173 goto end; 174 175 ok1: 176 /* 177 * Wait for the valid status bit to go active. 178 */ 179 for (count = 0; count < 100; count++) { 180 /* 181 * Read the AC97 status register. 182 * ACSTS = Status Register = 464h 183 * VSTS - Valid Status 184 */ 185 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS) 186 goto ok2; 187 udelay(10); 188 } 189 190 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg); 191 result = 0xffff; 192 goto end; 193 194 ok2: 195 /* 196 * Read the data returned from the AC97 register. 197 * ACSDA = Status Data Register = 474h 198 */ 199 #if 0 200 printk(KERN_DEBUG "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg, 201 snd_cs46xx_peekBA0(chip, BA0_ACSDA), 202 snd_cs46xx_peekBA0(chip, BA0_ACCAD)); 203 #endif 204 205 //snd_cs46xx_peekBA0(chip, BA0_ACCAD); 206 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 207 end: 208 chip->active_ctrl(chip, -1); 209 return result; 210 } 211 212 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97, 213 unsigned short reg) 214 { 215 struct snd_cs46xx *chip = ac97->private_data; 216 unsigned short val; 217 int codec_index = ac97->num; 218 219 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 220 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 221 return 0xffff; 222 223 val = snd_cs46xx_codec_read(chip, reg, codec_index); 224 225 return val; 226 } 227 228 229 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip, 230 unsigned short reg, 231 unsigned short val, 232 int codec_index) 233 { 234 int count; 235 236 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 237 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 238 return; 239 240 chip->active_ctrl(chip, 1); 241 242 /* 243 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 244 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 245 * 3. Write ACCTL = Control Register = 460h for initiating the write 246 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 247 * 5. if DCV not cleared, break and return error 248 */ 249 250 /* 251 * Setup the AC97 control registers on the CS461x to send the 252 * appropriate command to the AC97 to perform the read. 253 * ACCAD = Command Address Register = 46Ch 254 * ACCDA = Command Data Register = 470h 255 * ACCTL = Control Register = 460h 256 * set DCV - will clear when process completed 257 * reset CRW - Write command 258 * set VFRM - valid frame enabled 259 * set ESYN - ASYNC generation enabled 260 * set RSTN - ARST# inactive, AC97 codec not reset 261 */ 262 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg); 263 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val); 264 snd_cs46xx_peekBA0(chip, BA0_ACCTL); 265 266 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 267 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM | 268 ACCTL_ESYN | ACCTL_RSTN); 269 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | 270 ACCTL_ESYN | ACCTL_RSTN); 271 } else { 272 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 273 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 274 } 275 276 for (count = 0; count < 4000; count++) { 277 /* 278 * First, we want to wait for a short time. 279 */ 280 udelay(10); 281 /* 282 * Now, check to see if the write has completed. 283 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 284 */ 285 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) { 286 goto end; 287 } 288 } 289 snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val); 290 end: 291 chip->active_ctrl(chip, -1); 292 } 293 294 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97, 295 unsigned short reg, 296 unsigned short val) 297 { 298 struct snd_cs46xx *chip = ac97->private_data; 299 int codec_index = ac97->num; 300 301 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 302 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 303 return; 304 305 snd_cs46xx_codec_write(chip, reg, val, codec_index); 306 } 307 308 309 /* 310 * Chip initialization 311 */ 312 313 int snd_cs46xx_download(struct snd_cs46xx *chip, 314 u32 *src, 315 unsigned long offset, 316 unsigned long len) 317 { 318 void __iomem *dst; 319 unsigned int bank = offset >> 16; 320 offset = offset & 0xffff; 321 322 if (snd_BUG_ON((offset & 3) || (len & 3))) 323 return -EINVAL; 324 dst = chip->region.idx[bank+1].remap_addr + offset; 325 len /= sizeof(u32); 326 327 /* writel already converts 32-bit value to right endianess */ 328 while (len-- > 0) { 329 writel(*src++, dst); 330 dst += sizeof(u32); 331 } 332 return 0; 333 } 334 335 static inline void memcpy_le32(void *dst, const void *src, unsigned int len) 336 { 337 #ifdef __LITTLE_ENDIAN 338 memcpy(dst, src, len); 339 #else 340 u32 *_dst = dst; 341 const __le32 *_src = src; 342 len /= 4; 343 while (len-- > 0) 344 *_dst++ = le32_to_cpu(*_src++); 345 #endif 346 } 347 348 #ifdef CONFIG_SND_CS46XX_NEW_DSP 349 350 static const char *module_names[CS46XX_DSP_MODULES] = { 351 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma" 352 }; 353 354 MODULE_FIRMWARE("cs46xx/cwc4630"); 355 MODULE_FIRMWARE("cs46xx/cwcasync"); 356 MODULE_FIRMWARE("cs46xx/cwcsnoop"); 357 MODULE_FIRMWARE("cs46xx/cwcbinhack"); 358 MODULE_FIRMWARE("cs46xx/cwcdma"); 359 360 static void free_module_desc(struct dsp_module_desc *module) 361 { 362 if (!module) 363 return; 364 kfree(module->module_name); 365 kfree(module->symbol_table.symbols); 366 if (module->segments) { 367 int i; 368 for (i = 0; i < module->nsegments; i++) 369 kfree(module->segments[i].data); 370 kfree(module->segments); 371 } 372 kfree(module); 373 } 374 375 /* firmware binary format: 376 * le32 nsymbols; 377 * struct { 378 * le32 address; 379 * char symbol_name[DSP_MAX_SYMBOL_NAME]; 380 * le32 symbol_type; 381 * } symbols[nsymbols]; 382 * le32 nsegments; 383 * struct { 384 * le32 segment_type; 385 * le32 offset; 386 * le32 size; 387 * le32 data[size]; 388 * } segments[nsegments]; 389 */ 390 391 static int load_firmware(struct snd_cs46xx *chip, 392 struct dsp_module_desc **module_ret, 393 const char *fw_name) 394 { 395 int i, err; 396 unsigned int nums, fwlen, fwsize; 397 const __le32 *fwdat; 398 struct dsp_module_desc *module = NULL; 399 const struct firmware *fw; 400 char fw_path[32]; 401 402 sprintf(fw_path, "cs46xx/%s", fw_name); 403 err = request_firmware(&fw, fw_path, &chip->pci->dev); 404 if (err < 0) 405 return err; 406 fwsize = fw->size / 4; 407 if (fwsize < 2) { 408 err = -EINVAL; 409 goto error; 410 } 411 412 err = -ENOMEM; 413 module = kzalloc(sizeof(*module), GFP_KERNEL); 414 if (!module) 415 goto error; 416 module->module_name = kstrdup(fw_name, GFP_KERNEL); 417 if (!module->module_name) 418 goto error; 419 420 fwlen = 0; 421 fwdat = (const __le32 *)fw->data; 422 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]); 423 if (nums >= 40) 424 goto error_inval; 425 module->symbol_table.symbols = 426 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL); 427 if (!module->symbol_table.symbols) 428 goto error; 429 for (i = 0; i < nums; i++) { 430 struct dsp_symbol_entry *entry = 431 &module->symbol_table.symbols[i]; 432 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize) 433 goto error_inval; 434 entry->address = le32_to_cpu(fwdat[fwlen++]); 435 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1); 436 fwlen += DSP_MAX_SYMBOL_NAME / 4; 437 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]); 438 } 439 440 if (fwlen >= fwsize) 441 goto error_inval; 442 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]); 443 if (nums > 10) 444 goto error_inval; 445 module->segments = 446 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL); 447 if (!module->segments) 448 goto error; 449 for (i = 0; i < nums; i++) { 450 struct dsp_segment_desc *entry = &module->segments[i]; 451 if (fwlen + 3 > fwsize) 452 goto error_inval; 453 entry->segment_type = le32_to_cpu(fwdat[fwlen++]); 454 entry->offset = le32_to_cpu(fwdat[fwlen++]); 455 entry->size = le32_to_cpu(fwdat[fwlen++]); 456 if (fwlen + entry->size > fwsize) 457 goto error_inval; 458 entry->data = kmalloc(entry->size * 4, GFP_KERNEL); 459 if (!entry->data) 460 goto error; 461 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4); 462 fwlen += entry->size; 463 } 464 465 *module_ret = module; 466 release_firmware(fw); 467 return 0; 468 469 error_inval: 470 err = -EINVAL; 471 error: 472 free_module_desc(module); 473 release_firmware(fw); 474 return err; 475 } 476 477 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, 478 unsigned long offset, 479 unsigned long len) 480 { 481 void __iomem *dst; 482 unsigned int bank = offset >> 16; 483 offset = offset & 0xffff; 484 485 if (snd_BUG_ON((offset & 3) || (len & 3))) 486 return -EINVAL; 487 dst = chip->region.idx[bank+1].remap_addr + offset; 488 len /= sizeof(u32); 489 490 /* writel already converts 32-bit value to right endianess */ 491 while (len-- > 0) { 492 writel(0, dst); 493 dst += sizeof(u32); 494 } 495 return 0; 496 } 497 498 #else /* old DSP image */ 499 500 struct ba1_struct { 501 struct { 502 u32 offset; 503 u32 size; 504 } memory[BA1_MEMORY_COUNT]; 505 u32 map[BA1_DWORD_SIZE]; 506 }; 507 508 MODULE_FIRMWARE("cs46xx/ba1"); 509 510 static int load_firmware(struct snd_cs46xx *chip) 511 { 512 const struct firmware *fw; 513 int i, size, err; 514 515 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev); 516 if (err < 0) 517 return err; 518 if (fw->size != sizeof(*chip->ba1)) { 519 err = -EINVAL; 520 goto error; 521 } 522 523 chip->ba1 = vmalloc(sizeof(*chip->ba1)); 524 if (!chip->ba1) { 525 err = -ENOMEM; 526 goto error; 527 } 528 529 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1)); 530 531 /* sanity check */ 532 size = 0; 533 for (i = 0; i < BA1_MEMORY_COUNT; i++) 534 size += chip->ba1->memory[i].size; 535 if (size > BA1_DWORD_SIZE * 4) 536 err = -EINVAL; 537 538 error: 539 release_firmware(fw); 540 return err; 541 } 542 543 int snd_cs46xx_download_image(struct snd_cs46xx *chip) 544 { 545 int idx, err; 546 unsigned int offset = 0; 547 struct ba1_struct *ba1 = chip->ba1; 548 549 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) { 550 err = snd_cs46xx_download(chip, 551 &ba1->map[offset], 552 ba1->memory[idx].offset, 553 ba1->memory[idx].size); 554 if (err < 0) 555 return err; 556 offset += ba1->memory[idx].size >> 2; 557 } 558 return 0; 559 } 560 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 561 562 /* 563 * Chip reset 564 */ 565 566 static void snd_cs46xx_reset(struct snd_cs46xx *chip) 567 { 568 int idx; 569 570 /* 571 * Write the reset bit of the SP control register. 572 */ 573 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP); 574 575 /* 576 * Write the control register. 577 */ 578 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN); 579 580 /* 581 * Clear the trap registers. 582 */ 583 for (idx = 0; idx < 8; idx++) { 584 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx); 585 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF); 586 } 587 snd_cs46xx_poke(chip, BA1_DREG, 0); 588 589 /* 590 * Set the frame timer to reflect the number of cycles per frame. 591 */ 592 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 593 } 594 595 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout) 596 { 597 u32 i, status = 0; 598 /* 599 * Make sure the previous FIFO write operation has completed. 600 */ 601 for(i = 0; i < 50; i++){ 602 status = snd_cs46xx_peekBA0(chip, BA0_SERBST); 603 604 if( !(status & SERBST_WBSY) ) 605 break; 606 607 mdelay(retry_timeout); 608 } 609 610 if(status & SERBST_WBSY) { 611 snd_printk(KERN_ERR "cs46xx: failure waiting for " 612 "FIFO command to complete\n"); 613 return -EINVAL; 614 } 615 616 return 0; 617 } 618 619 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip) 620 { 621 int idx, powerdown = 0; 622 unsigned int tmp; 623 624 /* 625 * See if the devices are powered down. If so, we must power them up first 626 * or they will not respond. 627 */ 628 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 629 if (!(tmp & CLKCR1_SWCE)) { 630 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 631 powerdown = 1; 632 } 633 634 /* 635 * We want to clear out the serial port FIFOs so we don't end up playing 636 * whatever random garbage happens to be in them. We fill the sample FIFOS 637 * with zero (silence). 638 */ 639 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0); 640 641 /* 642 * Fill all 256 sample FIFO locations. 643 */ 644 for (idx = 0; idx < 0xFF; idx++) { 645 /* 646 * Make sure the previous FIFO write operation has completed. 647 */ 648 if (cs46xx_wait_for_fifo(chip,1)) { 649 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx); 650 651 if (powerdown) 652 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 653 654 break; 655 } 656 /* 657 * Write the serial port FIFO index. 658 */ 659 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 660 /* 661 * Tell the serial port to load the new value into the FIFO location. 662 */ 663 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 664 } 665 /* 666 * Now, if we powered up the devices, then power them back down again. 667 * This is kinda ugly, but should never happen. 668 */ 669 if (powerdown) 670 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 671 } 672 673 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip) 674 { 675 int cnt; 676 677 /* 678 * Set the frame timer to reflect the number of cycles per frame. 679 */ 680 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 681 /* 682 * Turn on the run, run at frame, and DMA enable bits in the local copy of 683 * the SP control register. 684 */ 685 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 686 /* 687 * Wait until the run at frame bit resets itself in the SP control 688 * register. 689 */ 690 for (cnt = 0; cnt < 25; cnt++) { 691 udelay(50); 692 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)) 693 break; 694 } 695 696 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR) 697 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n"); 698 } 699 700 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip) 701 { 702 /* 703 * Turn off the run, run at frame, and DMA enable bits in the local copy of 704 * the SP control register. 705 */ 706 snd_cs46xx_poke(chip, BA1_SPCR, 0); 707 } 708 709 /* 710 * Sample rate routines 711 */ 712 713 #define GOF_PER_SEC 200 714 715 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 716 { 717 unsigned long flags; 718 unsigned int tmp1, tmp2; 719 unsigned int phiIncr; 720 unsigned int correctionPerGOF, correctionPerSec; 721 722 /* 723 * Compute the values used to drive the actual sample rate conversion. 724 * The following formulas are being computed, using inline assembly 725 * since we need to use 64 bit arithmetic to compute the values: 726 * 727 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 728 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 729 * GOF_PER_SEC) 730 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M 731 * GOF_PER_SEC * correctionPerGOF 732 * 733 * i.e. 734 * 735 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out) 736 * correctionPerGOF:correctionPerSec = 737 * dividend:remainder(ulOther / GOF_PER_SEC) 738 */ 739 tmp1 = rate << 16; 740 phiIncr = tmp1 / 48000; 741 tmp1 -= phiIncr * 48000; 742 tmp1 <<= 10; 743 phiIncr <<= 10; 744 tmp2 = tmp1 / 48000; 745 phiIncr += tmp2; 746 tmp1 -= tmp2 * 48000; 747 correctionPerGOF = tmp1 / GOF_PER_SEC; 748 tmp1 -= correctionPerGOF * GOF_PER_SEC; 749 correctionPerSec = tmp1; 750 751 /* 752 * Fill in the SampleRateConverter control block. 753 */ 754 spin_lock_irqsave(&chip->reg_lock, flags); 755 snd_cs46xx_poke(chip, BA1_PSRC, 756 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 757 snd_cs46xx_poke(chip, BA1_PPI, phiIncr); 758 spin_unlock_irqrestore(&chip->reg_lock, flags); 759 } 760 761 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 762 { 763 unsigned long flags; 764 unsigned int phiIncr, coeffIncr, tmp1, tmp2; 765 unsigned int correctionPerGOF, correctionPerSec, initialDelay; 766 unsigned int frameGroupLength, cnt; 767 768 /* 769 * We can only decimate by up to a factor of 1/9th the hardware rate. 770 * Correct the value if an attempt is made to stray outside that limit. 771 */ 772 if ((rate * 9) < 48000) 773 rate = 48000 / 9; 774 775 /* 776 * We can not capture at at rate greater than the Input Rate (48000). 777 * Return an error if an attempt is made to stray outside that limit. 778 */ 779 if (rate > 48000) 780 rate = 48000; 781 782 /* 783 * Compute the values used to drive the actual sample rate conversion. 784 * The following formulas are being computed, using inline assembly 785 * since we need to use 64 bit arithmetic to compute the values: 786 * 787 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in) 788 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 789 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 790 * GOF_PER_SEC) 791 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr - 792 * GOF_PER_SEC * correctionPerGOF 793 * initialDelay = ceil((24 * Fs,in) / Fs,out) 794 * 795 * i.e. 796 * 797 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in)) 798 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out) 799 * correctionPerGOF:correctionPerSec = 800 * dividend:remainder(ulOther / GOF_PER_SEC) 801 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out) 802 */ 803 804 tmp1 = rate << 16; 805 coeffIncr = tmp1 / 48000; 806 tmp1 -= coeffIncr * 48000; 807 tmp1 <<= 7; 808 coeffIncr <<= 7; 809 coeffIncr += tmp1 / 48000; 810 coeffIncr ^= 0xFFFFFFFF; 811 coeffIncr++; 812 tmp1 = 48000 << 16; 813 phiIncr = tmp1 / rate; 814 tmp1 -= phiIncr * rate; 815 tmp1 <<= 10; 816 phiIncr <<= 10; 817 tmp2 = tmp1 / rate; 818 phiIncr += tmp2; 819 tmp1 -= tmp2 * rate; 820 correctionPerGOF = tmp1 / GOF_PER_SEC; 821 tmp1 -= correctionPerGOF * GOF_PER_SEC; 822 correctionPerSec = tmp1; 823 initialDelay = ((48000 * 24) + rate - 1) / rate; 824 825 /* 826 * Fill in the VariDecimate control block. 827 */ 828 spin_lock_irqsave(&chip->reg_lock, flags); 829 snd_cs46xx_poke(chip, BA1_CSRC, 830 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 831 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr); 832 snd_cs46xx_poke(chip, BA1_CD, 833 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80); 834 snd_cs46xx_poke(chip, BA1_CPI, phiIncr); 835 spin_unlock_irqrestore(&chip->reg_lock, flags); 836 837 /* 838 * Figure out the frame group length for the write back task. Basically, 839 * this is just the factors of 24000 (2^6*3*5^3) that are not present in 840 * the output sample rate. 841 */ 842 frameGroupLength = 1; 843 for (cnt = 2; cnt <= 64; cnt *= 2) { 844 if (((rate / cnt) * cnt) != rate) 845 frameGroupLength *= 2; 846 } 847 if (((rate / 3) * 3) != rate) { 848 frameGroupLength *= 3; 849 } 850 for (cnt = 5; cnt <= 125; cnt *= 5) { 851 if (((rate / cnt) * cnt) != rate) 852 frameGroupLength *= 5; 853 } 854 855 /* 856 * Fill in the WriteBack control block. 857 */ 858 spin_lock_irqsave(&chip->reg_lock, flags); 859 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength); 860 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength)); 861 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF); 862 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000)); 863 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF); 864 spin_unlock_irqrestore(&chip->reg_lock, flags); 865 } 866 867 /* 868 * PCM part 869 */ 870 871 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream, 872 struct snd_pcm_indirect *rec, size_t bytes) 873 { 874 struct snd_pcm_runtime *runtime = substream->runtime; 875 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 876 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes); 877 } 878 879 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream) 880 { 881 struct snd_pcm_runtime *runtime = substream->runtime; 882 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 883 snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy); 884 return 0; 885 } 886 887 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream, 888 struct snd_pcm_indirect *rec, size_t bytes) 889 { 890 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 891 struct snd_pcm_runtime *runtime = substream->runtime; 892 memcpy(runtime->dma_area + rec->sw_data, 893 chip->capt.hw_buf.area + rec->hw_data, bytes); 894 } 895 896 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream) 897 { 898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 899 snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy); 900 return 0; 901 } 902 903 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream) 904 { 905 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 906 size_t ptr; 907 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 908 909 if (snd_BUG_ON(!cpcm->pcm_channel)) 910 return -ENXIO; 911 912 #ifdef CONFIG_SND_CS46XX_NEW_DSP 913 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 914 #else 915 ptr = snd_cs46xx_peek(chip, BA1_PBA); 916 #endif 917 ptr -= cpcm->hw_buf.addr; 918 return ptr >> cpcm->shift; 919 } 920 921 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream) 922 { 923 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 924 size_t ptr; 925 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 926 927 #ifdef CONFIG_SND_CS46XX_NEW_DSP 928 if (snd_BUG_ON(!cpcm->pcm_channel)) 929 return -ENXIO; 930 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 931 #else 932 ptr = snd_cs46xx_peek(chip, BA1_PBA); 933 #endif 934 ptr -= cpcm->hw_buf.addr; 935 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr); 936 } 937 938 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream) 939 { 940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 942 return ptr >> chip->capt.shift; 943 } 944 945 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream) 946 { 947 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 948 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 949 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr); 950 } 951 952 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream, 953 int cmd) 954 { 955 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 956 /*struct snd_pcm_runtime *runtime = substream->runtime;*/ 957 int result = 0; 958 959 #ifdef CONFIG_SND_CS46XX_NEW_DSP 960 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 961 if (! cpcm->pcm_channel) { 962 return -ENXIO; 963 } 964 #endif 965 switch (cmd) { 966 case SNDRV_PCM_TRIGGER_START: 967 case SNDRV_PCM_TRIGGER_RESUME: 968 #ifdef CONFIG_SND_CS46XX_NEW_DSP 969 /* magic value to unmute PCM stream playback volume */ 970 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 971 SCBVolumeCtrl) << 2, 0x80008000); 972 973 if (cpcm->pcm_channel->unlinked) 974 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel); 975 976 if (substream->runtime->periods != CS46XX_FRAGS) 977 snd_cs46xx_playback_transfer(substream); 978 #else 979 spin_lock(&chip->reg_lock); 980 if (substream->runtime->periods != CS46XX_FRAGS) 981 snd_cs46xx_playback_transfer(substream); 982 { unsigned int tmp; 983 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 984 tmp &= 0x0000ffff; 985 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp); 986 } 987 spin_unlock(&chip->reg_lock); 988 #endif 989 break; 990 case SNDRV_PCM_TRIGGER_STOP: 991 case SNDRV_PCM_TRIGGER_SUSPEND: 992 #ifdef CONFIG_SND_CS46XX_NEW_DSP 993 /* magic mute channel */ 994 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 995 SCBVolumeCtrl) << 2, 0xffffffff); 996 997 if (!cpcm->pcm_channel->unlinked) 998 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel); 999 #else 1000 spin_lock(&chip->reg_lock); 1001 { unsigned int tmp; 1002 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 1003 tmp &= 0x0000ffff; 1004 snd_cs46xx_poke(chip, BA1_PCTL, tmp); 1005 } 1006 spin_unlock(&chip->reg_lock); 1007 #endif 1008 break; 1009 default: 1010 result = -EINVAL; 1011 break; 1012 } 1013 1014 return result; 1015 } 1016 1017 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream, 1018 int cmd) 1019 { 1020 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1021 unsigned int tmp; 1022 int result = 0; 1023 1024 spin_lock(&chip->reg_lock); 1025 switch (cmd) { 1026 case SNDRV_PCM_TRIGGER_START: 1027 case SNDRV_PCM_TRIGGER_RESUME: 1028 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 1029 tmp &= 0xffff0000; 1030 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp); 1031 break; 1032 case SNDRV_PCM_TRIGGER_STOP: 1033 case SNDRV_PCM_TRIGGER_SUSPEND: 1034 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 1035 tmp &= 0xffff0000; 1036 snd_cs46xx_poke(chip, BA1_CCTL, tmp); 1037 break; 1038 default: 1039 result = -EINVAL; 1040 break; 1041 } 1042 spin_unlock(&chip->reg_lock); 1043 1044 return result; 1045 } 1046 1047 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1048 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm, 1049 int sample_rate) 1050 { 1051 1052 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */ 1053 if ( cpcm->pcm_channel == NULL) { 1054 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, 1055 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id); 1056 if (cpcm->pcm_channel == NULL) { 1057 snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n"); 1058 return -ENOMEM; 1059 } 1060 cpcm->pcm_channel->sample_rate = sample_rate; 1061 } else 1062 /* if sample rate is changed */ 1063 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) { 1064 int unlinked = cpcm->pcm_channel->unlinked; 1065 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel); 1066 1067 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm, 1068 cpcm->hw_buf.addr, 1069 cpcm->pcm_channel_id)) == NULL) { 1070 snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n"); 1071 return -ENOMEM; 1072 } 1073 1074 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel); 1075 cpcm->pcm_channel->sample_rate = sample_rate; 1076 } 1077 1078 return 0; 1079 } 1080 #endif 1081 1082 1083 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream, 1084 struct snd_pcm_hw_params *hw_params) 1085 { 1086 struct snd_pcm_runtime *runtime = substream->runtime; 1087 struct snd_cs46xx_pcm *cpcm; 1088 int err; 1089 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1090 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1091 int sample_rate = params_rate(hw_params); 1092 int period_size = params_period_bytes(hw_params); 1093 #endif 1094 cpcm = runtime->private_data; 1095 1096 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1097 if (snd_BUG_ON(!sample_rate)) 1098 return -ENXIO; 1099 1100 mutex_lock(&chip->spos_mutex); 1101 1102 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) { 1103 mutex_unlock(&chip->spos_mutex); 1104 return -ENXIO; 1105 } 1106 1107 snd_BUG_ON(!cpcm->pcm_channel); 1108 if (!cpcm->pcm_channel) { 1109 mutex_unlock(&chip->spos_mutex); 1110 return -ENXIO; 1111 } 1112 1113 1114 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) { 1115 mutex_unlock(&chip->spos_mutex); 1116 return -EINVAL; 1117 } 1118 1119 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n", 1120 period_size, params_periods(hw_params), 1121 params_buffer_bytes(hw_params)); 1122 #endif 1123 1124 if (params_periods(hw_params) == CS46XX_FRAGS) { 1125 if (runtime->dma_area != cpcm->hw_buf.area) 1126 snd_pcm_lib_free_pages(substream); 1127 runtime->dma_area = cpcm->hw_buf.area; 1128 runtime->dma_addr = cpcm->hw_buf.addr; 1129 runtime->dma_bytes = cpcm->hw_buf.bytes; 1130 1131 1132 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1133 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 1134 substream->ops = &snd_cs46xx_playback_ops; 1135 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 1136 substream->ops = &snd_cs46xx_playback_rear_ops; 1137 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 1138 substream->ops = &snd_cs46xx_playback_clfe_ops; 1139 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 1140 substream->ops = &snd_cs46xx_playback_iec958_ops; 1141 } else { 1142 snd_BUG(); 1143 } 1144 #else 1145 substream->ops = &snd_cs46xx_playback_ops; 1146 #endif 1147 1148 } else { 1149 if (runtime->dma_area == cpcm->hw_buf.area) { 1150 runtime->dma_area = NULL; 1151 runtime->dma_addr = 0; 1152 runtime->dma_bytes = 0; 1153 } 1154 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) { 1155 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1156 mutex_unlock(&chip->spos_mutex); 1157 #endif 1158 return err; 1159 } 1160 1161 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1162 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 1163 substream->ops = &snd_cs46xx_playback_indirect_ops; 1164 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 1165 substream->ops = &snd_cs46xx_playback_indirect_rear_ops; 1166 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 1167 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops; 1168 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 1169 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops; 1170 } else { 1171 snd_BUG(); 1172 } 1173 #else 1174 substream->ops = &snd_cs46xx_playback_indirect_ops; 1175 #endif 1176 1177 } 1178 1179 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1180 mutex_unlock(&chip->spos_mutex); 1181 #endif 1182 1183 return 0; 1184 } 1185 1186 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream) 1187 { 1188 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/ 1189 struct snd_pcm_runtime *runtime = substream->runtime; 1190 struct snd_cs46xx_pcm *cpcm; 1191 1192 cpcm = runtime->private_data; 1193 1194 /* if play_back open fails, then this function 1195 is called and cpcm can actually be NULL here */ 1196 if (!cpcm) return -ENXIO; 1197 1198 if (runtime->dma_area != cpcm->hw_buf.area) 1199 snd_pcm_lib_free_pages(substream); 1200 1201 runtime->dma_area = NULL; 1202 runtime->dma_addr = 0; 1203 runtime->dma_bytes = 0; 1204 1205 return 0; 1206 } 1207 1208 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream) 1209 { 1210 unsigned int tmp; 1211 unsigned int pfie; 1212 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1213 struct snd_pcm_runtime *runtime = substream->runtime; 1214 struct snd_cs46xx_pcm *cpcm; 1215 1216 cpcm = runtime->private_data; 1217 1218 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1219 if (snd_BUG_ON(!cpcm->pcm_channel)) 1220 return -ENXIO; 1221 1222 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 ); 1223 pfie &= ~0x0000f03f; 1224 #else 1225 /* old dsp */ 1226 pfie = snd_cs46xx_peek(chip, BA1_PFIE); 1227 pfie &= ~0x0000f03f; 1228 #endif 1229 1230 cpcm->shift = 2; 1231 /* if to convert from stereo to mono */ 1232 if (runtime->channels == 1) { 1233 cpcm->shift--; 1234 pfie |= 0x00002000; 1235 } 1236 /* if to convert from 8 bit to 16 bit */ 1237 if (snd_pcm_format_width(runtime->format) == 8) { 1238 cpcm->shift--; 1239 pfie |= 0x00001000; 1240 } 1241 /* if to convert to unsigned */ 1242 if (snd_pcm_format_unsigned(runtime->format)) 1243 pfie |= 0x00008000; 1244 1245 /* Never convert byte order when sample stream is 8 bit */ 1246 if (snd_pcm_format_width(runtime->format) != 8) { 1247 /* convert from big endian to little endian */ 1248 if (snd_pcm_format_big_endian(runtime->format)) 1249 pfie |= 0x00004000; 1250 } 1251 1252 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec)); 1253 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1254 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift; 1255 1256 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1257 1258 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2); 1259 tmp &= ~0x000003ff; 1260 tmp |= (4 << cpcm->shift) - 1; 1261 /* playback transaction count register */ 1262 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp); 1263 1264 /* playback format && interrupt enable */ 1265 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot); 1266 #else 1267 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr); 1268 tmp = snd_cs46xx_peek(chip, BA1_PDTC); 1269 tmp &= ~0x000003ff; 1270 tmp |= (4 << cpcm->shift) - 1; 1271 snd_cs46xx_poke(chip, BA1_PDTC, tmp); 1272 snd_cs46xx_poke(chip, BA1_PFIE, pfie); 1273 snd_cs46xx_set_play_sample_rate(chip, runtime->rate); 1274 #endif 1275 1276 return 0; 1277 } 1278 1279 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream, 1280 struct snd_pcm_hw_params *hw_params) 1281 { 1282 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1283 struct snd_pcm_runtime *runtime = substream->runtime; 1284 int err; 1285 1286 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1287 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params)); 1288 #endif 1289 if (runtime->periods == CS46XX_FRAGS) { 1290 if (runtime->dma_area != chip->capt.hw_buf.area) 1291 snd_pcm_lib_free_pages(substream); 1292 runtime->dma_area = chip->capt.hw_buf.area; 1293 runtime->dma_addr = chip->capt.hw_buf.addr; 1294 runtime->dma_bytes = chip->capt.hw_buf.bytes; 1295 substream->ops = &snd_cs46xx_capture_ops; 1296 } else { 1297 if (runtime->dma_area == chip->capt.hw_buf.area) { 1298 runtime->dma_area = NULL; 1299 runtime->dma_addr = 0; 1300 runtime->dma_bytes = 0; 1301 } 1302 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) 1303 return err; 1304 substream->ops = &snd_cs46xx_capture_indirect_ops; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream) 1311 { 1312 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1313 struct snd_pcm_runtime *runtime = substream->runtime; 1314 1315 if (runtime->dma_area != chip->capt.hw_buf.area) 1316 snd_pcm_lib_free_pages(substream); 1317 runtime->dma_area = NULL; 1318 runtime->dma_addr = 0; 1319 runtime->dma_bytes = 0; 1320 1321 return 0; 1322 } 1323 1324 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream) 1325 { 1326 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1327 struct snd_pcm_runtime *runtime = substream->runtime; 1328 1329 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr); 1330 chip->capt.shift = 2; 1331 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec)); 1332 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1333 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2; 1334 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate); 1335 1336 return 0; 1337 } 1338 1339 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id) 1340 { 1341 struct snd_cs46xx *chip = dev_id; 1342 u32 status1; 1343 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1344 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1345 u32 status2; 1346 int i; 1347 struct snd_cs46xx_pcm *cpcm = NULL; 1348 #endif 1349 1350 /* 1351 * Read the Interrupt Status Register to clear the interrupt 1352 */ 1353 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR); 1354 if ((status1 & 0x7fffffff) == 0) { 1355 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1356 return IRQ_NONE; 1357 } 1358 1359 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1360 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0); 1361 1362 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) { 1363 if (i <= 15) { 1364 if ( status1 & (1 << i) ) { 1365 if (i == CS46XX_DSP_CAPTURE_CHANNEL) { 1366 if (chip->capt.substream) 1367 snd_pcm_period_elapsed(chip->capt.substream); 1368 } else { 1369 if (ins->pcm_channels[i].active && 1370 ins->pcm_channels[i].private_data && 1371 !ins->pcm_channels[i].unlinked) { 1372 cpcm = ins->pcm_channels[i].private_data; 1373 snd_pcm_period_elapsed(cpcm->substream); 1374 } 1375 } 1376 } 1377 } else { 1378 if ( status2 & (1 << (i - 16))) { 1379 if (ins->pcm_channels[i].active && 1380 ins->pcm_channels[i].private_data && 1381 !ins->pcm_channels[i].unlinked) { 1382 cpcm = ins->pcm_channels[i].private_data; 1383 snd_pcm_period_elapsed(cpcm->substream); 1384 } 1385 } 1386 } 1387 } 1388 1389 #else 1390 /* old dsp */ 1391 if ((status1 & HISR_VC0) && chip->playback_pcm) { 1392 if (chip->playback_pcm->substream) 1393 snd_pcm_period_elapsed(chip->playback_pcm->substream); 1394 } 1395 if ((status1 & HISR_VC1) && chip->pcm) { 1396 if (chip->capt.substream) 1397 snd_pcm_period_elapsed(chip->capt.substream); 1398 } 1399 #endif 1400 1401 if ((status1 & HISR_MIDI) && chip->rmidi) { 1402 unsigned char c; 1403 1404 spin_lock(&chip->reg_lock); 1405 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) { 1406 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP); 1407 if ((chip->midcr & MIDCR_RIE) == 0) 1408 continue; 1409 snd_rawmidi_receive(chip->midi_input, &c, 1); 1410 } 1411 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 1412 if ((chip->midcr & MIDCR_TIE) == 0) 1413 break; 1414 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1415 chip->midcr &= ~MIDCR_TIE; 1416 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1417 break; 1418 } 1419 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c); 1420 } 1421 spin_unlock(&chip->reg_lock); 1422 } 1423 /* 1424 * EOI to the PCI part....reenables interrupts 1425 */ 1426 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1427 1428 return IRQ_HANDLED; 1429 } 1430 1431 static struct snd_pcm_hardware snd_cs46xx_playback = 1432 { 1433 .info = (SNDRV_PCM_INFO_MMAP | 1434 SNDRV_PCM_INFO_INTERLEAVED | 1435 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1436 /*SNDRV_PCM_INFO_RESUME*/), 1437 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | 1438 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 1439 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE), 1440 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1441 .rate_min = 5500, 1442 .rate_max = 48000, 1443 .channels_min = 1, 1444 .channels_max = 2, 1445 .buffer_bytes_max = (256 * 1024), 1446 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1447 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1448 .periods_min = CS46XX_FRAGS, 1449 .periods_max = 1024, 1450 .fifo_size = 0, 1451 }; 1452 1453 static struct snd_pcm_hardware snd_cs46xx_capture = 1454 { 1455 .info = (SNDRV_PCM_INFO_MMAP | 1456 SNDRV_PCM_INFO_INTERLEAVED | 1457 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1458 /*SNDRV_PCM_INFO_RESUME*/), 1459 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1460 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1461 .rate_min = 5500, 1462 .rate_max = 48000, 1463 .channels_min = 2, 1464 .channels_max = 2, 1465 .buffer_bytes_max = (256 * 1024), 1466 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1467 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1468 .periods_min = CS46XX_FRAGS, 1469 .periods_max = 1024, 1470 .fifo_size = 0, 1471 }; 1472 1473 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1474 1475 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 }; 1476 1477 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = { 1478 .count = ARRAY_SIZE(period_sizes), 1479 .list = period_sizes, 1480 .mask = 0 1481 }; 1482 1483 #endif 1484 1485 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime) 1486 { 1487 kfree(runtime->private_data); 1488 } 1489 1490 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id) 1491 { 1492 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1493 struct snd_cs46xx_pcm * cpcm; 1494 struct snd_pcm_runtime *runtime = substream->runtime; 1495 1496 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL); 1497 if (cpcm == NULL) 1498 return -ENOMEM; 1499 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1500 PAGE_SIZE, &cpcm->hw_buf) < 0) { 1501 kfree(cpcm); 1502 return -ENOMEM; 1503 } 1504 1505 runtime->hw = snd_cs46xx_playback; 1506 runtime->private_data = cpcm; 1507 runtime->private_free = snd_cs46xx_pcm_free_substream; 1508 1509 cpcm->substream = substream; 1510 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1511 mutex_lock(&chip->spos_mutex); 1512 cpcm->pcm_channel = NULL; 1513 cpcm->pcm_channel_id = pcm_channel_id; 1514 1515 1516 snd_pcm_hw_constraint_list(runtime, 0, 1517 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1518 &hw_constraints_period_sizes); 1519 1520 mutex_unlock(&chip->spos_mutex); 1521 #else 1522 chip->playback_pcm = cpcm; /* HACK */ 1523 #endif 1524 1525 if (chip->accept_valid) 1526 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1527 chip->active_ctrl(chip, 1); 1528 1529 return 0; 1530 } 1531 1532 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream) 1533 { 1534 snd_printdd("open front channel\n"); 1535 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL); 1536 } 1537 1538 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1539 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream) 1540 { 1541 snd_printdd("open rear channel\n"); 1542 1543 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL); 1544 } 1545 1546 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream) 1547 { 1548 snd_printdd("open center - LFE channel\n"); 1549 1550 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL); 1551 } 1552 1553 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream) 1554 { 1555 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1556 1557 snd_printdd("open raw iec958 channel\n"); 1558 1559 mutex_lock(&chip->spos_mutex); 1560 cs46xx_iec958_pre_open (chip); 1561 mutex_unlock(&chip->spos_mutex); 1562 1563 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL); 1564 } 1565 1566 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream); 1567 1568 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream) 1569 { 1570 int err; 1571 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1572 1573 snd_printdd("close raw iec958 channel\n"); 1574 1575 err = snd_cs46xx_playback_close(substream); 1576 1577 mutex_lock(&chip->spos_mutex); 1578 cs46xx_iec958_post_close (chip); 1579 mutex_unlock(&chip->spos_mutex); 1580 1581 return err; 1582 } 1583 #endif 1584 1585 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream) 1586 { 1587 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1588 1589 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1590 PAGE_SIZE, &chip->capt.hw_buf) < 0) 1591 return -ENOMEM; 1592 chip->capt.substream = substream; 1593 substream->runtime->hw = snd_cs46xx_capture; 1594 1595 if (chip->accept_valid) 1596 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1597 1598 chip->active_ctrl(chip, 1); 1599 1600 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1601 snd_pcm_hw_constraint_list(substream->runtime, 0, 1602 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1603 &hw_constraints_period_sizes); 1604 #endif 1605 return 0; 1606 } 1607 1608 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream) 1609 { 1610 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1611 struct snd_pcm_runtime *runtime = substream->runtime; 1612 struct snd_cs46xx_pcm * cpcm; 1613 1614 cpcm = runtime->private_data; 1615 1616 /* when playback_open fails, then cpcm can be NULL */ 1617 if (!cpcm) return -ENXIO; 1618 1619 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1620 mutex_lock(&chip->spos_mutex); 1621 if (cpcm->pcm_channel) { 1622 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel); 1623 cpcm->pcm_channel = NULL; 1624 } 1625 mutex_unlock(&chip->spos_mutex); 1626 #else 1627 chip->playback_pcm = NULL; 1628 #endif 1629 1630 cpcm->substream = NULL; 1631 snd_dma_free_pages(&cpcm->hw_buf); 1632 chip->active_ctrl(chip, -1); 1633 1634 return 0; 1635 } 1636 1637 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) 1638 { 1639 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1640 1641 chip->capt.substream = NULL; 1642 snd_dma_free_pages(&chip->capt.hw_buf); 1643 chip->active_ctrl(chip, -1); 1644 1645 return 0; 1646 } 1647 1648 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1649 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { 1650 .open = snd_cs46xx_playback_open_rear, 1651 .close = snd_cs46xx_playback_close, 1652 .ioctl = snd_pcm_lib_ioctl, 1653 .hw_params = snd_cs46xx_playback_hw_params, 1654 .hw_free = snd_cs46xx_playback_hw_free, 1655 .prepare = snd_cs46xx_playback_prepare, 1656 .trigger = snd_cs46xx_playback_trigger, 1657 .pointer = snd_cs46xx_playback_direct_pointer, 1658 }; 1659 1660 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { 1661 .open = snd_cs46xx_playback_open_rear, 1662 .close = snd_cs46xx_playback_close, 1663 .ioctl = snd_pcm_lib_ioctl, 1664 .hw_params = snd_cs46xx_playback_hw_params, 1665 .hw_free = snd_cs46xx_playback_hw_free, 1666 .prepare = snd_cs46xx_playback_prepare, 1667 .trigger = snd_cs46xx_playback_trigger, 1668 .pointer = snd_cs46xx_playback_indirect_pointer, 1669 .ack = snd_cs46xx_playback_transfer, 1670 }; 1671 1672 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { 1673 .open = snd_cs46xx_playback_open_clfe, 1674 .close = snd_cs46xx_playback_close, 1675 .ioctl = snd_pcm_lib_ioctl, 1676 .hw_params = snd_cs46xx_playback_hw_params, 1677 .hw_free = snd_cs46xx_playback_hw_free, 1678 .prepare = snd_cs46xx_playback_prepare, 1679 .trigger = snd_cs46xx_playback_trigger, 1680 .pointer = snd_cs46xx_playback_direct_pointer, 1681 }; 1682 1683 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { 1684 .open = snd_cs46xx_playback_open_clfe, 1685 .close = snd_cs46xx_playback_close, 1686 .ioctl = snd_pcm_lib_ioctl, 1687 .hw_params = snd_cs46xx_playback_hw_params, 1688 .hw_free = snd_cs46xx_playback_hw_free, 1689 .prepare = snd_cs46xx_playback_prepare, 1690 .trigger = snd_cs46xx_playback_trigger, 1691 .pointer = snd_cs46xx_playback_indirect_pointer, 1692 .ack = snd_cs46xx_playback_transfer, 1693 }; 1694 1695 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { 1696 .open = snd_cs46xx_playback_open_iec958, 1697 .close = snd_cs46xx_playback_close_iec958, 1698 .ioctl = snd_pcm_lib_ioctl, 1699 .hw_params = snd_cs46xx_playback_hw_params, 1700 .hw_free = snd_cs46xx_playback_hw_free, 1701 .prepare = snd_cs46xx_playback_prepare, 1702 .trigger = snd_cs46xx_playback_trigger, 1703 .pointer = snd_cs46xx_playback_direct_pointer, 1704 }; 1705 1706 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { 1707 .open = snd_cs46xx_playback_open_iec958, 1708 .close = snd_cs46xx_playback_close_iec958, 1709 .ioctl = snd_pcm_lib_ioctl, 1710 .hw_params = snd_cs46xx_playback_hw_params, 1711 .hw_free = snd_cs46xx_playback_hw_free, 1712 .prepare = snd_cs46xx_playback_prepare, 1713 .trigger = snd_cs46xx_playback_trigger, 1714 .pointer = snd_cs46xx_playback_indirect_pointer, 1715 .ack = snd_cs46xx_playback_transfer, 1716 }; 1717 1718 #endif 1719 1720 static struct snd_pcm_ops snd_cs46xx_playback_ops = { 1721 .open = snd_cs46xx_playback_open, 1722 .close = snd_cs46xx_playback_close, 1723 .ioctl = snd_pcm_lib_ioctl, 1724 .hw_params = snd_cs46xx_playback_hw_params, 1725 .hw_free = snd_cs46xx_playback_hw_free, 1726 .prepare = snd_cs46xx_playback_prepare, 1727 .trigger = snd_cs46xx_playback_trigger, 1728 .pointer = snd_cs46xx_playback_direct_pointer, 1729 }; 1730 1731 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { 1732 .open = snd_cs46xx_playback_open, 1733 .close = snd_cs46xx_playback_close, 1734 .ioctl = snd_pcm_lib_ioctl, 1735 .hw_params = snd_cs46xx_playback_hw_params, 1736 .hw_free = snd_cs46xx_playback_hw_free, 1737 .prepare = snd_cs46xx_playback_prepare, 1738 .trigger = snd_cs46xx_playback_trigger, 1739 .pointer = snd_cs46xx_playback_indirect_pointer, 1740 .ack = snd_cs46xx_playback_transfer, 1741 }; 1742 1743 static struct snd_pcm_ops snd_cs46xx_capture_ops = { 1744 .open = snd_cs46xx_capture_open, 1745 .close = snd_cs46xx_capture_close, 1746 .ioctl = snd_pcm_lib_ioctl, 1747 .hw_params = snd_cs46xx_capture_hw_params, 1748 .hw_free = snd_cs46xx_capture_hw_free, 1749 .prepare = snd_cs46xx_capture_prepare, 1750 .trigger = snd_cs46xx_capture_trigger, 1751 .pointer = snd_cs46xx_capture_direct_pointer, 1752 }; 1753 1754 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { 1755 .open = snd_cs46xx_capture_open, 1756 .close = snd_cs46xx_capture_close, 1757 .ioctl = snd_pcm_lib_ioctl, 1758 .hw_params = snd_cs46xx_capture_hw_params, 1759 .hw_free = snd_cs46xx_capture_hw_free, 1760 .prepare = snd_cs46xx_capture_prepare, 1761 .trigger = snd_cs46xx_capture_trigger, 1762 .pointer = snd_cs46xx_capture_indirect_pointer, 1763 .ack = snd_cs46xx_capture_transfer, 1764 }; 1765 1766 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1767 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1) 1768 #else 1769 #define MAX_PLAYBACK_CHANNELS 1 1770 #endif 1771 1772 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm) 1773 { 1774 struct snd_pcm *pcm; 1775 int err; 1776 1777 if (rpcm) 1778 *rpcm = NULL; 1779 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0) 1780 return err; 1781 1782 pcm->private_data = chip; 1783 1784 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops); 1785 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops); 1786 1787 /* global setup */ 1788 pcm->info_flags = 0; 1789 strcpy(pcm->name, "CS46xx"); 1790 chip->pcm = pcm; 1791 1792 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1793 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1794 1795 if (rpcm) 1796 *rpcm = pcm; 1797 1798 return 0; 1799 } 1800 1801 1802 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1803 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, 1804 struct snd_pcm **rpcm) 1805 { 1806 struct snd_pcm *pcm; 1807 int err; 1808 1809 if (rpcm) 1810 *rpcm = NULL; 1811 1812 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) 1813 return err; 1814 1815 pcm->private_data = chip; 1816 1817 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops); 1818 1819 /* global setup */ 1820 pcm->info_flags = 0; 1821 strcpy(pcm->name, "CS46xx - Rear"); 1822 chip->pcm_rear = pcm; 1823 1824 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1825 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1826 1827 if (rpcm) 1828 *rpcm = pcm; 1829 1830 return 0; 1831 } 1832 1833 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, 1834 struct snd_pcm **rpcm) 1835 { 1836 struct snd_pcm *pcm; 1837 int err; 1838 1839 if (rpcm) 1840 *rpcm = NULL; 1841 1842 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0) 1843 return err; 1844 1845 pcm->private_data = chip; 1846 1847 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops); 1848 1849 /* global setup */ 1850 pcm->info_flags = 0; 1851 strcpy(pcm->name, "CS46xx - Center LFE"); 1852 chip->pcm_center_lfe = pcm; 1853 1854 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1855 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1856 1857 if (rpcm) 1858 *rpcm = pcm; 1859 1860 return 0; 1861 } 1862 1863 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, 1864 struct snd_pcm **rpcm) 1865 { 1866 struct snd_pcm *pcm; 1867 int err; 1868 1869 if (rpcm) 1870 *rpcm = NULL; 1871 1872 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0) 1873 return err; 1874 1875 pcm->private_data = chip; 1876 1877 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops); 1878 1879 /* global setup */ 1880 pcm->info_flags = 0; 1881 strcpy(pcm->name, "CS46xx - IEC958"); 1882 chip->pcm_rear = pcm; 1883 1884 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1885 snd_dma_pci_data(chip->pci), 64*1024, 256*1024); 1886 1887 if (rpcm) 1888 *rpcm = pcm; 1889 1890 return 0; 1891 } 1892 #endif 1893 1894 /* 1895 * Mixer routines 1896 */ 1897 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1898 { 1899 struct snd_cs46xx *chip = bus->private_data; 1900 1901 chip->ac97_bus = NULL; 1902 } 1903 1904 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97) 1905 { 1906 struct snd_cs46xx *chip = ac97->private_data; 1907 1908 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] && 1909 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])) 1910 return; 1911 1912 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) { 1913 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL; 1914 chip->eapd_switch = NULL; 1915 } 1916 else 1917 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL; 1918 } 1919 1920 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol, 1921 struct snd_ctl_elem_info *uinfo) 1922 { 1923 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1924 uinfo->count = 2; 1925 uinfo->value.integer.min = 0; 1926 uinfo->value.integer.max = 0x7fff; 1927 return 0; 1928 } 1929 1930 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1931 { 1932 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1933 int reg = kcontrol->private_value; 1934 unsigned int val = snd_cs46xx_peek(chip, reg); 1935 ucontrol->value.integer.value[0] = 0xffff - (val >> 16); 1936 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff); 1937 return 0; 1938 } 1939 1940 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1941 { 1942 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1943 int reg = kcontrol->private_value; 1944 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | 1945 (0xffff - ucontrol->value.integer.value[1])); 1946 unsigned int old = snd_cs46xx_peek(chip, reg); 1947 int change = (old != val); 1948 1949 if (change) { 1950 snd_cs46xx_poke(chip, reg, val); 1951 } 1952 1953 return change; 1954 } 1955 1956 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1957 1958 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1959 { 1960 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1961 1962 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left; 1963 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right; 1964 1965 return 0; 1966 } 1967 1968 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1969 { 1970 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1971 int change = 0; 1972 1973 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] || 1974 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) { 1975 cs46xx_dsp_set_dac_volume(chip, 1976 ucontrol->value.integer.value[0], 1977 ucontrol->value.integer.value[1]); 1978 change = 1; 1979 } 1980 1981 return change; 1982 } 1983 1984 #if 0 1985 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1986 { 1987 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1988 1989 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left; 1990 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right; 1991 return 0; 1992 } 1993 1994 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1995 { 1996 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1997 int change = 0; 1998 1999 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] || 2000 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) { 2001 cs46xx_dsp_set_iec958_volume (chip, 2002 ucontrol->value.integer.value[0], 2003 ucontrol->value.integer.value[1]); 2004 change = 1; 2005 } 2006 2007 return change; 2008 } 2009 #endif 2010 2011 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info 2012 2013 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol, 2014 struct snd_ctl_elem_value *ucontrol) 2015 { 2016 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2017 int reg = kcontrol->private_value; 2018 2019 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT) 2020 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 2021 else 2022 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in; 2023 2024 return 0; 2025 } 2026 2027 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol, 2028 struct snd_ctl_elem_value *ucontrol) 2029 { 2030 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2031 int change, res; 2032 2033 switch (kcontrol->private_value) { 2034 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT: 2035 mutex_lock(&chip->spos_mutex); 2036 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 2037 if (ucontrol->value.integer.value[0] && !change) 2038 cs46xx_dsp_enable_spdif_out(chip); 2039 else if (change && !ucontrol->value.integer.value[0]) 2040 cs46xx_dsp_disable_spdif_out(chip); 2041 2042 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED)); 2043 mutex_unlock(&chip->spos_mutex); 2044 break; 2045 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT: 2046 change = chip->dsp_spos_instance->spdif_status_in; 2047 if (ucontrol->value.integer.value[0] && !change) { 2048 cs46xx_dsp_enable_spdif_in(chip); 2049 /* restore volume */ 2050 } 2051 else if (change && !ucontrol->value.integer.value[0]) 2052 cs46xx_dsp_disable_spdif_in(chip); 2053 2054 res = (change != chip->dsp_spos_instance->spdif_status_in); 2055 break; 2056 default: 2057 res = -EINVAL; 2058 snd_BUG(); /* should never happen ... */ 2059 } 2060 2061 return res; 2062 } 2063 2064 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol, 2065 struct snd_ctl_elem_value *ucontrol) 2066 { 2067 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2068 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2069 2070 if (ins->adc_input != NULL) 2071 ucontrol->value.integer.value[0] = 1; 2072 else 2073 ucontrol->value.integer.value[0] = 0; 2074 2075 return 0; 2076 } 2077 2078 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol, 2079 struct snd_ctl_elem_value *ucontrol) 2080 { 2081 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2082 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2083 int change = 0; 2084 2085 if (ucontrol->value.integer.value[0] && !ins->adc_input) { 2086 cs46xx_dsp_enable_adc_capture(chip); 2087 change = 1; 2088 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) { 2089 cs46xx_dsp_disable_adc_capture(chip); 2090 change = 1; 2091 } 2092 return change; 2093 } 2094 2095 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol, 2096 struct snd_ctl_elem_value *ucontrol) 2097 { 2098 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2099 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2100 2101 if (ins->pcm_input != NULL) 2102 ucontrol->value.integer.value[0] = 1; 2103 else 2104 ucontrol->value.integer.value[0] = 0; 2105 2106 return 0; 2107 } 2108 2109 2110 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol, 2111 struct snd_ctl_elem_value *ucontrol) 2112 { 2113 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2114 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2115 int change = 0; 2116 2117 if (ucontrol->value.integer.value[0] && !ins->pcm_input) { 2118 cs46xx_dsp_enable_pcm_capture(chip); 2119 change = 1; 2120 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) { 2121 cs46xx_dsp_disable_pcm_capture(chip); 2122 change = 1; 2123 } 2124 2125 return change; 2126 } 2127 2128 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol, 2129 struct snd_ctl_elem_value *ucontrol) 2130 { 2131 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2132 2133 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 2134 2135 if (val1 & EGPIODR_GPOE0) 2136 ucontrol->value.integer.value[0] = 1; 2137 else 2138 ucontrol->value.integer.value[0] = 0; 2139 2140 return 0; 2141 } 2142 2143 /* 2144 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial. 2145 */ 2146 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol, 2147 struct snd_ctl_elem_value *ucontrol) 2148 { 2149 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2150 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 2151 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 2152 2153 if (ucontrol->value.integer.value[0]) { 2154 /* optical is default */ 2155 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 2156 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */ 2157 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 2158 EGPIOPTR_GPPT0 | val2); /* open-drain on output */ 2159 } else { 2160 /* coaxial */ 2161 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */ 2162 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */ 2163 } 2164 2165 /* checking diff from the EGPIO direction register 2166 should be enough */ 2167 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR)); 2168 } 2169 2170 2171 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2172 { 2173 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2174 uinfo->count = 1; 2175 return 0; 2176 } 2177 2178 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol, 2179 struct snd_ctl_elem_value *ucontrol) 2180 { 2181 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2182 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2183 2184 mutex_lock(&chip->spos_mutex); 2185 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff); 2186 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff); 2187 ucontrol->value.iec958.status[2] = 0; 2188 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff); 2189 mutex_unlock(&chip->spos_mutex); 2190 2191 return 0; 2192 } 2193 2194 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol, 2195 struct snd_ctl_elem_value *ucontrol) 2196 { 2197 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2198 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2199 unsigned int val; 2200 int change; 2201 2202 mutex_lock(&chip->spos_mutex); 2203 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2204 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) | 2205 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2206 /* left and right validity bit */ 2207 (1 << 13) | (1 << 12); 2208 2209 2210 change = (unsigned int)ins->spdif_csuv_default != val; 2211 ins->spdif_csuv_default = val; 2212 2213 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) ) 2214 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2215 2216 mutex_unlock(&chip->spos_mutex); 2217 2218 return change; 2219 } 2220 2221 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol, 2222 struct snd_ctl_elem_value *ucontrol) 2223 { 2224 ucontrol->value.iec958.status[0] = 0xff; 2225 ucontrol->value.iec958.status[1] = 0xff; 2226 ucontrol->value.iec958.status[2] = 0x00; 2227 ucontrol->value.iec958.status[3] = 0xff; 2228 return 0; 2229 } 2230 2231 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol, 2232 struct snd_ctl_elem_value *ucontrol) 2233 { 2234 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2235 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2236 2237 mutex_lock(&chip->spos_mutex); 2238 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff); 2239 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff); 2240 ucontrol->value.iec958.status[2] = 0; 2241 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff); 2242 mutex_unlock(&chip->spos_mutex); 2243 2244 return 0; 2245 } 2246 2247 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol, 2248 struct snd_ctl_elem_value *ucontrol) 2249 { 2250 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2251 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2252 unsigned int val; 2253 int change; 2254 2255 mutex_lock(&chip->spos_mutex); 2256 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2257 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) | 2258 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2259 /* left and right validity bit */ 2260 (1 << 13) | (1 << 12); 2261 2262 2263 change = ins->spdif_csuv_stream != val; 2264 ins->spdif_csuv_stream = val; 2265 2266 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN ) 2267 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2268 2269 mutex_unlock(&chip->spos_mutex); 2270 2271 return change; 2272 } 2273 2274 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2275 2276 2277 static struct snd_kcontrol_new snd_cs46xx_controls[] = { 2278 { 2279 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2280 .name = "DAC Volume", 2281 .info = snd_cs46xx_vol_info, 2282 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2283 .get = snd_cs46xx_vol_get, 2284 .put = snd_cs46xx_vol_put, 2285 .private_value = BA1_PVOL, 2286 #else 2287 .get = snd_cs46xx_vol_dac_get, 2288 .put = snd_cs46xx_vol_dac_put, 2289 #endif 2290 }, 2291 2292 { 2293 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2294 .name = "ADC Volume", 2295 .info = snd_cs46xx_vol_info, 2296 .get = snd_cs46xx_vol_get, 2297 .put = snd_cs46xx_vol_put, 2298 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2299 .private_value = BA1_CVOL, 2300 #else 2301 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2, 2302 #endif 2303 }, 2304 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2305 { 2306 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2307 .name = "ADC Capture Switch", 2308 .info = snd_mixer_boolean_info, 2309 .get = snd_cs46xx_adc_capture_get, 2310 .put = snd_cs46xx_adc_capture_put 2311 }, 2312 { 2313 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2314 .name = "DAC Capture Switch", 2315 .info = snd_mixer_boolean_info, 2316 .get = snd_cs46xx_pcm_capture_get, 2317 .put = snd_cs46xx_pcm_capture_put 2318 }, 2319 { 2320 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2321 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), 2322 .info = snd_mixer_boolean_info, 2323 .get = snd_cs46xx_iec958_get, 2324 .put = snd_cs46xx_iec958_put, 2325 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT, 2326 }, 2327 { 2328 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2329 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH), 2330 .info = snd_mixer_boolean_info, 2331 .get = snd_cs46xx_iec958_get, 2332 .put = snd_cs46xx_iec958_put, 2333 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT, 2334 }, 2335 #if 0 2336 /* Input IEC958 volume does not work for the moment. (Benny) */ 2337 { 2338 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2339 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME), 2340 .info = snd_cs46xx_vol_info, 2341 .get = snd_cs46xx_vol_iec958_get, 2342 .put = snd_cs46xx_vol_iec958_put, 2343 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2, 2344 }, 2345 #endif 2346 { 2347 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2348 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2349 .info = snd_cs46xx_spdif_info, 2350 .get = snd_cs46xx_spdif_default_get, 2351 .put = snd_cs46xx_spdif_default_put, 2352 }, 2353 { 2354 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2355 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 2356 .info = snd_cs46xx_spdif_info, 2357 .get = snd_cs46xx_spdif_mask_get, 2358 .access = SNDRV_CTL_ELEM_ACCESS_READ 2359 }, 2360 { 2361 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2362 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2363 .info = snd_cs46xx_spdif_info, 2364 .get = snd_cs46xx_spdif_stream_get, 2365 .put = snd_cs46xx_spdif_stream_put 2366 }, 2367 2368 #endif 2369 }; 2370 2371 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2372 /* set primary cs4294 codec into Extended Audio Mode */ 2373 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol, 2374 struct snd_ctl_elem_value *ucontrol) 2375 { 2376 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2377 unsigned short val; 2378 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE); 2379 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1; 2380 return 0; 2381 } 2382 2383 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol, 2384 struct snd_ctl_elem_value *ucontrol) 2385 { 2386 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2387 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2388 AC97_CSR_ACMODE, 0x200, 2389 ucontrol->value.integer.value[0] ? 0 : 0x200); 2390 } 2391 2392 static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = { 2393 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2394 .name = "Duplicate Front", 2395 .info = snd_mixer_boolean_info, 2396 .get = snd_cs46xx_front_dup_get, 2397 .put = snd_cs46xx_front_dup_put, 2398 }; 2399 #endif 2400 2401 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2402 /* Only available on the Hercules Game Theater XP soundcard */ 2403 static struct snd_kcontrol_new snd_hercules_controls[] = { 2404 { 2405 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2406 .name = "Optical/Coaxial SPDIF Input Switch", 2407 .info = snd_mixer_boolean_info, 2408 .get = snd_herc_spdif_select_get, 2409 .put = snd_herc_spdif_select_put, 2410 }, 2411 }; 2412 2413 2414 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97) 2415 { 2416 unsigned long end_time; 2417 int err; 2418 2419 /* reset to defaults */ 2420 snd_ac97_write(ac97, AC97_RESET, 0); 2421 2422 /* set the desired CODEC mode */ 2423 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) { 2424 snd_printdd("cs46xx: CODEC1 mode %04x\n", 0x0); 2425 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0); 2426 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) { 2427 snd_printdd("cs46xx: CODEC2 mode %04x\n", 0x3); 2428 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3); 2429 } else { 2430 snd_BUG(); /* should never happen ... */ 2431 } 2432 2433 udelay(50); 2434 2435 /* it's necessary to wait awhile until registers are accessible after RESET */ 2436 /* because the PCM or MASTER volume registers can be modified, */ 2437 /* the REC_GAIN register is used for tests */ 2438 end_time = jiffies + HZ; 2439 do { 2440 unsigned short ext_mid; 2441 2442 /* use preliminary reads to settle the communication */ 2443 snd_ac97_read(ac97, AC97_RESET); 2444 snd_ac97_read(ac97, AC97_VENDOR_ID1); 2445 snd_ac97_read(ac97, AC97_VENDOR_ID2); 2446 /* modem? */ 2447 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID); 2448 if (ext_mid != 0xffff && (ext_mid & 1) != 0) 2449 return; 2450 2451 /* test if we can write to the record gain volume register */ 2452 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05); 2453 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05) 2454 return; 2455 2456 msleep(10); 2457 } while (time_after_eq(end_time, jiffies)); 2458 2459 snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n"); 2460 } 2461 #endif 2462 2463 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec) 2464 { 2465 int idx, err; 2466 struct snd_ac97_template ac97; 2467 2468 memset(&ac97, 0, sizeof(ac97)); 2469 ac97.private_data = chip; 2470 ac97.private_free = snd_cs46xx_mixer_free_ac97; 2471 ac97.num = codec; 2472 if (chip->amplifier_ctrl == amp_voyetra) 2473 ac97.scaps = AC97_SCAP_INV_EAPD; 2474 2475 if (codec == CS46XX_SECONDARY_CODEC_INDEX) { 2476 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec); 2477 udelay(10); 2478 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) { 2479 snd_printdd("snd_cs46xx: seconadry codec not present\n"); 2480 return -ENXIO; 2481 } 2482 } 2483 2484 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec); 2485 for (idx = 0; idx < 100; ++idx) { 2486 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) { 2487 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]); 2488 return err; 2489 } 2490 msleep(10); 2491 } 2492 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec); 2493 return -ENXIO; 2494 } 2495 2496 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device) 2497 { 2498 struct snd_card *card = chip->card; 2499 struct snd_ctl_elem_id id; 2500 int err; 2501 unsigned int idx; 2502 static struct snd_ac97_bus_ops ops = { 2503 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2504 .reset = snd_cs46xx_codec_reset, 2505 #endif 2506 .write = snd_cs46xx_ac97_write, 2507 .read = snd_cs46xx_ac97_read, 2508 }; 2509 2510 /* detect primary codec */ 2511 chip->nr_ac97_codecs = 0; 2512 snd_printdd("snd_cs46xx: detecting primary codec\n"); 2513 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) 2514 return err; 2515 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus; 2516 2517 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0) 2518 return -ENXIO; 2519 chip->nr_ac97_codecs = 1; 2520 2521 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2522 snd_printdd("snd_cs46xx: detecting seconadry codec\n"); 2523 /* try detect a secondary codec */ 2524 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX)) 2525 chip->nr_ac97_codecs = 2; 2526 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2527 2528 /* add cs4630 mixer controls */ 2529 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) { 2530 struct snd_kcontrol *kctl; 2531 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip); 2532 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM) 2533 kctl->id.device = spdif_device; 2534 if ((err = snd_ctl_add(card, kctl)) < 0) 2535 return err; 2536 } 2537 2538 /* get EAPD mixer switch (for voyetra hack) */ 2539 memset(&id, 0, sizeof(id)); 2540 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2541 strcpy(id.name, "External Amplifier"); 2542 chip->eapd_switch = snd_ctl_find_id(chip->card, &id); 2543 2544 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2545 if (chip->nr_ac97_codecs == 1) { 2546 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff; 2547 if (id2 == 0x592b || id2 == 0x592d) { 2548 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip)); 2549 if (err < 0) 2550 return err; 2551 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2552 AC97_CSR_ACMODE, 0x200); 2553 } 2554 } 2555 /* do soundcard specific mixer setup */ 2556 if (chip->mixer_init) { 2557 snd_printdd ("calling chip->mixer_init(chip);\n"); 2558 chip->mixer_init(chip); 2559 } 2560 #endif 2561 2562 /* turn on amplifier */ 2563 chip->amplifier_ctrl(chip, 1); 2564 2565 return 0; 2566 } 2567 2568 /* 2569 * RawMIDI interface 2570 */ 2571 2572 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip) 2573 { 2574 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST); 2575 udelay(100); 2576 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2577 } 2578 2579 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream) 2580 { 2581 struct snd_cs46xx *chip = substream->rmidi->private_data; 2582 2583 chip->active_ctrl(chip, 1); 2584 spin_lock_irq(&chip->reg_lock); 2585 chip->uartm |= CS46XX_MODE_INPUT; 2586 chip->midcr |= MIDCR_RXE; 2587 chip->midi_input = substream; 2588 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2589 snd_cs46xx_midi_reset(chip); 2590 } else { 2591 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2592 } 2593 spin_unlock_irq(&chip->reg_lock); 2594 return 0; 2595 } 2596 2597 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream) 2598 { 2599 struct snd_cs46xx *chip = substream->rmidi->private_data; 2600 2601 spin_lock_irq(&chip->reg_lock); 2602 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE); 2603 chip->midi_input = NULL; 2604 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2605 snd_cs46xx_midi_reset(chip); 2606 } else { 2607 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2608 } 2609 chip->uartm &= ~CS46XX_MODE_INPUT; 2610 spin_unlock_irq(&chip->reg_lock); 2611 chip->active_ctrl(chip, -1); 2612 return 0; 2613 } 2614 2615 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream) 2616 { 2617 struct snd_cs46xx *chip = substream->rmidi->private_data; 2618 2619 chip->active_ctrl(chip, 1); 2620 2621 spin_lock_irq(&chip->reg_lock); 2622 chip->uartm |= CS46XX_MODE_OUTPUT; 2623 chip->midcr |= MIDCR_TXE; 2624 chip->midi_output = substream; 2625 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2626 snd_cs46xx_midi_reset(chip); 2627 } else { 2628 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2629 } 2630 spin_unlock_irq(&chip->reg_lock); 2631 return 0; 2632 } 2633 2634 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream) 2635 { 2636 struct snd_cs46xx *chip = substream->rmidi->private_data; 2637 2638 spin_lock_irq(&chip->reg_lock); 2639 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE); 2640 chip->midi_output = NULL; 2641 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2642 snd_cs46xx_midi_reset(chip); 2643 } else { 2644 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2645 } 2646 chip->uartm &= ~CS46XX_MODE_OUTPUT; 2647 spin_unlock_irq(&chip->reg_lock); 2648 chip->active_ctrl(chip, -1); 2649 return 0; 2650 } 2651 2652 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2653 { 2654 unsigned long flags; 2655 struct snd_cs46xx *chip = substream->rmidi->private_data; 2656 2657 spin_lock_irqsave(&chip->reg_lock, flags); 2658 if (up) { 2659 if ((chip->midcr & MIDCR_RIE) == 0) { 2660 chip->midcr |= MIDCR_RIE; 2661 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2662 } 2663 } else { 2664 if (chip->midcr & MIDCR_RIE) { 2665 chip->midcr &= ~MIDCR_RIE; 2666 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2667 } 2668 } 2669 spin_unlock_irqrestore(&chip->reg_lock, flags); 2670 } 2671 2672 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2673 { 2674 unsigned long flags; 2675 struct snd_cs46xx *chip = substream->rmidi->private_data; 2676 unsigned char byte; 2677 2678 spin_lock_irqsave(&chip->reg_lock, flags); 2679 if (up) { 2680 if ((chip->midcr & MIDCR_TIE) == 0) { 2681 chip->midcr |= MIDCR_TIE; 2682 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2683 while ((chip->midcr & MIDCR_TIE) && 2684 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 2685 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2686 chip->midcr &= ~MIDCR_TIE; 2687 } else { 2688 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte); 2689 } 2690 } 2691 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2692 } 2693 } else { 2694 if (chip->midcr & MIDCR_TIE) { 2695 chip->midcr &= ~MIDCR_TIE; 2696 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2697 } 2698 } 2699 spin_unlock_irqrestore(&chip->reg_lock, flags); 2700 } 2701 2702 static struct snd_rawmidi_ops snd_cs46xx_midi_output = 2703 { 2704 .open = snd_cs46xx_midi_output_open, 2705 .close = snd_cs46xx_midi_output_close, 2706 .trigger = snd_cs46xx_midi_output_trigger, 2707 }; 2708 2709 static struct snd_rawmidi_ops snd_cs46xx_midi_input = 2710 { 2711 .open = snd_cs46xx_midi_input_open, 2712 .close = snd_cs46xx_midi_input_close, 2713 .trigger = snd_cs46xx_midi_input_trigger, 2714 }; 2715 2716 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi) 2717 { 2718 struct snd_rawmidi *rmidi; 2719 int err; 2720 2721 if (rrawmidi) 2722 *rrawmidi = NULL; 2723 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0) 2724 return err; 2725 strcpy(rmidi->name, "CS46XX"); 2726 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output); 2727 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input); 2728 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 2729 rmidi->private_data = chip; 2730 chip->rmidi = rmidi; 2731 if (rrawmidi) 2732 *rrawmidi = NULL; 2733 return 0; 2734 } 2735 2736 2737 /* 2738 * gameport interface 2739 */ 2740 2741 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 2742 2743 static void snd_cs46xx_gameport_trigger(struct gameport *gameport) 2744 { 2745 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2746 2747 if (snd_BUG_ON(!chip)) 2748 return; 2749 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF); 2750 } 2751 2752 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport) 2753 { 2754 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2755 2756 if (snd_BUG_ON(!chip)) 2757 return 0; 2758 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io); 2759 } 2760 2761 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) 2762 { 2763 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2764 unsigned js1, js2, jst; 2765 2766 if (snd_BUG_ON(!chip)) 2767 return 0; 2768 2769 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1); 2770 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2); 2771 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT); 2772 2773 *buttons = (~jst >> 4) & 0x0F; 2774 2775 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 2776 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 2777 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 2778 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 2779 2780 for(jst=0;jst<4;++jst) 2781 if(axes[jst]==0xFFFF) axes[jst] = -1; 2782 return 0; 2783 } 2784 2785 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode) 2786 { 2787 switch (mode) { 2788 case GAMEPORT_MODE_COOKED: 2789 return 0; 2790 case GAMEPORT_MODE_RAW: 2791 return 0; 2792 default: 2793 return -1; 2794 } 2795 return 0; 2796 } 2797 2798 int snd_cs46xx_gameport(struct snd_cs46xx *chip) 2799 { 2800 struct gameport *gp; 2801 2802 chip->gameport = gp = gameport_allocate_port(); 2803 if (!gp) { 2804 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n"); 2805 return -ENOMEM; 2806 } 2807 2808 gameport_set_name(gp, "CS46xx Gameport"); 2809 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2810 gameport_set_dev_parent(gp, &chip->pci->dev); 2811 gameport_set_port_data(gp, chip); 2812 2813 gp->open = snd_cs46xx_gameport_open; 2814 gp->read = snd_cs46xx_gameport_read; 2815 gp->trigger = snd_cs46xx_gameport_trigger; 2816 gp->cooked_read = snd_cs46xx_gameport_cooked_read; 2817 2818 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 2819 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 2820 2821 gameport_register_port(gp); 2822 2823 return 0; 2824 } 2825 2826 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) 2827 { 2828 if (chip->gameport) { 2829 gameport_unregister_port(chip->gameport); 2830 chip->gameport = NULL; 2831 } 2832 } 2833 #else 2834 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; } 2835 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { } 2836 #endif /* CONFIG_GAMEPORT */ 2837 2838 #ifdef CONFIG_PROC_FS 2839 /* 2840 * proc interface 2841 */ 2842 2843 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry, 2844 void *file_private_data, 2845 struct file *file, char __user *buf, 2846 size_t count, loff_t pos) 2847 { 2848 struct snd_cs46xx_region *region = entry->private_data; 2849 2850 if (copy_to_user_fromio(buf, region->remap_addr + pos, count)) 2851 return -EFAULT; 2852 return count; 2853 } 2854 2855 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = { 2856 .read = snd_cs46xx_io_read, 2857 }; 2858 2859 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip) 2860 { 2861 struct snd_info_entry *entry; 2862 int idx; 2863 2864 for (idx = 0; idx < 5; idx++) { 2865 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2866 if (! snd_card_proc_new(card, region->name, &entry)) { 2867 entry->content = SNDRV_INFO_CONTENT_DATA; 2868 entry->private_data = chip; 2869 entry->c.ops = &snd_cs46xx_proc_io_ops; 2870 entry->size = region->size; 2871 entry->mode = S_IFREG | S_IRUSR; 2872 } 2873 } 2874 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2875 cs46xx_dsp_proc_init(card, chip); 2876 #endif 2877 return 0; 2878 } 2879 2880 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip) 2881 { 2882 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2883 cs46xx_dsp_proc_done(chip); 2884 #endif 2885 return 0; 2886 } 2887 #else /* !CONFIG_PROC_FS */ 2888 #define snd_cs46xx_proc_init(card, chip) 2889 #define snd_cs46xx_proc_done(chip) 2890 #endif 2891 2892 /* 2893 * stop the h/w 2894 */ 2895 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip) 2896 { 2897 unsigned int tmp; 2898 2899 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 2900 tmp &= ~0x0000f03f; 2901 tmp |= 0x00000010; 2902 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */ 2903 2904 tmp = snd_cs46xx_peek(chip, BA1_CIE); 2905 tmp &= ~0x0000003f; 2906 tmp |= 0x00000011; 2907 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */ 2908 2909 /* 2910 * Stop playback DMA. 2911 */ 2912 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 2913 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 2914 2915 /* 2916 * Stop capture DMA. 2917 */ 2918 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 2919 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 2920 2921 /* 2922 * Reset the processor. 2923 */ 2924 snd_cs46xx_reset(chip); 2925 2926 snd_cs46xx_proc_stop(chip); 2927 2928 /* 2929 * Power down the PLL. 2930 */ 2931 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2932 2933 /* 2934 * Turn off the Processor by turning off the software clock enable flag in 2935 * the clock control register. 2936 */ 2937 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; 2938 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 2939 } 2940 2941 2942 static int snd_cs46xx_free(struct snd_cs46xx *chip) 2943 { 2944 int idx; 2945 2946 if (snd_BUG_ON(!chip)) 2947 return -EINVAL; 2948 2949 if (chip->active_ctrl) 2950 chip->active_ctrl(chip, 1); 2951 2952 snd_cs46xx_remove_gameport(chip); 2953 2954 if (chip->amplifier_ctrl) 2955 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */ 2956 2957 snd_cs46xx_proc_done(chip); 2958 2959 if (chip->region.idx[0].resource) 2960 snd_cs46xx_hw_stop(chip); 2961 2962 if (chip->irq >= 0) 2963 free_irq(chip->irq, chip); 2964 2965 if (chip->active_ctrl) 2966 chip->active_ctrl(chip, -chip->amplifier); 2967 2968 for (idx = 0; idx < 5; idx++) { 2969 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2970 if (region->remap_addr) 2971 iounmap(region->remap_addr); 2972 release_and_free_resource(region->resource); 2973 } 2974 2975 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2976 if (chip->dsp_spos_instance) { 2977 cs46xx_dsp_spos_destroy(chip); 2978 chip->dsp_spos_instance = NULL; 2979 } 2980 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++) 2981 free_module_desc(chip->modules[idx]); 2982 #else 2983 vfree(chip->ba1); 2984 #endif 2985 2986 #ifdef CONFIG_PM_SLEEP 2987 kfree(chip->saved_regs); 2988 #endif 2989 2990 pci_disable_device(chip->pci); 2991 kfree(chip); 2992 return 0; 2993 } 2994 2995 static int snd_cs46xx_dev_free(struct snd_device *device) 2996 { 2997 struct snd_cs46xx *chip = device->device_data; 2998 return snd_cs46xx_free(chip); 2999 } 3000 3001 /* 3002 * initialize chip 3003 */ 3004 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip) 3005 { 3006 int timeout; 3007 3008 /* 3009 * First, blast the clock control register to zero so that the PLL starts 3010 * out in a known state, and blast the master serial port control register 3011 * to zero so that the serial ports also start out in a known state. 3012 */ 3013 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 3014 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0); 3015 3016 /* 3017 * If we are in AC97 mode, then we must set the part to a host controlled 3018 * AC-link. Otherwise, we won't be able to bring up the link. 3019 */ 3020 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3021 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 | 3022 SERACC_TWO_CODECS); /* 2.00 dual codecs */ 3023 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */ 3024 #else 3025 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */ 3026 #endif 3027 3028 /* 3029 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 3030 * spec) and then drive it high. This is done for non AC97 modes since 3031 * there might be logic external to the CS461x that uses the ARST# line 3032 * for a reset. 3033 */ 3034 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0); 3035 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3036 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0); 3037 #endif 3038 udelay(50); 3039 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN); 3040 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3041 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN); 3042 #endif 3043 3044 /* 3045 * The first thing we do here is to enable sync generation. As soon 3046 * as we start receiving bit clock, we'll start producing the SYNC 3047 * signal. 3048 */ 3049 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 3050 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3051 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN); 3052 #endif 3053 3054 /* 3055 * Now wait for a short while to allow the AC97 part to start 3056 * generating bit clock (so we don't try to start the PLL without an 3057 * input clock). 3058 */ 3059 mdelay(10); 3060 3061 /* 3062 * Set the serial port timing configuration, so that 3063 * the clock control circuit gets its clock from the correct place. 3064 */ 3065 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97); 3066 3067 /* 3068 * Write the selected clock control setup to the hardware. Do not turn on 3069 * SWCE yet (if requested), so that the devices clocked by the output of 3070 * PLL are not clocked until the PLL is stable. 3071 */ 3072 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 3073 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a); 3074 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8); 3075 3076 /* 3077 * Power up the PLL. 3078 */ 3079 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP); 3080 3081 /* 3082 * Wait until the PLL has stabilized. 3083 */ 3084 msleep(100); 3085 3086 /* 3087 * Turn on clocking of the core so that we can setup the serial ports. 3088 */ 3089 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 3090 3091 /* 3092 * Enable FIFO Host Bypass 3093 */ 3094 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP); 3095 3096 /* 3097 * Fill the serial port FIFOs with silence. 3098 */ 3099 snd_cs46xx_clear_serial_FIFOs(chip); 3100 3101 /* 3102 * Set the serial port FIFO pointer to the first sample in the FIFO. 3103 */ 3104 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */ 3105 3106 /* 3107 * Write the serial port configuration to the part. The master 3108 * enable bit is not set until all other values have been written. 3109 */ 3110 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 3111 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 3112 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 3113 3114 3115 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3116 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN); 3117 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0); 3118 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0); 3119 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0); 3120 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1); 3121 #endif 3122 3123 mdelay(5); 3124 3125 3126 /* 3127 * Wait for the codec ready signal from the AC97 codec. 3128 */ 3129 timeout = 150; 3130 while (timeout-- > 0) { 3131 /* 3132 * Read the AC97 status register to see if we've seen a CODEC READY 3133 * signal from the AC97 codec. 3134 */ 3135 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) 3136 goto ok1; 3137 msleep(10); 3138 } 3139 3140 3141 snd_printk(KERN_ERR "create - never read codec ready from AC'97\n"); 3142 snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n"); 3143 return -EIO; 3144 ok1: 3145 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3146 { 3147 int count; 3148 for (count = 0; count < 150; count++) { 3149 /* First, we want to wait for a short time. */ 3150 udelay(25); 3151 3152 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY) 3153 break; 3154 } 3155 3156 /* 3157 * Make sure CODEC is READY. 3158 */ 3159 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)) 3160 snd_printdd("cs46xx: never read card ready from secondary AC'97\n"); 3161 } 3162 #endif 3163 3164 /* 3165 * Assert the vaid frame signal so that we can start sending commands 3166 * to the AC97 codec. 3167 */ 3168 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 3169 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3170 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 3171 #endif 3172 3173 3174 /* 3175 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 3176 * the codec is pumping ADC data across the AC-link. 3177 */ 3178 timeout = 150; 3179 while (timeout-- > 0) { 3180 /* 3181 * Read the input slot valid register and see if input slots 3 and 3182 * 4 are valid yet. 3183 */ 3184 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 3185 goto ok2; 3186 msleep(10); 3187 } 3188 3189 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3190 snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n"); 3191 return -EIO; 3192 #else 3193 /* This may happen on a cold boot with a Terratec SiXPack 5.1. 3194 Reloading the driver may help, if there's other soundcards 3195 with the same problem I would like to know. (Benny) */ 3196 3197 snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n"); 3198 snd_printk(KERN_ERR " Try reloading the ALSA driver, if you find something\n"); 3199 snd_printk(KERN_ERR " broken or not working on your soundcard upon\n"); 3200 snd_printk(KERN_ERR " this message please report to alsa-devel@alsa-project.org\n"); 3201 3202 return -EIO; 3203 #endif 3204 ok2: 3205 3206 /* 3207 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 3208 * commense the transfer of digital audio data to the AC97 codec. 3209 */ 3210 3211 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 3212 3213 3214 /* 3215 * Power down the DAC and ADC. We will power them up (if) when we need 3216 * them. 3217 */ 3218 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */ 3219 3220 /* 3221 * Turn off the Processor by turning off the software clock enable flag in 3222 * the clock control register. 3223 */ 3224 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */ 3225 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */ 3226 3227 return 0; 3228 } 3229 3230 /* 3231 * start and load DSP 3232 */ 3233 3234 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip) 3235 { 3236 unsigned int tmp; 3237 3238 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM); 3239 3240 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 3241 tmp &= ~0x0000f03f; 3242 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */ 3243 3244 tmp = snd_cs46xx_peek(chip, BA1_CIE); 3245 tmp &= ~0x0000003f; 3246 tmp |= 0x00000001; 3247 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */ 3248 } 3249 3250 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip) 3251 { 3252 unsigned int tmp; 3253 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3254 int i; 3255 #endif 3256 int err; 3257 3258 /* 3259 * Reset the processor. 3260 */ 3261 snd_cs46xx_reset(chip); 3262 /* 3263 * Download the image to the processor. 3264 */ 3265 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3266 for (i = 0; i < CS46XX_DSP_MODULES; i++) { 3267 err = load_firmware(chip, &chip->modules[i], module_names[i]); 3268 if (err < 0) { 3269 snd_printk(KERN_ERR "firmware load error [%s]\n", 3270 module_names[i]); 3271 return err; 3272 } 3273 err = cs46xx_dsp_load_module(chip, chip->modules[i]); 3274 if (err < 0) { 3275 snd_printk(KERN_ERR "image download error [%s]\n", 3276 module_names[i]); 3277 return err; 3278 } 3279 } 3280 3281 if (cs46xx_dsp_scb_and_task_init(chip) < 0) 3282 return -EIO; 3283 #else 3284 err = load_firmware(chip); 3285 if (err < 0) 3286 return err; 3287 3288 /* old image */ 3289 err = snd_cs46xx_download_image(chip); 3290 if (err < 0) { 3291 snd_printk(KERN_ERR "image download error\n"); 3292 return err; 3293 } 3294 3295 /* 3296 * Stop playback DMA. 3297 */ 3298 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 3299 chip->play_ctl = tmp & 0xffff0000; 3300 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 3301 #endif 3302 3303 /* 3304 * Stop capture DMA. 3305 */ 3306 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3307 chip->capt.ctl = tmp & 0x0000ffff; 3308 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3309 3310 mdelay(5); 3311 3312 snd_cs46xx_set_play_sample_rate(chip, 8000); 3313 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3314 3315 snd_cs46xx_proc_start(chip); 3316 3317 cs46xx_enable_stream_irqs(chip); 3318 3319 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3320 /* set the attenuation to 0dB */ 3321 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000); 3322 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000); 3323 #endif 3324 3325 return 0; 3326 } 3327 3328 3329 /* 3330 * AMP control - null AMP 3331 */ 3332 3333 static void amp_none(struct snd_cs46xx *chip, int change) 3334 { 3335 } 3336 3337 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3338 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip) 3339 { 3340 3341 u32 idx, valid_slots,tmp,powerdown = 0; 3342 u16 modem_power,pin_config,logic_type; 3343 3344 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n"); 3345 3346 /* 3347 * See if the devices are powered down. If so, we must power them up first 3348 * or they will not respond. 3349 */ 3350 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 3351 3352 if (!(tmp & CLKCR1_SWCE)) { 3353 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 3354 powerdown = 1; 3355 } 3356 3357 /* 3358 * Clear PRA. The Bonzo chip will be used for GPIO not for modem 3359 * stuff. 3360 */ 3361 if(chip->nr_ac97_codecs != 2) { 3362 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n"); 3363 return -EINVAL; 3364 } 3365 3366 modem_power = snd_cs46xx_codec_read (chip, 3367 AC97_EXTENDED_MSTATUS, 3368 CS46XX_SECONDARY_CODEC_INDEX); 3369 modem_power &=0xFEFF; 3370 3371 snd_cs46xx_codec_write(chip, 3372 AC97_EXTENDED_MSTATUS, modem_power, 3373 CS46XX_SECONDARY_CODEC_INDEX); 3374 3375 /* 3376 * Set GPIO pin's 7 and 8 so that they are configured for output. 3377 */ 3378 pin_config = snd_cs46xx_codec_read (chip, 3379 AC97_GPIO_CFG, 3380 CS46XX_SECONDARY_CODEC_INDEX); 3381 pin_config &=0x27F; 3382 3383 snd_cs46xx_codec_write(chip, 3384 AC97_GPIO_CFG, pin_config, 3385 CS46XX_SECONDARY_CODEC_INDEX); 3386 3387 /* 3388 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic. 3389 */ 3390 3391 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY, 3392 CS46XX_SECONDARY_CODEC_INDEX); 3393 logic_type &=0x27F; 3394 3395 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type, 3396 CS46XX_SECONDARY_CODEC_INDEX); 3397 3398 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV); 3399 valid_slots |= 0x200; 3400 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots); 3401 3402 if ( cs46xx_wait_for_fifo(chip,1) ) { 3403 snd_printdd("FIFO is busy\n"); 3404 3405 return -EINVAL; 3406 } 3407 3408 /* 3409 * Fill slots 12 with the correct value for the GPIO pins. 3410 */ 3411 for(idx = 0x90; idx <= 0x9F; idx++) { 3412 /* 3413 * Initialize the fifo so that bits 7 and 8 are on. 3414 * 3415 * Remember that the GPIO pins in bonzo are shifted by 4 bits to 3416 * the left. 0x1800 corresponds to bits 7 and 8. 3417 */ 3418 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800); 3419 3420 /* 3421 * Wait for command to complete 3422 */ 3423 if ( cs46xx_wait_for_fifo(chip,200) ) { 3424 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx); 3425 3426 return -EINVAL; 3427 } 3428 3429 /* 3430 * Write the serial port FIFO index. 3431 */ 3432 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 3433 3434 /* 3435 * Tell the serial port to load the new value into the FIFO location. 3436 */ 3437 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 3438 } 3439 3440 /* wait for last command to complete */ 3441 cs46xx_wait_for_fifo(chip,200); 3442 3443 /* 3444 * Now, if we powered up the devices, then power them back down again. 3445 * This is kinda ugly, but should never happen. 3446 */ 3447 if (powerdown) 3448 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 3449 3450 return 0; 3451 } 3452 #endif 3453 3454 /* 3455 * Crystal EAPD mode 3456 */ 3457 3458 static void amp_voyetra(struct snd_cs46xx *chip, int change) 3459 { 3460 /* Manage the EAPD bit on the Crystal 4297 3461 and the Analog AD1885 */ 3462 3463 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3464 int old = chip->amplifier; 3465 #endif 3466 int oval, val; 3467 3468 chip->amplifier += change; 3469 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN, 3470 CS46XX_PRIMARY_CODEC_INDEX); 3471 val = oval; 3472 if (chip->amplifier) { 3473 /* Turn the EAPD amp on */ 3474 val |= 0x8000; 3475 } else { 3476 /* Turn the EAPD amp off */ 3477 val &= ~0x8000; 3478 } 3479 if (val != oval) { 3480 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val, 3481 CS46XX_PRIMARY_CODEC_INDEX); 3482 if (chip->eapd_switch) 3483 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 3484 &chip->eapd_switch->id); 3485 } 3486 3487 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3488 if (chip->amplifier && !old) { 3489 voyetra_setup_eapd_slot(chip); 3490 } 3491 #endif 3492 } 3493 3494 static void hercules_init(struct snd_cs46xx *chip) 3495 { 3496 /* default: AMP off, and SPDIF input optical */ 3497 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3498 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3499 } 3500 3501 3502 /* 3503 * Game Theatre XP card - EGPIO[2] is used to enable the external amp. 3504 */ 3505 static void amp_hercules(struct snd_cs46xx *chip, int change) 3506 { 3507 int old = chip->amplifier; 3508 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 3509 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 3510 3511 chip->amplifier += change; 3512 if (chip->amplifier && !old) { 3513 snd_printdd ("Hercules amplifier ON\n"); 3514 3515 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 3516 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */ 3517 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 3518 EGPIOPTR_GPPT2 | val2); /* open-drain on output */ 3519 } else if (old && !chip->amplifier) { 3520 snd_printdd ("Hercules amplifier OFF\n"); 3521 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */ 3522 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */ 3523 } 3524 } 3525 3526 static void voyetra_mixer_init (struct snd_cs46xx *chip) 3527 { 3528 snd_printdd ("initializing Voyetra mixer\n"); 3529 3530 /* Enable SPDIF out */ 3531 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3532 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3533 } 3534 3535 static void hercules_mixer_init (struct snd_cs46xx *chip) 3536 { 3537 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3538 unsigned int idx; 3539 int err; 3540 struct snd_card *card = chip->card; 3541 #endif 3542 3543 /* set EGPIO to default */ 3544 hercules_init(chip); 3545 3546 snd_printdd ("initializing Hercules mixer\n"); 3547 3548 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3549 if (chip->in_suspend) 3550 return; 3551 3552 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) { 3553 struct snd_kcontrol *kctl; 3554 3555 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip); 3556 if ((err = snd_ctl_add(card, kctl)) < 0) { 3557 printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err); 3558 break; 3559 } 3560 } 3561 #endif 3562 } 3563 3564 3565 #if 0 3566 /* 3567 * Untested 3568 */ 3569 3570 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change) 3571 { 3572 chip->amplifier += change; 3573 3574 if (chip->amplifier) { 3575 /* Switch the GPIO pins 7 and 8 to open drain */ 3576 snd_cs46xx_codec_write(chip, 0x4C, 3577 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F); 3578 snd_cs46xx_codec_write(chip, 0x4E, 3579 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180); 3580 /* Now wake the AMP (this might be backwards) */ 3581 snd_cs46xx_codec_write(chip, 0x54, 3582 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180); 3583 } else { 3584 snd_cs46xx_codec_write(chip, 0x54, 3585 snd_cs46xx_codec_read(chip, 0x54) | 0x0180); 3586 } 3587 } 3588 #endif 3589 3590 3591 /* 3592 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support 3593 * whenever we need to beat on the chip. 3594 * 3595 * The original idea and code for this hack comes from David Kaiser at 3596 * Linuxcare. Perhaps one day Crystal will document their chips well 3597 * enough to make them useful. 3598 */ 3599 3600 static void clkrun_hack(struct snd_cs46xx *chip, int change) 3601 { 3602 u16 control, nval; 3603 3604 if (!chip->acpi_port) 3605 return; 3606 3607 chip->amplifier += change; 3608 3609 /* Read ACPI port */ 3610 nval = control = inw(chip->acpi_port + 0x10); 3611 3612 /* Flip CLKRUN off while running */ 3613 if (! chip->amplifier) 3614 nval |= 0x2000; 3615 else 3616 nval &= ~0x2000; 3617 if (nval != control) 3618 outw(nval, chip->acpi_port + 0x10); 3619 } 3620 3621 3622 /* 3623 * detect intel piix4 3624 */ 3625 static void clkrun_init(struct snd_cs46xx *chip) 3626 { 3627 struct pci_dev *pdev; 3628 u8 pp; 3629 3630 chip->acpi_port = 0; 3631 3632 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 3633 PCI_DEVICE_ID_INTEL_82371AB_3, NULL); 3634 if (pdev == NULL) 3635 return; /* Not a thinkpad thats for sure */ 3636 3637 /* Find the control port */ 3638 pci_read_config_byte(pdev, 0x41, &pp); 3639 chip->acpi_port = pp << 8; 3640 pci_dev_put(pdev); 3641 } 3642 3643 3644 /* 3645 * Card subid table 3646 */ 3647 3648 struct cs_card_type 3649 { 3650 u16 vendor; 3651 u16 id; 3652 char *name; 3653 void (*init)(struct snd_cs46xx *); 3654 void (*amp)(struct snd_cs46xx *, int); 3655 void (*active)(struct snd_cs46xx *, int); 3656 void (*mixer_init)(struct snd_cs46xx *); 3657 }; 3658 3659 static struct cs_card_type cards[] = { 3660 { 3661 .vendor = 0x1489, 3662 .id = 0x7001, 3663 .name = "Genius Soundmaker 128 value", 3664 /* nothing special */ 3665 }, 3666 { 3667 .vendor = 0x5053, 3668 .id = 0x3357, 3669 .name = "Voyetra", 3670 .amp = amp_voyetra, 3671 .mixer_init = voyetra_mixer_init, 3672 }, 3673 { 3674 .vendor = 0x1071, 3675 .id = 0x6003, 3676 .name = "Mitac MI6020/21", 3677 .amp = amp_voyetra, 3678 }, 3679 /* Hercules Game Theatre XP */ 3680 { 3681 .vendor = 0x14af, /* Guillemot Corporation */ 3682 .id = 0x0050, 3683 .name = "Hercules Game Theatre XP", 3684 .amp = amp_hercules, 3685 .mixer_init = hercules_mixer_init, 3686 }, 3687 { 3688 .vendor = 0x1681, 3689 .id = 0x0050, 3690 .name = "Hercules Game Theatre XP", 3691 .amp = amp_hercules, 3692 .mixer_init = hercules_mixer_init, 3693 }, 3694 { 3695 .vendor = 0x1681, 3696 .id = 0x0051, 3697 .name = "Hercules Game Theatre XP", 3698 .amp = amp_hercules, 3699 .mixer_init = hercules_mixer_init, 3700 3701 }, 3702 { 3703 .vendor = 0x1681, 3704 .id = 0x0052, 3705 .name = "Hercules Game Theatre XP", 3706 .amp = amp_hercules, 3707 .mixer_init = hercules_mixer_init, 3708 }, 3709 { 3710 .vendor = 0x1681, 3711 .id = 0x0053, 3712 .name = "Hercules Game Theatre XP", 3713 .amp = amp_hercules, 3714 .mixer_init = hercules_mixer_init, 3715 }, 3716 { 3717 .vendor = 0x1681, 3718 .id = 0x0054, 3719 .name = "Hercules Game Theatre XP", 3720 .amp = amp_hercules, 3721 .mixer_init = hercules_mixer_init, 3722 }, 3723 /* Herculess Fortissimo */ 3724 { 3725 .vendor = 0x1681, 3726 .id = 0xa010, 3727 .name = "Hercules Gamesurround Fortissimo II", 3728 }, 3729 { 3730 .vendor = 0x1681, 3731 .id = 0xa011, 3732 .name = "Hercules Gamesurround Fortissimo III 7.1", 3733 }, 3734 /* Teratec */ 3735 { 3736 .vendor = 0x153b, 3737 .id = 0x112e, 3738 .name = "Terratec DMX XFire 1024", 3739 }, 3740 { 3741 .vendor = 0x153b, 3742 .id = 0x1136, 3743 .name = "Terratec SiXPack 5.1", 3744 }, 3745 /* Not sure if the 570 needs the clkrun hack */ 3746 { 3747 .vendor = PCI_VENDOR_ID_IBM, 3748 .id = 0x0132, 3749 .name = "Thinkpad 570", 3750 .init = clkrun_init, 3751 .active = clkrun_hack, 3752 }, 3753 { 3754 .vendor = PCI_VENDOR_ID_IBM, 3755 .id = 0x0153, 3756 .name = "Thinkpad 600X/A20/T20", 3757 .init = clkrun_init, 3758 .active = clkrun_hack, 3759 }, 3760 { 3761 .vendor = PCI_VENDOR_ID_IBM, 3762 .id = 0x1010, 3763 .name = "Thinkpad 600E (unsupported)", 3764 }, 3765 {} /* terminator */ 3766 }; 3767 3768 3769 /* 3770 * APM support 3771 */ 3772 #ifdef CONFIG_PM_SLEEP 3773 static unsigned int saved_regs[] = { 3774 BA0_ACOSV, 3775 /*BA0_ASER_FADDR,*/ 3776 BA0_ASER_MASTER, 3777 BA1_PVOL, 3778 BA1_CVOL, 3779 }; 3780 3781 static int snd_cs46xx_suspend(struct device *dev) 3782 { 3783 struct pci_dev *pci = to_pci_dev(dev); 3784 struct snd_card *card = dev_get_drvdata(dev); 3785 struct snd_cs46xx *chip = card->private_data; 3786 int i, amp_saved; 3787 3788 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3789 chip->in_suspend = 1; 3790 snd_pcm_suspend_all(chip->pcm); 3791 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL); 3792 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE); 3793 3794 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3795 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3796 3797 /* save some registers */ 3798 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3799 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]); 3800 3801 amp_saved = chip->amplifier; 3802 /* turn off amp */ 3803 chip->amplifier_ctrl(chip, -chip->amplifier); 3804 snd_cs46xx_hw_stop(chip); 3805 /* disable CLKRUN */ 3806 chip->active_ctrl(chip, -chip->amplifier); 3807 chip->amplifier = amp_saved; /* restore the status */ 3808 3809 pci_disable_device(pci); 3810 pci_save_state(pci); 3811 pci_set_power_state(pci, PCI_D3hot); 3812 return 0; 3813 } 3814 3815 static int snd_cs46xx_resume(struct device *dev) 3816 { 3817 struct pci_dev *pci = to_pci_dev(dev); 3818 struct snd_card *card = dev_get_drvdata(dev); 3819 struct snd_cs46xx *chip = card->private_data; 3820 int amp_saved; 3821 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3822 int i; 3823 #endif 3824 unsigned int tmp; 3825 3826 pci_set_power_state(pci, PCI_D0); 3827 pci_restore_state(pci); 3828 if (pci_enable_device(pci) < 0) { 3829 printk(KERN_ERR "cs46xx: pci_enable_device failed, " 3830 "disabling device\n"); 3831 snd_card_disconnect(card); 3832 return -EIO; 3833 } 3834 pci_set_master(pci); 3835 3836 amp_saved = chip->amplifier; 3837 chip->amplifier = 0; 3838 chip->active_ctrl(chip, 1); /* force to on */ 3839 3840 snd_cs46xx_chip_init(chip); 3841 3842 snd_cs46xx_reset(chip); 3843 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3844 cs46xx_dsp_resume(chip); 3845 /* restore some registers */ 3846 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3847 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]); 3848 #else 3849 snd_cs46xx_download_image(chip); 3850 #endif 3851 3852 #if 0 3853 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, 3854 chip->ac97_general_purpose); 3855 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL, 3856 chip->ac97_powerdown); 3857 mdelay(10); 3858 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN, 3859 chip->ac97_powerdown); 3860 mdelay(5); 3861 #endif 3862 3863 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3864 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3865 3866 /* 3867 * Stop capture DMA. 3868 */ 3869 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3870 chip->capt.ctl = tmp & 0x0000ffff; 3871 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3872 3873 mdelay(5); 3874 3875 /* reset playback/capture */ 3876 snd_cs46xx_set_play_sample_rate(chip, 8000); 3877 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3878 snd_cs46xx_proc_start(chip); 3879 3880 cs46xx_enable_stream_irqs(chip); 3881 3882 if (amp_saved) 3883 chip->amplifier_ctrl(chip, 1); /* turn amp on */ 3884 else 3885 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3886 chip->amplifier = amp_saved; 3887 chip->in_suspend = 0; 3888 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3889 return 0; 3890 } 3891 3892 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume); 3893 #endif /* CONFIG_PM_SLEEP */ 3894 3895 3896 /* 3897 */ 3898 3899 int snd_cs46xx_create(struct snd_card *card, 3900 struct pci_dev *pci, 3901 int external_amp, int thinkpad, 3902 struct snd_cs46xx **rchip) 3903 { 3904 struct snd_cs46xx *chip; 3905 int err, idx; 3906 struct snd_cs46xx_region *region; 3907 struct cs_card_type *cp; 3908 u16 ss_card, ss_vendor; 3909 static struct snd_device_ops ops = { 3910 .dev_free = snd_cs46xx_dev_free, 3911 }; 3912 3913 *rchip = NULL; 3914 3915 /* enable PCI device */ 3916 if ((err = pci_enable_device(pci)) < 0) 3917 return err; 3918 3919 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3920 if (chip == NULL) { 3921 pci_disable_device(pci); 3922 return -ENOMEM; 3923 } 3924 spin_lock_init(&chip->reg_lock); 3925 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3926 mutex_init(&chip->spos_mutex); 3927 #endif 3928 chip->card = card; 3929 chip->pci = pci; 3930 chip->irq = -1; 3931 chip->ba0_addr = pci_resource_start(pci, 0); 3932 chip->ba1_addr = pci_resource_start(pci, 1); 3933 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 || 3934 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) { 3935 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", 3936 chip->ba0_addr, chip->ba1_addr); 3937 snd_cs46xx_free(chip); 3938 return -ENOMEM; 3939 } 3940 3941 region = &chip->region.name.ba0; 3942 strcpy(region->name, "CS46xx_BA0"); 3943 region->base = chip->ba0_addr; 3944 region->size = CS46XX_BA0_SIZE; 3945 3946 region = &chip->region.name.data0; 3947 strcpy(region->name, "CS46xx_BA1_data0"); 3948 region->base = chip->ba1_addr + BA1_SP_DMEM0; 3949 region->size = CS46XX_BA1_DATA0_SIZE; 3950 3951 region = &chip->region.name.data1; 3952 strcpy(region->name, "CS46xx_BA1_data1"); 3953 region->base = chip->ba1_addr + BA1_SP_DMEM1; 3954 region->size = CS46XX_BA1_DATA1_SIZE; 3955 3956 region = &chip->region.name.pmem; 3957 strcpy(region->name, "CS46xx_BA1_pmem"); 3958 region->base = chip->ba1_addr + BA1_SP_PMEM; 3959 region->size = CS46XX_BA1_PRG_SIZE; 3960 3961 region = &chip->region.name.reg; 3962 strcpy(region->name, "CS46xx_BA1_reg"); 3963 region->base = chip->ba1_addr + BA1_SP_REG; 3964 region->size = CS46XX_BA1_REG_SIZE; 3965 3966 /* set up amp and clkrun hack */ 3967 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor); 3968 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card); 3969 3970 for (cp = &cards[0]; cp->name; cp++) { 3971 if (cp->vendor == ss_vendor && cp->id == ss_card) { 3972 snd_printdd ("hack for %s enabled\n", cp->name); 3973 3974 chip->amplifier_ctrl = cp->amp; 3975 chip->active_ctrl = cp->active; 3976 chip->mixer_init = cp->mixer_init; 3977 3978 if (cp->init) 3979 cp->init(chip); 3980 break; 3981 } 3982 } 3983 3984 if (external_amp) { 3985 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n"); 3986 chip->amplifier_ctrl = amp_voyetra; 3987 } 3988 3989 if (thinkpad) { 3990 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n"); 3991 chip->active_ctrl = clkrun_hack; 3992 clkrun_init(chip); 3993 } 3994 3995 if (chip->amplifier_ctrl == NULL) 3996 chip->amplifier_ctrl = amp_none; 3997 if (chip->active_ctrl == NULL) 3998 chip->active_ctrl = amp_none; 3999 4000 chip->active_ctrl(chip, 1); /* enable CLKRUN */ 4001 4002 pci_set_master(pci); 4003 4004 for (idx = 0; idx < 5; idx++) { 4005 region = &chip->region.idx[idx]; 4006 if ((region->resource = request_mem_region(region->base, region->size, 4007 region->name)) == NULL) { 4008 snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n", 4009 region->base, region->base + region->size - 1); 4010 snd_cs46xx_free(chip); 4011 return -EBUSY; 4012 } 4013 region->remap_addr = ioremap_nocache(region->base, region->size); 4014 if (region->remap_addr == NULL) { 4015 snd_printk(KERN_ERR "%s ioremap problem\n", region->name); 4016 snd_cs46xx_free(chip); 4017 return -ENOMEM; 4018 } 4019 } 4020 4021 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED, 4022 KBUILD_MODNAME, chip)) { 4023 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 4024 snd_cs46xx_free(chip); 4025 return -EBUSY; 4026 } 4027 chip->irq = pci->irq; 4028 4029 #ifdef CONFIG_SND_CS46XX_NEW_DSP 4030 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip); 4031 if (chip->dsp_spos_instance == NULL) { 4032 snd_cs46xx_free(chip); 4033 return -ENOMEM; 4034 } 4035 #endif 4036 4037 err = snd_cs46xx_chip_init(chip); 4038 if (err < 0) { 4039 snd_cs46xx_free(chip); 4040 return err; 4041 } 4042 4043 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 4044 snd_cs46xx_free(chip); 4045 return err; 4046 } 4047 4048 snd_cs46xx_proc_init(card, chip); 4049 4050 #ifdef CONFIG_PM_SLEEP 4051 chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) * 4052 ARRAY_SIZE(saved_regs), GFP_KERNEL); 4053 if (!chip->saved_regs) { 4054 snd_cs46xx_free(chip); 4055 return -ENOMEM; 4056 } 4057 #endif 4058 4059 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 4060 4061 snd_card_set_dev(card, &pci->dev); 4062 4063 *rchip = chip; 4064 return 0; 4065 } 4066