1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Abramo Bagnara <abramo@alsa-project.org> 5 * Cirrus Logic, Inc. 6 * Routines for control of Cirrus Logic CS461x chips 7 * 8 * KNOWN BUGS: 9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized 10 * and the SPDIF get somewhat "distorcionated", or/and left right channel 11 * are swapped. To get around this problem when it happens, mute and unmute 12 * the SPDIF input mixer control. 13 * - On the Hercules Game Theater XP the amplifier are sometimes turned 14 * off on inadecuate moments which causes distorcions on sound. 15 * 16 * TODO: 17 * - Secondary CODEC on some soundcards 18 * - SPDIF input support for other sample rates then 48khz 19 * - Posibility to mix the SPDIF output with analog sources. 20 * - PCM channels for Center and LFE on secondary codec 21 * 22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which 23 * is default configuration), no SPDIF, no secondary codec, no 24 * multi channel PCM. But known to work. 25 * 26 * FINALLY: A credit to the developers Tom and Jordan 27 * at Cirrus for have helping me out with the DSP, however we 28 * still don't have sufficient documentation and technical 29 * references to be able to implement all fancy feutures 30 * supported by the cs46xx DSP's. 31 * Benny <benny@hostmobility.com> 32 */ 33 34 #include <linux/delay.h> 35 #include <linux/pci.h> 36 #include <linux/pm.h> 37 #include <linux/init.h> 38 #include <linux/interrupt.h> 39 #include <linux/slab.h> 40 #include <linux/gameport.h> 41 #include <linux/mutex.h> 42 #include <linux/export.h> 43 #include <linux/module.h> 44 #include <linux/firmware.h> 45 #include <linux/vmalloc.h> 46 #include <linux/io.h> 47 48 #include <sound/core.h> 49 #include <sound/control.h> 50 #include <sound/info.h> 51 #include <sound/pcm.h> 52 #include <sound/pcm_params.h> 53 #include "cs46xx.h" 54 55 #include "cs46xx_lib.h" 56 #include "dsp_spos.h" 57 58 static void amp_voyetra(struct snd_cs46xx *chip, int change); 59 60 #ifdef CONFIG_SND_CS46XX_NEW_DSP 61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops; 62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; 63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; 64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; 65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; 66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; 67 #endif 68 69 static const struct snd_pcm_ops snd_cs46xx_playback_ops; 70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; 71 static const struct snd_pcm_ops snd_cs46xx_capture_ops; 72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; 73 74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, 75 unsigned short reg, 76 int codec_index) 77 { 78 int count; 79 unsigned short result,tmp; 80 u32 offset = 0; 81 82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 83 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 84 return 0xffff; 85 86 chip->active_ctrl(chip, 1); 87 88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX) 89 offset = CS46XX_SECONDARY_CODEC_OFFSET; 90 91 /* 92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55 95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 96 * 5. if DCV not cleared, break and return error 97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 98 */ 99 100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 101 102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL); 103 if ((tmp & ACCTL_VFRM) == 0) { 104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp); 105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM ); 106 msleep(50); 107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset); 108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM ); 109 110 } 111 112 /* 113 * Setup the AC97 control registers on the CS461x to send the 114 * appropriate command to the AC97 to perform the read. 115 * ACCAD = Command Address Register = 46Ch 116 * ACCDA = Command Data Register = 470h 117 * ACCTL = Control Register = 460h 118 * set DCV - will clear when process completed 119 * set CRW - Read command 120 * set VFRM - valid frame enabled 121 * set ESYN - ASYNC generation enabled 122 * set RSTN - ARST# inactive, AC97 codec not reset 123 */ 124 125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg); 126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0); 127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW | 129 ACCTL_VFRM | ACCTL_ESYN | 130 ACCTL_RSTN); 131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | 132 ACCTL_VFRM | ACCTL_ESYN | 133 ACCTL_RSTN); 134 } else { 135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | 137 ACCTL_RSTN); 138 } 139 140 /* 141 * Wait for the read to occur. 142 */ 143 for (count = 0; count < 1000; count++) { 144 /* 145 * First, we want to wait for a short time. 146 */ 147 udelay(10); 148 /* 149 * Now, check to see if the read has completed. 150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 151 */ 152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) 153 goto ok1; 154 } 155 156 dev_err(chip->card->dev, 157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 158 result = 0xffff; 159 goto end; 160 161 ok1: 162 /* 163 * Wait for the valid status bit to go active. 164 */ 165 for (count = 0; count < 100; count++) { 166 /* 167 * Read the AC97 status register. 168 * ACSTS = Status Register = 464h 169 * VSTS - Valid Status 170 */ 171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS) 172 goto ok2; 173 udelay(10); 174 } 175 176 dev_err(chip->card->dev, 177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", 178 codec_index, reg); 179 result = 0xffff; 180 goto end; 181 182 ok2: 183 /* 184 * Read the data returned from the AC97 register. 185 * ACSDA = Status Data Register = 474h 186 */ 187 #if 0 188 dev_dbg(chip->card->dev, 189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg, 190 snd_cs46xx_peekBA0(chip, BA0_ACSDA), 191 snd_cs46xx_peekBA0(chip, BA0_ACCAD)); 192 #endif 193 194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD); 195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 196 end: 197 chip->active_ctrl(chip, -1); 198 return result; 199 } 200 201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97, 202 unsigned short reg) 203 { 204 struct snd_cs46xx *chip = ac97->private_data; 205 unsigned short val; 206 int codec_index = ac97->num; 207 208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 209 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 210 return 0xffff; 211 212 val = snd_cs46xx_codec_read(chip, reg, codec_index); 213 214 return val; 215 } 216 217 218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip, 219 unsigned short reg, 220 unsigned short val, 221 int codec_index) 222 { 223 int count; 224 225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 226 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 227 return; 228 229 chip->active_ctrl(chip, 1); 230 231 /* 232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 234 * 3. Write ACCTL = Control Register = 460h for initiating the write 235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 236 * 5. if DCV not cleared, break and return error 237 */ 238 239 /* 240 * Setup the AC97 control registers on the CS461x to send the 241 * appropriate command to the AC97 to perform the read. 242 * ACCAD = Command Address Register = 46Ch 243 * ACCDA = Command Data Register = 470h 244 * ACCTL = Control Register = 460h 245 * set DCV - will clear when process completed 246 * reset CRW - Write command 247 * set VFRM - valid frame enabled 248 * set ESYN - ASYNC generation enabled 249 * set RSTN - ARST# inactive, AC97 codec not reset 250 */ 251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg); 252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val); 253 snd_cs46xx_peekBA0(chip, BA0_ACCTL); 254 255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM | 257 ACCTL_ESYN | ACCTL_RSTN); 258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | 259 ACCTL_ESYN | ACCTL_RSTN); 260 } else { 261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 263 } 264 265 for (count = 0; count < 4000; count++) { 266 /* 267 * First, we want to wait for a short time. 268 */ 269 udelay(10); 270 /* 271 * Now, check to see if the write has completed. 272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 273 */ 274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) { 275 goto end; 276 } 277 } 278 dev_err(chip->card->dev, 279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", 280 codec_index, reg, val); 281 end: 282 chip->active_ctrl(chip, -1); 283 } 284 285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97, 286 unsigned short reg, 287 unsigned short val) 288 { 289 struct snd_cs46xx *chip = ac97->private_data; 290 int codec_index = ac97->num; 291 292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 293 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 294 return; 295 296 snd_cs46xx_codec_write(chip, reg, val, codec_index); 297 } 298 299 300 /* 301 * Chip initialization 302 */ 303 304 int snd_cs46xx_download(struct snd_cs46xx *chip, 305 u32 *src, 306 unsigned long offset, 307 unsigned long len) 308 { 309 void __iomem *dst; 310 unsigned int bank = offset >> 16; 311 offset = offset & 0xffff; 312 313 if (snd_BUG_ON((offset & 3) || (len & 3))) 314 return -EINVAL; 315 dst = chip->region.idx[bank+1].remap_addr + offset; 316 len /= sizeof(u32); 317 318 /* writel already converts 32-bit value to right endianess */ 319 while (len-- > 0) { 320 writel(*src++, dst); 321 dst += sizeof(u32); 322 } 323 return 0; 324 } 325 326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len) 327 { 328 #ifdef __LITTLE_ENDIAN 329 memcpy(dst, src, len); 330 #else 331 u32 *_dst = dst; 332 const __le32 *_src = src; 333 len /= 4; 334 while (len-- > 0) 335 *_dst++ = le32_to_cpu(*_src++); 336 #endif 337 } 338 339 #ifdef CONFIG_SND_CS46XX_NEW_DSP 340 341 static const char *module_names[CS46XX_DSP_MODULES] = { 342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma" 343 }; 344 345 MODULE_FIRMWARE("cs46xx/cwc4630"); 346 MODULE_FIRMWARE("cs46xx/cwcasync"); 347 MODULE_FIRMWARE("cs46xx/cwcsnoop"); 348 MODULE_FIRMWARE("cs46xx/cwcbinhack"); 349 MODULE_FIRMWARE("cs46xx/cwcdma"); 350 351 static void free_module_desc(struct dsp_module_desc *module) 352 { 353 if (!module) 354 return; 355 kfree(module->module_name); 356 kfree(module->symbol_table.symbols); 357 if (module->segments) { 358 int i; 359 for (i = 0; i < module->nsegments; i++) 360 kfree(module->segments[i].data); 361 kfree(module->segments); 362 } 363 kfree(module); 364 } 365 366 /* firmware binary format: 367 * le32 nsymbols; 368 * struct { 369 * le32 address; 370 * char symbol_name[DSP_MAX_SYMBOL_NAME]; 371 * le32 symbol_type; 372 * } symbols[nsymbols]; 373 * le32 nsegments; 374 * struct { 375 * le32 segment_type; 376 * le32 offset; 377 * le32 size; 378 * le32 data[size]; 379 * } segments[nsegments]; 380 */ 381 382 static int load_firmware(struct snd_cs46xx *chip, 383 struct dsp_module_desc **module_ret, 384 const char *fw_name) 385 { 386 int i, err; 387 unsigned int nums, fwlen, fwsize; 388 const __le32 *fwdat; 389 struct dsp_module_desc *module = NULL; 390 const struct firmware *fw; 391 char fw_path[32]; 392 393 sprintf(fw_path, "cs46xx/%s", fw_name); 394 err = request_firmware(&fw, fw_path, &chip->pci->dev); 395 if (err < 0) 396 return err; 397 fwsize = fw->size / 4; 398 if (fwsize < 2) { 399 err = -EINVAL; 400 goto error; 401 } 402 403 err = -ENOMEM; 404 module = kzalloc(sizeof(*module), GFP_KERNEL); 405 if (!module) 406 goto error; 407 module->module_name = kstrdup(fw_name, GFP_KERNEL); 408 if (!module->module_name) 409 goto error; 410 411 fwlen = 0; 412 fwdat = (const __le32 *)fw->data; 413 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]); 414 if (nums >= 40) 415 goto error_inval; 416 module->symbol_table.symbols = 417 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL); 418 if (!module->symbol_table.symbols) 419 goto error; 420 for (i = 0; i < nums; i++) { 421 struct dsp_symbol_entry *entry = 422 &module->symbol_table.symbols[i]; 423 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize) 424 goto error_inval; 425 entry->address = le32_to_cpu(fwdat[fwlen++]); 426 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1); 427 fwlen += DSP_MAX_SYMBOL_NAME / 4; 428 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]); 429 } 430 431 if (fwlen >= fwsize) 432 goto error_inval; 433 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]); 434 if (nums > 10) 435 goto error_inval; 436 module->segments = 437 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL); 438 if (!module->segments) 439 goto error; 440 for (i = 0; i < nums; i++) { 441 struct dsp_segment_desc *entry = &module->segments[i]; 442 if (fwlen + 3 > fwsize) 443 goto error_inval; 444 entry->segment_type = le32_to_cpu(fwdat[fwlen++]); 445 entry->offset = le32_to_cpu(fwdat[fwlen++]); 446 entry->size = le32_to_cpu(fwdat[fwlen++]); 447 if (fwlen + entry->size > fwsize) 448 goto error_inval; 449 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL); 450 if (!entry->data) 451 goto error; 452 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4); 453 fwlen += entry->size; 454 } 455 456 *module_ret = module; 457 release_firmware(fw); 458 return 0; 459 460 error_inval: 461 err = -EINVAL; 462 error: 463 free_module_desc(module); 464 release_firmware(fw); 465 return err; 466 } 467 468 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, 469 unsigned long offset, 470 unsigned long len) 471 { 472 void __iomem *dst; 473 unsigned int bank = offset >> 16; 474 offset = offset & 0xffff; 475 476 if (snd_BUG_ON((offset & 3) || (len & 3))) 477 return -EINVAL; 478 dst = chip->region.idx[bank+1].remap_addr + offset; 479 len /= sizeof(u32); 480 481 /* writel already converts 32-bit value to right endianess */ 482 while (len-- > 0) { 483 writel(0, dst); 484 dst += sizeof(u32); 485 } 486 return 0; 487 } 488 489 #else /* old DSP image */ 490 491 struct ba1_struct { 492 struct { 493 u32 offset; 494 u32 size; 495 } memory[BA1_MEMORY_COUNT]; 496 u32 map[BA1_DWORD_SIZE]; 497 }; 498 499 MODULE_FIRMWARE("cs46xx/ba1"); 500 501 static int load_firmware(struct snd_cs46xx *chip) 502 { 503 const struct firmware *fw; 504 int i, size, err; 505 506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev); 507 if (err < 0) 508 return err; 509 if (fw->size != sizeof(*chip->ba1)) { 510 err = -EINVAL; 511 goto error; 512 } 513 514 chip->ba1 = vmalloc(sizeof(*chip->ba1)); 515 if (!chip->ba1) { 516 err = -ENOMEM; 517 goto error; 518 } 519 520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1)); 521 522 /* sanity check */ 523 size = 0; 524 for (i = 0; i < BA1_MEMORY_COUNT; i++) 525 size += chip->ba1->memory[i].size; 526 if (size > BA1_DWORD_SIZE * 4) 527 err = -EINVAL; 528 529 error: 530 release_firmware(fw); 531 return err; 532 } 533 534 int snd_cs46xx_download_image(struct snd_cs46xx *chip) 535 { 536 int idx, err; 537 unsigned int offset = 0; 538 struct ba1_struct *ba1 = chip->ba1; 539 540 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) { 541 err = snd_cs46xx_download(chip, 542 &ba1->map[offset], 543 ba1->memory[idx].offset, 544 ba1->memory[idx].size); 545 if (err < 0) 546 return err; 547 offset += ba1->memory[idx].size >> 2; 548 } 549 return 0; 550 } 551 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 552 553 /* 554 * Chip reset 555 */ 556 557 static void snd_cs46xx_reset(struct snd_cs46xx *chip) 558 { 559 int idx; 560 561 /* 562 * Write the reset bit of the SP control register. 563 */ 564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP); 565 566 /* 567 * Write the control register. 568 */ 569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN); 570 571 /* 572 * Clear the trap registers. 573 */ 574 for (idx = 0; idx < 8; idx++) { 575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx); 576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF); 577 } 578 snd_cs46xx_poke(chip, BA1_DREG, 0); 579 580 /* 581 * Set the frame timer to reflect the number of cycles per frame. 582 */ 583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 584 } 585 586 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout) 587 { 588 u32 i, status = 0; 589 /* 590 * Make sure the previous FIFO write operation has completed. 591 */ 592 for(i = 0; i < 50; i++){ 593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST); 594 595 if( !(status & SERBST_WBSY) ) 596 break; 597 598 mdelay(retry_timeout); 599 } 600 601 if(status & SERBST_WBSY) { 602 dev_err(chip->card->dev, 603 "failure waiting for FIFO command to complete\n"); 604 return -EINVAL; 605 } 606 607 return 0; 608 } 609 610 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip) 611 { 612 int idx, powerdown = 0; 613 unsigned int tmp; 614 615 /* 616 * See if the devices are powered down. If so, we must power them up first 617 * or they will not respond. 618 */ 619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 620 if (!(tmp & CLKCR1_SWCE)) { 621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 622 powerdown = 1; 623 } 624 625 /* 626 * We want to clear out the serial port FIFOs so we don't end up playing 627 * whatever random garbage happens to be in them. We fill the sample FIFOS 628 * with zero (silence). 629 */ 630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0); 631 632 /* 633 * Fill all 256 sample FIFO locations. 634 */ 635 for (idx = 0; idx < 0xFF; idx++) { 636 /* 637 * Make sure the previous FIFO write operation has completed. 638 */ 639 if (cs46xx_wait_for_fifo(chip,1)) { 640 dev_dbg(chip->card->dev, 641 "failed waiting for FIFO at addr (%02X)\n", 642 idx); 643 644 if (powerdown) 645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 646 647 break; 648 } 649 /* 650 * Write the serial port FIFO index. 651 */ 652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 653 /* 654 * Tell the serial port to load the new value into the FIFO location. 655 */ 656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 657 } 658 /* 659 * Now, if we powered up the devices, then power them back down again. 660 * This is kinda ugly, but should never happen. 661 */ 662 if (powerdown) 663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 664 } 665 666 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip) 667 { 668 int cnt; 669 670 /* 671 * Set the frame timer to reflect the number of cycles per frame. 672 */ 673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 674 /* 675 * Turn on the run, run at frame, and DMA enable bits in the local copy of 676 * the SP control register. 677 */ 678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 679 /* 680 * Wait until the run at frame bit resets itself in the SP control 681 * register. 682 */ 683 for (cnt = 0; cnt < 25; cnt++) { 684 udelay(50); 685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)) 686 break; 687 } 688 689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR) 690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n"); 691 } 692 693 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip) 694 { 695 /* 696 * Turn off the run, run at frame, and DMA enable bits in the local copy of 697 * the SP control register. 698 */ 699 snd_cs46xx_poke(chip, BA1_SPCR, 0); 700 } 701 702 /* 703 * Sample rate routines 704 */ 705 706 #define GOF_PER_SEC 200 707 708 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 709 { 710 unsigned long flags; 711 unsigned int tmp1, tmp2; 712 unsigned int phiIncr; 713 unsigned int correctionPerGOF, correctionPerSec; 714 715 /* 716 * Compute the values used to drive the actual sample rate conversion. 717 * The following formulas are being computed, using inline assembly 718 * since we need to use 64 bit arithmetic to compute the values: 719 * 720 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 721 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 722 * GOF_PER_SEC) 723 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M 724 * GOF_PER_SEC * correctionPerGOF 725 * 726 * i.e. 727 * 728 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out) 729 * correctionPerGOF:correctionPerSec = 730 * dividend:remainder(ulOther / GOF_PER_SEC) 731 */ 732 tmp1 = rate << 16; 733 phiIncr = tmp1 / 48000; 734 tmp1 -= phiIncr * 48000; 735 tmp1 <<= 10; 736 phiIncr <<= 10; 737 tmp2 = tmp1 / 48000; 738 phiIncr += tmp2; 739 tmp1 -= tmp2 * 48000; 740 correctionPerGOF = tmp1 / GOF_PER_SEC; 741 tmp1 -= correctionPerGOF * GOF_PER_SEC; 742 correctionPerSec = tmp1; 743 744 /* 745 * Fill in the SampleRateConverter control block. 746 */ 747 spin_lock_irqsave(&chip->reg_lock, flags); 748 snd_cs46xx_poke(chip, BA1_PSRC, 749 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr); 751 spin_unlock_irqrestore(&chip->reg_lock, flags); 752 } 753 754 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 755 { 756 unsigned long flags; 757 unsigned int phiIncr, coeffIncr, tmp1, tmp2; 758 unsigned int correctionPerGOF, correctionPerSec, initialDelay; 759 unsigned int frameGroupLength, cnt; 760 761 /* 762 * We can only decimate by up to a factor of 1/9th the hardware rate. 763 * Correct the value if an attempt is made to stray outside that limit. 764 */ 765 if ((rate * 9) < 48000) 766 rate = 48000 / 9; 767 768 /* 769 * We can not capture at a rate greater than the Input Rate (48000). 770 * Return an error if an attempt is made to stray outside that limit. 771 */ 772 if (rate > 48000) 773 rate = 48000; 774 775 /* 776 * Compute the values used to drive the actual sample rate conversion. 777 * The following formulas are being computed, using inline assembly 778 * since we need to use 64 bit arithmetic to compute the values: 779 * 780 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in) 781 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 782 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 783 * GOF_PER_SEC) 784 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr - 785 * GOF_PER_SEC * correctionPerGOF 786 * initialDelay = ceil((24 * Fs,in) / Fs,out) 787 * 788 * i.e. 789 * 790 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in)) 791 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out) 792 * correctionPerGOF:correctionPerSec = 793 * dividend:remainder(ulOther / GOF_PER_SEC) 794 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out) 795 */ 796 797 tmp1 = rate << 16; 798 coeffIncr = tmp1 / 48000; 799 tmp1 -= coeffIncr * 48000; 800 tmp1 <<= 7; 801 coeffIncr <<= 7; 802 coeffIncr += tmp1 / 48000; 803 coeffIncr ^= 0xFFFFFFFF; 804 coeffIncr++; 805 tmp1 = 48000 << 16; 806 phiIncr = tmp1 / rate; 807 tmp1 -= phiIncr * rate; 808 tmp1 <<= 10; 809 phiIncr <<= 10; 810 tmp2 = tmp1 / rate; 811 phiIncr += tmp2; 812 tmp1 -= tmp2 * rate; 813 correctionPerGOF = tmp1 / GOF_PER_SEC; 814 tmp1 -= correctionPerGOF * GOF_PER_SEC; 815 correctionPerSec = tmp1; 816 initialDelay = DIV_ROUND_UP(48000 * 24, rate); 817 818 /* 819 * Fill in the VariDecimate control block. 820 */ 821 spin_lock_irqsave(&chip->reg_lock, flags); 822 snd_cs46xx_poke(chip, BA1_CSRC, 823 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr); 825 snd_cs46xx_poke(chip, BA1_CD, 826 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80); 827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr); 828 spin_unlock_irqrestore(&chip->reg_lock, flags); 829 830 /* 831 * Figure out the frame group length for the write back task. Basically, 832 * this is just the factors of 24000 (2^6*3*5^3) that are not present in 833 * the output sample rate. 834 */ 835 frameGroupLength = 1; 836 for (cnt = 2; cnt <= 64; cnt *= 2) { 837 if (((rate / cnt) * cnt) != rate) 838 frameGroupLength *= 2; 839 } 840 if (((rate / 3) * 3) != rate) { 841 frameGroupLength *= 3; 842 } 843 for (cnt = 5; cnt <= 125; cnt *= 5) { 844 if (((rate / cnt) * cnt) != rate) 845 frameGroupLength *= 5; 846 } 847 848 /* 849 * Fill in the WriteBack control block. 850 */ 851 spin_lock_irqsave(&chip->reg_lock, flags); 852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength); 853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength)); 854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF); 855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000)); 856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF); 857 spin_unlock_irqrestore(&chip->reg_lock, flags); 858 } 859 860 /* 861 * PCM part 862 */ 863 864 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream, 865 struct snd_pcm_indirect *rec, size_t bytes) 866 { 867 struct snd_pcm_runtime *runtime = substream->runtime; 868 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 869 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes); 870 } 871 872 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream) 873 { 874 struct snd_pcm_runtime *runtime = substream->runtime; 875 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 876 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, 877 snd_cs46xx_pb_trans_copy); 878 } 879 880 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream, 881 struct snd_pcm_indirect *rec, size_t bytes) 882 { 883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 884 struct snd_pcm_runtime *runtime = substream->runtime; 885 memcpy(runtime->dma_area + rec->sw_data, 886 chip->capt.hw_buf.area + rec->hw_data, bytes); 887 } 888 889 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream) 890 { 891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, 893 snd_cs46xx_cp_trans_copy); 894 } 895 896 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream) 897 { 898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 899 size_t ptr; 900 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 901 902 if (snd_BUG_ON(!cpcm->pcm_channel)) 903 return -ENXIO; 904 905 #ifdef CONFIG_SND_CS46XX_NEW_DSP 906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 907 #else 908 ptr = snd_cs46xx_peek(chip, BA1_PBA); 909 #endif 910 ptr -= cpcm->hw_buf.addr; 911 return ptr >> cpcm->shift; 912 } 913 914 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream) 915 { 916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 917 size_t ptr; 918 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 919 920 #ifdef CONFIG_SND_CS46XX_NEW_DSP 921 if (snd_BUG_ON(!cpcm->pcm_channel)) 922 return -ENXIO; 923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 924 #else 925 ptr = snd_cs46xx_peek(chip, BA1_PBA); 926 #endif 927 ptr -= cpcm->hw_buf.addr; 928 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr); 929 } 930 931 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream) 932 { 933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 935 return ptr >> chip->capt.shift; 936 } 937 938 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream) 939 { 940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr); 943 } 944 945 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream, 946 int cmd) 947 { 948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 949 /*struct snd_pcm_runtime *runtime = substream->runtime;*/ 950 int result = 0; 951 952 #ifdef CONFIG_SND_CS46XX_NEW_DSP 953 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 954 if (! cpcm->pcm_channel) { 955 return -ENXIO; 956 } 957 #endif 958 switch (cmd) { 959 case SNDRV_PCM_TRIGGER_START: 960 case SNDRV_PCM_TRIGGER_RESUME: 961 #ifdef CONFIG_SND_CS46XX_NEW_DSP 962 /* magic value to unmute PCM stream playback volume */ 963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 964 SCBVolumeCtrl) << 2, 0x80008000); 965 966 if (cpcm->pcm_channel->unlinked) 967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel); 968 969 if (substream->runtime->periods != CS46XX_FRAGS) 970 snd_cs46xx_playback_transfer(substream); 971 #else 972 spin_lock(&chip->reg_lock); 973 if (substream->runtime->periods != CS46XX_FRAGS) 974 snd_cs46xx_playback_transfer(substream); 975 { unsigned int tmp; 976 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 977 tmp &= 0x0000ffff; 978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp); 979 } 980 spin_unlock(&chip->reg_lock); 981 #endif 982 break; 983 case SNDRV_PCM_TRIGGER_STOP: 984 case SNDRV_PCM_TRIGGER_SUSPEND: 985 #ifdef CONFIG_SND_CS46XX_NEW_DSP 986 /* magic mute channel */ 987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 988 SCBVolumeCtrl) << 2, 0xffffffff); 989 990 if (!cpcm->pcm_channel->unlinked) 991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel); 992 #else 993 spin_lock(&chip->reg_lock); 994 { unsigned int tmp; 995 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 996 tmp &= 0x0000ffff; 997 snd_cs46xx_poke(chip, BA1_PCTL, tmp); 998 } 999 spin_unlock(&chip->reg_lock); 1000 #endif 1001 break; 1002 default: 1003 result = -EINVAL; 1004 break; 1005 } 1006 1007 return result; 1008 } 1009 1010 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream, 1011 int cmd) 1012 { 1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1014 unsigned int tmp; 1015 int result = 0; 1016 1017 spin_lock(&chip->reg_lock); 1018 switch (cmd) { 1019 case SNDRV_PCM_TRIGGER_START: 1020 case SNDRV_PCM_TRIGGER_RESUME: 1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 1022 tmp &= 0xffff0000; 1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp); 1024 break; 1025 case SNDRV_PCM_TRIGGER_STOP: 1026 case SNDRV_PCM_TRIGGER_SUSPEND: 1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 1028 tmp &= 0xffff0000; 1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp); 1030 break; 1031 default: 1032 result = -EINVAL; 1033 break; 1034 } 1035 spin_unlock(&chip->reg_lock); 1036 1037 return result; 1038 } 1039 1040 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1041 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm, 1042 int sample_rate) 1043 { 1044 1045 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */ 1046 if ( cpcm->pcm_channel == NULL) { 1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, 1048 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id); 1049 if (cpcm->pcm_channel == NULL) { 1050 dev_err(chip->card->dev, 1051 "failed to create virtual PCM channel\n"); 1052 return -ENOMEM; 1053 } 1054 cpcm->pcm_channel->sample_rate = sample_rate; 1055 } else 1056 /* if sample rate is changed */ 1057 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) { 1058 int unlinked = cpcm->pcm_channel->unlinked; 1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel); 1060 1061 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm, 1062 cpcm->hw_buf.addr, 1063 cpcm->pcm_channel_id); 1064 if (!cpcm->pcm_channel) { 1065 dev_err(chip->card->dev, 1066 "failed to re-create virtual PCM channel\n"); 1067 return -ENOMEM; 1068 } 1069 1070 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel); 1071 cpcm->pcm_channel->sample_rate = sample_rate; 1072 } 1073 1074 return 0; 1075 } 1076 #endif 1077 1078 1079 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream, 1080 struct snd_pcm_hw_params *hw_params) 1081 { 1082 struct snd_pcm_runtime *runtime = substream->runtime; 1083 struct snd_cs46xx_pcm *cpcm; 1084 int err; 1085 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1086 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1087 int sample_rate = params_rate(hw_params); 1088 int period_size = params_period_bytes(hw_params); 1089 #endif 1090 cpcm = runtime->private_data; 1091 1092 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1093 if (snd_BUG_ON(!sample_rate)) 1094 return -ENXIO; 1095 1096 mutex_lock(&chip->spos_mutex); 1097 1098 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) { 1099 mutex_unlock(&chip->spos_mutex); 1100 return -ENXIO; 1101 } 1102 1103 snd_BUG_ON(!cpcm->pcm_channel); 1104 if (!cpcm->pcm_channel) { 1105 mutex_unlock(&chip->spos_mutex); 1106 return -ENXIO; 1107 } 1108 1109 1110 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) { 1111 mutex_unlock(&chip->spos_mutex); 1112 return -EINVAL; 1113 } 1114 1115 dev_dbg(chip->card->dev, 1116 "period_size (%d), periods (%d) buffer_size(%d)\n", 1117 period_size, params_periods(hw_params), 1118 params_buffer_bytes(hw_params)); 1119 #endif 1120 1121 if (params_periods(hw_params) == CS46XX_FRAGS) { 1122 if (runtime->dma_area != cpcm->hw_buf.area) 1123 snd_pcm_lib_free_pages(substream); 1124 runtime->dma_area = cpcm->hw_buf.area; 1125 runtime->dma_addr = cpcm->hw_buf.addr; 1126 runtime->dma_bytes = cpcm->hw_buf.bytes; 1127 1128 1129 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1130 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 1131 substream->ops = &snd_cs46xx_playback_ops; 1132 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 1133 substream->ops = &snd_cs46xx_playback_rear_ops; 1134 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 1135 substream->ops = &snd_cs46xx_playback_clfe_ops; 1136 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 1137 substream->ops = &snd_cs46xx_playback_iec958_ops; 1138 } else { 1139 snd_BUG(); 1140 } 1141 #else 1142 substream->ops = &snd_cs46xx_playback_ops; 1143 #endif 1144 1145 } else { 1146 if (runtime->dma_area == cpcm->hw_buf.area) { 1147 runtime->dma_area = NULL; 1148 runtime->dma_addr = 0; 1149 runtime->dma_bytes = 0; 1150 } 1151 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 1152 if (err < 0) { 1153 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1154 mutex_unlock(&chip->spos_mutex); 1155 #endif 1156 return err; 1157 } 1158 1159 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1160 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 1161 substream->ops = &snd_cs46xx_playback_indirect_ops; 1162 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 1163 substream->ops = &snd_cs46xx_playback_indirect_rear_ops; 1164 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 1165 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops; 1166 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 1167 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops; 1168 } else { 1169 snd_BUG(); 1170 } 1171 #else 1172 substream->ops = &snd_cs46xx_playback_indirect_ops; 1173 #endif 1174 1175 } 1176 1177 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1178 mutex_unlock(&chip->spos_mutex); 1179 #endif 1180 1181 return 0; 1182 } 1183 1184 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream) 1185 { 1186 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/ 1187 struct snd_pcm_runtime *runtime = substream->runtime; 1188 struct snd_cs46xx_pcm *cpcm; 1189 1190 cpcm = runtime->private_data; 1191 1192 /* if play_back open fails, then this function 1193 is called and cpcm can actually be NULL here */ 1194 if (!cpcm) return -ENXIO; 1195 1196 if (runtime->dma_area != cpcm->hw_buf.area) 1197 snd_pcm_lib_free_pages(substream); 1198 1199 runtime->dma_area = NULL; 1200 runtime->dma_addr = 0; 1201 runtime->dma_bytes = 0; 1202 1203 return 0; 1204 } 1205 1206 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream) 1207 { 1208 unsigned int tmp; 1209 unsigned int pfie; 1210 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1211 struct snd_pcm_runtime *runtime = substream->runtime; 1212 struct snd_cs46xx_pcm *cpcm; 1213 1214 cpcm = runtime->private_data; 1215 1216 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1217 if (snd_BUG_ON(!cpcm->pcm_channel)) 1218 return -ENXIO; 1219 1220 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 ); 1221 pfie &= ~0x0000f03f; 1222 #else 1223 /* old dsp */ 1224 pfie = snd_cs46xx_peek(chip, BA1_PFIE); 1225 pfie &= ~0x0000f03f; 1226 #endif 1227 1228 cpcm->shift = 2; 1229 /* if to convert from stereo to mono */ 1230 if (runtime->channels == 1) { 1231 cpcm->shift--; 1232 pfie |= 0x00002000; 1233 } 1234 /* if to convert from 8 bit to 16 bit */ 1235 if (snd_pcm_format_width(runtime->format) == 8) { 1236 cpcm->shift--; 1237 pfie |= 0x00001000; 1238 } 1239 /* if to convert to unsigned */ 1240 if (snd_pcm_format_unsigned(runtime->format)) 1241 pfie |= 0x00008000; 1242 1243 /* Never convert byte order when sample stream is 8 bit */ 1244 if (snd_pcm_format_width(runtime->format) != 8) { 1245 /* convert from big endian to little endian */ 1246 if (snd_pcm_format_big_endian(runtime->format)) 1247 pfie |= 0x00004000; 1248 } 1249 1250 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec)); 1251 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1252 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift; 1253 1254 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1255 1256 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2); 1257 tmp &= ~0x000003ff; 1258 tmp |= (4 << cpcm->shift) - 1; 1259 /* playback transaction count register */ 1260 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp); 1261 1262 /* playback format && interrupt enable */ 1263 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot); 1264 #else 1265 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr); 1266 tmp = snd_cs46xx_peek(chip, BA1_PDTC); 1267 tmp &= ~0x000003ff; 1268 tmp |= (4 << cpcm->shift) - 1; 1269 snd_cs46xx_poke(chip, BA1_PDTC, tmp); 1270 snd_cs46xx_poke(chip, BA1_PFIE, pfie); 1271 snd_cs46xx_set_play_sample_rate(chip, runtime->rate); 1272 #endif 1273 1274 return 0; 1275 } 1276 1277 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream, 1278 struct snd_pcm_hw_params *hw_params) 1279 { 1280 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1281 struct snd_pcm_runtime *runtime = substream->runtime; 1282 int err; 1283 1284 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1285 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params)); 1286 #endif 1287 if (runtime->periods == CS46XX_FRAGS) { 1288 if (runtime->dma_area != chip->capt.hw_buf.area) 1289 snd_pcm_lib_free_pages(substream); 1290 runtime->dma_area = chip->capt.hw_buf.area; 1291 runtime->dma_addr = chip->capt.hw_buf.addr; 1292 runtime->dma_bytes = chip->capt.hw_buf.bytes; 1293 substream->ops = &snd_cs46xx_capture_ops; 1294 } else { 1295 if (runtime->dma_area == chip->capt.hw_buf.area) { 1296 runtime->dma_area = NULL; 1297 runtime->dma_addr = 0; 1298 runtime->dma_bytes = 0; 1299 } 1300 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 1301 if (err < 0) 1302 return err; 1303 substream->ops = &snd_cs46xx_capture_indirect_ops; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream) 1310 { 1311 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1312 struct snd_pcm_runtime *runtime = substream->runtime; 1313 1314 if (runtime->dma_area != chip->capt.hw_buf.area) 1315 snd_pcm_lib_free_pages(substream); 1316 runtime->dma_area = NULL; 1317 runtime->dma_addr = 0; 1318 runtime->dma_bytes = 0; 1319 1320 return 0; 1321 } 1322 1323 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream) 1324 { 1325 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1326 struct snd_pcm_runtime *runtime = substream->runtime; 1327 1328 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr); 1329 chip->capt.shift = 2; 1330 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec)); 1331 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1332 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2; 1333 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate); 1334 1335 return 0; 1336 } 1337 1338 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id) 1339 { 1340 struct snd_cs46xx *chip = dev_id; 1341 u32 status1; 1342 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1343 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1344 u32 status2; 1345 int i; 1346 struct snd_cs46xx_pcm *cpcm = NULL; 1347 #endif 1348 1349 /* 1350 * Read the Interrupt Status Register to clear the interrupt 1351 */ 1352 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR); 1353 if ((status1 & 0x7fffffff) == 0) { 1354 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1355 return IRQ_NONE; 1356 } 1357 1358 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1359 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0); 1360 1361 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) { 1362 if (i <= 15) { 1363 if ( status1 & (1 << i) ) { 1364 if (i == CS46XX_DSP_CAPTURE_CHANNEL) { 1365 if (chip->capt.substream) 1366 snd_pcm_period_elapsed(chip->capt.substream); 1367 } else { 1368 if (ins->pcm_channels[i].active && 1369 ins->pcm_channels[i].private_data && 1370 !ins->pcm_channels[i].unlinked) { 1371 cpcm = ins->pcm_channels[i].private_data; 1372 snd_pcm_period_elapsed(cpcm->substream); 1373 } 1374 } 1375 } 1376 } else { 1377 if ( status2 & (1 << (i - 16))) { 1378 if (ins->pcm_channels[i].active && 1379 ins->pcm_channels[i].private_data && 1380 !ins->pcm_channels[i].unlinked) { 1381 cpcm = ins->pcm_channels[i].private_data; 1382 snd_pcm_period_elapsed(cpcm->substream); 1383 } 1384 } 1385 } 1386 } 1387 1388 #else 1389 /* old dsp */ 1390 if ((status1 & HISR_VC0) && chip->playback_pcm) { 1391 if (chip->playback_pcm->substream) 1392 snd_pcm_period_elapsed(chip->playback_pcm->substream); 1393 } 1394 if ((status1 & HISR_VC1) && chip->pcm) { 1395 if (chip->capt.substream) 1396 snd_pcm_period_elapsed(chip->capt.substream); 1397 } 1398 #endif 1399 1400 if ((status1 & HISR_MIDI) && chip->rmidi) { 1401 unsigned char c; 1402 1403 spin_lock(&chip->reg_lock); 1404 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) { 1405 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP); 1406 if ((chip->midcr & MIDCR_RIE) == 0) 1407 continue; 1408 snd_rawmidi_receive(chip->midi_input, &c, 1); 1409 } 1410 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 1411 if ((chip->midcr & MIDCR_TIE) == 0) 1412 break; 1413 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1414 chip->midcr &= ~MIDCR_TIE; 1415 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1416 break; 1417 } 1418 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c); 1419 } 1420 spin_unlock(&chip->reg_lock); 1421 } 1422 /* 1423 * EOI to the PCI part....reenables interrupts 1424 */ 1425 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1426 1427 return IRQ_HANDLED; 1428 } 1429 1430 static const struct snd_pcm_hardware snd_cs46xx_playback = 1431 { 1432 .info = (SNDRV_PCM_INFO_MMAP | 1433 SNDRV_PCM_INFO_INTERLEAVED | 1434 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1435 /*SNDRV_PCM_INFO_RESUME*/ | 1436 SNDRV_PCM_INFO_SYNC_APPLPTR), 1437 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | 1438 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 1439 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE), 1440 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1441 .rate_min = 5500, 1442 .rate_max = 48000, 1443 .channels_min = 1, 1444 .channels_max = 2, 1445 .buffer_bytes_max = (256 * 1024), 1446 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1447 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1448 .periods_min = CS46XX_FRAGS, 1449 .periods_max = 1024, 1450 .fifo_size = 0, 1451 }; 1452 1453 static const struct snd_pcm_hardware snd_cs46xx_capture = 1454 { 1455 .info = (SNDRV_PCM_INFO_MMAP | 1456 SNDRV_PCM_INFO_INTERLEAVED | 1457 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1458 /*SNDRV_PCM_INFO_RESUME*/ | 1459 SNDRV_PCM_INFO_SYNC_APPLPTR), 1460 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1461 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1462 .rate_min = 5500, 1463 .rate_max = 48000, 1464 .channels_min = 2, 1465 .channels_max = 2, 1466 .buffer_bytes_max = (256 * 1024), 1467 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1468 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1469 .periods_min = CS46XX_FRAGS, 1470 .periods_max = 1024, 1471 .fifo_size = 0, 1472 }; 1473 1474 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1475 1476 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 }; 1477 1478 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = { 1479 .count = ARRAY_SIZE(period_sizes), 1480 .list = period_sizes, 1481 .mask = 0 1482 }; 1483 1484 #endif 1485 1486 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime) 1487 { 1488 kfree(runtime->private_data); 1489 } 1490 1491 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id) 1492 { 1493 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1494 struct snd_cs46xx_pcm * cpcm; 1495 struct snd_pcm_runtime *runtime = substream->runtime; 1496 1497 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL); 1498 if (cpcm == NULL) 1499 return -ENOMEM; 1500 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 1501 PAGE_SIZE, &cpcm->hw_buf) < 0) { 1502 kfree(cpcm); 1503 return -ENOMEM; 1504 } 1505 1506 runtime->hw = snd_cs46xx_playback; 1507 runtime->private_data = cpcm; 1508 runtime->private_free = snd_cs46xx_pcm_free_substream; 1509 1510 cpcm->substream = substream; 1511 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1512 mutex_lock(&chip->spos_mutex); 1513 cpcm->pcm_channel = NULL; 1514 cpcm->pcm_channel_id = pcm_channel_id; 1515 1516 1517 snd_pcm_hw_constraint_list(runtime, 0, 1518 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1519 &hw_constraints_period_sizes); 1520 1521 mutex_unlock(&chip->spos_mutex); 1522 #else 1523 chip->playback_pcm = cpcm; /* HACK */ 1524 #endif 1525 1526 if (chip->accept_valid) 1527 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1528 chip->active_ctrl(chip, 1); 1529 1530 return 0; 1531 } 1532 1533 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream) 1534 { 1535 dev_dbg(substream->pcm->card->dev, "open front channel\n"); 1536 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL); 1537 } 1538 1539 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1540 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream) 1541 { 1542 dev_dbg(substream->pcm->card->dev, "open rear channel\n"); 1543 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL); 1544 } 1545 1546 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream) 1547 { 1548 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n"); 1549 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL); 1550 } 1551 1552 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream) 1553 { 1554 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1555 1556 dev_dbg(chip->card->dev, "open raw iec958 channel\n"); 1557 1558 mutex_lock(&chip->spos_mutex); 1559 cs46xx_iec958_pre_open (chip); 1560 mutex_unlock(&chip->spos_mutex); 1561 1562 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL); 1563 } 1564 1565 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream); 1566 1567 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream) 1568 { 1569 int err; 1570 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1571 1572 dev_dbg(chip->card->dev, "close raw iec958 channel\n"); 1573 1574 err = snd_cs46xx_playback_close(substream); 1575 1576 mutex_lock(&chip->spos_mutex); 1577 cs46xx_iec958_post_close (chip); 1578 mutex_unlock(&chip->spos_mutex); 1579 1580 return err; 1581 } 1582 #endif 1583 1584 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream) 1585 { 1586 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1587 1588 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 1589 PAGE_SIZE, &chip->capt.hw_buf) < 0) 1590 return -ENOMEM; 1591 chip->capt.substream = substream; 1592 substream->runtime->hw = snd_cs46xx_capture; 1593 1594 if (chip->accept_valid) 1595 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1596 1597 chip->active_ctrl(chip, 1); 1598 1599 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1600 snd_pcm_hw_constraint_list(substream->runtime, 0, 1601 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1602 &hw_constraints_period_sizes); 1603 #endif 1604 return 0; 1605 } 1606 1607 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream) 1608 { 1609 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1610 struct snd_pcm_runtime *runtime = substream->runtime; 1611 struct snd_cs46xx_pcm * cpcm; 1612 1613 cpcm = runtime->private_data; 1614 1615 /* when playback_open fails, then cpcm can be NULL */ 1616 if (!cpcm) return -ENXIO; 1617 1618 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1619 mutex_lock(&chip->spos_mutex); 1620 if (cpcm->pcm_channel) { 1621 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel); 1622 cpcm->pcm_channel = NULL; 1623 } 1624 mutex_unlock(&chip->spos_mutex); 1625 #else 1626 chip->playback_pcm = NULL; 1627 #endif 1628 1629 cpcm->substream = NULL; 1630 snd_dma_free_pages(&cpcm->hw_buf); 1631 chip->active_ctrl(chip, -1); 1632 1633 return 0; 1634 } 1635 1636 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) 1637 { 1638 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1639 1640 chip->capt.substream = NULL; 1641 snd_dma_free_pages(&chip->capt.hw_buf); 1642 chip->active_ctrl(chip, -1); 1643 1644 return 0; 1645 } 1646 1647 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1648 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { 1649 .open = snd_cs46xx_playback_open_rear, 1650 .close = snd_cs46xx_playback_close, 1651 .hw_params = snd_cs46xx_playback_hw_params, 1652 .hw_free = snd_cs46xx_playback_hw_free, 1653 .prepare = snd_cs46xx_playback_prepare, 1654 .trigger = snd_cs46xx_playback_trigger, 1655 .pointer = snd_cs46xx_playback_direct_pointer, 1656 }; 1657 1658 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { 1659 .open = snd_cs46xx_playback_open_rear, 1660 .close = snd_cs46xx_playback_close, 1661 .hw_params = snd_cs46xx_playback_hw_params, 1662 .hw_free = snd_cs46xx_playback_hw_free, 1663 .prepare = snd_cs46xx_playback_prepare, 1664 .trigger = snd_cs46xx_playback_trigger, 1665 .pointer = snd_cs46xx_playback_indirect_pointer, 1666 .ack = snd_cs46xx_playback_transfer, 1667 }; 1668 1669 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { 1670 .open = snd_cs46xx_playback_open_clfe, 1671 .close = snd_cs46xx_playback_close, 1672 .hw_params = snd_cs46xx_playback_hw_params, 1673 .hw_free = snd_cs46xx_playback_hw_free, 1674 .prepare = snd_cs46xx_playback_prepare, 1675 .trigger = snd_cs46xx_playback_trigger, 1676 .pointer = snd_cs46xx_playback_direct_pointer, 1677 }; 1678 1679 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { 1680 .open = snd_cs46xx_playback_open_clfe, 1681 .close = snd_cs46xx_playback_close, 1682 .hw_params = snd_cs46xx_playback_hw_params, 1683 .hw_free = snd_cs46xx_playback_hw_free, 1684 .prepare = snd_cs46xx_playback_prepare, 1685 .trigger = snd_cs46xx_playback_trigger, 1686 .pointer = snd_cs46xx_playback_indirect_pointer, 1687 .ack = snd_cs46xx_playback_transfer, 1688 }; 1689 1690 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { 1691 .open = snd_cs46xx_playback_open_iec958, 1692 .close = snd_cs46xx_playback_close_iec958, 1693 .hw_params = snd_cs46xx_playback_hw_params, 1694 .hw_free = snd_cs46xx_playback_hw_free, 1695 .prepare = snd_cs46xx_playback_prepare, 1696 .trigger = snd_cs46xx_playback_trigger, 1697 .pointer = snd_cs46xx_playback_direct_pointer, 1698 }; 1699 1700 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { 1701 .open = snd_cs46xx_playback_open_iec958, 1702 .close = snd_cs46xx_playback_close_iec958, 1703 .hw_params = snd_cs46xx_playback_hw_params, 1704 .hw_free = snd_cs46xx_playback_hw_free, 1705 .prepare = snd_cs46xx_playback_prepare, 1706 .trigger = snd_cs46xx_playback_trigger, 1707 .pointer = snd_cs46xx_playback_indirect_pointer, 1708 .ack = snd_cs46xx_playback_transfer, 1709 }; 1710 1711 #endif 1712 1713 static const struct snd_pcm_ops snd_cs46xx_playback_ops = { 1714 .open = snd_cs46xx_playback_open, 1715 .close = snd_cs46xx_playback_close, 1716 .hw_params = snd_cs46xx_playback_hw_params, 1717 .hw_free = snd_cs46xx_playback_hw_free, 1718 .prepare = snd_cs46xx_playback_prepare, 1719 .trigger = snd_cs46xx_playback_trigger, 1720 .pointer = snd_cs46xx_playback_direct_pointer, 1721 }; 1722 1723 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { 1724 .open = snd_cs46xx_playback_open, 1725 .close = snd_cs46xx_playback_close, 1726 .hw_params = snd_cs46xx_playback_hw_params, 1727 .hw_free = snd_cs46xx_playback_hw_free, 1728 .prepare = snd_cs46xx_playback_prepare, 1729 .trigger = snd_cs46xx_playback_trigger, 1730 .pointer = snd_cs46xx_playback_indirect_pointer, 1731 .ack = snd_cs46xx_playback_transfer, 1732 }; 1733 1734 static const struct snd_pcm_ops snd_cs46xx_capture_ops = { 1735 .open = snd_cs46xx_capture_open, 1736 .close = snd_cs46xx_capture_close, 1737 .hw_params = snd_cs46xx_capture_hw_params, 1738 .hw_free = snd_cs46xx_capture_hw_free, 1739 .prepare = snd_cs46xx_capture_prepare, 1740 .trigger = snd_cs46xx_capture_trigger, 1741 .pointer = snd_cs46xx_capture_direct_pointer, 1742 }; 1743 1744 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { 1745 .open = snd_cs46xx_capture_open, 1746 .close = snd_cs46xx_capture_close, 1747 .hw_params = snd_cs46xx_capture_hw_params, 1748 .hw_free = snd_cs46xx_capture_hw_free, 1749 .prepare = snd_cs46xx_capture_prepare, 1750 .trigger = snd_cs46xx_capture_trigger, 1751 .pointer = snd_cs46xx_capture_indirect_pointer, 1752 .ack = snd_cs46xx_capture_transfer, 1753 }; 1754 1755 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1756 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1) 1757 #else 1758 #define MAX_PLAYBACK_CHANNELS 1 1759 #endif 1760 1761 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device) 1762 { 1763 struct snd_pcm *pcm; 1764 int err; 1765 1766 err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm); 1767 if (err < 0) 1768 return err; 1769 1770 pcm->private_data = chip; 1771 1772 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops); 1773 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops); 1774 1775 /* global setup */ 1776 pcm->info_flags = 0; 1777 strcpy(pcm->name, "CS46xx"); 1778 chip->pcm = pcm; 1779 1780 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1781 &chip->pci->dev, 1782 64*1024, 256*1024); 1783 1784 return 0; 1785 } 1786 1787 1788 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1789 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device) 1790 { 1791 struct snd_pcm *pcm; 1792 int err; 1793 1794 err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm); 1795 if (err < 0) 1796 return err; 1797 1798 pcm->private_data = chip; 1799 1800 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops); 1801 1802 /* global setup */ 1803 pcm->info_flags = 0; 1804 strcpy(pcm->name, "CS46xx - Rear"); 1805 chip->pcm_rear = pcm; 1806 1807 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1808 &chip->pci->dev, 1809 64*1024, 256*1024); 1810 1811 return 0; 1812 } 1813 1814 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device) 1815 { 1816 struct snd_pcm *pcm; 1817 int err; 1818 1819 err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm); 1820 if (err < 0) 1821 return err; 1822 1823 pcm->private_data = chip; 1824 1825 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops); 1826 1827 /* global setup */ 1828 pcm->info_flags = 0; 1829 strcpy(pcm->name, "CS46xx - Center LFE"); 1830 chip->pcm_center_lfe = pcm; 1831 1832 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1833 &chip->pci->dev, 1834 64*1024, 256*1024); 1835 1836 return 0; 1837 } 1838 1839 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device) 1840 { 1841 struct snd_pcm *pcm; 1842 int err; 1843 1844 err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm); 1845 if (err < 0) 1846 return err; 1847 1848 pcm->private_data = chip; 1849 1850 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops); 1851 1852 /* global setup */ 1853 pcm->info_flags = 0; 1854 strcpy(pcm->name, "CS46xx - IEC958"); 1855 chip->pcm_iec958 = pcm; 1856 1857 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1858 &chip->pci->dev, 1859 64*1024, 256*1024); 1860 1861 return 0; 1862 } 1863 #endif 1864 1865 /* 1866 * Mixer routines 1867 */ 1868 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97) 1869 { 1870 struct snd_cs46xx *chip = ac97->private_data; 1871 1872 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] && 1873 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])) 1874 return; 1875 1876 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) { 1877 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL; 1878 chip->eapd_switch = NULL; 1879 } 1880 else 1881 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL; 1882 } 1883 1884 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol, 1885 struct snd_ctl_elem_info *uinfo) 1886 { 1887 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1888 uinfo->count = 2; 1889 uinfo->value.integer.min = 0; 1890 uinfo->value.integer.max = 0x7fff; 1891 return 0; 1892 } 1893 1894 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1895 { 1896 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1897 int reg = kcontrol->private_value; 1898 unsigned int val = snd_cs46xx_peek(chip, reg); 1899 ucontrol->value.integer.value[0] = 0xffff - (val >> 16); 1900 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff); 1901 return 0; 1902 } 1903 1904 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1905 { 1906 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1907 int reg = kcontrol->private_value; 1908 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | 1909 (0xffff - ucontrol->value.integer.value[1])); 1910 unsigned int old = snd_cs46xx_peek(chip, reg); 1911 int change = (old != val); 1912 1913 if (change) { 1914 snd_cs46xx_poke(chip, reg, val); 1915 } 1916 1917 return change; 1918 } 1919 1920 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1921 1922 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1923 { 1924 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1925 1926 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left; 1927 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right; 1928 1929 return 0; 1930 } 1931 1932 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1933 { 1934 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1935 int change = 0; 1936 1937 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] || 1938 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) { 1939 cs46xx_dsp_set_dac_volume(chip, 1940 ucontrol->value.integer.value[0], 1941 ucontrol->value.integer.value[1]); 1942 change = 1; 1943 } 1944 1945 return change; 1946 } 1947 1948 #if 0 1949 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1950 { 1951 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1952 1953 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left; 1954 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right; 1955 return 0; 1956 } 1957 1958 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1959 { 1960 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1961 int change = 0; 1962 1963 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] || 1964 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) { 1965 cs46xx_dsp_set_iec958_volume (chip, 1966 ucontrol->value.integer.value[0], 1967 ucontrol->value.integer.value[1]); 1968 change = 1; 1969 } 1970 1971 return change; 1972 } 1973 #endif 1974 1975 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info 1976 1977 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol, 1978 struct snd_ctl_elem_value *ucontrol) 1979 { 1980 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1981 int reg = kcontrol->private_value; 1982 1983 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT) 1984 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1985 else 1986 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in; 1987 1988 return 0; 1989 } 1990 1991 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol, 1992 struct snd_ctl_elem_value *ucontrol) 1993 { 1994 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1995 int change, res; 1996 1997 switch (kcontrol->private_value) { 1998 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT: 1999 mutex_lock(&chip->spos_mutex); 2000 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 2001 if (ucontrol->value.integer.value[0] && !change) 2002 cs46xx_dsp_enable_spdif_out(chip); 2003 else if (change && !ucontrol->value.integer.value[0]) 2004 cs46xx_dsp_disable_spdif_out(chip); 2005 2006 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED)); 2007 mutex_unlock(&chip->spos_mutex); 2008 break; 2009 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT: 2010 change = chip->dsp_spos_instance->spdif_status_in; 2011 if (ucontrol->value.integer.value[0] && !change) { 2012 cs46xx_dsp_enable_spdif_in(chip); 2013 /* restore volume */ 2014 } 2015 else if (change && !ucontrol->value.integer.value[0]) 2016 cs46xx_dsp_disable_spdif_in(chip); 2017 2018 res = (change != chip->dsp_spos_instance->spdif_status_in); 2019 break; 2020 default: 2021 res = -EINVAL; 2022 snd_BUG(); /* should never happen ... */ 2023 } 2024 2025 return res; 2026 } 2027 2028 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol, 2029 struct snd_ctl_elem_value *ucontrol) 2030 { 2031 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2032 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2033 2034 if (ins->adc_input != NULL) 2035 ucontrol->value.integer.value[0] = 1; 2036 else 2037 ucontrol->value.integer.value[0] = 0; 2038 2039 return 0; 2040 } 2041 2042 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol, 2043 struct snd_ctl_elem_value *ucontrol) 2044 { 2045 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2046 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2047 int change = 0; 2048 2049 if (ucontrol->value.integer.value[0] && !ins->adc_input) { 2050 cs46xx_dsp_enable_adc_capture(chip); 2051 change = 1; 2052 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) { 2053 cs46xx_dsp_disable_adc_capture(chip); 2054 change = 1; 2055 } 2056 return change; 2057 } 2058 2059 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol, 2060 struct snd_ctl_elem_value *ucontrol) 2061 { 2062 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2063 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2064 2065 if (ins->pcm_input != NULL) 2066 ucontrol->value.integer.value[0] = 1; 2067 else 2068 ucontrol->value.integer.value[0] = 0; 2069 2070 return 0; 2071 } 2072 2073 2074 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol, 2075 struct snd_ctl_elem_value *ucontrol) 2076 { 2077 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2078 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2079 int change = 0; 2080 2081 if (ucontrol->value.integer.value[0] && !ins->pcm_input) { 2082 cs46xx_dsp_enable_pcm_capture(chip); 2083 change = 1; 2084 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) { 2085 cs46xx_dsp_disable_pcm_capture(chip); 2086 change = 1; 2087 } 2088 2089 return change; 2090 } 2091 2092 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol, 2093 struct snd_ctl_elem_value *ucontrol) 2094 { 2095 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2096 2097 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 2098 2099 if (val1 & EGPIODR_GPOE0) 2100 ucontrol->value.integer.value[0] = 1; 2101 else 2102 ucontrol->value.integer.value[0] = 0; 2103 2104 return 0; 2105 } 2106 2107 /* 2108 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial. 2109 */ 2110 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol, 2111 struct snd_ctl_elem_value *ucontrol) 2112 { 2113 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2114 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 2115 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 2116 2117 if (ucontrol->value.integer.value[0]) { 2118 /* optical is default */ 2119 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 2120 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */ 2121 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 2122 EGPIOPTR_GPPT0 | val2); /* open-drain on output */ 2123 } else { 2124 /* coaxial */ 2125 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */ 2126 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */ 2127 } 2128 2129 /* checking diff from the EGPIO direction register 2130 should be enough */ 2131 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR)); 2132 } 2133 2134 2135 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2136 { 2137 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2138 uinfo->count = 1; 2139 return 0; 2140 } 2141 2142 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol, 2143 struct snd_ctl_elem_value *ucontrol) 2144 { 2145 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2146 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2147 2148 mutex_lock(&chip->spos_mutex); 2149 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff); 2150 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff); 2151 ucontrol->value.iec958.status[2] = 0; 2152 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff); 2153 mutex_unlock(&chip->spos_mutex); 2154 2155 return 0; 2156 } 2157 2158 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol, 2159 struct snd_ctl_elem_value *ucontrol) 2160 { 2161 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2162 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2163 unsigned int val; 2164 int change; 2165 2166 mutex_lock(&chip->spos_mutex); 2167 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2168 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) | 2169 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2170 /* left and right validity bit */ 2171 (1 << 13) | (1 << 12); 2172 2173 2174 change = (unsigned int)ins->spdif_csuv_default != val; 2175 ins->spdif_csuv_default = val; 2176 2177 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) ) 2178 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2179 2180 mutex_unlock(&chip->spos_mutex); 2181 2182 return change; 2183 } 2184 2185 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol, 2186 struct snd_ctl_elem_value *ucontrol) 2187 { 2188 ucontrol->value.iec958.status[0] = 0xff; 2189 ucontrol->value.iec958.status[1] = 0xff; 2190 ucontrol->value.iec958.status[2] = 0x00; 2191 ucontrol->value.iec958.status[3] = 0xff; 2192 return 0; 2193 } 2194 2195 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol, 2196 struct snd_ctl_elem_value *ucontrol) 2197 { 2198 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2199 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2200 2201 mutex_lock(&chip->spos_mutex); 2202 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff); 2203 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff); 2204 ucontrol->value.iec958.status[2] = 0; 2205 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff); 2206 mutex_unlock(&chip->spos_mutex); 2207 2208 return 0; 2209 } 2210 2211 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol, 2212 struct snd_ctl_elem_value *ucontrol) 2213 { 2214 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2215 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2216 unsigned int val; 2217 int change; 2218 2219 mutex_lock(&chip->spos_mutex); 2220 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2221 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) | 2222 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2223 /* left and right validity bit */ 2224 (1 << 13) | (1 << 12); 2225 2226 2227 change = ins->spdif_csuv_stream != val; 2228 ins->spdif_csuv_stream = val; 2229 2230 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN ) 2231 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2232 2233 mutex_unlock(&chip->spos_mutex); 2234 2235 return change; 2236 } 2237 2238 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2239 2240 2241 static const struct snd_kcontrol_new snd_cs46xx_controls[] = { 2242 { 2243 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2244 .name = "DAC Volume", 2245 .info = snd_cs46xx_vol_info, 2246 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2247 .get = snd_cs46xx_vol_get, 2248 .put = snd_cs46xx_vol_put, 2249 .private_value = BA1_PVOL, 2250 #else 2251 .get = snd_cs46xx_vol_dac_get, 2252 .put = snd_cs46xx_vol_dac_put, 2253 #endif 2254 }, 2255 2256 { 2257 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2258 .name = "ADC Volume", 2259 .info = snd_cs46xx_vol_info, 2260 .get = snd_cs46xx_vol_get, 2261 .put = snd_cs46xx_vol_put, 2262 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2263 .private_value = BA1_CVOL, 2264 #else 2265 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2, 2266 #endif 2267 }, 2268 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2269 { 2270 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2271 .name = "ADC Capture Switch", 2272 .info = snd_mixer_boolean_info, 2273 .get = snd_cs46xx_adc_capture_get, 2274 .put = snd_cs46xx_adc_capture_put 2275 }, 2276 { 2277 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2278 .name = "DAC Capture Switch", 2279 .info = snd_mixer_boolean_info, 2280 .get = snd_cs46xx_pcm_capture_get, 2281 .put = snd_cs46xx_pcm_capture_put 2282 }, 2283 { 2284 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2285 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), 2286 .info = snd_mixer_boolean_info, 2287 .get = snd_cs46xx_iec958_get, 2288 .put = snd_cs46xx_iec958_put, 2289 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT, 2290 }, 2291 { 2292 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2293 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH), 2294 .info = snd_mixer_boolean_info, 2295 .get = snd_cs46xx_iec958_get, 2296 .put = snd_cs46xx_iec958_put, 2297 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT, 2298 }, 2299 #if 0 2300 /* Input IEC958 volume does not work for the moment. (Benny) */ 2301 { 2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2303 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME), 2304 .info = snd_cs46xx_vol_info, 2305 .get = snd_cs46xx_vol_iec958_get, 2306 .put = snd_cs46xx_vol_iec958_put, 2307 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2, 2308 }, 2309 #endif 2310 { 2311 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2312 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2313 .info = snd_cs46xx_spdif_info, 2314 .get = snd_cs46xx_spdif_default_get, 2315 .put = snd_cs46xx_spdif_default_put, 2316 }, 2317 { 2318 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2319 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 2320 .info = snd_cs46xx_spdif_info, 2321 .get = snd_cs46xx_spdif_mask_get, 2322 .access = SNDRV_CTL_ELEM_ACCESS_READ 2323 }, 2324 { 2325 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2326 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2327 .info = snd_cs46xx_spdif_info, 2328 .get = snd_cs46xx_spdif_stream_get, 2329 .put = snd_cs46xx_spdif_stream_put 2330 }, 2331 2332 #endif 2333 }; 2334 2335 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2336 /* set primary cs4294 codec into Extended Audio Mode */ 2337 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol, 2338 struct snd_ctl_elem_value *ucontrol) 2339 { 2340 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2341 unsigned short val; 2342 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE); 2343 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1; 2344 return 0; 2345 } 2346 2347 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol, 2348 struct snd_ctl_elem_value *ucontrol) 2349 { 2350 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2351 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2352 AC97_CSR_ACMODE, 0x200, 2353 ucontrol->value.integer.value[0] ? 0 : 0x200); 2354 } 2355 2356 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = { 2357 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2358 .name = "Duplicate Front", 2359 .info = snd_mixer_boolean_info, 2360 .get = snd_cs46xx_front_dup_get, 2361 .put = snd_cs46xx_front_dup_put, 2362 }; 2363 #endif 2364 2365 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2366 /* Only available on the Hercules Game Theater XP soundcard */ 2367 static const struct snd_kcontrol_new snd_hercules_controls[] = { 2368 { 2369 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2370 .name = "Optical/Coaxial SPDIF Input Switch", 2371 .info = snd_mixer_boolean_info, 2372 .get = snd_herc_spdif_select_get, 2373 .put = snd_herc_spdif_select_put, 2374 }, 2375 }; 2376 2377 2378 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97) 2379 { 2380 unsigned long end_time; 2381 int err; 2382 2383 /* reset to defaults */ 2384 snd_ac97_write(ac97, AC97_RESET, 0); 2385 2386 /* set the desired CODEC mode */ 2387 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) { 2388 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0); 2389 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0); 2390 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) { 2391 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3); 2392 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3); 2393 } else { 2394 snd_BUG(); /* should never happen ... */ 2395 } 2396 2397 udelay(50); 2398 2399 /* it's necessary to wait awhile until registers are accessible after RESET */ 2400 /* because the PCM or MASTER volume registers can be modified, */ 2401 /* the REC_GAIN register is used for tests */ 2402 end_time = jiffies + HZ; 2403 do { 2404 unsigned short ext_mid; 2405 2406 /* use preliminary reads to settle the communication */ 2407 snd_ac97_read(ac97, AC97_RESET); 2408 snd_ac97_read(ac97, AC97_VENDOR_ID1); 2409 snd_ac97_read(ac97, AC97_VENDOR_ID2); 2410 /* modem? */ 2411 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID); 2412 if (ext_mid != 0xffff && (ext_mid & 1) != 0) 2413 return; 2414 2415 /* test if we can write to the record gain volume register */ 2416 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05); 2417 err = snd_ac97_read(ac97, AC97_REC_GAIN); 2418 if (err == 0x8a05) 2419 return; 2420 2421 msleep(10); 2422 } while (time_after_eq(end_time, jiffies)); 2423 2424 dev_err(ac97->bus->card->dev, 2425 "CS46xx secondary codec doesn't respond!\n"); 2426 } 2427 #endif 2428 2429 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec) 2430 { 2431 int idx, err; 2432 struct snd_ac97_template ac97; 2433 2434 memset(&ac97, 0, sizeof(ac97)); 2435 ac97.private_data = chip; 2436 ac97.private_free = snd_cs46xx_mixer_free_ac97; 2437 ac97.num = codec; 2438 if (chip->amplifier_ctrl == amp_voyetra) 2439 ac97.scaps = AC97_SCAP_INV_EAPD; 2440 2441 if (codec == CS46XX_SECONDARY_CODEC_INDEX) { 2442 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec); 2443 udelay(10); 2444 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) { 2445 dev_dbg(chip->card->dev, 2446 "secondary codec not present\n"); 2447 return -ENXIO; 2448 } 2449 } 2450 2451 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec); 2452 for (idx = 0; idx < 100; ++idx) { 2453 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) { 2454 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]); 2455 return err; 2456 } 2457 msleep(10); 2458 } 2459 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec); 2460 return -ENXIO; 2461 } 2462 2463 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device) 2464 { 2465 struct snd_card *card = chip->card; 2466 struct snd_ctl_elem_id id; 2467 int err; 2468 unsigned int idx; 2469 static const struct snd_ac97_bus_ops ops = { 2470 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2471 .reset = snd_cs46xx_codec_reset, 2472 #endif 2473 .write = snd_cs46xx_ac97_write, 2474 .read = snd_cs46xx_ac97_read, 2475 }; 2476 2477 /* detect primary codec */ 2478 chip->nr_ac97_codecs = 0; 2479 dev_dbg(chip->card->dev, "detecting primary codec\n"); 2480 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus); 2481 if (err < 0) 2482 return err; 2483 2484 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0) 2485 return -ENXIO; 2486 chip->nr_ac97_codecs = 1; 2487 2488 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2489 dev_dbg(chip->card->dev, "detecting secondary codec\n"); 2490 /* try detect a secondary codec */ 2491 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX)) 2492 chip->nr_ac97_codecs = 2; 2493 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2494 2495 /* add cs4630 mixer controls */ 2496 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) { 2497 struct snd_kcontrol *kctl; 2498 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip); 2499 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM) 2500 kctl->id.device = spdif_device; 2501 err = snd_ctl_add(card, kctl); 2502 if (err < 0) 2503 return err; 2504 } 2505 2506 /* get EAPD mixer switch (for voyetra hack) */ 2507 memset(&id, 0, sizeof(id)); 2508 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2509 strcpy(id.name, "External Amplifier"); 2510 chip->eapd_switch = snd_ctl_find_id(chip->card, &id); 2511 2512 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2513 if (chip->nr_ac97_codecs == 1) { 2514 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff; 2515 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */ 2516 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip)); 2517 if (err < 0) 2518 return err; 2519 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2520 AC97_CSR_ACMODE, 0x200); 2521 } 2522 } 2523 /* do soundcard specific mixer setup */ 2524 if (chip->mixer_init) { 2525 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n"); 2526 chip->mixer_init(chip); 2527 } 2528 #endif 2529 2530 /* turn on amplifier */ 2531 chip->amplifier_ctrl(chip, 1); 2532 2533 return 0; 2534 } 2535 2536 /* 2537 * RawMIDI interface 2538 */ 2539 2540 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip) 2541 { 2542 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST); 2543 udelay(100); 2544 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2545 } 2546 2547 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream) 2548 { 2549 struct snd_cs46xx *chip = substream->rmidi->private_data; 2550 2551 chip->active_ctrl(chip, 1); 2552 spin_lock_irq(&chip->reg_lock); 2553 chip->uartm |= CS46XX_MODE_INPUT; 2554 chip->midcr |= MIDCR_RXE; 2555 chip->midi_input = substream; 2556 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2557 snd_cs46xx_midi_reset(chip); 2558 } else { 2559 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2560 } 2561 spin_unlock_irq(&chip->reg_lock); 2562 return 0; 2563 } 2564 2565 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream) 2566 { 2567 struct snd_cs46xx *chip = substream->rmidi->private_data; 2568 2569 spin_lock_irq(&chip->reg_lock); 2570 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE); 2571 chip->midi_input = NULL; 2572 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2573 snd_cs46xx_midi_reset(chip); 2574 } else { 2575 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2576 } 2577 chip->uartm &= ~CS46XX_MODE_INPUT; 2578 spin_unlock_irq(&chip->reg_lock); 2579 chip->active_ctrl(chip, -1); 2580 return 0; 2581 } 2582 2583 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream) 2584 { 2585 struct snd_cs46xx *chip = substream->rmidi->private_data; 2586 2587 chip->active_ctrl(chip, 1); 2588 2589 spin_lock_irq(&chip->reg_lock); 2590 chip->uartm |= CS46XX_MODE_OUTPUT; 2591 chip->midcr |= MIDCR_TXE; 2592 chip->midi_output = substream; 2593 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2594 snd_cs46xx_midi_reset(chip); 2595 } else { 2596 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2597 } 2598 spin_unlock_irq(&chip->reg_lock); 2599 return 0; 2600 } 2601 2602 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream) 2603 { 2604 struct snd_cs46xx *chip = substream->rmidi->private_data; 2605 2606 spin_lock_irq(&chip->reg_lock); 2607 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE); 2608 chip->midi_output = NULL; 2609 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2610 snd_cs46xx_midi_reset(chip); 2611 } else { 2612 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2613 } 2614 chip->uartm &= ~CS46XX_MODE_OUTPUT; 2615 spin_unlock_irq(&chip->reg_lock); 2616 chip->active_ctrl(chip, -1); 2617 return 0; 2618 } 2619 2620 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2621 { 2622 unsigned long flags; 2623 struct snd_cs46xx *chip = substream->rmidi->private_data; 2624 2625 spin_lock_irqsave(&chip->reg_lock, flags); 2626 if (up) { 2627 if ((chip->midcr & MIDCR_RIE) == 0) { 2628 chip->midcr |= MIDCR_RIE; 2629 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2630 } 2631 } else { 2632 if (chip->midcr & MIDCR_RIE) { 2633 chip->midcr &= ~MIDCR_RIE; 2634 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2635 } 2636 } 2637 spin_unlock_irqrestore(&chip->reg_lock, flags); 2638 } 2639 2640 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2641 { 2642 unsigned long flags; 2643 struct snd_cs46xx *chip = substream->rmidi->private_data; 2644 unsigned char byte; 2645 2646 spin_lock_irqsave(&chip->reg_lock, flags); 2647 if (up) { 2648 if ((chip->midcr & MIDCR_TIE) == 0) { 2649 chip->midcr |= MIDCR_TIE; 2650 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2651 while ((chip->midcr & MIDCR_TIE) && 2652 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 2653 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2654 chip->midcr &= ~MIDCR_TIE; 2655 } else { 2656 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte); 2657 } 2658 } 2659 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2660 } 2661 } else { 2662 if (chip->midcr & MIDCR_TIE) { 2663 chip->midcr &= ~MIDCR_TIE; 2664 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2665 } 2666 } 2667 spin_unlock_irqrestore(&chip->reg_lock, flags); 2668 } 2669 2670 static const struct snd_rawmidi_ops snd_cs46xx_midi_output = 2671 { 2672 .open = snd_cs46xx_midi_output_open, 2673 .close = snd_cs46xx_midi_output_close, 2674 .trigger = snd_cs46xx_midi_output_trigger, 2675 }; 2676 2677 static const struct snd_rawmidi_ops snd_cs46xx_midi_input = 2678 { 2679 .open = snd_cs46xx_midi_input_open, 2680 .close = snd_cs46xx_midi_input_close, 2681 .trigger = snd_cs46xx_midi_input_trigger, 2682 }; 2683 2684 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device) 2685 { 2686 struct snd_rawmidi *rmidi; 2687 int err; 2688 2689 err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi); 2690 if (err < 0) 2691 return err; 2692 strcpy(rmidi->name, "CS46XX"); 2693 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output); 2694 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input); 2695 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 2696 rmidi->private_data = chip; 2697 chip->rmidi = rmidi; 2698 return 0; 2699 } 2700 2701 2702 /* 2703 * gameport interface 2704 */ 2705 2706 #if IS_REACHABLE(CONFIG_GAMEPORT) 2707 2708 static void snd_cs46xx_gameport_trigger(struct gameport *gameport) 2709 { 2710 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2711 2712 if (snd_BUG_ON(!chip)) 2713 return; 2714 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF); 2715 } 2716 2717 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport) 2718 { 2719 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2720 2721 if (snd_BUG_ON(!chip)) 2722 return 0; 2723 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io); 2724 } 2725 2726 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) 2727 { 2728 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2729 unsigned js1, js2, jst; 2730 2731 if (snd_BUG_ON(!chip)) 2732 return 0; 2733 2734 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1); 2735 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2); 2736 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT); 2737 2738 *buttons = (~jst >> 4) & 0x0F; 2739 2740 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 2741 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 2742 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 2743 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 2744 2745 for(jst=0;jst<4;++jst) 2746 if(axes[jst]==0xFFFF) axes[jst] = -1; 2747 return 0; 2748 } 2749 2750 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode) 2751 { 2752 switch (mode) { 2753 case GAMEPORT_MODE_COOKED: 2754 return 0; 2755 case GAMEPORT_MODE_RAW: 2756 return 0; 2757 default: 2758 return -1; 2759 } 2760 return 0; 2761 } 2762 2763 int snd_cs46xx_gameport(struct snd_cs46xx *chip) 2764 { 2765 struct gameport *gp; 2766 2767 chip->gameport = gp = gameport_allocate_port(); 2768 if (!gp) { 2769 dev_err(chip->card->dev, 2770 "cannot allocate memory for gameport\n"); 2771 return -ENOMEM; 2772 } 2773 2774 gameport_set_name(gp, "CS46xx Gameport"); 2775 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2776 gameport_set_dev_parent(gp, &chip->pci->dev); 2777 gameport_set_port_data(gp, chip); 2778 2779 gp->open = snd_cs46xx_gameport_open; 2780 gp->read = snd_cs46xx_gameport_read; 2781 gp->trigger = snd_cs46xx_gameport_trigger; 2782 gp->cooked_read = snd_cs46xx_gameport_cooked_read; 2783 2784 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 2785 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 2786 2787 gameport_register_port(gp); 2788 2789 return 0; 2790 } 2791 2792 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) 2793 { 2794 if (chip->gameport) { 2795 gameport_unregister_port(chip->gameport); 2796 chip->gameport = NULL; 2797 } 2798 } 2799 #else 2800 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; } 2801 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { } 2802 #endif /* CONFIG_GAMEPORT */ 2803 2804 #ifdef CONFIG_SND_PROC_FS 2805 /* 2806 * proc interface 2807 */ 2808 2809 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry, 2810 void *file_private_data, 2811 struct file *file, char __user *buf, 2812 size_t count, loff_t pos) 2813 { 2814 struct snd_cs46xx_region *region = entry->private_data; 2815 2816 if (copy_to_user_fromio(buf, region->remap_addr + pos, count)) 2817 return -EFAULT; 2818 return count; 2819 } 2820 2821 static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = { 2822 .read = snd_cs46xx_io_read, 2823 }; 2824 2825 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip) 2826 { 2827 struct snd_info_entry *entry; 2828 int idx; 2829 2830 for (idx = 0; idx < 5; idx++) { 2831 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2832 if (! snd_card_proc_new(card, region->name, &entry)) { 2833 entry->content = SNDRV_INFO_CONTENT_DATA; 2834 entry->private_data = chip; 2835 entry->c.ops = &snd_cs46xx_proc_io_ops; 2836 entry->size = region->size; 2837 entry->mode = S_IFREG | 0400; 2838 } 2839 } 2840 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2841 cs46xx_dsp_proc_init(card, chip); 2842 #endif 2843 return 0; 2844 } 2845 2846 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip) 2847 { 2848 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2849 cs46xx_dsp_proc_done(chip); 2850 #endif 2851 return 0; 2852 } 2853 #else /* !CONFIG_SND_PROC_FS */ 2854 #define snd_cs46xx_proc_init(card, chip) 2855 #define snd_cs46xx_proc_done(chip) 2856 #endif 2857 2858 /* 2859 * stop the h/w 2860 */ 2861 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip) 2862 { 2863 unsigned int tmp; 2864 2865 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 2866 tmp &= ~0x0000f03f; 2867 tmp |= 0x00000010; 2868 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */ 2869 2870 tmp = snd_cs46xx_peek(chip, BA1_CIE); 2871 tmp &= ~0x0000003f; 2872 tmp |= 0x00000011; 2873 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */ 2874 2875 /* 2876 * Stop playback DMA. 2877 */ 2878 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 2879 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 2880 2881 /* 2882 * Stop capture DMA. 2883 */ 2884 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 2885 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 2886 2887 /* 2888 * Reset the processor. 2889 */ 2890 snd_cs46xx_reset(chip); 2891 2892 snd_cs46xx_proc_stop(chip); 2893 2894 /* 2895 * Power down the PLL. 2896 */ 2897 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2898 2899 /* 2900 * Turn off the Processor by turning off the software clock enable flag in 2901 * the clock control register. 2902 */ 2903 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; 2904 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 2905 } 2906 2907 2908 static void snd_cs46xx_free(struct snd_card *card) 2909 { 2910 struct snd_cs46xx *chip = card->private_data; 2911 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2912 int idx; 2913 #endif 2914 2915 if (chip->active_ctrl) 2916 chip->active_ctrl(chip, 1); 2917 2918 snd_cs46xx_remove_gameport(chip); 2919 2920 if (chip->amplifier_ctrl) 2921 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */ 2922 2923 snd_cs46xx_proc_done(chip); 2924 2925 snd_cs46xx_hw_stop(chip); 2926 2927 if (chip->active_ctrl) 2928 chip->active_ctrl(chip, -chip->amplifier); 2929 2930 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2931 if (chip->dsp_spos_instance) { 2932 cs46xx_dsp_spos_destroy(chip); 2933 chip->dsp_spos_instance = NULL; 2934 } 2935 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++) 2936 free_module_desc(chip->modules[idx]); 2937 #else 2938 vfree(chip->ba1); 2939 #endif 2940 } 2941 2942 /* 2943 * initialize chip 2944 */ 2945 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip) 2946 { 2947 int timeout; 2948 2949 /* 2950 * First, blast the clock control register to zero so that the PLL starts 2951 * out in a known state, and blast the master serial port control register 2952 * to zero so that the serial ports also start out in a known state. 2953 */ 2954 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2955 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0); 2956 2957 /* 2958 * If we are in AC97 mode, then we must set the part to a host controlled 2959 * AC-link. Otherwise, we won't be able to bring up the link. 2960 */ 2961 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2962 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 | 2963 SERACC_TWO_CODECS); /* 2.00 dual codecs */ 2964 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */ 2965 #else 2966 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */ 2967 #endif 2968 2969 /* 2970 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 2971 * spec) and then drive it high. This is done for non AC97 modes since 2972 * there might be logic external to the CS461x that uses the ARST# line 2973 * for a reset. 2974 */ 2975 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0); 2976 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2977 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0); 2978 #endif 2979 udelay(50); 2980 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN); 2981 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2982 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN); 2983 #endif 2984 2985 /* 2986 * The first thing we do here is to enable sync generation. As soon 2987 * as we start receiving bit clock, we'll start producing the SYNC 2988 * signal. 2989 */ 2990 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 2991 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2992 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN); 2993 #endif 2994 2995 /* 2996 * Now wait for a short while to allow the AC97 part to start 2997 * generating bit clock (so we don't try to start the PLL without an 2998 * input clock). 2999 */ 3000 mdelay(10); 3001 3002 /* 3003 * Set the serial port timing configuration, so that 3004 * the clock control circuit gets its clock from the correct place. 3005 */ 3006 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97); 3007 3008 /* 3009 * Write the selected clock control setup to the hardware. Do not turn on 3010 * SWCE yet (if requested), so that the devices clocked by the output of 3011 * PLL are not clocked until the PLL is stable. 3012 */ 3013 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 3014 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a); 3015 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8); 3016 3017 /* 3018 * Power up the PLL. 3019 */ 3020 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP); 3021 3022 /* 3023 * Wait until the PLL has stabilized. 3024 */ 3025 msleep(100); 3026 3027 /* 3028 * Turn on clocking of the core so that we can setup the serial ports. 3029 */ 3030 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 3031 3032 /* 3033 * Enable FIFO Host Bypass 3034 */ 3035 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP); 3036 3037 /* 3038 * Fill the serial port FIFOs with silence. 3039 */ 3040 snd_cs46xx_clear_serial_FIFOs(chip); 3041 3042 /* 3043 * Set the serial port FIFO pointer to the first sample in the FIFO. 3044 */ 3045 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */ 3046 3047 /* 3048 * Write the serial port configuration to the part. The master 3049 * enable bit is not set until all other values have been written. 3050 */ 3051 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 3052 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 3053 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 3054 3055 3056 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3057 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN); 3058 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0); 3059 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0); 3060 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0); 3061 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1); 3062 #endif 3063 3064 mdelay(5); 3065 3066 3067 /* 3068 * Wait for the codec ready signal from the AC97 codec. 3069 */ 3070 timeout = 150; 3071 while (timeout-- > 0) { 3072 /* 3073 * Read the AC97 status register to see if we've seen a CODEC READY 3074 * signal from the AC97 codec. 3075 */ 3076 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) 3077 goto ok1; 3078 msleep(10); 3079 } 3080 3081 3082 dev_err(chip->card->dev, 3083 "create - never read codec ready from AC'97\n"); 3084 dev_err(chip->card->dev, 3085 "it is not probably bug, try to use CS4236 driver\n"); 3086 return -EIO; 3087 ok1: 3088 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3089 { 3090 int count; 3091 for (count = 0; count < 150; count++) { 3092 /* First, we want to wait for a short time. */ 3093 udelay(25); 3094 3095 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY) 3096 break; 3097 } 3098 3099 /* 3100 * Make sure CODEC is READY. 3101 */ 3102 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)) 3103 dev_dbg(chip->card->dev, 3104 "never read card ready from secondary AC'97\n"); 3105 } 3106 #endif 3107 3108 /* 3109 * Assert the vaid frame signal so that we can start sending commands 3110 * to the AC97 codec. 3111 */ 3112 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 3113 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3114 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 3115 #endif 3116 3117 3118 /* 3119 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 3120 * the codec is pumping ADC data across the AC-link. 3121 */ 3122 timeout = 150; 3123 while (timeout-- > 0) { 3124 /* 3125 * Read the input slot valid register and see if input slots 3 and 3126 * 4 are valid yet. 3127 */ 3128 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 3129 goto ok2; 3130 msleep(10); 3131 } 3132 3133 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3134 dev_err(chip->card->dev, 3135 "create - never read ISV3 & ISV4 from AC'97\n"); 3136 return -EIO; 3137 #else 3138 /* This may happen on a cold boot with a Terratec SiXPack 5.1. 3139 Reloading the driver may help, if there's other soundcards 3140 with the same problem I would like to know. (Benny) */ 3141 3142 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n"); 3143 dev_err(chip->card->dev, 3144 "Try reloading the ALSA driver, if you find something\n"); 3145 dev_err(chip->card->dev, 3146 "broken or not working on your soundcard upon\n"); 3147 dev_err(chip->card->dev, 3148 "this message please report to alsa-devel@alsa-project.org\n"); 3149 3150 return -EIO; 3151 #endif 3152 ok2: 3153 3154 /* 3155 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 3156 * commense the transfer of digital audio data to the AC97 codec. 3157 */ 3158 3159 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 3160 3161 3162 /* 3163 * Power down the DAC and ADC. We will power them up (if) when we need 3164 * them. 3165 */ 3166 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */ 3167 3168 /* 3169 * Turn off the Processor by turning off the software clock enable flag in 3170 * the clock control register. 3171 */ 3172 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */ 3173 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */ 3174 3175 return 0; 3176 } 3177 3178 /* 3179 * start and load DSP 3180 */ 3181 3182 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip) 3183 { 3184 unsigned int tmp; 3185 3186 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM); 3187 3188 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 3189 tmp &= ~0x0000f03f; 3190 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */ 3191 3192 tmp = snd_cs46xx_peek(chip, BA1_CIE); 3193 tmp &= ~0x0000003f; 3194 tmp |= 0x00000001; 3195 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */ 3196 } 3197 3198 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip) 3199 { 3200 unsigned int tmp; 3201 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3202 int i; 3203 #endif 3204 int err; 3205 3206 /* 3207 * Reset the processor. 3208 */ 3209 snd_cs46xx_reset(chip); 3210 /* 3211 * Download the image to the processor. 3212 */ 3213 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3214 for (i = 0; i < CS46XX_DSP_MODULES; i++) { 3215 err = load_firmware(chip, &chip->modules[i], module_names[i]); 3216 if (err < 0) { 3217 dev_err(chip->card->dev, "firmware load error [%s]\n", 3218 module_names[i]); 3219 return err; 3220 } 3221 err = cs46xx_dsp_load_module(chip, chip->modules[i]); 3222 if (err < 0) { 3223 dev_err(chip->card->dev, "image download error [%s]\n", 3224 module_names[i]); 3225 return err; 3226 } 3227 } 3228 3229 if (cs46xx_dsp_scb_and_task_init(chip) < 0) 3230 return -EIO; 3231 #else 3232 err = load_firmware(chip); 3233 if (err < 0) 3234 return err; 3235 3236 /* old image */ 3237 err = snd_cs46xx_download_image(chip); 3238 if (err < 0) { 3239 dev_err(chip->card->dev, "image download error\n"); 3240 return err; 3241 } 3242 3243 /* 3244 * Stop playback DMA. 3245 */ 3246 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 3247 chip->play_ctl = tmp & 0xffff0000; 3248 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 3249 #endif 3250 3251 /* 3252 * Stop capture DMA. 3253 */ 3254 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3255 chip->capt.ctl = tmp & 0x0000ffff; 3256 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3257 3258 mdelay(5); 3259 3260 snd_cs46xx_set_play_sample_rate(chip, 8000); 3261 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3262 3263 snd_cs46xx_proc_start(chip); 3264 3265 cs46xx_enable_stream_irqs(chip); 3266 3267 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3268 /* set the attenuation to 0dB */ 3269 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000); 3270 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000); 3271 #endif 3272 3273 return 0; 3274 } 3275 3276 3277 /* 3278 * AMP control - null AMP 3279 */ 3280 3281 static void amp_none(struct snd_cs46xx *chip, int change) 3282 { 3283 } 3284 3285 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3286 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip) 3287 { 3288 3289 u32 idx, valid_slots,tmp,powerdown = 0; 3290 u16 modem_power,pin_config,logic_type; 3291 3292 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n"); 3293 3294 /* 3295 * See if the devices are powered down. If so, we must power them up first 3296 * or they will not respond. 3297 */ 3298 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 3299 3300 if (!(tmp & CLKCR1_SWCE)) { 3301 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 3302 powerdown = 1; 3303 } 3304 3305 /* 3306 * Clear PRA. The Bonzo chip will be used for GPIO not for modem 3307 * stuff. 3308 */ 3309 if(chip->nr_ac97_codecs != 2) { 3310 dev_err(chip->card->dev, 3311 "cs46xx_setup_eapd_slot() - no secondary codec configured\n"); 3312 return -EINVAL; 3313 } 3314 3315 modem_power = snd_cs46xx_codec_read (chip, 3316 AC97_EXTENDED_MSTATUS, 3317 CS46XX_SECONDARY_CODEC_INDEX); 3318 modem_power &=0xFEFF; 3319 3320 snd_cs46xx_codec_write(chip, 3321 AC97_EXTENDED_MSTATUS, modem_power, 3322 CS46XX_SECONDARY_CODEC_INDEX); 3323 3324 /* 3325 * Set GPIO pin's 7 and 8 so that they are configured for output. 3326 */ 3327 pin_config = snd_cs46xx_codec_read (chip, 3328 AC97_GPIO_CFG, 3329 CS46XX_SECONDARY_CODEC_INDEX); 3330 pin_config &=0x27F; 3331 3332 snd_cs46xx_codec_write(chip, 3333 AC97_GPIO_CFG, pin_config, 3334 CS46XX_SECONDARY_CODEC_INDEX); 3335 3336 /* 3337 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic. 3338 */ 3339 3340 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY, 3341 CS46XX_SECONDARY_CODEC_INDEX); 3342 logic_type &=0x27F; 3343 3344 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type, 3345 CS46XX_SECONDARY_CODEC_INDEX); 3346 3347 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV); 3348 valid_slots |= 0x200; 3349 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots); 3350 3351 if ( cs46xx_wait_for_fifo(chip,1) ) { 3352 dev_dbg(chip->card->dev, "FIFO is busy\n"); 3353 3354 return -EINVAL; 3355 } 3356 3357 /* 3358 * Fill slots 12 with the correct value for the GPIO pins. 3359 */ 3360 for(idx = 0x90; idx <= 0x9F; idx++) { 3361 /* 3362 * Initialize the fifo so that bits 7 and 8 are on. 3363 * 3364 * Remember that the GPIO pins in bonzo are shifted by 4 bits to 3365 * the left. 0x1800 corresponds to bits 7 and 8. 3366 */ 3367 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800); 3368 3369 /* 3370 * Wait for command to complete 3371 */ 3372 if ( cs46xx_wait_for_fifo(chip,200) ) { 3373 dev_dbg(chip->card->dev, 3374 "failed waiting for FIFO at addr (%02X)\n", 3375 idx); 3376 3377 return -EINVAL; 3378 } 3379 3380 /* 3381 * Write the serial port FIFO index. 3382 */ 3383 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 3384 3385 /* 3386 * Tell the serial port to load the new value into the FIFO location. 3387 */ 3388 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 3389 } 3390 3391 /* wait for last command to complete */ 3392 cs46xx_wait_for_fifo(chip,200); 3393 3394 /* 3395 * Now, if we powered up the devices, then power them back down again. 3396 * This is kinda ugly, but should never happen. 3397 */ 3398 if (powerdown) 3399 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 3400 3401 return 0; 3402 } 3403 #endif 3404 3405 /* 3406 * Crystal EAPD mode 3407 */ 3408 3409 static void amp_voyetra(struct snd_cs46xx *chip, int change) 3410 { 3411 /* Manage the EAPD bit on the Crystal 4297 3412 and the Analog AD1885 */ 3413 3414 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3415 int old = chip->amplifier; 3416 #endif 3417 int oval, val; 3418 3419 chip->amplifier += change; 3420 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN, 3421 CS46XX_PRIMARY_CODEC_INDEX); 3422 val = oval; 3423 if (chip->amplifier) { 3424 /* Turn the EAPD amp on */ 3425 val |= 0x8000; 3426 } else { 3427 /* Turn the EAPD amp off */ 3428 val &= ~0x8000; 3429 } 3430 if (val != oval) { 3431 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val, 3432 CS46XX_PRIMARY_CODEC_INDEX); 3433 if (chip->eapd_switch) 3434 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 3435 &chip->eapd_switch->id); 3436 } 3437 3438 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3439 if (chip->amplifier && !old) { 3440 voyetra_setup_eapd_slot(chip); 3441 } 3442 #endif 3443 } 3444 3445 static void hercules_init(struct snd_cs46xx *chip) 3446 { 3447 /* default: AMP off, and SPDIF input optical */ 3448 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3449 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3450 } 3451 3452 3453 /* 3454 * Game Theatre XP card - EGPIO[2] is used to enable the external amp. 3455 */ 3456 static void amp_hercules(struct snd_cs46xx *chip, int change) 3457 { 3458 int old = chip->amplifier; 3459 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 3460 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 3461 3462 chip->amplifier += change; 3463 if (chip->amplifier && !old) { 3464 dev_dbg(chip->card->dev, "Hercules amplifier ON\n"); 3465 3466 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 3467 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */ 3468 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 3469 EGPIOPTR_GPPT2 | val2); /* open-drain on output */ 3470 } else if (old && !chip->amplifier) { 3471 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n"); 3472 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */ 3473 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */ 3474 } 3475 } 3476 3477 static void voyetra_mixer_init (struct snd_cs46xx *chip) 3478 { 3479 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n"); 3480 3481 /* Enable SPDIF out */ 3482 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3483 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3484 } 3485 3486 static void hercules_mixer_init (struct snd_cs46xx *chip) 3487 { 3488 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3489 unsigned int idx; 3490 int err; 3491 struct snd_card *card = chip->card; 3492 #endif 3493 3494 /* set EGPIO to default */ 3495 hercules_init(chip); 3496 3497 dev_dbg(chip->card->dev, "initializing Hercules mixer\n"); 3498 3499 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3500 if (chip->in_suspend) 3501 return; 3502 3503 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) { 3504 struct snd_kcontrol *kctl; 3505 3506 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip); 3507 err = snd_ctl_add(card, kctl); 3508 if (err < 0) { 3509 dev_err(card->dev, 3510 "failed to initialize Hercules mixer (%d)\n", 3511 err); 3512 break; 3513 } 3514 } 3515 #endif 3516 } 3517 3518 3519 #if 0 3520 /* 3521 * Untested 3522 */ 3523 3524 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change) 3525 { 3526 chip->amplifier += change; 3527 3528 if (chip->amplifier) { 3529 /* Switch the GPIO pins 7 and 8 to open drain */ 3530 snd_cs46xx_codec_write(chip, 0x4C, 3531 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F); 3532 snd_cs46xx_codec_write(chip, 0x4E, 3533 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180); 3534 /* Now wake the AMP (this might be backwards) */ 3535 snd_cs46xx_codec_write(chip, 0x54, 3536 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180); 3537 } else { 3538 snd_cs46xx_codec_write(chip, 0x54, 3539 snd_cs46xx_codec_read(chip, 0x54) | 0x0180); 3540 } 3541 } 3542 #endif 3543 3544 3545 /* 3546 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support 3547 * whenever we need to beat on the chip. 3548 * 3549 * The original idea and code for this hack comes from David Kaiser at 3550 * Linuxcare. Perhaps one day Crystal will document their chips well 3551 * enough to make them useful. 3552 */ 3553 3554 static void clkrun_hack(struct snd_cs46xx *chip, int change) 3555 { 3556 u16 control, nval; 3557 3558 if (!chip->acpi_port) 3559 return; 3560 3561 chip->amplifier += change; 3562 3563 /* Read ACPI port */ 3564 nval = control = inw(chip->acpi_port + 0x10); 3565 3566 /* Flip CLKRUN off while running */ 3567 if (! chip->amplifier) 3568 nval |= 0x2000; 3569 else 3570 nval &= ~0x2000; 3571 if (nval != control) 3572 outw(nval, chip->acpi_port + 0x10); 3573 } 3574 3575 3576 /* 3577 * detect intel piix4 3578 */ 3579 static void clkrun_init(struct snd_cs46xx *chip) 3580 { 3581 struct pci_dev *pdev; 3582 u8 pp; 3583 3584 chip->acpi_port = 0; 3585 3586 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 3587 PCI_DEVICE_ID_INTEL_82371AB_3, NULL); 3588 if (pdev == NULL) 3589 return; /* Not a thinkpad thats for sure */ 3590 3591 /* Find the control port */ 3592 pci_read_config_byte(pdev, 0x41, &pp); 3593 chip->acpi_port = pp << 8; 3594 pci_dev_put(pdev); 3595 } 3596 3597 3598 /* 3599 * Card subid table 3600 */ 3601 3602 struct cs_card_type 3603 { 3604 u16 vendor; 3605 u16 id; 3606 char *name; 3607 void (*init)(struct snd_cs46xx *); 3608 void (*amp)(struct snd_cs46xx *, int); 3609 void (*active)(struct snd_cs46xx *, int); 3610 void (*mixer_init)(struct snd_cs46xx *); 3611 }; 3612 3613 static struct cs_card_type cards[] = { 3614 { 3615 .vendor = 0x1489, 3616 .id = 0x7001, 3617 .name = "Genius Soundmaker 128 value", 3618 /* nothing special */ 3619 }, 3620 { 3621 .vendor = 0x5053, 3622 .id = 0x3357, 3623 .name = "Voyetra", 3624 .amp = amp_voyetra, 3625 .mixer_init = voyetra_mixer_init, 3626 }, 3627 { 3628 .vendor = 0x1071, 3629 .id = 0x6003, 3630 .name = "Mitac MI6020/21", 3631 .amp = amp_voyetra, 3632 }, 3633 /* Hercules Game Theatre XP */ 3634 { 3635 .vendor = 0x14af, /* Guillemot Corporation */ 3636 .id = 0x0050, 3637 .name = "Hercules Game Theatre XP", 3638 .amp = amp_hercules, 3639 .mixer_init = hercules_mixer_init, 3640 }, 3641 { 3642 .vendor = 0x1681, 3643 .id = 0x0050, 3644 .name = "Hercules Game Theatre XP", 3645 .amp = amp_hercules, 3646 .mixer_init = hercules_mixer_init, 3647 }, 3648 { 3649 .vendor = 0x1681, 3650 .id = 0x0051, 3651 .name = "Hercules Game Theatre XP", 3652 .amp = amp_hercules, 3653 .mixer_init = hercules_mixer_init, 3654 3655 }, 3656 { 3657 .vendor = 0x1681, 3658 .id = 0x0052, 3659 .name = "Hercules Game Theatre XP", 3660 .amp = amp_hercules, 3661 .mixer_init = hercules_mixer_init, 3662 }, 3663 { 3664 .vendor = 0x1681, 3665 .id = 0x0053, 3666 .name = "Hercules Game Theatre XP", 3667 .amp = amp_hercules, 3668 .mixer_init = hercules_mixer_init, 3669 }, 3670 { 3671 .vendor = 0x1681, 3672 .id = 0x0054, 3673 .name = "Hercules Game Theatre XP", 3674 .amp = amp_hercules, 3675 .mixer_init = hercules_mixer_init, 3676 }, 3677 /* Herculess Fortissimo */ 3678 { 3679 .vendor = 0x1681, 3680 .id = 0xa010, 3681 .name = "Hercules Gamesurround Fortissimo II", 3682 }, 3683 { 3684 .vendor = 0x1681, 3685 .id = 0xa011, 3686 .name = "Hercules Gamesurround Fortissimo III 7.1", 3687 }, 3688 /* Teratec */ 3689 { 3690 .vendor = 0x153b, 3691 .id = 0x112e, 3692 .name = "Terratec DMX XFire 1024", 3693 }, 3694 { 3695 .vendor = 0x153b, 3696 .id = 0x1136, 3697 .name = "Terratec SiXPack 5.1", 3698 }, 3699 /* Not sure if the 570 needs the clkrun hack */ 3700 { 3701 .vendor = PCI_VENDOR_ID_IBM, 3702 .id = 0x0132, 3703 .name = "Thinkpad 570", 3704 .init = clkrun_init, 3705 .active = clkrun_hack, 3706 }, 3707 { 3708 .vendor = PCI_VENDOR_ID_IBM, 3709 .id = 0x0153, 3710 .name = "Thinkpad 600X/A20/T20", 3711 .init = clkrun_init, 3712 .active = clkrun_hack, 3713 }, 3714 { 3715 .vendor = PCI_VENDOR_ID_IBM, 3716 .id = 0x1010, 3717 .name = "Thinkpad 600E (unsupported)", 3718 }, 3719 {} /* terminator */ 3720 }; 3721 3722 3723 /* 3724 * APM support 3725 */ 3726 #ifdef CONFIG_PM_SLEEP 3727 static const unsigned int saved_regs[] = { 3728 BA0_ACOSV, 3729 /*BA0_ASER_FADDR,*/ 3730 BA0_ASER_MASTER, 3731 BA1_PVOL, 3732 BA1_CVOL, 3733 }; 3734 3735 static int snd_cs46xx_suspend(struct device *dev) 3736 { 3737 struct snd_card *card = dev_get_drvdata(dev); 3738 struct snd_cs46xx *chip = card->private_data; 3739 int i, amp_saved; 3740 3741 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3742 chip->in_suspend = 1; 3743 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL); 3744 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE); 3745 3746 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3747 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3748 3749 /* save some registers */ 3750 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3751 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]); 3752 3753 amp_saved = chip->amplifier; 3754 /* turn off amp */ 3755 chip->amplifier_ctrl(chip, -chip->amplifier); 3756 snd_cs46xx_hw_stop(chip); 3757 /* disable CLKRUN */ 3758 chip->active_ctrl(chip, -chip->amplifier); 3759 chip->amplifier = amp_saved; /* restore the status */ 3760 return 0; 3761 } 3762 3763 static int snd_cs46xx_resume(struct device *dev) 3764 { 3765 struct snd_card *card = dev_get_drvdata(dev); 3766 struct snd_cs46xx *chip = card->private_data; 3767 int amp_saved; 3768 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3769 int i; 3770 #endif 3771 unsigned int tmp; 3772 3773 amp_saved = chip->amplifier; 3774 chip->amplifier = 0; 3775 chip->active_ctrl(chip, 1); /* force to on */ 3776 3777 snd_cs46xx_chip_init(chip); 3778 3779 snd_cs46xx_reset(chip); 3780 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3781 cs46xx_dsp_resume(chip); 3782 /* restore some registers */ 3783 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3784 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]); 3785 #else 3786 snd_cs46xx_download_image(chip); 3787 #endif 3788 3789 #if 0 3790 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, 3791 chip->ac97_general_purpose); 3792 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL, 3793 chip->ac97_powerdown); 3794 mdelay(10); 3795 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN, 3796 chip->ac97_powerdown); 3797 mdelay(5); 3798 #endif 3799 3800 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3801 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3802 3803 /* 3804 * Stop capture DMA. 3805 */ 3806 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3807 chip->capt.ctl = tmp & 0x0000ffff; 3808 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3809 3810 mdelay(5); 3811 3812 /* reset playback/capture */ 3813 snd_cs46xx_set_play_sample_rate(chip, 8000); 3814 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3815 snd_cs46xx_proc_start(chip); 3816 3817 cs46xx_enable_stream_irqs(chip); 3818 3819 if (amp_saved) 3820 chip->amplifier_ctrl(chip, 1); /* turn amp on */ 3821 else 3822 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3823 chip->amplifier = amp_saved; 3824 chip->in_suspend = 0; 3825 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3826 return 0; 3827 } 3828 3829 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume); 3830 #endif /* CONFIG_PM_SLEEP */ 3831 3832 3833 /* 3834 */ 3835 3836 int snd_cs46xx_create(struct snd_card *card, 3837 struct pci_dev *pci, 3838 int external_amp, int thinkpad) 3839 { 3840 struct snd_cs46xx *chip = card->private_data; 3841 int err, idx; 3842 struct snd_cs46xx_region *region; 3843 struct cs_card_type *cp; 3844 u16 ss_card, ss_vendor; 3845 3846 /* enable PCI device */ 3847 err = pcim_enable_device(pci); 3848 if (err < 0) 3849 return err; 3850 3851 spin_lock_init(&chip->reg_lock); 3852 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3853 mutex_init(&chip->spos_mutex); 3854 #endif 3855 chip->card = card; 3856 chip->pci = pci; 3857 chip->irq = -1; 3858 3859 err = pci_request_regions(pci, "CS46xx"); 3860 if (err < 0) 3861 return err; 3862 chip->ba0_addr = pci_resource_start(pci, 0); 3863 chip->ba1_addr = pci_resource_start(pci, 1); 3864 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 || 3865 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) { 3866 dev_err(chip->card->dev, 3867 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", 3868 chip->ba0_addr, chip->ba1_addr); 3869 return -ENOMEM; 3870 } 3871 3872 region = &chip->region.name.ba0; 3873 strcpy(region->name, "CS46xx_BA0"); 3874 region->base = chip->ba0_addr; 3875 region->size = CS46XX_BA0_SIZE; 3876 3877 region = &chip->region.name.data0; 3878 strcpy(region->name, "CS46xx_BA1_data0"); 3879 region->base = chip->ba1_addr + BA1_SP_DMEM0; 3880 region->size = CS46XX_BA1_DATA0_SIZE; 3881 3882 region = &chip->region.name.data1; 3883 strcpy(region->name, "CS46xx_BA1_data1"); 3884 region->base = chip->ba1_addr + BA1_SP_DMEM1; 3885 region->size = CS46XX_BA1_DATA1_SIZE; 3886 3887 region = &chip->region.name.pmem; 3888 strcpy(region->name, "CS46xx_BA1_pmem"); 3889 region->base = chip->ba1_addr + BA1_SP_PMEM; 3890 region->size = CS46XX_BA1_PRG_SIZE; 3891 3892 region = &chip->region.name.reg; 3893 strcpy(region->name, "CS46xx_BA1_reg"); 3894 region->base = chip->ba1_addr + BA1_SP_REG; 3895 region->size = CS46XX_BA1_REG_SIZE; 3896 3897 /* set up amp and clkrun hack */ 3898 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor); 3899 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card); 3900 3901 for (cp = &cards[0]; cp->name; cp++) { 3902 if (cp->vendor == ss_vendor && cp->id == ss_card) { 3903 dev_dbg(chip->card->dev, "hack for %s enabled\n", 3904 cp->name); 3905 3906 chip->amplifier_ctrl = cp->amp; 3907 chip->active_ctrl = cp->active; 3908 chip->mixer_init = cp->mixer_init; 3909 3910 if (cp->init) 3911 cp->init(chip); 3912 break; 3913 } 3914 } 3915 3916 if (external_amp) { 3917 dev_info(chip->card->dev, 3918 "Crystal EAPD support forced on.\n"); 3919 chip->amplifier_ctrl = amp_voyetra; 3920 } 3921 3922 if (thinkpad) { 3923 dev_info(chip->card->dev, 3924 "Activating CLKRUN hack for Thinkpad.\n"); 3925 chip->active_ctrl = clkrun_hack; 3926 clkrun_init(chip); 3927 } 3928 3929 if (chip->amplifier_ctrl == NULL) 3930 chip->amplifier_ctrl = amp_none; 3931 if (chip->active_ctrl == NULL) 3932 chip->active_ctrl = amp_none; 3933 3934 chip->active_ctrl(chip, 1); /* enable CLKRUN */ 3935 3936 pci_set_master(pci); 3937 3938 for (idx = 0; idx < 5; idx++) { 3939 region = &chip->region.idx[idx]; 3940 region->remap_addr = devm_ioremap(&pci->dev, region->base, 3941 region->size); 3942 if (region->remap_addr == NULL) { 3943 dev_err(chip->card->dev, 3944 "%s ioremap problem\n", region->name); 3945 return -ENOMEM; 3946 } 3947 } 3948 3949 if (devm_request_irq(&pci->dev, pci->irq, snd_cs46xx_interrupt, 3950 IRQF_SHARED, KBUILD_MODNAME, chip)) { 3951 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq); 3952 return -EBUSY; 3953 } 3954 chip->irq = pci->irq; 3955 card->sync_irq = chip->irq; 3956 card->private_free = snd_cs46xx_free; 3957 3958 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3959 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip); 3960 if (!chip->dsp_spos_instance) 3961 return -ENOMEM; 3962 #endif 3963 3964 err = snd_cs46xx_chip_init(chip); 3965 if (err < 0) 3966 return err; 3967 3968 snd_cs46xx_proc_init(card, chip); 3969 3970 #ifdef CONFIG_PM_SLEEP 3971 chip->saved_regs = devm_kmalloc_array(&pci->dev, 3972 ARRAY_SIZE(saved_regs), 3973 sizeof(*chip->saved_regs), 3974 GFP_KERNEL); 3975 if (!chip->saved_regs) 3976 return -ENOMEM; 3977 #endif 3978 3979 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3980 return 0; 3981 } 3982