1 #ifndef __SOUND_AZT3328_H 2 #define __SOUND_AZT3328_H 3 4 /* "PU" == "power-up value", as tested on PCI168 PCI rev. 10 */ 5 6 /*** main I/O area port indices ***/ 7 /* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */ 8 #define AZF_IO_SIZE_CODEC 0x80 9 #define AZF_IO_SIZE_CODEC_PM 0x70 10 11 /* the driver initialisation suggests a layout of 4 main areas: 12 * from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe MPU401??). 13 * And another area from 0x60 to 0x6f (DirectX timer, IRQ management, 14 * power management etc.???). */ 15 16 /** playback area **/ 17 #define IDX_IO_PLAY_FLAGS 0x00 /* PU:0x0000 */ 18 /* able to reactivate output after output muting due to 8/16bit 19 * output change, just like 0x0002. 20 * 0x0001 is the only bit that's able to start the DMA counter */ 21 #define DMA_RESUME 0x0001 /* paused if cleared ? */ 22 /* 0x0002 *temporarily* set during DMA stopping. hmm 23 * both 0x0002 and 0x0004 set in playback setup. */ 24 /* able to reactivate output after output muting due to 8/16bit 25 * output change, just like 0x0001. */ 26 #define DMA_PLAY_SOMETHING1 0x0002 /* \ alternated (toggled) */ 27 /* 0x0004: NOT able to reactivate output */ 28 #define DMA_PLAY_SOMETHING2 0x0004 /* / bits */ 29 #define SOMETHING_ALMOST_ALWAYS_SET 0x0008 /* ???; can be modified */ 30 #define DMA_EPILOGUE_SOMETHING 0x0010 31 #define DMA_SOMETHING_ELSE 0x0020 /* ??? */ 32 #define SOMETHING_UNMODIFIABLE 0xffc0 /* unused ? not modifiable */ 33 #define IDX_IO_PLAY_IRQTYPE 0x02 /* PU:0x0001 */ 34 /* write back to flags in case flags are set, in order to ACK IRQ in handler 35 * (bit 1 of port 0x64 indicates interrupt for one of these three types) 36 * sometimes in this case it just writes 0xffff to globally ACK all IRQs 37 * settings written are not reflected when reading back, though. 38 * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows ? */ 39 #define IRQ_PLAY_SOMETHING 0x0001 /* something & ACK */ 40 #define IRQ_FINISHED_PLAYBUF_1 0x0002 /* 1st dmabuf finished & ACK */ 41 #define IRQ_FINISHED_PLAYBUF_2 0x0004 /* 2nd dmabuf finished & ACK */ 42 #define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */ 43 #define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */ 44 #define IRQMASK_UNMODIFIABLE 0xffe0 /* unused ? not modifiable */ 45 #define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area, PU:0x00000000 */ 46 #define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area, PU:0x00000000 */ 47 #define IDX_IO_PLAY_DMA_LEN_1 0x0c /* length of 1st DMA play area, PU:0x0000 */ 48 #define IDX_IO_PLAY_DMA_LEN_2 0x0e /* length of 2nd DMA play area, PU:0x0000 */ 49 #define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */ 50 #define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area, PU:0x0000 */ 51 #define IDX_IO_PLAY_SOUNDFORMAT 0x16 /* PU:0x0010 */ 52 /* all unspecified bits can't be modified */ 53 #define SOUNDFORMAT_FREQUENCY_MASK 0x000f 54 #define SOUNDFORMAT_XTAL1 0x00 55 #define SOUNDFORMAT_XTAL2 0x01 56 /* all _SUSPECTED_ values are not used by Windows drivers, so we don't 57 * have any hard facts, only rough measurements. 58 * All we know is that the crystal used on the board has 24.576MHz, 59 * like many soundcards (which results in the frequencies below when 60 * using certain divider values selected by the values below) */ 61 #define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c | SOUNDFORMAT_XTAL1 62 #define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a | SOUNDFORMAT_XTAL1 63 #define SOUNDFORMAT_FREQ_5510 0x0c | SOUNDFORMAT_XTAL2 64 #define SOUNDFORMAT_FREQ_6620 0x0a | SOUNDFORMAT_XTAL2 65 #define SOUNDFORMAT_FREQ_8000 0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */ 66 #define SOUNDFORMAT_FREQ_9600 0x08 | SOUNDFORMAT_XTAL1 67 #define SOUNDFORMAT_FREQ_11025 0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */ 68 #define SOUNDFORMAT_FREQ_SUSPECTED_13240 0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */ 69 #define SOUNDFORMAT_FREQ_16000 0x02 | SOUNDFORMAT_XTAL1 70 #define SOUNDFORMAT_FREQ_22050 0x02 | SOUNDFORMAT_XTAL2 71 #define SOUNDFORMAT_FREQ_32000 0x04 | SOUNDFORMAT_XTAL1 72 #define SOUNDFORMAT_FREQ_44100 0x04 | SOUNDFORMAT_XTAL2 73 #define SOUNDFORMAT_FREQ_48000 0x06 | SOUNDFORMAT_XTAL1 74 #define SOUNDFORMAT_FREQ_SUSPECTED_66200 0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */ 75 #define SOUNDFORMAT_FLAG_16BIT 0x0010 76 #define SOUNDFORMAT_FLAG_2CHANNELS 0x0020 77 78 /* define frequency helpers, for maximum value safety */ 79 enum { 80 #define AZF_FREQ(rate) AZF_FREQ_##rate = rate 81 AZF_FREQ(4000), 82 AZF_FREQ(4800), 83 AZF_FREQ(5512), 84 AZF_FREQ(6620), 85 AZF_FREQ(8000), 86 AZF_FREQ(9600), 87 AZF_FREQ(11025), 88 AZF_FREQ(13240), 89 AZF_FREQ(16000), 90 AZF_FREQ(22050), 91 AZF_FREQ(32000), 92 AZF_FREQ(44100), 93 AZF_FREQ(48000), 94 AZF_FREQ(66200), 95 #undef AZF_FREQ 96 } AZF_FREQUENCIES; 97 98 /** recording area (see also: playback bit flag definitions) **/ 99 #define IDX_IO_REC_FLAGS 0x20 /* ??, PU:0x0000 */ 100 #define IDX_IO_REC_IRQTYPE 0x22 /* ??, PU:0x0000 */ 101 #define IRQ_REC_SOMETHING 0x0001 /* something & ACK */ 102 #define IRQ_FINISHED_RECBUF_1 0x0002 /* 1st dmabuf finished & ACK */ 103 #define IRQ_FINISHED_RECBUF_2 0x0004 /* 2nd dmabuf finished & ACK */ 104 /* hmm, maybe these are just the corresponding *recording* flags ? 105 * but OTOH they are most likely at port 0x22 instead */ 106 #define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */ 107 #define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */ 108 #define IDX_IO_REC_DMA_START_1 0x24 /* PU:0x00000000 */ 109 #define IDX_IO_REC_DMA_START_2 0x28 /* PU:0x00000000 */ 110 #define IDX_IO_REC_DMA_LEN_1 0x2c /* PU:0x0000 */ 111 #define IDX_IO_REC_DMA_LEN_2 0x2e /* PU:0x0000 */ 112 #define IDX_IO_REC_DMA_CURRPOS 0x30 /* PU:0x00000000 */ 113 #define IDX_IO_REC_DMA_CURROFS 0x34 /* PU:0x00000000 */ 114 #define IDX_IO_REC_SOUNDFORMAT 0x36 /* PU:0x0000 */ 115 116 /** hmm, what is this I/O area for? MPU401?? or external DAC via I2S?? (after playback, recording, ???, timer) **/ 117 #define IDX_IO_SOMETHING_FLAGS 0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init, PU:0x0000 */ 118 /* general */ 119 #define IDX_IO_42H 0x42 /* PU:0x0001 */ 120 121 /** DirectX timer, main interrupt area (FIXME: and something else?) **/ 122 #define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */ 123 /* timer countdown value; triggers IRQ when timer is finished */ 124 #define TIMER_VALUE_MASK 0x000fffffUL 125 /* activate timer countdown */ 126 #define TIMER_COUNTDOWN_ENABLE 0x01000000UL 127 /* trigger timer IRQ on zero transition */ 128 #define TIMER_IRQ_ENABLE 0x02000000UL 129 /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?) 130 * had 0x0020 set upon IRQ handler */ 131 #define TIMER_IRQ_ACK 0x04000000UL 132 #define IDX_IO_IRQSTATUS 0x64 133 /* some IRQ bit in here might also be used to signal a power-management timer 134 * timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing). 135 * Some OPL3 hardware (e.g. in LM4560) has some special timer hardware which 136 * can trigger an OPL3 timer IRQ, so maybe there's such a thing as well... */ 137 138 #define IRQ_PLAYBACK 0x0001 139 #define IRQ_RECORDING 0x0002 140 #define IRQ_UNKNOWN1 0x0004 /* most probably I2S port */ 141 #define IRQ_GAMEPORT 0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */ 142 #define IRQ_MPU401 0x0010 143 #define IRQ_TIMER 0x0020 /* DirectX timer */ 144 #define IRQ_UNKNOWN2 0x0040 /* probably unused, or possibly I2S port? */ 145 #define IRQ_UNKNOWN3 0x0080 /* probably unused, or possibly I2S port? */ 146 #define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */ 147 /* this is set to e.g. 0x3ff or 0x300, and writable; 148 * maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */ 149 #define IDX_IO_SOME_VALUE 0x68 150 #define IO_68_RANDOM_TOGGLE1 0x0100 /* toggles randomly */ 151 #define IO_68_RANDOM_TOGGLE2 0x0200 /* toggles randomly */ 152 /* umm, nope, behaviour of these bits changes depending on what we wrote 153 * to 0x6b!! */ 154 155 /* this WORD can be set to have bits 0x0028 activated (FIXME: correct??); 156 * actually inhibits PCM playback!!! maybe power management??: */ 157 #define IDX_IO_6AH 0x6A 158 /* bit 5: enabling this will activate permanent counting of bytes 2/3 159 * at gameport I/O (0xb402/3) (equal values each) and cause 160 * gameport legacy I/O at 0x0200 to be _DISABLED_! 161 * Is this Digital Enhanced Game Port Enable??? Or maybe it's Testmode 162 * for Enhanced Digital Gameport (see 4D Wave DX card): */ 163 #define IO_6A_SOMETHING1_GAMEPORT 0x0020 164 /* bit 8; sure, this _pauses_ playback (later resumes at same spot!), 165 * but what the heck is this really about??: */ 166 #define IO_6A_PAUSE_PLAYBACK_BIT8 0x0100 167 /* bit 9; sure, this _pauses_ playback (later resumes at same spot!), 168 * but what the heck is this really about??: */ 169 #define IO_6A_PAUSE_PLAYBACK_BIT9 0x0200 170 /* BIT8 and BIT9 are _NOT_ able to affect OPL3 MIDI playback, 171 * thus it suggests influence on PCM only!! 172 * However OTOH there seems to be no bit anywhere around here 173 * which is able to disable OPL3... */ 174 /* bit 10: enabling this actually changes values at legacy gameport 175 * I/O address (0x200); is this enabling of the Digital Enhanced Game Port??? 176 * Or maybe this simply switches off the NE558 circuit, since enabling this 177 * still lets us evaluate button states, but not axis states */ 178 #define IO_6A_SOMETHING2_GAMEPORT 0x0400 179 /* writing 0x0300: causes quite some crackling during 180 * PC activity such as switching windows (PCI traffic?? 181 * --> FIFO/timing settings???) */ 182 /* writing 0x0100 plus/or 0x0200 inhibits playback */ 183 /* since the Windows .INF file has Flag_Enable_JoyStick and 184 * Flag_Enable_SB_DOS_Emulation directly together, it stands to reason 185 * that some other bit in this same register might be responsible 186 * for SB DOS Emulation activation (note that the file did NOT define 187 * a switch for OPL3!) */ 188 #define IDX_IO_6CH 0x6C /* unknown; fully read-writable */ 189 #define IDX_IO_6EH 0x6E 190 /* writing 0xffff returns 0x83fe (or 0x03fe only). 191 * writing 0x83 (and only 0x83!!) to 0x6f will cause 0x6c to switch 192 * from 0000 to ffff. */ 193 194 /* further I/O indices not saved/restored and not readable after writing, 195 * so probably not used */ 196 197 198 /*** Gameport area port indices ***/ 199 /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */ 200 #define AZF_IO_SIZE_GAME 0x08 201 #define AZF_IO_SIZE_GAME_PM 0x06 202 203 enum { 204 AZF_GAME_LEGACY_IO_PORT = 0x200 205 } AZF_GAME_CONFIGS; 206 207 #define IDX_GAME_LEGACY_COMPATIBLE 0x00 208 /* in some operation mode, writing anything to this port 209 * triggers an interrupt: 210 * yup, that's in case IDX_GAME_01H has one of the 211 * axis measurement bits enabled 212 * (and of course one needs to have GAME_HWCFG_IRQ_ENABLE, too) */ 213 214 #define IDX_GAME_AXES_CONFIG 0x01 215 /* NOTE: layout of this register awfully similar (read: "identical??") 216 * to AD1815JS.pdf (p.29) */ 217 218 /* enables axis 1 (X axis) measurement: */ 219 #define GAME_AXES_ENABLE_1 0x01 220 /* enables axis 2 (Y axis) measurement: */ 221 #define GAME_AXES_ENABLE_2 0x02 222 /* enables axis 3 (X axis) measurement: */ 223 #define GAME_AXES_ENABLE_3 0x04 224 /* enables axis 4 (Y axis) measurement: */ 225 #define GAME_AXES_ENABLE_4 0x08 226 /* selects the current axis to read the measured value of 227 * (at IDX_GAME_AXIS_VALUE): 228 * 00 = axis 1, 01 = axis 2, 10 = axis 3, 11 = axis 4: */ 229 #define GAME_AXES_READ_MASK 0x30 230 /* enable to have the latch continuously accept ADC values 231 * (and continuously cause interrupts in case interrupts are enabled); 232 * AD1815JS.pdf says it's ~16ms interval there: */ 233 #define GAME_AXES_LATCH_ENABLE 0x40 234 /* joystick data (measured axes) ready for reading: */ 235 #define GAME_AXES_SAMPLING_READY 0x80 236 237 /* NOTE: other card specs (SiS960 and others!) state that the 238 * game position latches should be frozen when reading and be freed 239 * (== reset?) after reading!!! 240 * Freezing most likely means disabling 0x40 (GAME_AXES_LATCH_ENABLE), 241 * but how to free the value? */ 242 /* An internet search for "gameport latch ADC" should provide some insight 243 * into how to program such a gameport system. */ 244 245 /* writing 0xf0 to 01H once reset both counters to 0, in some special mode!? 246 * yup, in case 6AH 0x20 is not enabled 247 * (and 0x40 is sufficient, 0xf0 is not needed) */ 248 249 #define IDX_GAME_AXIS_VALUE 0x02 250 /* R: value of currently configured axis (word value!); 251 * W: trigger axis measurement */ 252 253 #define IDX_GAME_HWCONFIG 0x04 254 /* note: bits 4 to 7 are never set (== 0) when reading! 255 * --> reserved bits? */ 256 /* enables IRQ notification upon axes measurement ready: */ 257 #define GAME_HWCFG_IRQ_ENABLE 0x01 258 /* these bits choose a different frequency for the 259 * internal ADC counter increment. 260 * hmm, seems to be a combo of bits: 261 * 00 --> standard frequency 262 * 10 --> 1/2 263 * 01 --> 1/20 264 * 11 --> 1/200: */ 265 #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK 0x06 266 267 /* enable gameport legacy I/O address (0x200) 268 * I was unable to locate any configurability for a different address: */ 269 #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE 0x08 270 271 /*** MPU401 ***/ 272 #define AZF_IO_SIZE_MPU 0x04 273 #define AZF_IO_SIZE_MPU_PM 0x04 274 275 /*** OPL3 synth ***/ 276 #define AZF_IO_SIZE_OPL3 0x08 277 #define AZF_IO_SIZE_OPL3_PM 0x06 278 /* hmm, given that a standard OPL3 has 4 registers only, 279 * there might be some enhanced functionality lurking at the end 280 * (especially since register 0x04 has a "non-empty" value 0xfe) */ 281 282 /*** mixer I/O area port indices ***/ 283 /* (only 0x22 of 0x40 bytes saved/restored by Windows driver) 284 * UNFORTUNATELY azf3328 is NOT truly AC97 compliant: see main file intro */ 285 #define AZF_IO_SIZE_MIXER 0x40 286 #define AZF_IO_SIZE_MIXER_PM 0x22 287 288 #define MIXER_VOLUME_RIGHT_MASK 0x001f 289 #define MIXER_VOLUME_LEFT_MASK 0x1f00 290 #define MIXER_MUTE_MASK 0x8000 291 #define IDX_MIXER_RESET 0x00 /* does NOT seem to have AC97 ID bits */ 292 #define IDX_MIXER_PLAY_MASTER 0x02 293 #define IDX_MIXER_MODEMOUT 0x04 294 #define IDX_MIXER_BASSTREBLE 0x06 295 #define MIXER_BASSTREBLE_TREBLE_VOLUME_MASK 0x000e 296 #define MIXER_BASSTREBLE_BASS_VOLUME_MASK 0x0e00 297 #define IDX_MIXER_PCBEEP 0x08 298 #define IDX_MIXER_MODEMIN 0x0a 299 #define IDX_MIXER_MIC 0x0c 300 #define MIXER_MIC_MICGAIN_20DB_ENHANCEMENT_MASK 0x0040 301 #define IDX_MIXER_LINEIN 0x0e 302 #define IDX_MIXER_CDAUDIO 0x10 303 #define IDX_MIXER_VIDEO 0x12 304 #define IDX_MIXER_AUX 0x14 305 #define IDX_MIXER_WAVEOUT 0x16 306 #define IDX_MIXER_FMSYNTH 0x18 307 #define IDX_MIXER_REC_SELECT 0x1a 308 #define MIXER_REC_SELECT_MIC 0x00 309 #define MIXER_REC_SELECT_CD 0x01 310 #define MIXER_REC_SELECT_VIDEO 0x02 311 #define MIXER_REC_SELECT_AUX 0x03 312 #define MIXER_REC_SELECT_LINEIN 0x04 313 #define MIXER_REC_SELECT_MIXSTEREO 0x05 314 #define MIXER_REC_SELECT_MIXMONO 0x06 315 #define MIXER_REC_SELECT_MONOIN 0x07 316 #define IDX_MIXER_REC_VOLUME 0x1c 317 #define IDX_MIXER_ADVCTL1 0x1e 318 /* unlisted bits are unmodifiable */ 319 #define MIXER_ADVCTL1_3DWIDTH_MASK 0x000e 320 #define MIXER_ADVCTL1_HIFI3D_MASK 0x0300 /* yup, this is missing the high bit that official AC97 contains, plus it doesn't have linear bit value range behaviour but instead acts weirdly (possibly we're dealing with two *different* 3D settings here??) */ 321 #define IDX_MIXER_ADVCTL2 0x20 /* subset of AC97_GENERAL_PURPOSE reg! */ 322 /* unlisted bits are unmodifiable */ 323 #define MIXER_ADVCTL2_LPBK 0x0080 /* Loopback mode -- Win driver: "WaveOut3DBypass"? mutes WaveOut at LineOut */ 324 #define MIXER_ADVCTL2_MS 0x0100 /* Mic Select 0=Mic1, 1=Mic2 -- Win driver: "ModemOutSelect"?? */ 325 #define MIXER_ADVCTL2_MIX 0x0200 /* Mono output select 0=Mix, 1=Mic; Win driver: "MonoSelectSource"?? */ 326 #define MIXER_ADVCTL2_3D 0x2000 /* 3D Enhancement 1=on */ 327 #define MIXER_ADVCTL2_POP 0x8000 /* Pcm Out Path, 0=pre 3D, 1=post 3D */ 328 329 #define IDX_MIXER_SOMETHING30H 0x30 /* used, but unknown??? */ 330 331 /* driver internal flags */ 332 #define SET_CHAN_LEFT 1 333 #define SET_CHAN_RIGHT 2 334 335 #endif /* __SOUND_AZT3328_H */ 336