1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168). 3 * Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de> 4 * 5 * Framework borrowed from Bart Hartgers's als4000.c. 6 * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801), 7 * found in a Fujitsu-Siemens PC ("Cordant", aluminum case). 8 * Other versions are: 9 * PCI168 A(W), sub ID 1800 10 * PCI168 A/AP, sub ID 8000 11 * Please give me feedback in case you try my driver with one of these!! 12 * 13 * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download 14 * (XP/Vista do not support this card at all but every Linux distribution 15 * has very good support out of the box; 16 * just to make sure that the right people hit this and get to know that, 17 * despite the high level of Internet ignorance - as usual :-P - 18 * about very good support for this card - on Linux!) 19 * 20 * NOTES 21 * Since Aztech does not provide any chipset documentation, 22 * even on repeated request to various addresses, 23 * and the answer that was finally given was negative 24 * (and I was stupid enough to manage to get hold of a PCI168 soundcard 25 * in the first place >:-P}), 26 * I was forced to base this driver on reverse engineering 27 * (3 weeks' worth of evenings filled with driver work). 28 * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros) 29 * 30 * It is quite likely that the AZF3328 chip is the PCI cousin of the 31 * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs. 32 * 33 * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name 34 * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec, 35 * Fincitec acquired by National Semiconductor in 2002, together with the 36 * Fincitec-related company ARSmikro) has the following features: 37 * 38 * - compatibility & compliance: 39 * - Microsoft PC 97 ("PC 97 Hardware Design Guide", 40 * http://www.microsoft.com/whdc/archive/pcguides.mspx) 41 * - Microsoft PC 98 Baseline Audio 42 * - MPU401 UART 43 * - Sound Blaster Emulation (DOS Box) 44 * - builtin AC97 conformant codec (SNR over 80dB) 45 * Note that "conformant" != "compliant"!! this chip's mixer register layout 46 * *differs* from the standard AC97 layout: 47 * they chose to not implement the headphone register (which is not a 48 * problem since it's merely optional), yet when doing this, they committed 49 * the grave sin of letting other registers follow immediately instead of 50 * keeping a headphone dummy register, thereby shifting the mixer register 51 * addresses illegally. So far unfortunately it looks like the very flexible 52 * ALSA AC97 support is still not enough to easily compensate for such a 53 * grave layout violation despite all tweaks and quirks mechanisms it offers. 54 * Well, not quite: now ac97 layer is much improved (bus-specific ops!), 55 * thus I was able to implement support - it's actually working quite well. 56 * An interesting item might be Aztech AMR 2800-W, since it's an AC97 57 * modem card which might reveal the Aztech-specific codec ID which 58 * we might want to pretend, too. Dito PCI168's brother, PCI368, 59 * where the advertising datasheet says it's AC97-based and has a 60 * Digital Enhanced Game Port. 61 * - builtin genuine OPL3 - verified to work fine, 20080506 62 * - full duplex 16bit playback/record at independent sampling rate 63 * - MPU401 (+ legacy address support, claimed by one official spec sheet) 64 * FIXME: how to enable legacy addr?? 65 * - game port (legacy address support) 66 * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven 67 * features supported). - See common term "Digital Enhanced Game Port"... 68 * (probably DirectInput 3.0 spec - confirm) 69 * - builtin 3D enhancement (said to be YAMAHA Ymersion) 70 * - built-in General DirectX timer having a 20 bits counter 71 * with 1us resolution (see below!) 72 * - I2S serial output port for external DAC 73 * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?] 74 * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI 75 * - supports hardware volume control 76 * - single chip low cost solution (128 pin QFP) 77 * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip] 78 * required for Microsoft's logo compliance (FIXME: where?) 79 * At least the Trident 4D Wave DX has one bit somewhere 80 * to enable writes to PCI subsystem VID registers, that should be it. 81 * This might easily be in extended PCI reg space, since PCI168 also has 82 * some custom data starting at 0x80. What kind of config settings 83 * are located in our extended PCI space anyway?? 84 * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms 85 * [TDA1517P chip] 86 * 87 * Note that this driver now is actually *better* than the Windows driver, 88 * since it additionally supports the card's 1MHz DirectX timer - just try 89 * the following snd-seq module parameters etc.: 90 * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0 91 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0 92 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000 93 * - "timidity -iAv -B2,8 -Os -EFreverb=0" 94 * - "pmidi -p 128:0 jazz.mid" 95 * 96 * OPL3 hardware playback testing, try something like: 97 * cat /proc/asound/hwdep 98 * and 99 * aconnect -o 100 * Then use 101 * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3 102 * where x,y is the xx-yy number as given in hwdep. 103 * Then try 104 * pmidi -p a:b jazz.mid 105 * where a:b is the client number plus 0 usually, as given by aconnect above. 106 * Oh, and make sure to unmute the FM mixer control (doh!) 107 * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!) 108 * despite no CPU activity, possibly due to hindering ACPI idling somehow. 109 * Shouldn't be a problem of the AZF3328 chip itself, I'd hope. 110 * Higher PCM / FM mixer levels seem to conflict (causes crackling), 111 * at least sometimes. Maybe even use with hardware sequencer timer above :) 112 * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too. 113 * 114 * Certain PCI versions of this card are susceptible to DMA traffic underruns 115 * in some systems (resulting in sound crackling/clicking/popping), 116 * probably because they don't have a DMA FIFO buffer or so. 117 * Overview (PCI ID/PCI subID/PCI rev.): 118 * - no DMA crackling on SiS735: 0x50DC/0x1801/16 119 * - unknown performance: 0x50DC/0x1801/10 120 * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler) 121 * 122 * Crackling happens with VIA chipsets or, in my case, an SiS735, which is 123 * supposed to be very fast and supposed to get rid of crackling much 124 * better than a VIA, yet ironically I still get crackling, like many other 125 * people with the same chipset. 126 * Possible remedies: 127 * - use speaker (amplifier) output instead of headphone output 128 * (in case crackling is due to overloaded output clipping) 129 * - plug card into a different PCI slot, preferably one that isn't shared 130 * too much (this helps a lot, but not completely!) 131 * - get rid of PCI VGA card, use AGP instead 132 * - upgrade or downgrade BIOS 133 * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX) 134 * Not too helpful. 135 * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS 136 * 137 * BUGS 138 * - full-duplex might *still* be problematic, however a recent test was fine 139 * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated 140 * if you set PCM output switch to "pre 3D" instead of "post 3D". 141 * If this can't be set, then get a mixer application that Isn't Stupid (tm) 142 * (e.g. kmix, gamix) - unfortunately several are!! 143 * - locking is not entirely clean, especially the audio stream activity 144 * ints --> may be racy 145 * - an _unconnected_ secondary joystick at the gameport will be reported 146 * to be "active" (floating values, not precisely -1) due to the way we need 147 * to read the Digital Enhanced Game Port. Not sure whether it is fixable. 148 * 149 * TODO 150 * - use PCI_VDEVICE 151 * - verify driver status on x86_64 152 * - test multi-card driver operation 153 * - (ab)use 1MHz DirectX timer as kernel clocksource 154 * - test MPU401 MIDI playback etc. 155 * - add more power micro-management (disable various units of the card 156 * as long as they're unused, to improve audio quality and save power). 157 * However this requires more I/O ports which I haven't figured out yet 158 * and which thus might not even exist... 159 * The standard suspend/resume functionality could probably make use of 160 * some improvement, too... 161 * - figure out what all unknown port bits are responsible for 162 * - figure out some cleverly evil scheme to possibly make ALSA AC97 code 163 * fully accept our quite incompatible ""AC97"" mixer and thus save some 164 * code (but I'm not too optimistic that doing this is possible at all) 165 * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport. 166 */ 167 168 #include <linux/io.h> 169 #include <linux/init.h> 170 #include <linux/bug.h> /* WARN_ONCE */ 171 #include <linux/pci.h> 172 #include <linux/delay.h> 173 #include <linux/slab.h> 174 #include <linux/gameport.h> 175 #include <linux/module.h> 176 #include <linux/dma-mapping.h> 177 #include <sound/core.h> 178 #include <sound/control.h> 179 #include <sound/pcm.h> 180 #include <sound/rawmidi.h> 181 #include <sound/mpu401.h> 182 #include <sound/opl3.h> 183 #include <sound/initval.h> 184 /* 185 * Config switch, to use ALSA's AC97 layer instead of old custom mixer crap. 186 * If the AC97 compatibility parts we needed to implement locally turn out 187 * to work nicely, then remove the old implementation eventually. 188 */ 189 #define AZF_USE_AC97_LAYER 1 190 191 #ifdef AZF_USE_AC97_LAYER 192 #include <sound/ac97_codec.h> 193 #endif 194 #include "azt3328.h" 195 196 MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>"); 197 MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)"); 198 MODULE_LICENSE("GPL"); 199 200 #if IS_REACHABLE(CONFIG_GAMEPORT) 201 #define SUPPORT_GAMEPORT 1 202 #endif 203 204 /* === Debug settings === 205 Further diagnostic functionality than the settings below 206 does not need to be provided, since one can easily write a POSIX shell script 207 to dump the card's I/O ports (those listed in lspci -v -v): 208 dump() 209 { 210 local descr=$1; local addr=$2; local count=$3 211 212 echo "${descr}: ${count} @ ${addr}:" 213 dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \ 214 2>/dev/null| hexdump -C 215 } 216 and then use something like 217 "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8", 218 "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8", 219 possibly within a "while true; do ... sleep 1; done" loop. 220 Tweaking ports could be done using 221 VALSTRING="`printf "%02x" $value`" 222 printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \ 223 2>/dev/null 224 */ 225 226 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 227 module_param_array(index, int, NULL, 0444); 228 MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard."); 229 230 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 231 module_param_array(id, charp, NULL, 0444); 232 MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard."); 233 234 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 235 module_param_array(enable, bool, NULL, 0444); 236 MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard."); 237 238 static int seqtimer_scaling = 128; 239 module_param(seqtimer_scaling, int, 0444); 240 MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128."); 241 242 enum snd_azf3328_codec_type { 243 /* warning: fixed indices (also used for bitmask checks!) */ 244 AZF_CODEC_PLAYBACK = 0, 245 AZF_CODEC_CAPTURE = 1, 246 AZF_CODEC_I2S_OUT = 2, 247 }; 248 249 struct snd_azf3328_codec_data { 250 unsigned long io_base; /* keep first! (avoid offset calc) */ 251 unsigned int dma_base; /* helper to avoid an indirection in hotpath */ 252 spinlock_t *lock; /* TODO: convert to our own per-codec lock member */ 253 struct snd_pcm_substream *substream; 254 bool running; 255 enum snd_azf3328_codec_type type; 256 const char *name; 257 }; 258 259 struct snd_azf3328 { 260 /* often-used fields towards beginning, then grouped */ 261 262 unsigned long ctrl_io; /* usually 0xb000, size 128 */ 263 unsigned long game_io; /* usually 0xb400, size 8 */ 264 unsigned long mpu_io; /* usually 0xb800, size 4 */ 265 unsigned long opl3_io; /* usually 0xbc00, size 8 */ 266 unsigned long mixer_io; /* usually 0xc000, size 64 */ 267 268 spinlock_t reg_lock; 269 270 struct snd_timer *timer; 271 272 struct snd_pcm *pcm[3]; 273 274 /* playback, recording and I2S out codecs */ 275 struct snd_azf3328_codec_data codecs[3]; 276 277 #ifdef AZF_USE_AC97_LAYER 278 struct snd_ac97 *ac97; 279 #endif 280 281 struct snd_card *card; 282 struct snd_rawmidi *rmidi; 283 284 #ifdef SUPPORT_GAMEPORT 285 struct gameport *gameport; 286 u16 axes[4]; 287 #endif 288 289 struct pci_dev *pci; 290 int irq; 291 292 /* register 0x6a is write-only, thus need to remember setting. 293 * If we need to add more registers here, then we might try to fold this 294 * into some transparent combined shadow register handling with 295 * CONFIG_PM register storage below, but that's slightly difficult. */ 296 u16 shadow_reg_ctrl_6AH; 297 298 #ifdef CONFIG_PM_SLEEP 299 /* register value containers for power management 300 * Note: not always full I/O range preserved (similar to Win driver!) */ 301 u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4]; 302 u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4]; 303 u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4]; 304 u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4]; 305 u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4]; 306 #endif 307 }; 308 309 static const struct pci_device_id snd_azf3328_ids[] = { 310 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */ 311 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */ 312 { 0, } 313 }; 314 315 MODULE_DEVICE_TABLE(pci, snd_azf3328_ids); 316 317 318 static int 319 snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) 320 { 321 /* Well, strictly spoken, the inb/outb sequence isn't atomic 322 and would need locking. However we currently don't care 323 since it potentially complicates matters. */ 324 u8 prev = inb(reg), new; 325 326 new = (do_set) ? (prev|mask) : (prev & ~mask); 327 /* we need to always write the new value no matter whether it differs 328 * or not, since some register bits don't indicate their setting */ 329 outb(new, reg); 330 if (new != prev) 331 return 1; 332 333 return 0; 334 } 335 336 static inline void 337 snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec, 338 unsigned reg, 339 u8 value 340 ) 341 { 342 outb(value, codec->io_base + reg); 343 } 344 345 static inline u8 346 snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg) 347 { 348 return inb(codec->io_base + reg); 349 } 350 351 static inline void 352 snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec, 353 unsigned reg, 354 u16 value 355 ) 356 { 357 outw(value, codec->io_base + reg); 358 } 359 360 static inline u16 361 snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg) 362 { 363 return inw(codec->io_base + reg); 364 } 365 366 static inline void 367 snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec, 368 unsigned reg, 369 u32 value 370 ) 371 { 372 outl(value, codec->io_base + reg); 373 } 374 375 static inline void 376 snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec, 377 unsigned reg, const void *buffer, int count 378 ) 379 { 380 unsigned long addr = codec->io_base + reg; 381 if (count) { 382 const u32 *buf = buffer; 383 do { 384 outl(*buf++, addr); 385 addr += 4; 386 } while (--count); 387 } 388 } 389 390 static inline u32 391 snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg) 392 { 393 return inl(codec->io_base + reg); 394 } 395 396 static inline void 397 snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) 398 { 399 outb(value, chip->ctrl_io + reg); 400 } 401 402 static inline u8 403 snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg) 404 { 405 return inb(chip->ctrl_io + reg); 406 } 407 408 static inline u16 409 snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg) 410 { 411 return inw(chip->ctrl_io + reg); 412 } 413 414 static inline void 415 snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 416 { 417 outw(value, chip->ctrl_io + reg); 418 } 419 420 static inline void 421 snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value) 422 { 423 outl(value, chip->ctrl_io + reg); 424 } 425 426 static inline void 427 snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) 428 { 429 outb(value, chip->game_io + reg); 430 } 431 432 static inline void 433 snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 434 { 435 outw(value, chip->game_io + reg); 436 } 437 438 static inline u8 439 snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg) 440 { 441 return inb(chip->game_io + reg); 442 } 443 444 static inline u16 445 snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg) 446 { 447 return inw(chip->game_io + reg); 448 } 449 450 static inline void 451 snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 452 { 453 outw(value, chip->mixer_io + reg); 454 } 455 456 static inline u16 457 snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg) 458 { 459 return inw(chip->mixer_io + reg); 460 } 461 462 #define AZF_MUTE_BIT 0x80 463 464 static bool 465 snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip, 466 unsigned reg, bool do_mute 467 ) 468 { 469 unsigned long portbase = chip->mixer_io + reg + 1; 470 bool updated; 471 472 /* the mute bit is on the *second* (i.e. right) register of a 473 * left/right channel setting */ 474 updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute); 475 476 /* indicate whether it was muted before */ 477 return (do_mute) ? !updated : updated; 478 } 479 480 static inline bool 481 snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip, 482 bool do_mute 483 ) 484 { 485 return snd_azf3328_mixer_mute_control( 486 chip, 487 IDX_MIXER_PLAY_MASTER, 488 do_mute 489 ); 490 } 491 492 static inline bool 493 snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip, 494 bool do_mute 495 ) 496 { 497 return snd_azf3328_mixer_mute_control( 498 chip, 499 IDX_MIXER_WAVEOUT, 500 do_mute 501 ); 502 } 503 504 static inline void 505 snd_azf3328_mixer_reset(const struct snd_azf3328 *chip) 506 { 507 /* reset (close) mixer: 508 * first mute master volume, then reset 509 */ 510 snd_azf3328_mixer_mute_control_master(chip, 1); 511 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 512 } 513 514 #ifdef AZF_USE_AC97_LAYER 515 516 static inline void 517 snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip, 518 unsigned short reg, const char *mode) 519 { 520 /* need to add some more or less clever emulation? */ 521 dev_warn(chip->card->dev, 522 "missing %s emulation for AC97 register 0x%02x!\n", 523 mode, reg); 524 } 525 526 /* 527 * Need to have _special_ AC97 mixer hardware register index mapper, 528 * to compensate for the issue of a rather AC97-incompatible hardware layout. 529 */ 530 #define AZF_REG_MASK 0x3f 531 #define AZF_AC97_REG_UNSUPPORTED 0x8000 532 #define AZF_AC97_REG_REAL_IO_READ 0x4000 533 #define AZF_AC97_REG_REAL_IO_WRITE 0x2000 534 #define AZF_AC97_REG_REAL_IO_RW \ 535 (AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE) 536 #define AZF_AC97_REG_EMU_IO_READ 0x0400 537 #define AZF_AC97_REG_EMU_IO_WRITE 0x0200 538 #define AZF_AC97_REG_EMU_IO_RW \ 539 (AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE) 540 static unsigned short 541 snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg) 542 { 543 static const struct { 544 unsigned short azf_reg; 545 } azf_reg_mapper[] = { 546 /* Especially when taking into consideration 547 * mono/stereo-based sequence of azf vs. AC97 control series, 548 * it's quite obvious that azf simply got rid 549 * of the AC97_HEADPHONE control at its intended offset, 550 * thus shifted _all_ controls by one, 551 * and _then_ simply added it as an FMSYNTH control at the end, 552 * to make up for the offset. 553 * This means we'll have to translate indices here as 554 * needed and then do some tiny AC97 patch action 555 * (snd_ac97_rename_vol_ctl() etc.) - that's it. 556 */ 557 { /* AC97_RESET */ IDX_MIXER_RESET 558 | AZF_AC97_REG_REAL_IO_WRITE 559 | AZF_AC97_REG_EMU_IO_READ }, 560 { /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER }, 561 /* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */ 562 { /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH }, 563 { /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT }, 564 { /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE }, 565 { /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP }, 566 { /* AC97_PHONE */ IDX_MIXER_MODEMIN }, 567 { /* AC97_MIC */ IDX_MIXER_MIC }, 568 { /* AC97_LINE */ IDX_MIXER_LINEIN }, 569 { /* AC97_CD */ IDX_MIXER_CDAUDIO }, 570 { /* AC97_VIDEO */ IDX_MIXER_VIDEO }, 571 { /* AC97_AUX */ IDX_MIXER_AUX }, 572 { /* AC97_PCM */ IDX_MIXER_WAVEOUT }, 573 { /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT }, 574 { /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME }, 575 { /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW }, 576 { /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 }, 577 { /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 }, 578 }; 579 580 unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED; 581 582 /* azf3328 supports the low-numbered and low-spec:ed range 583 of AC97 regs only */ 584 if (reg <= AC97_3D_CONTROL) { 585 unsigned short reg_idx = reg / 2; 586 reg_azf = azf_reg_mapper[reg_idx].azf_reg; 587 /* a translation-only entry means it's real read/write: */ 588 if (!(reg_azf & ~AZF_REG_MASK)) 589 reg_azf |= AZF_AC97_REG_REAL_IO_RW; 590 } else { 591 switch (reg) { 592 case AC97_POWERDOWN: 593 reg_azf = AZF_AC97_REG_EMU_IO_RW; 594 break; 595 case AC97_EXTENDED_ID: 596 reg_azf = AZF_AC97_REG_EMU_IO_READ; 597 break; 598 case AC97_EXTENDED_STATUS: 599 /* I don't know what the h*ll AC97 layer 600 * would consult this _extended_ register for 601 * given a base-AC97-advertised card, 602 * but let's just emulate it anyway :-P 603 */ 604 reg_azf = AZF_AC97_REG_EMU_IO_RW; 605 break; 606 case AC97_VENDOR_ID1: 607 case AC97_VENDOR_ID2: 608 reg_azf = AZF_AC97_REG_EMU_IO_READ; 609 break; 610 } 611 } 612 return reg_azf; 613 } 614 615 static const unsigned short 616 azf_emulated_ac97_caps = 617 AC97_BC_DEDICATED_MIC | 618 AC97_BC_BASS_TREBLE | 619 /* Headphone is an FM Synth control here */ 620 AC97_BC_HEADPHONE | 621 /* no AC97_BC_LOUDNESS! */ 622 /* mask 0x7c00 is 623 vendor-specific 3D enhancement 624 vendor indicator. 625 Since there actually _is_ an 626 entry for Aztech Labs 627 (13), make damn sure 628 to indicate it. */ 629 (13 << 10); 630 631 static const unsigned short 632 azf_emulated_ac97_powerdown = 633 /* pretend everything to be active */ 634 AC97_PD_ADC_STATUS | 635 AC97_PD_DAC_STATUS | 636 AC97_PD_MIXER_STATUS | 637 AC97_PD_VREF_STATUS; 638 639 /* 640 * Emulated, _inofficial_ vendor ID 641 * (there might be some devices such as the MR 2800-W 642 * which could reveal the real Aztech AC97 ID). 643 * We choose to use "AZT" prefix, and then use 1 to indicate PCI168 644 * (better don't use 0x68 since there's a PCI368 as well). 645 */ 646 static const unsigned int 647 azf_emulated_ac97_vendor_id = 0x415a5401; 648 649 static unsigned short 650 snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97) 651 { 652 const struct snd_azf3328 *chip = ac97->private_data; 653 unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); 654 unsigned short reg_val = 0; 655 bool unsupported = false; 656 657 dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n", 658 reg_ac97); 659 if (reg_azf & AZF_AC97_REG_UNSUPPORTED) 660 unsupported = true; 661 else { 662 if (reg_azf & AZF_AC97_REG_REAL_IO_READ) 663 reg_val = snd_azf3328_mixer_inw(chip, 664 reg_azf & AZF_REG_MASK); 665 else { 666 /* 667 * Proceed with dummy I/O read, 668 * to ensure compatible timing where this may matter. 669 * (ALSA AC97 layer usually doesn't call I/O functions 670 * due to intelligent I/O caching anyway) 671 * Choose a mixer register that's thoroughly unrelated 672 * to common audio (try to minimize distortion). 673 */ 674 snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H); 675 } 676 677 if (reg_azf & AZF_AC97_REG_EMU_IO_READ) { 678 switch (reg_ac97) { 679 case AC97_RESET: 680 reg_val |= azf_emulated_ac97_caps; 681 break; 682 case AC97_POWERDOWN: 683 reg_val |= azf_emulated_ac97_powerdown; 684 break; 685 case AC97_EXTENDED_ID: 686 case AC97_EXTENDED_STATUS: 687 /* AFAICS we simply can't support anything: */ 688 reg_val |= 0; 689 break; 690 case AC97_VENDOR_ID1: 691 reg_val = azf_emulated_ac97_vendor_id >> 16; 692 break; 693 case AC97_VENDOR_ID2: 694 reg_val = azf_emulated_ac97_vendor_id & 0xffff; 695 break; 696 default: 697 unsupported = true; 698 break; 699 } 700 } 701 } 702 if (unsupported) 703 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read"); 704 705 return reg_val; 706 } 707 708 static void 709 snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97, 710 unsigned short reg_ac97, unsigned short val) 711 { 712 const struct snd_azf3328 *chip = ac97->private_data; 713 unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); 714 bool unsupported = false; 715 716 dev_dbg(chip->card->dev, 717 "snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n", 718 reg_ac97, val); 719 if (reg_azf & AZF_AC97_REG_UNSUPPORTED) 720 unsupported = true; 721 else { 722 if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE) 723 snd_azf3328_mixer_outw( 724 chip, 725 reg_azf & AZF_REG_MASK, 726 val 727 ); 728 else 729 if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) { 730 switch (reg_ac97) { 731 case AC97_REC_GAIN_MIC: 732 case AC97_POWERDOWN: 733 case AC97_EXTENDED_STATUS: 734 /* 735 * Silently swallow these writes. 736 * Since for most registers our card doesn't 737 * actually support a comparable feature, 738 * this is exactly what we should do here. 739 * The AC97 layer's I/O caching probably 740 * automatically takes care of all the rest... 741 * (remembers written values etc.) 742 */ 743 break; 744 default: 745 unsupported = true; 746 break; 747 } 748 } 749 } 750 if (unsupported) 751 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write"); 752 } 753 754 static int 755 snd_azf3328_mixer_new(struct snd_azf3328 *chip) 756 { 757 struct snd_ac97_bus *bus; 758 struct snd_ac97_template ac97; 759 static const struct snd_ac97_bus_ops ops = { 760 .write = snd_azf3328_mixer_ac97_write, 761 .read = snd_azf3328_mixer_ac97_read, 762 }; 763 int rc; 764 765 memset(&ac97, 0, sizeof(ac97)); 766 ac97.scaps = AC97_SCAP_SKIP_MODEM 767 | AC97_SCAP_AUDIO /* we support audio! */ 768 | AC97_SCAP_NO_SPDIF; 769 ac97.private_data = chip; 770 ac97.pci = chip->pci; 771 772 /* 773 * ALSA's AC97 layer has terrible init crackling issues, 774 * unfortunately, and since it makes use of AC97_RESET, 775 * there's no use trying to mute Master Playback proactively. 776 */ 777 778 rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus); 779 if (!rc) 780 rc = snd_ac97_mixer(bus, &ac97, &chip->ac97); 781 /* 782 * Make sure to complain loudly in case of AC97 init failure, 783 * since failure may happen quite often, 784 * due to this card being a very quirky AC97 "lookalike". 785 */ 786 if (rc) 787 dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc); 788 789 /* If we return an error here, then snd_card_free() should 790 * free up any ac97 codecs that got created, as well as the bus. 791 */ 792 return rc; 793 } 794 #else /* AZF_USE_AC97_LAYER */ 795 static void 796 snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, 797 unsigned reg, 798 unsigned char dst_vol_left, 799 unsigned char dst_vol_right, 800 int chan_sel, int delay 801 ) 802 { 803 unsigned long portbase = chip->mixer_io + reg; 804 unsigned char curr_vol_left = 0, curr_vol_right = 0; 805 int left_change = 0, right_change = 0; 806 807 if (chan_sel & SET_CHAN_LEFT) { 808 curr_vol_left = inb(portbase + 1); 809 810 /* take care of muting flag contained in left channel */ 811 if (curr_vol_left & AZF_MUTE_BIT) 812 dst_vol_left |= AZF_MUTE_BIT; 813 else 814 dst_vol_left &= ~AZF_MUTE_BIT; 815 816 left_change = (curr_vol_left > dst_vol_left) ? -1 : 1; 817 } 818 819 if (chan_sel & SET_CHAN_RIGHT) { 820 curr_vol_right = inb(portbase + 0); 821 822 right_change = (curr_vol_right > dst_vol_right) ? -1 : 1; 823 } 824 825 do { 826 if (left_change) { 827 if (curr_vol_left != dst_vol_left) { 828 curr_vol_left += left_change; 829 outb(curr_vol_left, portbase + 1); 830 } else 831 left_change = 0; 832 } 833 if (right_change) { 834 if (curr_vol_right != dst_vol_right) { 835 curr_vol_right += right_change; 836 837 /* during volume change, the right channel is crackling 838 * somewhat more than the left channel, unfortunately. 839 * This seems to be a hardware issue. */ 840 outb(curr_vol_right, portbase + 0); 841 } else 842 right_change = 0; 843 } 844 if (delay) 845 mdelay(delay); 846 } while ((left_change) || (right_change)); 847 } 848 849 /* 850 * general mixer element 851 */ 852 struct azf3328_mixer_reg { 853 unsigned reg; 854 unsigned int lchan_shift, rchan_shift; 855 unsigned int mask; 856 unsigned int invert: 1; 857 unsigned int stereo: 1; 858 unsigned int enum_c: 4; 859 }; 860 861 #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ 862 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \ 863 (mask << 16) | \ 864 (invert << 24) | \ 865 (stereo << 25) | \ 866 (enum_c << 26)) 867 868 static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val) 869 { 870 r->reg = val & 0xff; 871 r->lchan_shift = (val >> 8) & 0x0f; 872 r->rchan_shift = (val >> 12) & 0x0f; 873 r->mask = (val >> 16) & 0xff; 874 r->invert = (val >> 24) & 1; 875 r->stereo = (val >> 25) & 1; 876 r->enum_c = (val >> 26) & 0x0f; 877 } 878 879 /* 880 * mixer switches/volumes 881 */ 882 883 #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \ 884 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 885 .info = snd_azf3328_info_mixer, \ 886 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 887 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \ 888 } 889 890 #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ 891 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 892 .info = snd_azf3328_info_mixer, \ 893 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 894 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ 895 } 896 897 #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ 898 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 899 .info = snd_azf3328_info_mixer, \ 900 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 901 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ 902 } 903 904 #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ 905 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 906 .info = snd_azf3328_info_mixer, \ 907 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 908 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ 909 } 910 911 #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \ 912 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 913 .info = snd_azf3328_info_mixer_enum, \ 914 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \ 915 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \ 916 } 917 918 static int 919 snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol, 920 struct snd_ctl_elem_info *uinfo) 921 { 922 struct azf3328_mixer_reg reg; 923 924 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 925 uinfo->type = reg.mask == 1 ? 926 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 927 uinfo->count = reg.stereo + 1; 928 uinfo->value.integer.min = 0; 929 uinfo->value.integer.max = reg.mask; 930 return 0; 931 } 932 933 static int 934 snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol, 935 struct snd_ctl_elem_value *ucontrol) 936 { 937 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 938 struct azf3328_mixer_reg reg; 939 u16 oreg, val; 940 941 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 942 943 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 944 val = (oreg >> reg.lchan_shift) & reg.mask; 945 if (reg.invert) 946 val = reg.mask - val; 947 ucontrol->value.integer.value[0] = val; 948 if (reg.stereo) { 949 val = (oreg >> reg.rchan_shift) & reg.mask; 950 if (reg.invert) 951 val = reg.mask - val; 952 ucontrol->value.integer.value[1] = val; 953 } 954 dev_dbg(chip->card->dev, 955 "get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n", 956 reg.reg, oreg, 957 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 958 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); 959 return 0; 960 } 961 962 static int 963 snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol, 964 struct snd_ctl_elem_value *ucontrol) 965 { 966 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 967 struct azf3328_mixer_reg reg; 968 u16 oreg, nreg, val; 969 970 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 971 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 972 val = ucontrol->value.integer.value[0] & reg.mask; 973 if (reg.invert) 974 val = reg.mask - val; 975 nreg = oreg & ~(reg.mask << reg.lchan_shift); 976 nreg |= (val << reg.lchan_shift); 977 if (reg.stereo) { 978 val = ucontrol->value.integer.value[1] & reg.mask; 979 if (reg.invert) 980 val = reg.mask - val; 981 nreg &= ~(reg.mask << reg.rchan_shift); 982 nreg |= (val << reg.rchan_shift); 983 } 984 if (reg.mask >= 0x07) /* it's a volume control, so better take care */ 985 snd_azf3328_mixer_write_volume_gradually( 986 chip, reg.reg, nreg >> 8, nreg & 0xff, 987 /* just set both channels, doesn't matter */ 988 SET_CHAN_LEFT|SET_CHAN_RIGHT, 989 0); 990 else 991 snd_azf3328_mixer_outw(chip, reg.reg, nreg); 992 993 dev_dbg(chip->card->dev, 994 "put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n", 995 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 996 oreg, reg.lchan_shift, reg.rchan_shift, 997 nreg, snd_azf3328_mixer_inw(chip, reg.reg)); 998 return (nreg != oreg); 999 } 1000 1001 static int 1002 snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol, 1003 struct snd_ctl_elem_info *uinfo) 1004 { 1005 static const char * const texts1[] = { 1006 "Mic1", "Mic2" 1007 }; 1008 static const char * const texts2[] = { 1009 "Mix", "Mic" 1010 }; 1011 static const char * const texts3[] = { 1012 "Mic", "CD", "Video", "Aux", 1013 "Line", "Mix", "Mix Mono", "Phone" 1014 }; 1015 static const char * const texts4[] = { 1016 "pre 3D", "post 3D" 1017 }; 1018 struct azf3328_mixer_reg reg; 1019 const char * const *p = NULL; 1020 1021 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1022 if (reg.reg == IDX_MIXER_ADVCTL2) { 1023 switch(reg.lchan_shift) { 1024 case 8: /* modem out sel */ 1025 p = texts1; 1026 break; 1027 case 9: /* mono sel source */ 1028 p = texts2; 1029 break; 1030 case 15: /* PCM Out Path */ 1031 p = texts4; 1032 break; 1033 } 1034 } else if (reg.reg == IDX_MIXER_REC_SELECT) 1035 p = texts3; 1036 1037 return snd_ctl_enum_info(uinfo, 1038 (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1, 1039 reg.enum_c, p); 1040 } 1041 1042 static int 1043 snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol, 1044 struct snd_ctl_elem_value *ucontrol) 1045 { 1046 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 1047 struct azf3328_mixer_reg reg; 1048 unsigned short val; 1049 1050 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1051 val = snd_azf3328_mixer_inw(chip, reg.reg); 1052 if (reg.reg == IDX_MIXER_REC_SELECT) { 1053 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); 1054 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); 1055 } else 1056 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); 1057 1058 dev_dbg(chip->card->dev, 1059 "get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n", 1060 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], 1061 reg.lchan_shift, reg.enum_c); 1062 return 0; 1063 } 1064 1065 static int 1066 snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol, 1067 struct snd_ctl_elem_value *ucontrol) 1068 { 1069 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 1070 struct azf3328_mixer_reg reg; 1071 u16 oreg, nreg, val; 1072 1073 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1074 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 1075 val = oreg; 1076 if (reg.reg == IDX_MIXER_REC_SELECT) { 1077 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U || 1078 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U) 1079 return -EINVAL; 1080 val = (ucontrol->value.enumerated.item[0] << 8) | 1081 (ucontrol->value.enumerated.item[1] << 0); 1082 } else { 1083 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U) 1084 return -EINVAL; 1085 val &= ~((reg.enum_c - 1) << reg.lchan_shift); 1086 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); 1087 } 1088 snd_azf3328_mixer_outw(chip, reg.reg, val); 1089 nreg = val; 1090 1091 dev_dbg(chip->card->dev, 1092 "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); 1093 return (nreg != oreg); 1094 } 1095 1096 static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] = { 1097 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1), 1098 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1), 1099 AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1), 1100 AZF3328_MIXER_VOL_STEREO("PCM Playback Volume", 1101 IDX_MIXER_WAVEOUT, 0x1f, 1), 1102 AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch", 1103 IDX_MIXER_ADVCTL2, 7, 1), 1104 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1), 1105 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1), 1106 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1), 1107 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1), 1108 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1), 1109 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0), 1110 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0), 1111 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1), 1112 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1), 1113 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0), 1114 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1), 1115 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1), 1116 AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1), 1117 AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1), 1118 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1), 1119 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1), 1120 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1), 1121 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1), 1122 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1), 1123 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1), 1124 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1), 1125 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1), 1126 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8), 1127 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9), 1128 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */ 1129 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0), 1130 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0), 1131 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0), 1132 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */ 1133 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */ 1134 #if MIXER_TESTING 1135 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0), 1136 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0), 1137 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0), 1138 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0), 1139 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0), 1140 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0), 1141 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0), 1142 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0), 1143 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0), 1144 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0), 1145 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0), 1146 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0), 1147 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0), 1148 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0), 1149 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0), 1150 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0), 1151 #endif 1152 }; 1153 1154 static const u16 snd_azf3328_init_values[][2] = { 1155 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f }, 1156 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f }, 1157 { IDX_MIXER_BASSTREBLE, 0x0000 }, 1158 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f }, 1159 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f }, 1160 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f }, 1161 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f }, 1162 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f }, 1163 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f }, 1164 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f }, 1165 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f }, 1166 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f }, 1167 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 }, 1168 }; 1169 1170 static int 1171 snd_azf3328_mixer_new(struct snd_azf3328 *chip) 1172 { 1173 struct snd_card *card; 1174 const struct snd_kcontrol_new *sw; 1175 unsigned int idx; 1176 int err; 1177 1178 if (snd_BUG_ON(!chip || !chip->card)) 1179 return -EINVAL; 1180 1181 card = chip->card; 1182 1183 /* mixer reset */ 1184 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 1185 1186 /* mute and zero volume channels */ 1187 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) { 1188 snd_azf3328_mixer_outw(chip, 1189 snd_azf3328_init_values[idx][0], 1190 snd_azf3328_init_values[idx][1]); 1191 } 1192 1193 /* add mixer controls */ 1194 sw = snd_azf3328_mixer_controls; 1195 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); 1196 ++idx, ++sw) { 1197 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0) 1198 return err; 1199 } 1200 snd_component_add(card, "AZF3328 mixer"); 1201 strcpy(card->mixername, "AZF3328 mixer"); 1202 1203 return 0; 1204 } 1205 #endif /* AZF_USE_AC97_LAYER */ 1206 1207 static void 1208 snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec, 1209 enum azf_freq_t bitrate, 1210 unsigned int format_width, 1211 unsigned int channels 1212 ) 1213 { 1214 unsigned long flags; 1215 u16 val = 0xff00; 1216 u8 freq = 0; 1217 1218 switch (bitrate) { 1219 case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break; 1220 case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break; 1221 case AZF_FREQ_5512: 1222 /* the AZF3328 names it "5510" for some strange reason */ 1223 freq = SOUNDFORMAT_FREQ_5510; break; 1224 case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break; 1225 case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break; 1226 case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break; 1227 case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break; 1228 case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break; 1229 case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break; 1230 case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break; 1231 case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break; 1232 default: 1233 snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate); 1234 fallthrough; 1235 case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break; 1236 case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break; 1237 case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break; 1238 } 1239 /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */ 1240 /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */ 1241 /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */ 1242 /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */ 1243 /* val = 0xff05; 5m11.556s (... -> 44100Hz) */ 1244 /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */ 1245 /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */ 1246 /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */ 1247 /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */ 1248 1249 val |= freq; 1250 1251 if (channels == 2) 1252 val |= SOUNDFORMAT_FLAG_2CHANNELS; 1253 1254 if (format_width == 16) 1255 val |= SOUNDFORMAT_FLAG_16BIT; 1256 1257 spin_lock_irqsave(codec->lock, flags); 1258 1259 /* set bitrate/format */ 1260 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val); 1261 1262 /* changing the bitrate/format settings switches off the 1263 * audio output with an annoying click in case of 8/16bit format change 1264 * (maybe shutting down DAC/ADC?), thus immediately 1265 * do some tweaking to reenable it and get rid of the clicking 1266 * (FIXME: yes, it works, but what exactly am I doing here?? :) 1267 * FIXME: does this have some side effects for full-duplex 1268 * or other dramatic side effects? */ 1269 /* do it for non-capture codecs only */ 1270 if (codec->type != AZF_CODEC_CAPTURE) 1271 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1272 snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) | 1273 DMA_RUN_SOMETHING1 | 1274 DMA_RUN_SOMETHING2 | 1275 SOMETHING_ALMOST_ALWAYS_SET | 1276 DMA_EPILOGUE_SOMETHING | 1277 DMA_SOMETHING_ELSE 1278 ); 1279 1280 spin_unlock_irqrestore(codec->lock, flags); 1281 } 1282 1283 static inline void 1284 snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec 1285 ) 1286 { 1287 /* choose lowest frequency for low power consumption. 1288 * While this will cause louder noise due to rather coarse frequency, 1289 * it should never matter since output should always 1290 * get disabled properly when idle anyway. */ 1291 snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1); 1292 } 1293 1294 static void 1295 snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip, 1296 unsigned bitmask, 1297 bool enable 1298 ) 1299 { 1300 bool do_mask = !enable; 1301 if (do_mask) 1302 chip->shadow_reg_ctrl_6AH |= bitmask; 1303 else 1304 chip->shadow_reg_ctrl_6AH &= ~bitmask; 1305 dev_dbg(chip->card->dev, 1306 "6AH_update mask 0x%04x do_mask %d: val 0x%04x\n", 1307 bitmask, do_mask, chip->shadow_reg_ctrl_6AH); 1308 snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH); 1309 } 1310 1311 static inline void 1312 snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable) 1313 { 1314 dev_dbg(chip->card->dev, "codec_enable %d\n", enable); 1315 /* no idea what exactly is being done here, but I strongly assume it's 1316 * PM related */ 1317 snd_azf3328_ctrl_reg_6AH_update( 1318 chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable 1319 ); 1320 } 1321 1322 static void 1323 snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip, 1324 enum snd_azf3328_codec_type codec_type, 1325 bool enable 1326 ) 1327 { 1328 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; 1329 bool need_change = (codec->running != enable); 1330 1331 dev_dbg(chip->card->dev, 1332 "codec_activity: %s codec, enable %d, need_change %d\n", 1333 codec->name, enable, need_change 1334 ); 1335 if (need_change) { 1336 static const struct { 1337 enum snd_azf3328_codec_type other1; 1338 enum snd_azf3328_codec_type other2; 1339 } peer_codecs[3] = 1340 { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT }, 1341 { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT }, 1342 { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } }; 1343 bool call_function; 1344 1345 if (enable) 1346 /* if enable codec, call enable_codecs func 1347 to enable codec supply... */ 1348 call_function = 1; 1349 else { 1350 /* ...otherwise call enable_codecs func 1351 (which globally shuts down operation of codecs) 1352 only in case the other codecs are currently 1353 not active either! */ 1354 call_function = 1355 ((!chip->codecs[peer_codecs[codec_type].other1] 1356 .running) 1357 && (!chip->codecs[peer_codecs[codec_type].other2] 1358 .running)); 1359 } 1360 if (call_function) 1361 snd_azf3328_ctrl_enable_codecs(chip, enable); 1362 1363 /* ...and adjust clock, too 1364 * (reduce noise and power consumption) */ 1365 if (!enable) 1366 snd_azf3328_codec_setfmt_lowpower(codec); 1367 codec->running = enable; 1368 } 1369 } 1370 1371 static void 1372 snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip, 1373 struct snd_azf3328_codec_data *codec, 1374 unsigned long addr, 1375 unsigned int period_bytes, 1376 unsigned int buffer_bytes 1377 ) 1378 { 1379 WARN_ONCE(period_bytes & 1, "odd period length!?\n"); 1380 WARN_ONCE(buffer_bytes != 2 * period_bytes, 1381 "missed our input expectations! %u vs. %u\n", 1382 buffer_bytes, period_bytes); 1383 if (!codec->running) { 1384 /* AZF3328 uses a two buffer pointer DMA transfer approach */ 1385 1386 unsigned long flags; 1387 1388 /* width 32bit (prevent overflow): */ 1389 u32 area_length; 1390 struct codec_setup_io { 1391 u32 dma_start_1; 1392 u32 dma_start_2; 1393 u32 dma_lengths; 1394 } __attribute__((packed)) setup_io; 1395 1396 area_length = buffer_bytes/2; 1397 1398 setup_io.dma_start_1 = addr; 1399 setup_io.dma_start_2 = addr+area_length; 1400 1401 dev_dbg(chip->card->dev, 1402 "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n", 1403 setup_io.dma_start_1, area_length, 1404 setup_io.dma_start_2, area_length, 1405 period_bytes, buffer_bytes); 1406 1407 /* Hmm, are we really supposed to decrement this by 1?? 1408 Most definitely certainly not: configuring full length does 1409 work properly (i.e. likely better), and BTW we 1410 violated possibly differing frame sizes with this... 1411 1412 area_length--; |* max. index *| 1413 */ 1414 1415 /* build combined I/O buffer length word */ 1416 setup_io.dma_lengths = (area_length << 16) | (area_length); 1417 1418 spin_lock_irqsave(codec->lock, flags); 1419 snd_azf3328_codec_outl_multi( 1420 codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3 1421 ); 1422 spin_unlock_irqrestore(codec->lock, flags); 1423 } 1424 } 1425 1426 static int 1427 snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream) 1428 { 1429 struct snd_pcm_runtime *runtime = substream->runtime; 1430 struct snd_azf3328_codec_data *codec = runtime->private_data; 1431 #if 0 1432 unsigned int size = snd_pcm_lib_buffer_bytes(substream); 1433 unsigned int count = snd_pcm_lib_period_bytes(substream); 1434 #endif 1435 1436 codec->dma_base = runtime->dma_addr; 1437 1438 #if 0 1439 snd_azf3328_codec_setfmt(codec, 1440 runtime->rate, 1441 snd_pcm_format_width(runtime->format), 1442 runtime->channels); 1443 snd_azf3328_codec_setdmaa(chip, codec, 1444 runtime->dma_addr, count, size); 1445 #endif 1446 return 0; 1447 } 1448 1449 static int 1450 snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1451 { 1452 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1453 struct snd_pcm_runtime *runtime = substream->runtime; 1454 struct snd_azf3328_codec_data *codec = runtime->private_data; 1455 int result = 0; 1456 u16 flags1; 1457 bool previously_muted = false; 1458 bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type); 1459 1460 switch (cmd) { 1461 case SNDRV_PCM_TRIGGER_START: 1462 dev_dbg(chip->card->dev, "START PCM %s\n", codec->name); 1463 1464 if (is_main_mixer_playback_codec) { 1465 /* mute WaveOut (avoid clicking during setup) */ 1466 previously_muted = 1467 snd_azf3328_mixer_mute_control_pcm( 1468 chip, 1 1469 ); 1470 } 1471 1472 snd_azf3328_codec_setfmt(codec, 1473 runtime->rate, 1474 snd_pcm_format_width(runtime->format), 1475 runtime->channels); 1476 1477 spin_lock(codec->lock); 1478 /* first, remember current value: */ 1479 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); 1480 1481 /* stop transfer */ 1482 flags1 &= ~DMA_RESUME; 1483 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1484 1485 /* FIXME: clear interrupts or what??? */ 1486 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff); 1487 spin_unlock(codec->lock); 1488 1489 snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr, 1490 snd_pcm_lib_period_bytes(substream), 1491 snd_pcm_lib_buffer_bytes(substream) 1492 ); 1493 1494 spin_lock(codec->lock); 1495 #ifdef WIN9X 1496 /* FIXME: enable playback/recording??? */ 1497 flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2; 1498 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1499 1500 /* start transfer again */ 1501 /* FIXME: what is this value (0x0010)??? */ 1502 flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING; 1503 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1504 #else /* NT4 */ 1505 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1506 0x0000); 1507 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1508 DMA_RUN_SOMETHING1); 1509 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1510 DMA_RUN_SOMETHING1 | 1511 DMA_RUN_SOMETHING2); 1512 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1513 DMA_RESUME | 1514 SOMETHING_ALMOST_ALWAYS_SET | 1515 DMA_EPILOGUE_SOMETHING | 1516 DMA_SOMETHING_ELSE); 1517 #endif 1518 spin_unlock(codec->lock); 1519 snd_azf3328_ctrl_codec_activity(chip, codec->type, 1); 1520 1521 if (is_main_mixer_playback_codec) { 1522 /* now unmute WaveOut */ 1523 if (!previously_muted) 1524 snd_azf3328_mixer_mute_control_pcm( 1525 chip, 0 1526 ); 1527 } 1528 1529 dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name); 1530 break; 1531 case SNDRV_PCM_TRIGGER_RESUME: 1532 dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name); 1533 /* resume codec if we were active */ 1534 spin_lock(codec->lock); 1535 if (codec->running) 1536 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1537 snd_azf3328_codec_inw( 1538 codec, IDX_IO_CODEC_DMA_FLAGS 1539 ) | DMA_RESUME 1540 ); 1541 spin_unlock(codec->lock); 1542 break; 1543 case SNDRV_PCM_TRIGGER_STOP: 1544 dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name); 1545 1546 if (is_main_mixer_playback_codec) { 1547 /* mute WaveOut (avoid clicking during setup) */ 1548 previously_muted = 1549 snd_azf3328_mixer_mute_control_pcm( 1550 chip, 1 1551 ); 1552 } 1553 1554 spin_lock(codec->lock); 1555 /* first, remember current value: */ 1556 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); 1557 1558 /* stop transfer */ 1559 flags1 &= ~DMA_RESUME; 1560 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1561 1562 /* hmm, is this really required? we're resetting the same bit 1563 * immediately thereafter... */ 1564 flags1 |= DMA_RUN_SOMETHING1; 1565 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1566 1567 flags1 &= ~DMA_RUN_SOMETHING1; 1568 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1569 spin_unlock(codec->lock); 1570 snd_azf3328_ctrl_codec_activity(chip, codec->type, 0); 1571 1572 if (is_main_mixer_playback_codec) { 1573 /* now unmute WaveOut */ 1574 if (!previously_muted) 1575 snd_azf3328_mixer_mute_control_pcm( 1576 chip, 0 1577 ); 1578 } 1579 1580 dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name); 1581 break; 1582 case SNDRV_PCM_TRIGGER_SUSPEND: 1583 dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name); 1584 /* make sure codec is stopped */ 1585 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1586 snd_azf3328_codec_inw( 1587 codec, IDX_IO_CODEC_DMA_FLAGS 1588 ) & ~DMA_RESUME 1589 ); 1590 break; 1591 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1592 WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n"); 1593 break; 1594 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1595 WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n"); 1596 break; 1597 default: 1598 WARN(1, "FIXME: unknown trigger mode!\n"); 1599 return -EINVAL; 1600 } 1601 1602 return result; 1603 } 1604 1605 static snd_pcm_uframes_t 1606 snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream 1607 ) 1608 { 1609 const struct snd_azf3328_codec_data *codec = 1610 substream->runtime->private_data; 1611 unsigned long result; 1612 snd_pcm_uframes_t frmres; 1613 1614 result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS); 1615 1616 /* calculate offset */ 1617 #ifdef QUERY_HARDWARE 1618 result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1); 1619 #else 1620 result -= codec->dma_base; 1621 #endif 1622 frmres = bytes_to_frames( substream->runtime, result); 1623 dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n", 1624 jiffies, codec->name, result, frmres); 1625 return frmres; 1626 } 1627 1628 /******************************************************************/ 1629 1630 #ifdef SUPPORT_GAMEPORT 1631 static inline void 1632 snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip, 1633 bool enable 1634 ) 1635 { 1636 snd_azf3328_io_reg_setb( 1637 chip->game_io+IDX_GAME_HWCONFIG, 1638 GAME_HWCFG_IRQ_ENABLE, 1639 enable 1640 ); 1641 } 1642 1643 static inline void 1644 snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip, 1645 bool enable 1646 ) 1647 { 1648 snd_azf3328_io_reg_setb( 1649 chip->game_io+IDX_GAME_HWCONFIG, 1650 GAME_HWCFG_LEGACY_ADDRESS_ENABLE, 1651 enable 1652 ); 1653 } 1654 1655 static void 1656 snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip, 1657 unsigned int freq_cfg 1658 ) 1659 { 1660 snd_azf3328_io_reg_setb( 1661 chip->game_io+IDX_GAME_HWCONFIG, 1662 0x02, 1663 (freq_cfg & 1) != 0 1664 ); 1665 snd_azf3328_io_reg_setb( 1666 chip->game_io+IDX_GAME_HWCONFIG, 1667 0x04, 1668 (freq_cfg & 2) != 0 1669 ); 1670 } 1671 1672 static inline void 1673 snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable) 1674 { 1675 snd_azf3328_ctrl_reg_6AH_update( 1676 chip, IO_6A_SOMETHING2_GAMEPORT, enable 1677 ); 1678 } 1679 1680 static inline void 1681 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) 1682 { 1683 /* 1684 * skeleton handler only 1685 * (we do not want axis reading in interrupt handler - too much load!) 1686 */ 1687 dev_dbg(chip->card->dev, "gameport irq\n"); 1688 1689 /* this should ACK the gameport IRQ properly, hopefully. */ 1690 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE); 1691 } 1692 1693 static int 1694 snd_azf3328_gameport_open(struct gameport *gameport, int mode) 1695 { 1696 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1697 int res; 1698 1699 dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode); 1700 switch (mode) { 1701 case GAMEPORT_MODE_COOKED: 1702 case GAMEPORT_MODE_RAW: 1703 res = 0; 1704 break; 1705 default: 1706 res = -1; 1707 break; 1708 } 1709 1710 snd_azf3328_gameport_set_counter_frequency(chip, 1711 GAME_HWCFG_ADC_COUNTER_FREQ_STD); 1712 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0)); 1713 1714 return res; 1715 } 1716 1717 static void 1718 snd_azf3328_gameport_close(struct gameport *gameport) 1719 { 1720 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1721 1722 dev_dbg(chip->card->dev, "gameport_close\n"); 1723 snd_azf3328_gameport_set_counter_frequency(chip, 1724 GAME_HWCFG_ADC_COUNTER_FREQ_1_200); 1725 snd_azf3328_gameport_axis_circuit_enable(chip, 0); 1726 } 1727 1728 static int 1729 snd_azf3328_gameport_cooked_read(struct gameport *gameport, 1730 int *axes, 1731 int *buttons 1732 ) 1733 { 1734 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1735 int i; 1736 u8 val; 1737 unsigned long flags; 1738 1739 if (snd_BUG_ON(!chip)) 1740 return 0; 1741 1742 spin_lock_irqsave(&chip->reg_lock, flags); 1743 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE); 1744 *buttons = (~(val) >> 4) & 0xf; 1745 1746 /* ok, this one is a bit dirty: cooked_read is being polled by a timer, 1747 * thus we're atomic and cannot actively wait in here 1748 * (which would be useful for us since it probably would be better 1749 * to trigger a measurement in here, then wait a short amount of 1750 * time until it's finished, then read values of _this_ measurement). 1751 * 1752 * Thus we simply resort to reading values if they're available already 1753 * and trigger the next measurement. 1754 */ 1755 1756 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG); 1757 if (val & GAME_AXES_SAMPLING_READY) { 1758 for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) { 1759 /* configure the axis to read */ 1760 val = (i << 4) | 0x0f; 1761 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); 1762 1763 chip->axes[i] = snd_azf3328_game_inw( 1764 chip, IDX_GAME_AXIS_VALUE 1765 ); 1766 } 1767 } 1768 1769 /* trigger next sampling of axes, to be evaluated the next time we 1770 * enter this function */ 1771 1772 /* for some very, very strange reason we cannot enable 1773 * Measurement Ready monitoring for all axes here, 1774 * at least not when only one joystick connected */ 1775 val = 0x03; /* we're able to monitor axes 1 and 2 only */ 1776 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); 1777 1778 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff); 1779 spin_unlock_irqrestore(&chip->reg_lock, flags); 1780 1781 for (i = 0; i < ARRAY_SIZE(chip->axes); i++) { 1782 axes[i] = chip->axes[i]; 1783 if (axes[i] == 0xffff) 1784 axes[i] = -1; 1785 } 1786 1787 dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n", 1788 axes[0], axes[1], axes[2], axes[3], *buttons); 1789 1790 return 0; 1791 } 1792 1793 static int 1794 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) 1795 { 1796 struct gameport *gp; 1797 1798 chip->gameport = gp = gameport_allocate_port(); 1799 if (!gp) { 1800 dev_err(chip->card->dev, "cannot alloc memory for gameport\n"); 1801 return -ENOMEM; 1802 } 1803 1804 gameport_set_name(gp, "AZF3328 Gameport"); 1805 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1806 gameport_set_dev_parent(gp, &chip->pci->dev); 1807 gp->io = chip->game_io; 1808 gameport_set_port_data(gp, chip); 1809 1810 gp->open = snd_azf3328_gameport_open; 1811 gp->close = snd_azf3328_gameport_close; 1812 gp->fuzz = 16; /* seems ok */ 1813 gp->cooked_read = snd_azf3328_gameport_cooked_read; 1814 1815 /* DISABLE legacy address: we don't need it! */ 1816 snd_azf3328_gameport_legacy_address_enable(chip, 0); 1817 1818 snd_azf3328_gameport_set_counter_frequency(chip, 1819 GAME_HWCFG_ADC_COUNTER_FREQ_1_200); 1820 snd_azf3328_gameport_axis_circuit_enable(chip, 0); 1821 1822 gameport_register_port(chip->gameport); 1823 1824 return 0; 1825 } 1826 1827 static void 1828 snd_azf3328_gameport_free(struct snd_azf3328 *chip) 1829 { 1830 if (chip->gameport) { 1831 gameport_unregister_port(chip->gameport); 1832 chip->gameport = NULL; 1833 } 1834 snd_azf3328_gameport_irq_enable(chip, 0); 1835 } 1836 #else 1837 static inline int 1838 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; } 1839 static inline void 1840 snd_azf3328_gameport_free(struct snd_azf3328 *chip) { } 1841 static inline void 1842 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) 1843 { 1844 dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n"); 1845 } 1846 #endif /* SUPPORT_GAMEPORT */ 1847 1848 /******************************************************************/ 1849 1850 static inline void 1851 snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which) 1852 { 1853 dev_dbg(chip->card->dev, 1854 "unknown IRQ type (%x) occurred, please report!\n", 1855 which); 1856 } 1857 1858 static inline void 1859 snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip, 1860 const struct snd_azf3328_codec_data *first_codec, 1861 u8 status 1862 ) 1863 { 1864 u8 which; 1865 enum snd_azf3328_codec_type codec_type; 1866 const struct snd_azf3328_codec_data *codec = first_codec; 1867 1868 for (codec_type = AZF_CODEC_PLAYBACK; 1869 codec_type <= AZF_CODEC_I2S_OUT; 1870 ++codec_type, ++codec) { 1871 1872 /* skip codec if there's no interrupt for it */ 1873 if (!(status & (1 << codec_type))) 1874 continue; 1875 1876 spin_lock(codec->lock); 1877 which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE); 1878 /* ack all IRQ types immediately */ 1879 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which); 1880 spin_unlock(codec->lock); 1881 1882 if (codec->substream) { 1883 snd_pcm_period_elapsed(codec->substream); 1884 dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n", 1885 codec->name, 1886 which, 1887 snd_azf3328_codec_inl( 1888 codec, IDX_IO_CODEC_DMA_CURRPOS)); 1889 } else 1890 dev_warn(chip->card->dev, "irq handler problem!\n"); 1891 if (which & IRQ_SOMETHING) 1892 snd_azf3328_irq_log_unknown_type(chip, which); 1893 } 1894 } 1895 1896 static irqreturn_t 1897 snd_azf3328_interrupt(int irq, void *dev_id) 1898 { 1899 struct snd_azf3328 *chip = dev_id; 1900 u8 status; 1901 static unsigned long irq_count; 1902 1903 status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS); 1904 1905 /* fast path out, to ease interrupt sharing */ 1906 if (!(status & 1907 (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT 1908 |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER) 1909 )) 1910 return IRQ_NONE; /* must be interrupt for another device */ 1911 1912 dev_dbg(chip->card->dev, 1913 "irq_count %ld! IDX_IO_IRQSTATUS %04x\n", 1914 irq_count++ /* debug-only */, 1915 status); 1916 1917 if (status & IRQ_TIMER) { 1918 /* dev_dbg(chip->card->dev, "timer %ld\n", 1919 snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE) 1920 & TIMER_VALUE_MASK 1921 ); */ 1922 if (chip->timer) 1923 snd_timer_interrupt(chip->timer, chip->timer->sticks); 1924 /* ACK timer */ 1925 spin_lock(&chip->reg_lock); 1926 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07); 1927 spin_unlock(&chip->reg_lock); 1928 dev_dbg(chip->card->dev, "timer IRQ\n"); 1929 } 1930 1931 if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT)) 1932 snd_azf3328_pcm_interrupt(chip, chip->codecs, status); 1933 1934 if (status & IRQ_GAMEPORT) 1935 snd_azf3328_gameport_interrupt(chip); 1936 1937 /* MPU401 has less critical IRQ requirements 1938 * than timer and playback/recording, right? */ 1939 if (status & IRQ_MPU401) { 1940 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); 1941 1942 /* hmm, do we have to ack the IRQ here somehow? 1943 * If so, then I don't know how yet... */ 1944 dev_dbg(chip->card->dev, "MPU401 IRQ\n"); 1945 } 1946 return IRQ_HANDLED; 1947 } 1948 1949 /*****************************************************************/ 1950 1951 /* as long as we think we have identical snd_pcm_hardware parameters 1952 for playback, capture and i2s out, we can use the same physical struct 1953 since the struct is simply being copied into a member. 1954 */ 1955 static const struct snd_pcm_hardware snd_azf3328_hardware = 1956 { 1957 /* FIXME!! Correct? */ 1958 .info = SNDRV_PCM_INFO_MMAP | 1959 SNDRV_PCM_INFO_INTERLEAVED | 1960 SNDRV_PCM_INFO_MMAP_VALID, 1961 .formats = SNDRV_PCM_FMTBIT_S8 | 1962 SNDRV_PCM_FMTBIT_U8 | 1963 SNDRV_PCM_FMTBIT_S16_LE | 1964 SNDRV_PCM_FMTBIT_U16_LE, 1965 .rates = SNDRV_PCM_RATE_5512 | 1966 SNDRV_PCM_RATE_8000_48000 | 1967 SNDRV_PCM_RATE_KNOT, 1968 .rate_min = AZF_FREQ_4000, 1969 .rate_max = AZF_FREQ_66200, 1970 .channels_min = 1, 1971 .channels_max = 2, 1972 .buffer_bytes_max = (64*1024), 1973 .period_bytes_min = 1024, 1974 .period_bytes_max = (32*1024), 1975 /* We simply have two DMA areas (instead of a list of descriptors 1976 such as other cards); I believe that this is a fixed hardware 1977 attribute and there isn't much driver magic to be done to expand it. 1978 Thus indicate that we have at least and at most 2 periods. */ 1979 .periods_min = 2, 1980 .periods_max = 2, 1981 /* FIXME: maybe that card actually has a FIFO? 1982 * Hmm, it seems newer revisions do have one, but we still don't know 1983 * its size... */ 1984 .fifo_size = 0, 1985 }; 1986 1987 1988 static const unsigned int snd_azf3328_fixed_rates[] = { 1989 AZF_FREQ_4000, 1990 AZF_FREQ_4800, 1991 AZF_FREQ_5512, 1992 AZF_FREQ_6620, 1993 AZF_FREQ_8000, 1994 AZF_FREQ_9600, 1995 AZF_FREQ_11025, 1996 AZF_FREQ_13240, 1997 AZF_FREQ_16000, 1998 AZF_FREQ_22050, 1999 AZF_FREQ_32000, 2000 AZF_FREQ_44100, 2001 AZF_FREQ_48000, 2002 AZF_FREQ_66200 2003 }; 2004 2005 static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = { 2006 .count = ARRAY_SIZE(snd_azf3328_fixed_rates), 2007 .list = snd_azf3328_fixed_rates, 2008 .mask = 0, 2009 }; 2010 2011 /*****************************************************************/ 2012 2013 static int 2014 snd_azf3328_pcm_open(struct snd_pcm_substream *substream, 2015 enum snd_azf3328_codec_type codec_type 2016 ) 2017 { 2018 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 2019 struct snd_pcm_runtime *runtime = substream->runtime; 2020 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; 2021 2022 codec->substream = substream; 2023 2024 /* same parameters for all our codecs - at least we think so... */ 2025 runtime->hw = snd_azf3328_hardware; 2026 2027 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 2028 &snd_azf3328_hw_constraints_rates); 2029 runtime->private_data = codec; 2030 return 0; 2031 } 2032 2033 static int 2034 snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream) 2035 { 2036 return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK); 2037 } 2038 2039 static int 2040 snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream) 2041 { 2042 return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE); 2043 } 2044 2045 static int 2046 snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream) 2047 { 2048 return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT); 2049 } 2050 2051 static int 2052 snd_azf3328_pcm_close(struct snd_pcm_substream *substream 2053 ) 2054 { 2055 struct snd_azf3328_codec_data *codec = 2056 substream->runtime->private_data; 2057 2058 codec->substream = NULL; 2059 return 0; 2060 } 2061 2062 /******************************************************************/ 2063 2064 static const struct snd_pcm_ops snd_azf3328_playback_ops = { 2065 .open = snd_azf3328_pcm_playback_open, 2066 .close = snd_azf3328_pcm_close, 2067 .prepare = snd_azf3328_pcm_prepare, 2068 .trigger = snd_azf3328_pcm_trigger, 2069 .pointer = snd_azf3328_pcm_pointer 2070 }; 2071 2072 static const struct snd_pcm_ops snd_azf3328_capture_ops = { 2073 .open = snd_azf3328_pcm_capture_open, 2074 .close = snd_azf3328_pcm_close, 2075 .prepare = snd_azf3328_pcm_prepare, 2076 .trigger = snd_azf3328_pcm_trigger, 2077 .pointer = snd_azf3328_pcm_pointer 2078 }; 2079 2080 static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = { 2081 .open = snd_azf3328_pcm_i2s_out_open, 2082 .close = snd_azf3328_pcm_close, 2083 .prepare = snd_azf3328_pcm_prepare, 2084 .trigger = snd_azf3328_pcm_trigger, 2085 .pointer = snd_azf3328_pcm_pointer 2086 }; 2087 2088 static int 2089 snd_azf3328_pcm(struct snd_azf3328 *chip) 2090 { 2091 /* pcm devices */ 2092 enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS }; 2093 2094 struct snd_pcm *pcm; 2095 int err; 2096 2097 err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD, 2098 1, 1, &pcm); 2099 if (err < 0) 2100 return err; 2101 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 2102 &snd_azf3328_playback_ops); 2103 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 2104 &snd_azf3328_capture_ops); 2105 2106 pcm->private_data = chip; 2107 pcm->info_flags = 0; 2108 strcpy(pcm->name, chip->card->shortname); 2109 /* same pcm object for playback/capture (see snd_pcm_new() above) */ 2110 chip->pcm[AZF_CODEC_PLAYBACK] = pcm; 2111 chip->pcm[AZF_CODEC_CAPTURE] = pcm; 2112 2113 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 2114 64*1024, 64*1024); 2115 2116 err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT, 2117 1, 0, &pcm); 2118 if (err < 0) 2119 return err; 2120 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 2121 &snd_azf3328_i2s_out_ops); 2122 2123 pcm->private_data = chip; 2124 pcm->info_flags = 0; 2125 strcpy(pcm->name, chip->card->shortname); 2126 chip->pcm[AZF_CODEC_I2S_OUT] = pcm; 2127 2128 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 2129 64*1024, 64*1024); 2130 2131 return 0; 2132 } 2133 2134 /******************************************************************/ 2135 2136 /*** NOTE: the physical timer resolution actually is 1024000 ticks per second 2137 *** (probably derived from main crystal via a divider of 24), 2138 *** but announcing those attributes to user-space would make programs 2139 *** configure the timer to a 1 tick value, resulting in an absolutely fatal 2140 *** timer IRQ storm. 2141 *** Thus I chose to announce a down-scaled virtual timer to the outside and 2142 *** calculate real timer countdown values internally. 2143 *** (the scale factor can be set via module parameter "seqtimer_scaling"). 2144 ***/ 2145 2146 static int 2147 snd_azf3328_timer_start(struct snd_timer *timer) 2148 { 2149 struct snd_azf3328 *chip; 2150 unsigned long flags; 2151 unsigned int delay; 2152 2153 chip = snd_timer_chip(timer); 2154 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK; 2155 if (delay < 49) { 2156 /* uhoh, that's not good, since user-space won't know about 2157 * this timing tweak 2158 * (we need to do it to avoid a lockup, though) */ 2159 2160 dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay); 2161 delay = 49; /* minimum time is 49 ticks */ 2162 } 2163 dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay); 2164 delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE; 2165 spin_lock_irqsave(&chip->reg_lock, flags); 2166 snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay); 2167 spin_unlock_irqrestore(&chip->reg_lock, flags); 2168 return 0; 2169 } 2170 2171 static int 2172 snd_azf3328_timer_stop(struct snd_timer *timer) 2173 { 2174 struct snd_azf3328 *chip; 2175 unsigned long flags; 2176 2177 chip = snd_timer_chip(timer); 2178 spin_lock_irqsave(&chip->reg_lock, flags); 2179 /* disable timer countdown and interrupt */ 2180 /* Hmm, should we write TIMER_IRQ_ACK here? 2181 YES indeed, otherwise a rogue timer operation - which prompts 2182 ALSA(?) to call repeated stop() in vain, but NOT start() - 2183 will never end (value 0x03 is kept shown in control byte). 2184 Simply manually poking 0x04 _once_ immediately successfully stops 2185 the hardware/ALSA interrupt activity. */ 2186 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04); 2187 spin_unlock_irqrestore(&chip->reg_lock, flags); 2188 return 0; 2189 } 2190 2191 2192 static int 2193 snd_azf3328_timer_precise_resolution(struct snd_timer *timer, 2194 unsigned long *num, unsigned long *den) 2195 { 2196 *num = 1; 2197 *den = 1024000 / seqtimer_scaling; 2198 return 0; 2199 } 2200 2201 static struct snd_timer_hardware snd_azf3328_timer_hw = { 2202 .flags = SNDRV_TIMER_HW_AUTO, 2203 .resolution = 977, /* 1000000/1024000 = 0.9765625us */ 2204 .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */ 2205 .start = snd_azf3328_timer_start, 2206 .stop = snd_azf3328_timer_stop, 2207 .precise_resolution = snd_azf3328_timer_precise_resolution, 2208 }; 2209 2210 static int 2211 snd_azf3328_timer(struct snd_azf3328 *chip, int device) 2212 { 2213 struct snd_timer *timer = NULL; 2214 struct snd_timer_id tid; 2215 int err; 2216 2217 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 2218 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 2219 tid.card = chip->card->number; 2220 tid.device = device; 2221 tid.subdevice = 0; 2222 2223 snd_azf3328_timer_hw.resolution *= seqtimer_scaling; 2224 snd_azf3328_timer_hw.ticks /= seqtimer_scaling; 2225 2226 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer); 2227 if (err < 0) 2228 goto out; 2229 2230 strcpy(timer->name, "AZF3328 timer"); 2231 timer->private_data = chip; 2232 timer->hw = snd_azf3328_timer_hw; 2233 2234 chip->timer = timer; 2235 2236 snd_azf3328_timer_stop(timer); 2237 2238 err = 0; 2239 2240 out: 2241 return err; 2242 } 2243 2244 /******************************************************************/ 2245 2246 static int 2247 snd_azf3328_free(struct snd_azf3328 *chip) 2248 { 2249 if (chip->irq < 0) 2250 goto __end_hw; 2251 2252 snd_azf3328_mixer_reset(chip); 2253 2254 snd_azf3328_timer_stop(chip->timer); 2255 snd_azf3328_gameport_free(chip); 2256 2257 __end_hw: 2258 if (chip->irq >= 0) 2259 free_irq(chip->irq, chip); 2260 pci_release_regions(chip->pci); 2261 pci_disable_device(chip->pci); 2262 2263 kfree(chip); 2264 return 0; 2265 } 2266 2267 static int 2268 snd_azf3328_dev_free(struct snd_device *device) 2269 { 2270 struct snd_azf3328 *chip = device->device_data; 2271 return snd_azf3328_free(chip); 2272 } 2273 2274 #if 0 2275 /* check whether a bit can be modified */ 2276 static void 2277 snd_azf3328_test_bit(unsigned unsigned reg, int bit) 2278 { 2279 unsigned char val, valoff, valon; 2280 2281 val = inb(reg); 2282 2283 outb(val & ~(1 << bit), reg); 2284 valoff = inb(reg); 2285 2286 outb(val|(1 << bit), reg); 2287 valon = inb(reg); 2288 2289 outb(val, reg); 2290 2291 printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n", 2292 reg, bit, val, valoff, valon 2293 ); 2294 } 2295 #endif 2296 2297 static inline void 2298 snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) 2299 { 2300 u16 tmp; 2301 2302 dev_dbg(chip->card->dev, 2303 "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, " 2304 "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n", 2305 chip->ctrl_io, chip->game_io, chip->mpu_io, 2306 chip->opl3_io, chip->mixer_io, chip->irq); 2307 2308 dev_dbg(chip->card->dev, 2309 "game %02x %02x %02x %02x %02x %02x\n", 2310 snd_azf3328_game_inb(chip, 0), 2311 snd_azf3328_game_inb(chip, 1), 2312 snd_azf3328_game_inb(chip, 2), 2313 snd_azf3328_game_inb(chip, 3), 2314 snd_azf3328_game_inb(chip, 4), 2315 snd_azf3328_game_inb(chip, 5)); 2316 2317 for (tmp = 0; tmp < 0x07; tmp += 1) 2318 dev_dbg(chip->card->dev, 2319 "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp)); 2320 2321 for (tmp = 0; tmp <= 0x07; tmp += 1) 2322 dev_dbg(chip->card->dev, 2323 "0x%02x: game200 0x%04x, game208 0x%04x\n", 2324 tmp, inb(0x200 + tmp), inb(0x208 + tmp)); 2325 2326 for (tmp = 0; tmp <= 0x01; tmp += 1) 2327 dev_dbg(chip->card->dev, 2328 "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, " 2329 "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n", 2330 tmp, 2331 inb(0x300 + tmp), 2332 inb(0x310 + tmp), 2333 inb(0x320 + tmp), 2334 inb(0x330 + tmp), 2335 inb(0x388 + tmp), 2336 inb(0x38c + tmp)); 2337 2338 for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2) 2339 dev_dbg(chip->card->dev, 2340 "ctrl 0x%02x: 0x%04x\n", 2341 tmp, snd_azf3328_ctrl_inw(chip, tmp)); 2342 2343 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2) 2344 dev_dbg(chip->card->dev, 2345 "mixer 0x%02x: 0x%04x\n", 2346 tmp, snd_azf3328_mixer_inw(chip, tmp)); 2347 } 2348 2349 static int 2350 snd_azf3328_create(struct snd_card *card, 2351 struct pci_dev *pci, 2352 unsigned long device_type, 2353 struct snd_azf3328 **rchip) 2354 { 2355 struct snd_azf3328 *chip; 2356 int err; 2357 static const struct snd_device_ops ops = { 2358 .dev_free = snd_azf3328_dev_free, 2359 }; 2360 u8 dma_init; 2361 enum snd_azf3328_codec_type codec_type; 2362 struct snd_azf3328_codec_data *codec_setup; 2363 2364 *rchip = NULL; 2365 2366 err = pci_enable_device(pci); 2367 if (err < 0) 2368 return err; 2369 2370 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2371 if (chip == NULL) { 2372 err = -ENOMEM; 2373 goto out_err; 2374 } 2375 spin_lock_init(&chip->reg_lock); 2376 chip->card = card; 2377 chip->pci = pci; 2378 chip->irq = -1; 2379 2380 /* check if we can restrict PCI DMA transfers to 24 bits */ 2381 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) { 2382 dev_err(card->dev, 2383 "architecture does not support 24bit PCI busmaster DMA\n" 2384 ); 2385 err = -ENXIO; 2386 goto out_err; 2387 } 2388 2389 err = pci_request_regions(pci, "Aztech AZF3328"); 2390 if (err < 0) 2391 goto out_err; 2392 2393 chip->ctrl_io = pci_resource_start(pci, 0); 2394 chip->game_io = pci_resource_start(pci, 1); 2395 chip->mpu_io = pci_resource_start(pci, 2); 2396 chip->opl3_io = pci_resource_start(pci, 3); 2397 chip->mixer_io = pci_resource_start(pci, 4); 2398 2399 codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK]; 2400 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK; 2401 codec_setup->lock = &chip->reg_lock; 2402 codec_setup->type = AZF_CODEC_PLAYBACK; 2403 codec_setup->name = "PLAYBACK"; 2404 2405 codec_setup = &chip->codecs[AZF_CODEC_CAPTURE]; 2406 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE; 2407 codec_setup->lock = &chip->reg_lock; 2408 codec_setup->type = AZF_CODEC_CAPTURE; 2409 codec_setup->name = "CAPTURE"; 2410 2411 codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT]; 2412 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT; 2413 codec_setup->lock = &chip->reg_lock; 2414 codec_setup->type = AZF_CODEC_I2S_OUT; 2415 codec_setup->name = "I2S_OUT"; 2416 2417 if (request_irq(pci->irq, snd_azf3328_interrupt, 2418 IRQF_SHARED, KBUILD_MODNAME, chip)) { 2419 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 2420 err = -EBUSY; 2421 goto out_err; 2422 } 2423 chip->irq = pci->irq; 2424 card->sync_irq = chip->irq; 2425 pci_set_master(pci); 2426 2427 snd_azf3328_debug_show_ports(chip); 2428 2429 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 2430 if (err < 0) 2431 goto out_err; 2432 2433 /* create mixer interface & switches */ 2434 err = snd_azf3328_mixer_new(chip); 2435 if (err < 0) 2436 goto out_err; 2437 2438 /* standard codec init stuff */ 2439 /* default DMA init value */ 2440 dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE; 2441 2442 for (codec_type = AZF_CODEC_PLAYBACK; 2443 codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) { 2444 struct snd_azf3328_codec_data *codec = 2445 &chip->codecs[codec_type]; 2446 2447 /* shutdown codecs to reduce power / noise */ 2448 /* have ...ctrl_codec_activity() act properly */ 2449 codec->running = true; 2450 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0); 2451 2452 spin_lock_irq(codec->lock); 2453 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS, 2454 dma_init); 2455 spin_unlock_irq(codec->lock); 2456 } 2457 2458 *rchip = chip; 2459 2460 err = 0; 2461 goto out; 2462 2463 out_err: 2464 if (chip) 2465 snd_azf3328_free(chip); 2466 pci_disable_device(pci); 2467 2468 out: 2469 return err; 2470 } 2471 2472 static int 2473 snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2474 { 2475 static int dev; 2476 struct snd_card *card; 2477 struct snd_azf3328 *chip; 2478 struct snd_opl3 *opl3; 2479 int err; 2480 2481 if (dev >= SNDRV_CARDS) { 2482 err = -ENODEV; 2483 goto out; 2484 } 2485 if (!enable[dev]) { 2486 dev++; 2487 err = -ENOENT; 2488 goto out; 2489 } 2490 2491 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2492 0, &card); 2493 if (err < 0) 2494 goto out; 2495 2496 strcpy(card->driver, "AZF3328"); 2497 strcpy(card->shortname, "Aztech AZF3328 (PCI168)"); 2498 2499 err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip); 2500 if (err < 0) 2501 goto out_err; 2502 2503 card->private_data = chip; 2504 2505 /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401, 2506 since our hardware ought to be similar, thus use same ID. */ 2507 err = snd_mpu401_uart_new( 2508 card, 0, 2509 MPU401_HW_AZT2320, chip->mpu_io, 2510 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, 2511 -1, &chip->rmidi 2512 ); 2513 if (err < 0) { 2514 dev_err(card->dev, "no MPU-401 device at 0x%lx?\n", 2515 chip->mpu_io 2516 ); 2517 goto out_err; 2518 } 2519 2520 err = snd_azf3328_timer(chip, 0); 2521 if (err < 0) 2522 goto out_err; 2523 2524 err = snd_azf3328_pcm(chip); 2525 if (err < 0) 2526 goto out_err; 2527 2528 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2, 2529 OPL3_HW_AUTO, 1, &opl3) < 0) { 2530 dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n", 2531 chip->opl3_io, chip->opl3_io+2 2532 ); 2533 } else { 2534 /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */ 2535 err = snd_opl3_timer_new(opl3, 1, 2); 2536 if (err < 0) 2537 goto out_err; 2538 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); 2539 if (err < 0) 2540 goto out_err; 2541 opl3->private_data = chip; 2542 } 2543 2544 sprintf(card->longname, "%s at 0x%lx, irq %i", 2545 card->shortname, chip->ctrl_io, chip->irq); 2546 2547 err = snd_card_register(card); 2548 if (err < 0) 2549 goto out_err; 2550 2551 #ifdef MODULE 2552 dev_info(card->dev, 2553 "Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"); 2554 dev_info(card->dev, 2555 "Hardware was completely undocumented, unfortunately.\n"); 2556 dev_info(card->dev, 2557 "Feel free to contact andi AT lisas.de for bug reports etc.!\n"); 2558 dev_info(card->dev, 2559 "User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n", 2560 1024000 / seqtimer_scaling, seqtimer_scaling); 2561 #endif 2562 2563 snd_azf3328_gameport(chip, dev); 2564 2565 pci_set_drvdata(pci, card); 2566 dev++; 2567 2568 err = 0; 2569 goto out; 2570 2571 out_err: 2572 dev_err(card->dev, "something failed, exiting\n"); 2573 snd_card_free(card); 2574 2575 out: 2576 return err; 2577 } 2578 2579 static void 2580 snd_azf3328_remove(struct pci_dev *pci) 2581 { 2582 snd_card_free(pci_get_drvdata(pci)); 2583 } 2584 2585 #ifdef CONFIG_PM_SLEEP 2586 static inline void 2587 snd_azf3328_suspend_regs(const struct snd_azf3328 *chip, 2588 unsigned long io_addr, unsigned count, u32 *saved_regs) 2589 { 2590 unsigned reg; 2591 2592 for (reg = 0; reg < count; ++reg) { 2593 *saved_regs = inl(io_addr); 2594 dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n", 2595 io_addr, *saved_regs); 2596 ++saved_regs; 2597 io_addr += sizeof(*saved_regs); 2598 } 2599 } 2600 2601 static inline void 2602 snd_azf3328_resume_regs(const struct snd_azf3328 *chip, 2603 const u32 *saved_regs, 2604 unsigned long io_addr, 2605 unsigned count 2606 ) 2607 { 2608 unsigned reg; 2609 2610 for (reg = 0; reg < count; ++reg) { 2611 outl(*saved_regs, io_addr); 2612 dev_dbg(chip->card->dev, 2613 "resume: io 0x%04lx: 0x%08x --> 0x%08x\n", 2614 io_addr, *saved_regs, inl(io_addr)); 2615 ++saved_regs; 2616 io_addr += sizeof(*saved_regs); 2617 } 2618 } 2619 2620 static inline void 2621 snd_azf3328_suspend_ac97(struct snd_azf3328 *chip) 2622 { 2623 #ifdef AZF_USE_AC97_LAYER 2624 snd_ac97_suspend(chip->ac97); 2625 #else 2626 snd_azf3328_suspend_regs(chip, chip->mixer_io, 2627 ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer); 2628 2629 /* make sure to disable master volume etc. to prevent looping sound */ 2630 snd_azf3328_mixer_mute_control_master(chip, 1); 2631 snd_azf3328_mixer_mute_control_pcm(chip, 1); 2632 #endif /* AZF_USE_AC97_LAYER */ 2633 } 2634 2635 static inline void 2636 snd_azf3328_resume_ac97(const struct snd_azf3328 *chip) 2637 { 2638 #ifdef AZF_USE_AC97_LAYER 2639 snd_ac97_resume(chip->ac97); 2640 #else 2641 snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io, 2642 ARRAY_SIZE(chip->saved_regs_mixer)); 2643 2644 /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02) 2645 and IDX_MIXER_RESET (offset 0x00) get touched at the same time, 2646 resulting in a mixer reset condition persisting until _after_ 2647 master vol was restored. Thus master vol needs an extra restore. */ 2648 outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2); 2649 #endif /* AZF_USE_AC97_LAYER */ 2650 } 2651 2652 static int 2653 snd_azf3328_suspend(struct device *dev) 2654 { 2655 struct snd_card *card = dev_get_drvdata(dev); 2656 struct snd_azf3328 *chip = card->private_data; 2657 u16 *saved_regs_ctrl_u16; 2658 2659 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2660 2661 snd_azf3328_suspend_ac97(chip); 2662 2663 snd_azf3328_suspend_regs(chip, chip->ctrl_io, 2664 ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl); 2665 2666 /* manually store the one currently relevant write-only reg, too */ 2667 saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl; 2668 saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH; 2669 2670 snd_azf3328_suspend_regs(chip, chip->game_io, 2671 ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game); 2672 snd_azf3328_suspend_regs(chip, chip->mpu_io, 2673 ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu); 2674 snd_azf3328_suspend_regs(chip, chip->opl3_io, 2675 ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3); 2676 return 0; 2677 } 2678 2679 static int 2680 snd_azf3328_resume(struct device *dev) 2681 { 2682 struct snd_card *card = dev_get_drvdata(dev); 2683 const struct snd_azf3328 *chip = card->private_data; 2684 2685 snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io, 2686 ARRAY_SIZE(chip->saved_regs_game)); 2687 snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io, 2688 ARRAY_SIZE(chip->saved_regs_mpu)); 2689 snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io, 2690 ARRAY_SIZE(chip->saved_regs_opl3)); 2691 2692 snd_azf3328_resume_ac97(chip); 2693 2694 snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io, 2695 ARRAY_SIZE(chip->saved_regs_ctrl)); 2696 2697 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2698 return 0; 2699 } 2700 2701 static SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume); 2702 #define SND_AZF3328_PM_OPS &snd_azf3328_pm 2703 #else 2704 #define SND_AZF3328_PM_OPS NULL 2705 #endif /* CONFIG_PM_SLEEP */ 2706 2707 static struct pci_driver azf3328_driver = { 2708 .name = KBUILD_MODNAME, 2709 .id_table = snd_azf3328_ids, 2710 .probe = snd_azf3328_probe, 2711 .remove = snd_azf3328_remove, 2712 .driver = { 2713 .pm = SND_AZF3328_PM_OPS, 2714 }, 2715 }; 2716 2717 module_pci_driver(azf3328_driver); 2718