1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License as published by 4 * the Free Software Foundation; either version 2 of the License, or 5 * (at your option) any later version. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU Library General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 15 */ 16 17 /* 18 Vortex core low level functions. 19 20 Author: Manuel Jander (mjander@users.sourceforge.cl) 21 These functions are mainly the result of translations made 22 from the original disassembly of the au88x0 binary drivers, 23 written by Aureal before they went down. 24 Many thanks to the Jeff Muizelaar, Kester Maddock, and whoever 25 contributed to the OpenVortex project. 26 The author of this file, put the few available pieces together 27 and translated the rest of the riddle (Mix, Src and connection stuff). 28 Some things are still to be discovered, and their meanings are unclear. 29 30 Some of these functions aren't intended to be really used, rather 31 to help to understand how does the AU88X0 chips work. Keep them in, because 32 they could be used somewhere in the future. 33 34 This code hasn't been tested or proof read thoroughly. If you wanna help, 35 take a look at the AU88X0 assembly and check if this matches. 36 Functions tested ok so far are (they show the desired effect 37 at least): 38 vortex_routes(); (1 bug fixed). 39 vortex_adb_addroute(); 40 vortex_adb_addroutes(); 41 vortex_connect_codecplay(); 42 vortex_src_flushbuffers(); 43 vortex_adbdma_setmode(); note: still some unknown arguments! 44 vortex_adbdma_startfifo(); 45 vortex_adbdma_stopfifo(); 46 vortex_fifo_setadbctrl(); note: still some unknown arguments! 47 vortex_mix_setinputvolumebyte(); 48 vortex_mix_enableinput(); 49 vortex_mixer_addWTD(); (fixed) 50 vortex_connection_adbdma_src_src(); 51 vortex_connection_adbdma_src(); 52 vortex_src_change_convratio(); 53 vortex_src_addWTD(); (fixed) 54 55 History: 56 57 01-03-2003 First revision. 58 01-21-2003 Some bug fixes. 59 17-02-2003 many bugfixes after a big versioning mess. 60 18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy ! 61 (2 hours later...) I cant believe it! Im really lucky today. 62 Now the SRC is working too! Yeah! XMMS works ! 63 20-02-2003 First steps into the ALSA world. 64 28-02-2003 As my birthday present, i discovered how the DMA buffer pages really 65 work :-). It was all wrong. 66 12-03-2003 ALSA driver starts working (2 channels). 67 16-03-2003 More srcblock_setupchannel discoveries. 68 12-04-2003 AU8830 playback support. Recording in the works. 69 17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording 70 works now, but chipn' dale effect is still there. 71 16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely 72 into au88x0_pcm.c . 73 06-06-2003 Buffer shifter bugfix. Mixer volume fix. 74 07-12-2003 A3D routing finally fixed. Believed to be OK. 75 25-03-2004 Many thanks to Claudia, for such valuable bug reports. 76 77 */ 78 79 #include "au88x0.h" 80 #include "au88x0_a3d.h" 81 #include <linux/delay.h> 82 83 /* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */ 84 85 // FIXME: get rid of this. 86 static int mchannels[NR_MIXIN]; 87 static int rampchs[NR_MIXIN]; 88 89 static void vortex_mixer_en_sr(vortex_t * vortex, int channel) 90 { 91 hwwrite(vortex->mmio, VORTEX_MIXER_SR, 92 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); 93 } 94 static void vortex_mixer_dis_sr(vortex_t * vortex, int channel) 95 { 96 hwwrite(vortex->mmio, VORTEX_MIXER_SR, 97 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); 98 } 99 100 #if 0 101 static void 102 vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix, 103 unsigned char channel) 104 { 105 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel), 106 0x80); 107 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel), 108 0x80); 109 } 110 111 static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix) 112 { 113 int a; 114 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff; 115 //FP2LinearFrac(a); 116 return (a); 117 } 118 119 static int 120 vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix, 121 int channel, int *vol) 122 { 123 int a; 124 if (!(mchannels[mix] & (1 << channel))) 125 return 0; 126 a = hwread(vortex->mmio, 127 VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2)); 128 /* 129 if (rampchs[mix] == 0) 130 a = FP2LinearFrac(a); 131 else 132 a = FP2LinearFracWT(a); 133 */ 134 *vol = a; 135 return (0); 136 } 137 138 static unsigned int vortex_mix_boost6db(unsigned char vol) 139 { 140 return (vol + 8); /* WOW! what a complex function! */ 141 } 142 143 static void vortex_mix_rampvolume(vortex_t * vortex, int mix) 144 { 145 int ch; 146 char a; 147 // This function is intended for ramping down only (see vortex_disableinput()). 148 for (ch = 0; ch < 0x20; ch++) { 149 if (((1 << ch) & rampchs[mix]) == 0) 150 continue; 151 a = hwread(vortex->mmio, 152 VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2)); 153 if (a > -126) { 154 a -= 2; 155 hwwrite(vortex->mmio, 156 VORTEX_MIX_INVOL_A + 157 (((mix << 5) + ch) << 2), a); 158 hwwrite(vortex->mmio, 159 VORTEX_MIX_INVOL_B + 160 (((mix << 5) + ch) << 2), a); 161 } else 162 vortex_mix_killinput(vortex, mix, ch); 163 } 164 } 165 166 static int 167 vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin) 168 { 169 int addr, temp; 170 if (mixin >= 0) 171 addr = mixin; 172 else 173 addr = mixin + 3; 174 addr = ((mix << 3) + (addr >> 2)) << 2; 175 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr); 176 return ((temp >> (mixin & 3)) & 1); 177 } 178 #endif 179 static void 180 vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix, 181 unsigned char vol) 182 { 183 int temp; 184 hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol); 185 if (1) { /*if (this_10) */ 186 temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2)); 187 if ((temp != 0x80) || (vol == 0x80)) 188 return; 189 } 190 hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol); 191 } 192 193 static void 194 vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix, 195 int mixin, unsigned char vol) 196 { 197 int temp; 198 199 hwwrite(vortex->mmio, 200 VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol); 201 if (1) { /* this_10, initialized to 1. */ 202 temp = 203 hwread(vortex->mmio, 204 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2)); 205 if ((temp != 0x80) || (vol == 0x80)) 206 return; 207 } 208 hwwrite(vortex->mmio, 209 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol); 210 } 211 212 static void 213 vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en) 214 { 215 int temp, addr; 216 217 if (mixin < 0) 218 addr = (mixin + 3); 219 else 220 addr = mixin; 221 addr = ((mix << 3) + (addr >> 2)) << 2; 222 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr); 223 if (en) 224 temp |= (1 << (mixin & 3)); 225 else 226 temp &= ~(1 << (mixin & 3)); 227 /* Mute input. Astatic void crackling? */ 228 hwwrite(vortex->mmio, 229 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80); 230 /* Looks like clear buffer. */ 231 hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0); 232 hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0); 233 /* Write enable bit. */ 234 hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp); 235 } 236 237 static void 238 vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin) 239 { 240 rampchs[mix] &= ~(1 << mixin); 241 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); 242 mchannels[mix] &= ~(1 << mixin); 243 vortex_mix_setenablebit(vortex, mix, mixin, 0); 244 } 245 246 static void 247 vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin) 248 { 249 vortex_mix_killinput(vortex, mix, mixin); 250 if ((mchannels[mix] & (1 << mixin)) == 0) { 251 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); /*0x80 : mute */ 252 mchannels[mix] |= (1 << mixin); 253 } 254 vortex_mix_setenablebit(vortex, mix, mixin, 1); 255 } 256 257 static void 258 vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel, 259 int ramp) 260 { 261 if (ramp) { 262 rampchs[mix] |= (1 << channel); 263 // Register callback. 264 //vortex_mix_startrampvolume(vortex); 265 vortex_mix_killinput(vortex, mix, channel); 266 } else 267 vortex_mix_killinput(vortex, mix, channel); 268 } 269 270 static int 271 vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch) 272 { 273 int temp, lifeboat = 0, prev; 274 275 temp = hwread(vortex->mmio, VORTEX_MIXER_SR); 276 if ((temp & (1 << ch)) == 0) { 277 hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix); 278 vortex_mixer_en_sr(vortex, ch); 279 return 1; 280 } 281 prev = VORTEX_MIXER_CHNBASE + (ch << 2); 282 temp = hwread(vortex->mmio, prev); 283 while (temp & 0x10) { 284 prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2); 285 temp = hwread(vortex->mmio, prev); 286 //printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp); 287 if ((++lifeboat) > 0xf) { 288 dev_err(vortex->card->dev, 289 "vortex_mixer_addWTD: lifeboat overflow\n"); 290 return 0; 291 } 292 } 293 hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix); 294 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10); 295 return 1; 296 } 297 298 static int 299 vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch) 300 { 301 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0; 302 //int esp1f=edi(while)=src, esp10=ch; 303 304 eax = hwread(vortex->mmio, VORTEX_MIXER_SR); 305 if (((1 << ch) & eax) == 0) { 306 dev_err(vortex->card->dev, "mix ALARM %x\n", eax); 307 return 0; 308 } 309 ebp = VORTEX_MIXER_CHNBASE + (ch << 2); 310 esp18 = hwread(vortex->mmio, ebp); 311 if (esp18 & 0x10) { 312 ebx = (esp18 & 0xf); 313 if (mix == ebx) { 314 ebx = VORTEX_MIXER_RTBASE + (mix << 2); 315 edx = hwread(vortex->mmio, ebx); 316 //7b60 317 hwwrite(vortex->mmio, ebp, edx); 318 hwwrite(vortex->mmio, ebx, 0); 319 } else { 320 //7ad3 321 edx = 322 hwread(vortex->mmio, 323 VORTEX_MIXER_RTBASE + (ebx << 2)); 324 //printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src); 325 while ((edx & 0xf) != mix) { 326 if ((esi) > 0xf) { 327 dev_err(vortex->card->dev, 328 "mixdelWTD: error lifeboat overflow\n"); 329 return 0; 330 } 331 esp14 = ebx; 332 ebx = edx & 0xf; 333 ebp = ebx << 2; 334 edx = 335 hwread(vortex->mmio, 336 VORTEX_MIXER_RTBASE + ebp); 337 //printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx); 338 esi++; 339 } 340 //7b30 341 ebp = ebx << 2; 342 if (edx & 0x10) { /* Delete entry in between others */ 343 ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2); 344 edx = hwread(vortex->mmio, ebx); 345 //7b60 346 hwwrite(vortex->mmio, 347 VORTEX_MIXER_RTBASE + ebp, edx); 348 hwwrite(vortex->mmio, ebx, 0); 349 //printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx); 350 } else { /* Delete last entry */ 351 //7b83 352 if (esp14 == -1) 353 hwwrite(vortex->mmio, 354 VORTEX_MIXER_CHNBASE + 355 (ch << 2), esp18 & 0xef); 356 else { 357 ebx = (0xffffffe0 & edx) | (0xf & ebx); 358 hwwrite(vortex->mmio, 359 VORTEX_MIXER_RTBASE + 360 (esp14 << 2), ebx); 361 //printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx); 362 } 363 hwwrite(vortex->mmio, 364 VORTEX_MIXER_RTBASE + ebp, 0); 365 return 1; 366 } 367 } 368 } else { 369 //printk(KERN_INFO "removed last mix\n"); 370 //7be0 371 vortex_mixer_dis_sr(vortex, ch); 372 hwwrite(vortex->mmio, ebp, 0); 373 } 374 return 1; 375 } 376 377 static void vortex_mixer_init(vortex_t * vortex) 378 { 379 u32 addr; 380 int x; 381 382 // FIXME: get rid of this crap. 383 memset(mchannels, 0, NR_MIXOUT * sizeof(int)); 384 memset(rampchs, 0, NR_MIXOUT * sizeof(int)); 385 386 addr = VORTEX_MIX_SMP + 0x17c; 387 for (x = 0x5f; x >= 0; x--) { 388 hwwrite(vortex->mmio, addr, 0); 389 addr -= 4; 390 } 391 addr = VORTEX_MIX_ENIN + 0x1fc; 392 for (x = 0x7f; x >= 0; x--) { 393 hwwrite(vortex->mmio, addr, 0); 394 addr -= 4; 395 } 396 addr = VORTEX_MIX_SMP + 0x17c; 397 for (x = 0x5f; x >= 0; x--) { 398 hwwrite(vortex->mmio, addr, 0); 399 addr -= 4; 400 } 401 addr = VORTEX_MIX_INVOL_A + 0x7fc; 402 for (x = 0x1ff; x >= 0; x--) { 403 hwwrite(vortex->mmio, addr, 0x80); 404 addr -= 4; 405 } 406 addr = VORTEX_MIX_VOL_A + 0x3c; 407 for (x = 0xf; x >= 0; x--) { 408 hwwrite(vortex->mmio, addr, 0x80); 409 addr -= 4; 410 } 411 addr = VORTEX_MIX_INVOL_B + 0x7fc; 412 for (x = 0x1ff; x >= 0; x--) { 413 hwwrite(vortex->mmio, addr, 0x80); 414 addr -= 4; 415 } 416 addr = VORTEX_MIX_VOL_B + 0x3c; 417 for (x = 0xf; x >= 0; x--) { 418 hwwrite(vortex->mmio, addr, 0x80); 419 addr -= 4; 420 } 421 addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4; 422 for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) { 423 hwwrite(vortex->mmio, addr, 0x0); 424 addr -= 4; 425 } 426 hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0); 427 428 /* Set clipping ceiling (this may be all wrong). */ 429 /* 430 for (x = 0; x < 0x80; x++) { 431 hwwrite(vortex->mmio, VORTEX_MIXER_CLIP + (x << 2), 0x3ffff); 432 } 433 */ 434 /* 435 call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____ 436 Register ISR callback for volume smooth fade out. 437 Maybe this avoids clicks when press "stop" ? 438 */ 439 } 440 441 /* SRC (CAsp4Src.s and CAsp4SrcBlock) */ 442 443 static void vortex_src_en_sr(vortex_t * vortex, int channel) 444 { 445 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, 446 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel)); 447 } 448 449 static void vortex_src_dis_sr(vortex_t * vortex, int channel) 450 { 451 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR, 452 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel)); 453 } 454 455 static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src) 456 { 457 int i; 458 459 for (i = 0x1f; i >= 0; i--) 460 hwwrite(vortex->mmio, 461 VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0); 462 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0); 463 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0); 464 } 465 466 static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src) 467 { 468 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0); 469 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0); 470 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1); 471 } 472 473 static void 474 vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en) 475 { 476 int temp; 477 478 temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE); 479 if (en) 480 temp |= 1 << src; 481 else 482 temp &= ~(1 << src); 483 hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp); 484 } 485 486 static int 487 vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio) 488 { 489 int temp, lifeboat = 0; 490 491 do { 492 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio); 493 temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2)); 494 if ((++lifeboat) > 0x9) { 495 dev_err(vortex->card->dev, "Src cvr fail\n"); 496 break; 497 } 498 } 499 while (temp != ratio); 500 return temp; 501 } 502 503 #if 0 504 static void vortex_src_slowlock(vortex_t * vortex, unsigned char src) 505 { 506 int temp; 507 508 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1); 509 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0); 510 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2)); 511 if (temp & 0x200) 512 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2), 513 temp & ~0x200L); 514 } 515 516 static void 517 vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio) 518 { 519 int temp, a; 520 521 if ((ratio & 0x10000) && (ratio != 0x10000)) { 522 if (ratio & 0x3fff) 523 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1; 524 else 525 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2; 526 } else 527 a = 0xc; 528 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2)); 529 if (((temp >> 4) & 0xf) != a) 530 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2), 531 (temp & 0xf) | ((a & 0xf) << 4)); 532 533 vortex_src_persist_convratio(vortex, src, ratio); 534 } 535 536 static int 537 vortex_src_checkratio(vortex_t * vortex, unsigned char src, 538 unsigned int desired_ratio) 539 { 540 int hw_ratio, lifeboat = 0; 541 542 hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2)); 543 544 while (hw_ratio != desired_ratio) { 545 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio); 546 547 if ((lifeboat++) > 15) { 548 pr_err( "Vortex: could not set src-%d from %d to %d\n", 549 src, hw_ratio, desired_ratio); 550 break; 551 } 552 } 553 554 return hw_ratio; 555 } 556 557 #endif 558 /* 559 Objective: Set samplerate for given SRC module. 560 Arguments: 561 card: pointer to vortex_t strcut. 562 src: Integer index of the SRC module. 563 cr: Current sample rate conversion factor. 564 b: unknown 16 bit value. 565 sweep: Enable Samplerate fade from cr toward tr flag. 566 dirplay: 1: playback, 0: recording. 567 sl: Slow Lock flag. 568 tr: Target samplerate conversion. 569 thsource: Throttle source flag (no idea what that means). 570 */ 571 static void vortex_src_setupchannel(vortex_t * card, unsigned char src, 572 unsigned int cr, unsigned int b, int sweep, int d, 573 int dirplay, int sl, unsigned int tr, int thsource) 574 { 575 // noplayback: d=2,4,7,0xa,0xb when using first 2 src's. 576 // c: enables pitch sweep. 577 // looks like g is c related. Maybe g is a sweep parameter ? 578 // g = cvr 579 // dirplay: 0 = recording, 1 = playback 580 // d = src hw index. 581 582 int esi, ebp = 0, esp10; 583 584 vortex_src_flushbuffers(card, src); 585 586 if (sweep) { 587 if ((tr & 0x10000) && (tr != 0x10000)) { 588 tr = 0; 589 esi = 0x7; 590 } else { 591 if ((((short)tr) < 0) && (tr != 0x8000)) { 592 tr = 0; 593 esi = 0x8; 594 } else { 595 tr = 1; 596 esi = 0xc; 597 } 598 } 599 } else { 600 if ((cr & 0x10000) && (cr != 0x10000)) { 601 tr = 0; /*ebx = 0 */ 602 esi = 0x11 - ((cr >> 0xe) & 7); 603 if (cr & 0x3fff) 604 esi -= 1; 605 else 606 esi -= 2; 607 } else { 608 tr = 1; 609 esi = 0xc; 610 } 611 } 612 vortex_src_cleardrift(card, src); 613 vortex_src_set_throttlesource(card, src, thsource); 614 615 if ((dirplay == 0) && (sweep == 0)) { 616 if (tr) 617 esp10 = 0xf; 618 else 619 esp10 = 0xc; 620 ebp = 0; 621 } else { 622 if (tr) 623 ebp = 0xf; 624 else 625 ebp = 0xc; 626 esp10 = 0; 627 } 628 hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2), 629 (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d); 630 /* 0xc0 esi=0xc c=f=0 d=0 */ 631 vortex_src_persist_convratio(card, src, cr); 632 hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff); 633 /* 0 b=0 */ 634 hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2), 635 (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10); 636 /* 0x30f00 e=g=1 esp10=0 ebp=f */ 637 //printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp); 638 } 639 640 static void vortex_srcblock_init(vortex_t * vortex) 641 { 642 u32 addr; 643 int x; 644 hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff); 645 /* 646 for (x=0; x<0x10; x++) { 647 vortex_src_init(&vortex_src[x], x); 648 } 649 */ 650 //addr = 0xcc3c; 651 //addr = 0x26c3c; 652 addr = VORTEX_SRC_RTBASE + 0x3c; 653 for (x = 0xf; x >= 0; x--) { 654 hwwrite(vortex->mmio, addr, 0); 655 addr -= 4; 656 } 657 //addr = 0xcc94; 658 //addr = 0x26c94; 659 addr = VORTEX_SRC_CHNBASE + 0x54; 660 for (x = 0x15; x >= 0; x--) { 661 hwwrite(vortex->mmio, addr, 0); 662 addr -= 4; 663 } 664 } 665 666 static int 667 vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch) 668 { 669 int temp, lifeboat = 0, prev; 670 // esp13 = src 671 672 temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR); 673 if ((temp & (1 << ch)) == 0) { 674 hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src); 675 vortex_src_en_sr(vortex, ch); 676 return 1; 677 } 678 prev = VORTEX_SRC_CHNBASE + (ch << 2); /*ebp */ 679 temp = hwread(vortex->mmio, prev); 680 //while (temp & NR_SRC) { 681 while (temp & 0x10) { 682 prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12 */ 683 //prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/ 684 temp = hwread(vortex->mmio, prev); 685 //printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp); 686 if ((++lifeboat) > 0xf) { 687 dev_err(vortex->card->dev, 688 "vortex_src_addWTD: lifeboat overflow\n"); 689 return 0; 690 } 691 } 692 hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src); 693 //hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC); 694 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10); 695 return 1; 696 } 697 698 static int 699 vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch) 700 { 701 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0; 702 //int esp1f=edi(while)=src, esp10=ch; 703 704 eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR); 705 if (((1 << ch) & eax) == 0) { 706 dev_err(vortex->card->dev, "src alarm\n"); 707 return 0; 708 } 709 ebp = VORTEX_SRC_CHNBASE + (ch << 2); 710 esp18 = hwread(vortex->mmio, ebp); 711 if (esp18 & 0x10) { 712 ebx = (esp18 & 0xf); 713 if (src == ebx) { 714 ebx = VORTEX_SRC_RTBASE + (src << 2); 715 edx = hwread(vortex->mmio, ebx); 716 //7b60 717 hwwrite(vortex->mmio, ebp, edx); 718 hwwrite(vortex->mmio, ebx, 0); 719 } else { 720 //7ad3 721 edx = 722 hwread(vortex->mmio, 723 VORTEX_SRC_RTBASE + (ebx << 2)); 724 //printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src); 725 while ((edx & 0xf) != src) { 726 if ((esi) > 0xf) { 727 dev_warn(vortex->card->dev, 728 "srcdelWTD: error, lifeboat overflow\n"); 729 return 0; 730 } 731 esp14 = ebx; 732 ebx = edx & 0xf; 733 ebp = ebx << 2; 734 edx = 735 hwread(vortex->mmio, 736 VORTEX_SRC_RTBASE + ebp); 737 //printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx); 738 esi++; 739 } 740 //7b30 741 ebp = ebx << 2; 742 if (edx & 0x10) { /* Delete entry in between others */ 743 ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2); 744 edx = hwread(vortex->mmio, ebx); 745 //7b60 746 hwwrite(vortex->mmio, 747 VORTEX_SRC_RTBASE + ebp, edx); 748 hwwrite(vortex->mmio, ebx, 0); 749 //printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx); 750 } else { /* Delete last entry */ 751 //7b83 752 if (esp14 == -1) 753 hwwrite(vortex->mmio, 754 VORTEX_SRC_CHNBASE + 755 (ch << 2), esp18 & 0xef); 756 else { 757 ebx = (0xffffffe0 & edx) | (0xf & ebx); 758 hwwrite(vortex->mmio, 759 VORTEX_SRC_RTBASE + 760 (esp14 << 2), ebx); 761 //printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx); 762 } 763 hwwrite(vortex->mmio, 764 VORTEX_SRC_RTBASE + ebp, 0); 765 return 1; 766 } 767 } 768 } else { 769 //7be0 770 vortex_src_dis_sr(vortex, ch); 771 hwwrite(vortex->mmio, ebp, 0); 772 } 773 return 1; 774 } 775 776 /*FIFO*/ 777 778 static void 779 vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x) 780 { 781 for (x--; x >= 0; x--) 782 hwwrite(vortex->mmio, 783 VORTEX_FIFO_ADBDATA + 784 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0); 785 } 786 787 #if 0 788 static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j) 789 { 790 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); 791 #ifdef CHIP_AU8820 792 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), 793 (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); 794 #else 795 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), 796 (FIFO_U1 | ((j & FIFO_MASK) << 0xc))); 797 #endif 798 } 799 #endif 800 static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en) 801 { 802 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), 803 (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) & 804 0xffffffef) | ((1 & en) << 4) | FIFO_U1); 805 } 806 807 static void 808 vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int stereo, int priority, 809 int empty, int valid, int f) 810 { 811 int temp, lifeboat = 0; 812 //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */ 813 int this_4 = 0x2; 814 /* f seems priority related. 815 * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1 816 * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority 817 * is never called, thus the f related bits remain a mystery for now. 818 */ 819 do { 820 temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)); 821 if (lifeboat++ > 0xbb8) { 822 dev_err(vortex->card->dev, 823 "vortex_fifo_setadbctrl fail\n"); 824 break; 825 } 826 } 827 while (temp & FIFO_RDONLY); 828 829 // AU8830 semes to take some special care about fifo content (data). 830 // But i'm just to lazy to translate that :) 831 if (valid) { 832 if ((temp & FIFO_VALID) == 0) { 833 //this_8[fifo] = 0; 834 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); // this_4 835 #ifdef CHIP_AU8820 836 temp = (this_4 & 0x1f) << 0xb; 837 #else 838 temp = (this_4 & 0x3f) << 0xc; 839 #endif 840 temp = (temp & 0xfffffffd) | ((stereo & 1) << 1); 841 temp = (temp & 0xfffffff3) | ((priority & 3) << 2); 842 temp = (temp & 0xffffffef) | ((valid & 1) << 4); 843 temp |= FIFO_U1; 844 temp = (temp & 0xffffffdf) | ((empty & 1) << 5); 845 #ifdef CHIP_AU8820 846 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12); 847 #endif 848 #ifdef CHIP_AU8830 849 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b); 850 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c); 851 #endif 852 #ifdef CHIP_AU8810 853 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18); 854 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19); 855 #endif 856 } 857 } else { 858 if (temp & FIFO_VALID) { 859 #ifdef CHIP_AU8820 860 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef); 861 #endif 862 #ifdef CHIP_AU8830 863 temp = 864 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS; 865 #endif 866 #ifdef CHIP_AU8810 867 temp = 868 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS; 869 #endif 870 } else 871 /*if (this_8[fifo]) */ 872 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); 873 } 874 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp); 875 hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)); 876 } 877 878 #ifndef CHIP_AU8810 879 static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x) 880 { 881 if (x < 1) 882 return; 883 for (x--; x >= 0; x--) 884 hwwrite(vortex->mmio, 885 VORTEX_FIFO_WTDATA + 886 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0); 887 } 888 889 static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j) 890 { 891 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); 892 #ifdef CHIP_AU8820 893 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), 894 (FIFO_U1 | ((j & FIFO_MASK) << 0xb))); 895 #else 896 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), 897 (FIFO_U1 | ((j & FIFO_MASK) << 0xc))); 898 #endif 899 } 900 901 static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en) 902 { 903 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), 904 (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) & 905 0xffffffef) | ((en & 1) << 4) | FIFO_U1); 906 } 907 908 static void 909 vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority, 910 int empty, int valid, int f) 911 { 912 int temp = 0, lifeboat = 0; 913 int this_4 = 2; 914 915 do { 916 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)); 917 if (lifeboat++ > 0xbb8) { 918 dev_err(vortex->card->dev, 919 "vortex_fifo_setwtctrl fail\n"); 920 break; 921 } 922 } 923 while (temp & FIFO_RDONLY); 924 925 if (valid) { 926 if ((temp & FIFO_VALID) == 0) { 927 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); // this_4 928 #ifdef CHIP_AU8820 929 temp = (this_4 & 0x1f) << 0xb; 930 #else 931 temp = (this_4 & 0x3f) << 0xc; 932 #endif 933 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1); 934 temp = (temp & 0xfffffff3) | ((priority & 3) << 2); 935 temp = (temp & 0xffffffef) | ((valid & 1) << 4); 936 temp |= FIFO_U1; 937 temp = (temp & 0xffffffdf) | ((empty & 1) << 5); 938 #ifdef CHIP_AU8820 939 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12); 940 #endif 941 #ifdef CHIP_AU8830 942 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b); 943 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c); 944 #endif 945 #ifdef CHIP_AU8810 946 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18); 947 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19); 948 #endif 949 } 950 } else { 951 if (temp & FIFO_VALID) { 952 #ifdef CHIP_AU8820 953 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef); 954 #endif 955 #ifdef CHIP_AU8830 956 temp = 957 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS; 958 #endif 959 #ifdef CHIP_AU8810 960 temp = 961 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS; 962 #endif 963 } else 964 /*if (this_8[fifo]) */ 965 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); 966 } 967 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); 968 hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)); 969 970 /* 971 do { 972 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)); 973 if (lifeboat++ > 0xbb8) { 974 pr_err( "Vortex: vortex_fifo_setwtctrl fail (hanging)\n"); 975 break; 976 } 977 } while ((temp & FIFO_RDONLY)&&(temp & FIFO_VALID)&&(temp != 0xFFFFFFFF)); 978 979 980 if (valid) { 981 if (temp & FIFO_VALID) { 982 temp = 0x40000; 983 //temp |= 0x08000000; 984 //temp |= 0x10000000; 985 //temp |= 0x04000000; 986 //temp |= 0x00400000; 987 temp |= 0x1c400000; 988 temp &= 0xFFFFFFF3; 989 temp &= 0xFFFFFFEF; 990 temp |= (valid & 1) << 4; 991 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); 992 return; 993 } else { 994 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); 995 return; 996 } 997 } else { 998 temp &= 0xffffffef; 999 temp |= 0x08000000; 1000 temp |= 0x10000000; 1001 temp |= 0x04000000; 1002 temp |= 0x00400000; 1003 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); 1004 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)); 1005 //((temp >> 6) & 0x3f) 1006 1007 priority = 0; 1008 if (((temp & 0x0fc0) ^ ((temp >> 6) & 0x0fc0)) & 0FFFFFFC0) 1009 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); 1010 valid = 0xfb; 1011 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1); 1012 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11); 1013 temp = (temp & 0xfffffff3) | ((priority & 3) << 2); 1014 temp = (temp & 0xffffffef) | ((valid & 1) << 4); 1015 temp = (temp & 0xffffffdf) | ((empty & 1) << 5); 1016 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); 1017 } 1018 1019 */ 1020 1021 /* 1022 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1); 1023 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11); 1024 temp = (temp & 0xfffffff3) | ((priority & 3) << 2); 1025 temp = (temp & 0xffffffef) | ((valid & 1) << 4); 1026 temp = (temp & 0xffffffdf) | ((empty & 1) << 5); 1027 #ifdef FIFO_BITS 1028 temp = temp | FIFO_BITS | 40000; 1029 #endif 1030 // 0x1c440010, 0x1c400000 1031 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp); 1032 */ 1033 } 1034 1035 #endif 1036 static void vortex_fifo_init(vortex_t * vortex) 1037 { 1038 int x; 1039 u32 addr; 1040 1041 /* ADB DMA channels fifos. */ 1042 addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4); 1043 for (x = NR_ADB - 1; x >= 0; x--) { 1044 hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1)); 1045 if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1)) 1046 dev_err(vortex->card->dev, "bad adb fifo reset!\n"); 1047 vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE); 1048 addr -= 4; 1049 } 1050 1051 #ifndef CHIP_AU8810 1052 /* WT DMA channels fifos. */ 1053 addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4); 1054 for (x = NR_WT - 1; x >= 0; x--) { 1055 hwwrite(vortex->mmio, addr, FIFO_U0); 1056 if (hwread(vortex->mmio, addr) != FIFO_U0) 1057 dev_err(vortex->card->dev, 1058 "bad wt fifo reset (0x%08x, 0x%08x)!\n", 1059 addr, hwread(vortex->mmio, addr)); 1060 vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE); 1061 addr -= 4; 1062 } 1063 #endif 1064 /* trigger... */ 1065 #ifdef CHIP_AU8820 1066 hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b 1067 #else 1068 #ifdef CHIP_AU8830 1069 hwwrite(vortex->mmio, 0x17000, 0x61); /* wt a */ 1070 hwwrite(vortex->mmio, 0x17004, 0x61); /* wt b */ 1071 #endif 1072 hwwrite(vortex->mmio, 0x17008, 0x61); /* adb */ 1073 #endif 1074 } 1075 1076 /* ADBDMA */ 1077 1078 static void vortex_adbdma_init(vortex_t * vortex) 1079 { 1080 } 1081 1082 static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma) 1083 { 1084 stream_t *dma = &vortex->dma_adb[adbdma]; 1085 1086 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), 1087 dma->dma_ctrl); 1088 } 1089 1090 static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb) 1091 { 1092 stream_t *dma = &vortex->dma_adb[adbdma]; 1093 //hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << (((NR_ADB-1)-((adbdma&0xf)*2)))); 1094 hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), 1095 sb << ((0xf - (adbdma & 0xf)) * 2)); 1096 dma->period_real = dma->period_virt = sb; 1097 } 1098 1099 static void 1100 vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma, 1101 int psize, int count) 1102 { 1103 stream_t *dma = &vortex->dma_adb[adbdma]; 1104 1105 dma->period_bytes = psize; 1106 dma->nr_periods = count; 1107 1108 dma->cfg0 = 0; 1109 dma->cfg1 = 0; 1110 switch (count) { 1111 /* Four or more pages */ 1112 default: 1113 case 4: 1114 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1); 1115 hwwrite(vortex->mmio, 1116 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc, 1117 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3)); 1118 /* fall through */ 1119 /* 3 pages */ 1120 case 3: 1121 dma->cfg0 |= 0x12000000; 1122 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc); 1123 hwwrite(vortex->mmio, 1124 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8, 1125 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2)); 1126 /* fall through */ 1127 /* 2 pages */ 1128 case 2: 1129 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1); 1130 hwwrite(vortex->mmio, 1131 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4, 1132 snd_pcm_sgbuf_get_addr(dma->substream, psize)); 1133 /* fall through */ 1134 /* 1 page */ 1135 case 1: 1136 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc); 1137 hwwrite(vortex->mmio, 1138 VORTEX_ADBDMA_BUFBASE + (adbdma << 4), 1139 snd_pcm_sgbuf_get_addr(dma->substream, 0)); 1140 break; 1141 } 1142 /* 1143 pr_debug( "vortex: cfg0 = 0x%x\nvortex: cfg1=0x%x\n", 1144 dma->cfg0, dma->cfg1); 1145 */ 1146 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0); 1147 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1); 1148 1149 vortex_adbdma_setfirstbuffer(vortex, adbdma); 1150 vortex_adbdma_setstartbuffer(vortex, adbdma, 0); 1151 } 1152 1153 static void 1154 vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir, 1155 int fmt, int stereo, u32 offset) 1156 { 1157 stream_t *dma = &vortex->dma_adb[adbdma]; 1158 1159 dma->dma_unknown = stereo; 1160 dma->dma_ctrl = 1161 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); 1162 /* Enable PCMOUT interrupts. */ 1163 dma->dma_ctrl = 1164 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK); 1165 1166 dma->dma_ctrl = 1167 (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK); 1168 dma->dma_ctrl = 1169 (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK); 1170 1171 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), 1172 dma->dma_ctrl); 1173 hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2)); 1174 } 1175 1176 static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma) 1177 { 1178 stream_t *dma = &vortex->dma_adb[adbdma]; 1179 int page, p, pp, delta, i; 1180 1181 page = 1182 (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) & 1183 ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT; 1184 if (dma->nr_periods >= 4) 1185 delta = (page - dma->period_real) & 3; 1186 else { 1187 delta = (page - dma->period_real); 1188 if (delta < 0) 1189 delta += dma->nr_periods; 1190 } 1191 if (delta == 0) 1192 return 0; 1193 1194 /* refresh hw page table */ 1195 if (dma->nr_periods > 4) { 1196 for (i = 0; i < delta; i++) { 1197 /* p: audio buffer page index */ 1198 p = dma->period_virt + i + 4; 1199 if (p >= dma->nr_periods) 1200 p -= dma->nr_periods; 1201 /* pp: hardware DMA page index. */ 1202 pp = dma->period_real + i; 1203 if (pp >= 4) 1204 pp -= 4; 1205 //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr); 1206 hwwrite(vortex->mmio, 1207 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2), 1208 snd_pcm_sgbuf_get_addr(dma->substream, 1209 dma->period_bytes * p)); 1210 /* Force write thru cache. */ 1211 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + 1212 (((adbdma << 2) + pp) << 2)); 1213 } 1214 } 1215 dma->period_virt += delta; 1216 dma->period_real = page; 1217 if (dma->period_virt >= dma->nr_periods) 1218 dma->period_virt -= dma->nr_periods; 1219 if (delta != 1) 1220 dev_info(vortex->card->dev, 1221 "%d virt=%d, real=%d, delta=%d\n", 1222 adbdma, dma->period_virt, dma->period_real, delta); 1223 1224 return delta; 1225 } 1226 1227 1228 static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma) { 1229 stream_t *dma = &vortex->dma_adb[adbdma]; 1230 int p, pp, i; 1231 1232 /* refresh hw page table */ 1233 for (i=0 ; i < 4 && i < dma->nr_periods; i++) { 1234 /* p: audio buffer page index */ 1235 p = dma->period_virt + i; 1236 if (p >= dma->nr_periods) 1237 p -= dma->nr_periods; 1238 /* pp: hardware DMA page index. */ 1239 pp = dma->period_real + i; 1240 if (dma->nr_periods < 4) { 1241 if (pp >= dma->nr_periods) 1242 pp -= dma->nr_periods; 1243 } 1244 else { 1245 if (pp >= 4) 1246 pp -= 4; 1247 } 1248 hwwrite(vortex->mmio, 1249 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2), 1250 snd_pcm_sgbuf_get_addr(dma->substream, 1251 dma->period_bytes * p)); 1252 /* Force write thru cache. */ 1253 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2)+pp) << 2)); 1254 } 1255 } 1256 1257 static inline int vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma) 1258 { 1259 stream_t *dma = &vortex->dma_adb[adbdma]; 1260 int temp, page, delta; 1261 1262 temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)); 1263 page = (temp & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT; 1264 if (dma->nr_periods >= 4) 1265 delta = (page - dma->period_real) & 3; 1266 else { 1267 delta = (page - dma->period_real); 1268 if (delta < 0) 1269 delta += dma->nr_periods; 1270 } 1271 return (dma->period_virt + delta) * dma->period_bytes 1272 + (temp & (dma->period_bytes - 1)); 1273 } 1274 1275 static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma) 1276 { 1277 int this_8 = 0 /*empty */ , this_4 = 0 /*priority */ ; 1278 stream_t *dma = &vortex->dma_adb[adbdma]; 1279 1280 switch (dma->fifo_status) { 1281 case FIFO_START: 1282 vortex_fifo_setadbvalid(vortex, adbdma, 1283 dma->fifo_enabled ? 1 : 0); 1284 break; 1285 case FIFO_STOP: 1286 this_8 = 1; 1287 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), 1288 dma->dma_ctrl); 1289 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, 1290 this_4, this_8, 1291 dma->fifo_enabled ? 1 : 0, 0); 1292 break; 1293 case FIFO_PAUSE: 1294 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, 1295 this_4, this_8, 1296 dma->fifo_enabled ? 1 : 0, 0); 1297 break; 1298 } 1299 dma->fifo_status = FIFO_START; 1300 } 1301 1302 static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma) 1303 { 1304 stream_t *dma = &vortex->dma_adb[adbdma]; 1305 1306 int this_8 = 1, this_4 = 0; 1307 switch (dma->fifo_status) { 1308 case FIFO_STOP: 1309 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), 1310 dma->dma_ctrl); 1311 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, 1312 this_4, this_8, 1313 dma->fifo_enabled ? 1 : 0, 0); 1314 break; 1315 case FIFO_PAUSE: 1316 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, 1317 this_4, this_8, 1318 dma->fifo_enabled ? 1 : 0, 0); 1319 break; 1320 } 1321 dma->fifo_status = FIFO_START; 1322 } 1323 1324 static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma) 1325 { 1326 stream_t *dma = &vortex->dma_adb[adbdma]; 1327 1328 int this_8 = 0, this_4 = 0; 1329 switch (dma->fifo_status) { 1330 case FIFO_START: 1331 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, 1332 this_4, this_8, 0, 0); 1333 break; 1334 case FIFO_STOP: 1335 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2), 1336 dma->dma_ctrl); 1337 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, 1338 this_4, this_8, 0, 0); 1339 break; 1340 } 1341 dma->fifo_status = FIFO_PAUSE; 1342 } 1343 1344 static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma) 1345 { 1346 stream_t *dma = &vortex->dma_adb[adbdma]; 1347 1348 int this_4 = 0, this_8 = 0; 1349 if (dma->fifo_status == FIFO_START) 1350 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown, 1351 this_4, this_8, 0, 0); 1352 else if (dma->fifo_status == FIFO_STOP) 1353 return; 1354 dma->fifo_status = FIFO_STOP; 1355 dma->fifo_enabled = 0; 1356 } 1357 1358 /* WTDMA */ 1359 1360 #ifndef CHIP_AU8810 1361 static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma) 1362 { 1363 //int this_7c=dma_ctrl; 1364 stream_t *dma = &vortex->dma_wt[wtdma]; 1365 1366 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); 1367 } 1368 1369 static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb) 1370 { 1371 stream_t *dma = &vortex->dma_wt[wtdma]; 1372 //hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0x1f-(wtdma&0xf)*2))); 1373 hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), 1374 sb << ((0xf - (wtdma & 0xf)) * 2)); 1375 dma->period_real = dma->period_virt = sb; 1376 } 1377 1378 static void 1379 vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma, 1380 int psize, int count) 1381 { 1382 stream_t *dma = &vortex->dma_wt[wtdma]; 1383 1384 dma->period_bytes = psize; 1385 dma->nr_periods = count; 1386 1387 dma->cfg0 = 0; 1388 dma->cfg1 = 0; 1389 switch (count) { 1390 /* Four or more pages */ 1391 default: 1392 case 4: 1393 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1); 1394 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0xc, 1395 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3)); 1396 /* fall through */ 1397 /* 3 pages */ 1398 case 3: 1399 dma->cfg0 |= 0x12000000; 1400 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc); 1401 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x8, 1402 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2)); 1403 /* fall through */ 1404 /* 2 pages */ 1405 case 2: 1406 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1); 1407 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x4, 1408 snd_pcm_sgbuf_get_addr(dma->substream, psize)); 1409 /* fall through */ 1410 /* 1 page */ 1411 case 1: 1412 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc); 1413 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4), 1414 snd_pcm_sgbuf_get_addr(dma->substream, 0)); 1415 break; 1416 } 1417 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0); 1418 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1); 1419 1420 vortex_wtdma_setfirstbuffer(vortex, wtdma); 1421 vortex_wtdma_setstartbuffer(vortex, wtdma, 0); 1422 } 1423 1424 static void 1425 vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d, 1426 /*int e, */ u32 offset) 1427 { 1428 stream_t *dma = &vortex->dma_wt[wtdma]; 1429 1430 //dma->this_08 = e; 1431 dma->dma_unknown = d; 1432 dma->dma_ctrl = 0; 1433 dma->dma_ctrl = 1434 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK)); 1435 /* PCMOUT interrupt */ 1436 dma->dma_ctrl = 1437 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK); 1438 /* Always playback. */ 1439 dma->dma_ctrl |= (1 << DIR_SHIFT); 1440 /* Audio Format */ 1441 dma->dma_ctrl = 1442 (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK); 1443 /* Write into hardware */ 1444 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl); 1445 } 1446 1447 static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma) 1448 { 1449 stream_t *dma = &vortex->dma_wt[wtdma]; 1450 int page, p, pp, delta, i; 1451 1452 page = 1453 (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) 1454 >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK; 1455 if (dma->nr_periods >= 4) 1456 delta = (page - dma->period_real) & 3; 1457 else { 1458 delta = (page - dma->period_real); 1459 if (delta < 0) 1460 delta += dma->nr_periods; 1461 } 1462 if (delta == 0) 1463 return 0; 1464 1465 /* refresh hw page table */ 1466 if (dma->nr_periods > 4) { 1467 for (i = 0; i < delta; i++) { 1468 /* p: audio buffer page index */ 1469 p = dma->period_virt + i + 4; 1470 if (p >= dma->nr_periods) 1471 p -= dma->nr_periods; 1472 /* pp: hardware DMA page index. */ 1473 pp = dma->period_real + i; 1474 if (pp >= 4) 1475 pp -= 4; 1476 hwwrite(vortex->mmio, 1477 VORTEX_WTDMA_BUFBASE + 1478 (((wtdma << 2) + pp) << 2), 1479 snd_pcm_sgbuf_get_addr(dma->substream, 1480 dma->period_bytes * p)); 1481 /* Force write thru cache. */ 1482 hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE + 1483 (((wtdma << 2) + pp) << 2)); 1484 } 1485 } 1486 dma->period_virt += delta; 1487 if (dma->period_virt >= dma->nr_periods) 1488 dma->period_virt -= dma->nr_periods; 1489 dma->period_real = page; 1490 1491 if (delta != 1) 1492 dev_warn(vortex->card->dev, "wt virt = %d, delta = %d\n", 1493 dma->period_virt, delta); 1494 1495 return delta; 1496 } 1497 1498 #if 0 1499 static void 1500 vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos) 1501 { 1502 int temp; 1503 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); 1504 *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK; 1505 *pos = temp & POS_MASK; 1506 } 1507 1508 static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma) 1509 { 1510 return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >> 1511 POS_SHIFT) & POS_MASK); 1512 } 1513 #endif 1514 static inline int vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma) 1515 { 1516 stream_t *dma = &vortex->dma_wt[wtdma]; 1517 int temp; 1518 1519 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); 1520 temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1)); 1521 return temp; 1522 } 1523 1524 static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma) 1525 { 1526 stream_t *dma = &vortex->dma_wt[wtdma]; 1527 int this_8 = 0, this_4 = 0; 1528 1529 switch (dma->fifo_status) { 1530 case FIFO_START: 1531 vortex_fifo_setwtvalid(vortex, wtdma, 1532 dma->fifo_enabled ? 1 : 0); 1533 break; 1534 case FIFO_STOP: 1535 this_8 = 1; 1536 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), 1537 dma->dma_ctrl); 1538 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, 1539 this_4, this_8, 1540 dma->fifo_enabled ? 1 : 0, 0); 1541 break; 1542 case FIFO_PAUSE: 1543 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, 1544 this_4, this_8, 1545 dma->fifo_enabled ? 1 : 0, 0); 1546 break; 1547 } 1548 dma->fifo_status = FIFO_START; 1549 } 1550 1551 static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma) 1552 { 1553 stream_t *dma = &vortex->dma_wt[wtdma]; 1554 1555 int this_8 = 0, this_4 = 0; 1556 switch (dma->fifo_status) { 1557 case FIFO_STOP: 1558 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), 1559 dma->dma_ctrl); 1560 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, 1561 this_4, this_8, 1562 dma->fifo_enabled ? 1 : 0, 0); 1563 break; 1564 case FIFO_PAUSE: 1565 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, 1566 this_4, this_8, 1567 dma->fifo_enabled ? 1 : 0, 0); 1568 break; 1569 } 1570 dma->fifo_status = FIFO_START; 1571 } 1572 1573 static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma) 1574 { 1575 stream_t *dma = &vortex->dma_wt[wtdma]; 1576 1577 int this_8 = 0, this_4 = 0; 1578 switch (dma->fifo_status) { 1579 case FIFO_START: 1580 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, 1581 this_4, this_8, 0, 0); 1582 break; 1583 case FIFO_STOP: 1584 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), 1585 dma->dma_ctrl); 1586 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, 1587 this_4, this_8, 0, 0); 1588 break; 1589 } 1590 dma->fifo_status = FIFO_PAUSE; 1591 } 1592 1593 static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma) 1594 { 1595 stream_t *dma = &vortex->dma_wt[wtdma]; 1596 1597 int this_4 = 0, this_8 = 0; 1598 if (dma->fifo_status == FIFO_START) 1599 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown, 1600 this_4, this_8, 0, 0); 1601 else if (dma->fifo_status == FIFO_STOP) 1602 return; 1603 dma->fifo_status = FIFO_STOP; 1604 dma->fifo_enabled = 0; 1605 } 1606 1607 #endif 1608 /* ADB Routes */ 1609 1610 typedef int ADBRamLink; 1611 static void vortex_adb_init(vortex_t * vortex) 1612 { 1613 int i; 1614 /* it looks like we are writing more than we need to... 1615 * if we write what we are supposed to it breaks things... */ 1616 hwwrite(vortex->mmio, VORTEX_ADB_SR, 0); 1617 for (i = 0; i < VORTEX_ADB_RTBASE_COUNT; i++) 1618 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2), 1619 hwread(vortex->mmio, 1620 VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK); 1621 for (i = 0; i < VORTEX_ADB_CHNBASE_COUNT; i++) { 1622 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2), 1623 hwread(vortex->mmio, 1624 VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK); 1625 } 1626 } 1627 1628 static void vortex_adb_en_sr(vortex_t * vortex, int channel) 1629 { 1630 hwwrite(vortex->mmio, VORTEX_ADB_SR, 1631 hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel)); 1632 } 1633 1634 static void vortex_adb_dis_sr(vortex_t * vortex, int channel) 1635 { 1636 hwwrite(vortex->mmio, VORTEX_ADB_SR, 1637 hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel)); 1638 } 1639 1640 static void 1641 vortex_adb_addroutes(vortex_t * vortex, unsigned char channel, 1642 ADBRamLink * route, int rnum) 1643 { 1644 int temp, prev, lifeboat = 0; 1645 1646 if ((rnum <= 0) || (route == NULL)) 1647 return; 1648 /* Write last routes. */ 1649 rnum--; 1650 hwwrite(vortex->mmio, 1651 VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2), 1652 ROUTE_MASK); 1653 while (rnum > 0) { 1654 hwwrite(vortex->mmio, 1655 VORTEX_ADB_RTBASE + 1656 ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]); 1657 rnum--; 1658 } 1659 /* Write first route. */ 1660 temp = 1661 hwread(vortex->mmio, 1662 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK; 1663 if (temp == ADB_MASK) { 1664 /* First entry on this channel. */ 1665 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2), 1666 route[0]); 1667 vortex_adb_en_sr(vortex, channel); 1668 return; 1669 } 1670 /* Not first entry on this channel. Need to link. */ 1671 do { 1672 prev = temp; 1673 temp = 1674 hwread(vortex->mmio, 1675 VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK; 1676 if ((lifeboat++) > ADB_MASK) { 1677 dev_err(vortex->card->dev, 1678 "vortex_adb_addroutes: unending route! 0x%x\n", 1679 *route); 1680 return; 1681 } 1682 } 1683 while (temp != ADB_MASK); 1684 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]); 1685 } 1686 1687 static void 1688 vortex_adb_delroutes(vortex_t * vortex, unsigned char channel, 1689 ADBRamLink route0, ADBRamLink route1) 1690 { 1691 int temp, lifeboat = 0, prev; 1692 1693 /* Find route. */ 1694 temp = 1695 hwread(vortex->mmio, 1696 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK; 1697 if (temp == (route0 & ADB_MASK)) { 1698 temp = 1699 hwread(vortex->mmio, 1700 VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2)); 1701 if ((temp & ADB_MASK) == ADB_MASK) 1702 vortex_adb_dis_sr(vortex, channel); 1703 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2), 1704 temp); 1705 return; 1706 } 1707 do { 1708 prev = temp; 1709 temp = 1710 hwread(vortex->mmio, 1711 VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK; 1712 if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) { 1713 dev_err(vortex->card->dev, 1714 "vortex_adb_delroutes: route not found! 0x%x\n", 1715 route0); 1716 return; 1717 } 1718 } 1719 while (temp != (route0 & ADB_MASK)); 1720 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2)); 1721 if ((temp & ADB_MASK) == route1) 1722 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2)); 1723 /* Make bridge over deleted route. */ 1724 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp); 1725 } 1726 1727 static void 1728 vortex_route(vortex_t * vortex, int en, unsigned char channel, 1729 unsigned char source, unsigned char dest) 1730 { 1731 ADBRamLink route; 1732 1733 route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); 1734 if (en) { 1735 vortex_adb_addroutes(vortex, channel, &route, 1); 1736 if ((source < (OFFSET_SRCOUT + NR_SRC)) 1737 && (source >= OFFSET_SRCOUT)) 1738 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT), 1739 channel); 1740 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT)) 1741 && (source >= OFFSET_MIXOUT)) 1742 vortex_mixer_addWTD(vortex, 1743 (source - OFFSET_MIXOUT), channel); 1744 } else { 1745 vortex_adb_delroutes(vortex, channel, route, route); 1746 if ((source < (OFFSET_SRCOUT + NR_SRC)) 1747 && (source >= OFFSET_SRCOUT)) 1748 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT), 1749 channel); 1750 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT)) 1751 && (source >= OFFSET_MIXOUT)) 1752 vortex_mixer_delWTD(vortex, 1753 (source - OFFSET_MIXOUT), channel); 1754 } 1755 } 1756 1757 #if 0 1758 static void 1759 vortex_routes(vortex_t * vortex, int en, unsigned char channel, 1760 unsigned char source, unsigned char dest0, unsigned char dest1) 1761 { 1762 ADBRamLink route[2]; 1763 1764 route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK); 1765 route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK); 1766 1767 if (en) { 1768 vortex_adb_addroutes(vortex, channel, route, 2); 1769 if ((source < (OFFSET_SRCOUT + NR_SRC)) 1770 && (source >= (OFFSET_SRCOUT))) 1771 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT), 1772 channel); 1773 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT)) 1774 && (source >= (OFFSET_MIXOUT))) 1775 vortex_mixer_addWTD(vortex, 1776 (source - OFFSET_MIXOUT), channel); 1777 } else { 1778 vortex_adb_delroutes(vortex, channel, route[0], route[1]); 1779 if ((source < (OFFSET_SRCOUT + NR_SRC)) 1780 && (source >= (OFFSET_SRCOUT))) 1781 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT), 1782 channel); 1783 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT)) 1784 && (source >= (OFFSET_MIXOUT))) 1785 vortex_mixer_delWTD(vortex, 1786 (source - OFFSET_MIXOUT), channel); 1787 } 1788 } 1789 1790 #endif 1791 /* Route two sources to same target. Sources must be of same class !!! */ 1792 static void 1793 vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch, 1794 unsigned char source0, unsigned char source1, 1795 unsigned char dest) 1796 { 1797 ADBRamLink route[2]; 1798 1799 route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); 1800 route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK); 1801 1802 if (dest < 0x10) 1803 route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20); /* fifo A */ 1804 1805 if (en) { 1806 vortex_adb_addroutes(vortex, ch, route, 2); 1807 if ((source0 < (OFFSET_SRCOUT + NR_SRC)) 1808 && (source0 >= OFFSET_SRCOUT)) { 1809 vortex_src_addWTD(vortex, 1810 (source0 - OFFSET_SRCOUT), ch); 1811 vortex_src_addWTD(vortex, 1812 (source1 - OFFSET_SRCOUT), ch); 1813 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT)) 1814 && (source0 >= OFFSET_MIXOUT)) { 1815 vortex_mixer_addWTD(vortex, 1816 (source0 - OFFSET_MIXOUT), ch); 1817 vortex_mixer_addWTD(vortex, 1818 (source1 - OFFSET_MIXOUT), ch); 1819 } 1820 } else { 1821 vortex_adb_delroutes(vortex, ch, route[0], route[1]); 1822 if ((source0 < (OFFSET_SRCOUT + NR_SRC)) 1823 && (source0 >= OFFSET_SRCOUT)) { 1824 vortex_src_delWTD(vortex, 1825 (source0 - OFFSET_SRCOUT), ch); 1826 vortex_src_delWTD(vortex, 1827 (source1 - OFFSET_SRCOUT), ch); 1828 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT)) 1829 && (source0 >= OFFSET_MIXOUT)) { 1830 vortex_mixer_delWTD(vortex, 1831 (source0 - OFFSET_MIXOUT), ch); 1832 vortex_mixer_delWTD(vortex, 1833 (source1 - OFFSET_MIXOUT), ch); 1834 } 1835 } 1836 } 1837 1838 /* Connection stuff */ 1839 1840 // Connect adbdma to src('s). 1841 static void 1842 vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch, 1843 unsigned char adbdma, unsigned char src) 1844 { 1845 vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src)); 1846 } 1847 1848 // Connect SRC to mixin. 1849 static void 1850 vortex_connection_src_mixin(vortex_t * vortex, int en, 1851 unsigned char channel, unsigned char src, 1852 unsigned char mixin) 1853 { 1854 vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin)); 1855 } 1856 1857 // Connect mixin with mix output. 1858 static void 1859 vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin, 1860 unsigned char mix, int a) 1861 { 1862 if (en) { 1863 vortex_mix_enableinput(vortex, mix, mixin); 1864 vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN); // added to original code. 1865 } else 1866 vortex_mix_disableinput(vortex, mix, mixin, a); 1867 } 1868 1869 // Connect absolut address to mixin. 1870 static void 1871 vortex_connection_adb_mixin(vortex_t * vortex, int en, 1872 unsigned char channel, unsigned char source, 1873 unsigned char mixin) 1874 { 1875 vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin)); 1876 } 1877 1878 static void 1879 vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch, 1880 unsigned char src, unsigned char adbdma) 1881 { 1882 vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma)); 1883 } 1884 1885 static void 1886 vortex_connection_src_src_adbdma(vortex_t * vortex, int en, 1887 unsigned char ch, unsigned char src0, 1888 unsigned char src1, unsigned char adbdma) 1889 { 1890 1891 vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1), 1892 ADB_DMA(adbdma)); 1893 } 1894 1895 // mix to absolut address. 1896 static void 1897 vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch, 1898 unsigned char mix, unsigned char dest) 1899 { 1900 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest); 1901 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code. 1902 } 1903 1904 // mixer to src. 1905 static void 1906 vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch, 1907 unsigned char mix, unsigned char src) 1908 { 1909 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src)); 1910 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code. 1911 } 1912 1913 #if 0 1914 static void 1915 vortex_connection_adbdma_src_src(vortex_t * vortex, int en, 1916 unsigned char channel, 1917 unsigned char adbdma, unsigned char src0, 1918 unsigned char src1) 1919 { 1920 vortex_routes(vortex, en, channel, ADB_DMA(adbdma), 1921 ADB_SRCIN(src0), ADB_SRCIN(src1)); 1922 } 1923 1924 // Connect two mix to AdbDma. 1925 static void 1926 vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en, 1927 unsigned char ch, unsigned char mix0, 1928 unsigned char mix1, unsigned char adbdma) 1929 { 1930 1931 ADBRamLink routes[2]; 1932 routes[0] = 1933 (((mix0 + 1934 OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK); 1935 routes[1] = 1936 (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma + 1937 0x20) & 1938 ADB_MASK); 1939 if (en) { 1940 vortex_adb_addroutes(vortex, ch, routes, 0x2); 1941 vortex_mixer_addWTD(vortex, mix0, ch); 1942 vortex_mixer_addWTD(vortex, mix1, ch); 1943 } else { 1944 vortex_adb_delroutes(vortex, ch, routes[0], routes[1]); 1945 vortex_mixer_delWTD(vortex, mix0, ch); 1946 vortex_mixer_delWTD(vortex, mix1, ch); 1947 } 1948 } 1949 #endif 1950 1951 /* CODEC connect. */ 1952 1953 static void 1954 vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[]) 1955 { 1956 #ifdef CHIP_AU8820 1957 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0)); 1958 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1)); 1959 #else 1960 #if 1 1961 // Connect front channels through EQ. 1962 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0)); 1963 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1)); 1964 /* Lower volume, since EQ has some gain. */ 1965 vortex_mix_setvolumebyte(vortex, mixers[0], 0); 1966 vortex_mix_setvolumebyte(vortex, mixers[1], 0); 1967 vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0)); 1968 vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1)); 1969 1970 /* Check if reg 0x28 has SDAC bit set. */ 1971 if (VORTEX_IS_QUAD(vortex)) { 1972 /* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */ 1973 vortex_connection_mix_adb(vortex, en, 0x11, mixers[2], 1974 ADB_CODECOUT(0 + 4)); 1975 vortex_connection_mix_adb(vortex, en, 0x11, mixers[3], 1976 ADB_CODECOUT(1 + 4)); 1977 /* pr_debug( "SDAC detected "); */ 1978 } 1979 #else 1980 // Use plain direct output to codec. 1981 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0)); 1982 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1)); 1983 #endif 1984 #endif 1985 } 1986 1987 static void 1988 vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0, 1989 unsigned char mixin1) 1990 { 1991 /* 1992 Enable: 0x1, 0x1 1993 Channel: 0x11, 0x11 1994 ADB Source address: 0x48, 0x49 1995 Destination Asp4Topology_0x9c,0x98 1996 */ 1997 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0); 1998 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1); 1999 } 2000 2001 // Higher level ADB audio path (de)allocator. 2002 2003 /* Resource manager */ 2004 static int resnum[VORTEX_RESOURCE_LAST] = 2005 { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D }; 2006 /* 2007 Checkout/Checkin resource of given type. 2008 resmap: resource map to be used. If NULL means that we want to allocate 2009 a DMA resource (root of all other resources of a dma channel). 2010 out: Mean checkout if != 0. Else mean Checkin resource. 2011 restype: Indicates type of resource to be checked in or out. 2012 */ 2013 static char 2014 vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype) 2015 { 2016 int i, qty = resnum[restype], resinuse = 0; 2017 2018 if (out) { 2019 /* Gather used resources by all streams. */ 2020 for (i = 0; i < NR_ADB; i++) { 2021 resinuse |= vortex->dma_adb[i].resources[restype]; 2022 } 2023 resinuse |= vortex->fixed_res[restype]; 2024 /* Find and take free resource. */ 2025 for (i = 0; i < qty; i++) { 2026 if ((resinuse & (1 << i)) == 0) { 2027 if (resmap != NULL) 2028 resmap[restype] |= (1 << i); 2029 else 2030 vortex->dma_adb[i].resources[restype] |= (1 << i); 2031 /* 2032 pr_debug( 2033 "vortex: ResManager: type %d out %d\n", 2034 restype, i); 2035 */ 2036 return i; 2037 } 2038 } 2039 } else { 2040 if (resmap == NULL) 2041 return -EINVAL; 2042 /* Checkin first resource of type restype. */ 2043 for (i = 0; i < qty; i++) { 2044 if (resmap[restype] & (1 << i)) { 2045 resmap[restype] &= ~(1 << i); 2046 /* 2047 pr_debug( 2048 "vortex: ResManager: type %d in %d\n", 2049 restype, i); 2050 */ 2051 return i; 2052 } 2053 } 2054 } 2055 dev_err(vortex->card->dev, 2056 "FATAL: ResManager: resource type %d exhausted.\n", 2057 restype); 2058 return -ENOMEM; 2059 } 2060 2061 /* Default Connections */ 2062 2063 static void vortex_connect_default(vortex_t * vortex, int en) 2064 { 2065 // Connect AC97 codec. 2066 vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, 2067 VORTEX_RESOURCE_MIXOUT); 2068 vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, 2069 VORTEX_RESOURCE_MIXOUT); 2070 if (VORTEX_IS_QUAD(vortex)) { 2071 vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, 2072 VORTEX_RESOURCE_MIXOUT); 2073 vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, 2074 VORTEX_RESOURCE_MIXOUT); 2075 } 2076 vortex_connect_codecplay(vortex, en, vortex->mixplayb); 2077 2078 vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, 2079 VORTEX_RESOURCE_MIXIN); 2080 vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, 2081 VORTEX_RESOURCE_MIXIN); 2082 vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1)); 2083 2084 // Connect SPDIF 2085 #ifndef CHIP_AU8820 2086 vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, 2087 VORTEX_RESOURCE_MIXOUT); 2088 vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en, 2089 VORTEX_RESOURCE_MIXOUT); 2090 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0], 2091 ADB_SPDIFOUT(0)); 2092 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1], 2093 ADB_SPDIFOUT(1)); 2094 #endif 2095 // Connect WT 2096 #ifndef CHIP_AU8810 2097 vortex_wt_connect(vortex, en); 2098 #endif 2099 // A3D (crosstalk canceler and A3D slices). AU8810 disabled for now. 2100 #ifndef CHIP_AU8820 2101 vortex_Vort3D_connect(vortex, en); 2102 #endif 2103 // Connect I2S 2104 2105 // Connect DSP interface for SQ3500 turbo (not here i think...) 2106 2107 // Connect AC98 modem codec 2108 2109 } 2110 2111 /* 2112 Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes 2113 are deallocated. 2114 dma: DMA engine routes to be deallocated when dma >= 0. 2115 nr_ch: Number of channels to be de/allocated. 2116 dir: direction of stream. Uses same values as substream->stream. 2117 type: Type of audio output/source (codec, spdif, i2s, dsp, etc) 2118 Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0. 2119 */ 2120 static int 2121 vortex_adb_allocroute(vortex_t *vortex, int dma, int nr_ch, int dir, 2122 int type, int subdev) 2123 { 2124 stream_t *stream; 2125 int i, en; 2126 struct pcm_vol *p; 2127 2128 if (dma >= 0) { 2129 en = 0; 2130 vortex_adb_checkinout(vortex, 2131 vortex->dma_adb[dma].resources, en, 2132 VORTEX_RESOURCE_DMA); 2133 } else { 2134 en = 1; 2135 if ((dma = 2136 vortex_adb_checkinout(vortex, NULL, en, 2137 VORTEX_RESOURCE_DMA)) < 0) 2138 return -EBUSY; 2139 } 2140 2141 stream = &vortex->dma_adb[dma]; 2142 stream->dma = dma; 2143 stream->dir = dir; 2144 stream->type = type; 2145 2146 /* PLAYBACK ROUTES. */ 2147 if (dir == SNDRV_PCM_STREAM_PLAYBACK) { 2148 int src[4], mix[4], ch_top; 2149 #ifndef CHIP_AU8820 2150 int a3d = 0; 2151 #endif 2152 /* Get SRC and MIXER hardware resources. */ 2153 if (stream->type != VORTEX_PCM_SPDIF) { 2154 for (i = 0; i < nr_ch; i++) { 2155 if ((src[i] = vortex_adb_checkinout(vortex, 2156 stream->resources, en, 2157 VORTEX_RESOURCE_SRC)) < 0) { 2158 memset(stream->resources, 0, 2159 sizeof(stream->resources)); 2160 return -EBUSY; 2161 } 2162 if (stream->type != VORTEX_PCM_A3D) { 2163 if ((mix[i] = vortex_adb_checkinout(vortex, 2164 stream->resources, 2165 en, 2166 VORTEX_RESOURCE_MIXIN)) < 0) { 2167 memset(stream->resources, 2168 0, 2169 sizeof(stream->resources)); 2170 return -EBUSY; 2171 } 2172 } 2173 } 2174 } 2175 #ifndef CHIP_AU8820 2176 if (stream->type == VORTEX_PCM_A3D) { 2177 if ((a3d = 2178 vortex_adb_checkinout(vortex, 2179 stream->resources, en, 2180 VORTEX_RESOURCE_A3D)) < 0) { 2181 memset(stream->resources, 0, 2182 sizeof(stream->resources)); 2183 dev_err(vortex->card->dev, 2184 "out of A3D sources. Sorry\n"); 2185 return -EBUSY; 2186 } 2187 /* (De)Initialize A3D hardware source. */ 2188 vortex_Vort3D_InitializeSource(&vortex->a3d[a3d], en, 2189 vortex); 2190 } 2191 /* Make SPDIF out exclusive to "spdif" device when in use. */ 2192 if ((stream->type == VORTEX_PCM_SPDIF) && (en)) { 2193 vortex_route(vortex, 0, 0x14, 2194 ADB_MIXOUT(vortex->mixspdif[0]), 2195 ADB_SPDIFOUT(0)); 2196 vortex_route(vortex, 0, 0x14, 2197 ADB_MIXOUT(vortex->mixspdif[1]), 2198 ADB_SPDIFOUT(1)); 2199 } 2200 #endif 2201 /* Make playback routes. */ 2202 for (i = 0; i < nr_ch; i++) { 2203 if (stream->type == VORTEX_PCM_ADB) { 2204 vortex_connection_adbdma_src(vortex, en, 2205 src[nr_ch - 1], 2206 dma, 2207 src[i]); 2208 vortex_connection_src_mixin(vortex, en, 2209 0x11, src[i], 2210 mix[i]); 2211 vortex_connection_mixin_mix(vortex, en, 2212 mix[i], 2213 MIX_PLAYB(i), 0); 2214 #ifndef CHIP_AU8820 2215 vortex_connection_mixin_mix(vortex, en, 2216 mix[i], 2217 MIX_SPDIF(i % 2), 0); 2218 vortex_mix_setinputvolumebyte(vortex, 2219 MIX_SPDIF(i % 2), 2220 mix[i], 2221 MIX_DEFIGAIN); 2222 #endif 2223 } 2224 #ifndef CHIP_AU8820 2225 if (stream->type == VORTEX_PCM_A3D) { 2226 vortex_connection_adbdma_src(vortex, en, 2227 src[nr_ch - 1], 2228 dma, 2229 src[i]); 2230 vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d)); 2231 /* XTalk test. */ 2232 //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4)); 2233 //vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_XTALKIN(i?4:9)); 2234 } 2235 if (stream->type == VORTEX_PCM_SPDIF) 2236 vortex_route(vortex, en, 0x14, 2237 ADB_DMA(stream->dma), 2238 ADB_SPDIFOUT(i)); 2239 #endif 2240 } 2241 if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) { 2242 ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2); 2243 for (i = nr_ch; i < ch_top; i++) { 2244 vortex_connection_mixin_mix(vortex, en, 2245 mix[i % nr_ch], 2246 MIX_PLAYB(i), 0); 2247 #ifndef CHIP_AU8820 2248 vortex_connection_mixin_mix(vortex, en, 2249 mix[i % nr_ch], 2250 MIX_SPDIF(i % 2), 2251 0); 2252 vortex_mix_setinputvolumebyte(vortex, 2253 MIX_SPDIF(i % 2), 2254 mix[i % nr_ch], 2255 MIX_DEFIGAIN); 2256 #endif 2257 } 2258 if (stream->type == VORTEX_PCM_ADB && en) { 2259 p = &vortex->pcm_vol[subdev]; 2260 p->dma = dma; 2261 for (i = 0; i < nr_ch; i++) 2262 p->mixin[i] = mix[i]; 2263 for (i = 0; i < ch_top; i++) 2264 p->vol[i] = 0; 2265 } 2266 } 2267 #ifndef CHIP_AU8820 2268 else { 2269 if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF) 2270 vortex_route(vortex, en, 0x14, 2271 ADB_DMA(stream->dma), 2272 ADB_SPDIFOUT(1)); 2273 } 2274 /* Reconnect SPDIF out when "spdif" device is down. */ 2275 if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) { 2276 vortex_route(vortex, 1, 0x14, 2277 ADB_MIXOUT(vortex->mixspdif[0]), 2278 ADB_SPDIFOUT(0)); 2279 vortex_route(vortex, 1, 0x14, 2280 ADB_MIXOUT(vortex->mixspdif[1]), 2281 ADB_SPDIFOUT(1)); 2282 } 2283 #endif 2284 /* CAPTURE ROUTES. */ 2285 } else { 2286 int src[2], mix[2]; 2287 2288 if (nr_ch < 1) 2289 return -EINVAL; 2290 2291 /* Get SRC and MIXER hardware resources. */ 2292 for (i = 0; i < nr_ch; i++) { 2293 if ((mix[i] = 2294 vortex_adb_checkinout(vortex, 2295 stream->resources, en, 2296 VORTEX_RESOURCE_MIXOUT)) 2297 < 0) { 2298 memset(stream->resources, 0, 2299 sizeof(stream->resources)); 2300 return -EBUSY; 2301 } 2302 if ((src[i] = 2303 vortex_adb_checkinout(vortex, 2304 stream->resources, en, 2305 VORTEX_RESOURCE_SRC)) < 0) { 2306 memset(stream->resources, 0, 2307 sizeof(stream->resources)); 2308 return -EBUSY; 2309 } 2310 } 2311 2312 /* Make capture routes. */ 2313 vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0); 2314 vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]); 2315 if (nr_ch == 1) { 2316 vortex_connection_mixin_mix(vortex, en, 2317 MIX_CAPT(1), mix[0], 0); 2318 vortex_connection_src_adbdma(vortex, en, 2319 src[0], 2320 src[0], dma); 2321 } else { 2322 vortex_connection_mixin_mix(vortex, en, 2323 MIX_CAPT(1), mix[1], 0); 2324 vortex_connection_mix_src(vortex, en, 0x11, mix[1], 2325 src[1]); 2326 vortex_connection_src_src_adbdma(vortex, en, 2327 src[1], src[0], 2328 src[1], dma); 2329 } 2330 } 2331 vortex->dma_adb[dma].nr_ch = nr_ch; 2332 2333 #if 0 2334 /* AC97 Codec channel setup. FIXME: this has no effect on some cards !! */ 2335 if (nr_ch < 4) { 2336 /* Copy stereo to rear channel (surround) */ 2337 snd_ac97_write_cache(vortex->codec, 2338 AC97_SIGMATEL_DAC2INVERT, 2339 snd_ac97_read(vortex->codec, 2340 AC97_SIGMATEL_DAC2INVERT) 2341 | 4); 2342 } else { 2343 /* Allow separate front and rear channels. */ 2344 snd_ac97_write_cache(vortex->codec, 2345 AC97_SIGMATEL_DAC2INVERT, 2346 snd_ac97_read(vortex->codec, 2347 AC97_SIGMATEL_DAC2INVERT) 2348 & ~((u32) 2349 4)); 2350 } 2351 #endif 2352 return dma; 2353 } 2354 2355 /* 2356 Set the SampleRate of the SRC's attached to the given DMA engine. 2357 */ 2358 static void 2359 vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir) 2360 { 2361 stream_t *stream = &(vortex->dma_adb[adbdma]); 2362 int i, cvrt; 2363 2364 /* dir=1:play ; dir=0:rec */ 2365 if (dir) 2366 cvrt = SRC_RATIO(rate, 48000); 2367 else 2368 cvrt = SRC_RATIO(48000, rate); 2369 2370 /* Setup SRC's */ 2371 for (i = 0; i < NR_SRC; i++) { 2372 if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i)) 2373 vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir); 2374 } 2375 } 2376 2377 // Timer and ISR functions. 2378 2379 static void vortex_settimer(vortex_t * vortex, int period) 2380 { 2381 //set the timer period to <period> 48000ths of a second. 2382 hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period); 2383 } 2384 2385 #if 0 2386 static void vortex_enable_timer_int(vortex_t * card) 2387 { 2388 hwwrite(card->mmio, VORTEX_IRQ_CTRL, 2389 hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60); 2390 } 2391 2392 static void vortex_disable_timer_int(vortex_t * card) 2393 { 2394 hwwrite(card->mmio, VORTEX_IRQ_CTRL, 2395 hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER); 2396 } 2397 2398 #endif 2399 static void vortex_enable_int(vortex_t * card) 2400 { 2401 // CAsp4ISR__EnableVortexInt_void_ 2402 hwwrite(card->mmio, VORTEX_CTRL, 2403 hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE); 2404 hwwrite(card->mmio, VORTEX_IRQ_CTRL, 2405 (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24); 2406 } 2407 2408 static void vortex_disable_int(vortex_t * card) 2409 { 2410 hwwrite(card->mmio, VORTEX_CTRL, 2411 hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE); 2412 } 2413 2414 static irqreturn_t vortex_interrupt(int irq, void *dev_id) 2415 { 2416 vortex_t *vortex = dev_id; 2417 int i, handled; 2418 u32 source; 2419 2420 //check if the interrupt is ours. 2421 if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1)) 2422 return IRQ_NONE; 2423 2424 // This is the Interrupt Enable flag we set before (consistency check). 2425 if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE)) 2426 return IRQ_NONE; 2427 2428 source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE); 2429 // Reset IRQ flags. 2430 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source); 2431 hwread(vortex->mmio, VORTEX_IRQ_SOURCE); 2432 // Is at least one IRQ flag set? 2433 if (source == 0) { 2434 dev_err(vortex->card->dev, "missing irq source\n"); 2435 return IRQ_NONE; 2436 } 2437 2438 handled = 0; 2439 // Attend every interrupt source. 2440 if (unlikely(source & IRQ_ERR_MASK)) { 2441 if (source & IRQ_FATAL) { 2442 dev_err(vortex->card->dev, "IRQ fatal error\n"); 2443 } 2444 if (source & IRQ_PARITY) { 2445 dev_err(vortex->card->dev, "IRQ parity error\n"); 2446 } 2447 if (source & IRQ_REG) { 2448 dev_err(vortex->card->dev, "IRQ reg error\n"); 2449 } 2450 if (source & IRQ_FIFO) { 2451 dev_err(vortex->card->dev, "IRQ fifo error\n"); 2452 } 2453 if (source & IRQ_DMA) { 2454 dev_err(vortex->card->dev, "IRQ dma error\n"); 2455 } 2456 handled = 1; 2457 } 2458 if (source & IRQ_PCMOUT) { 2459 /* ALSA period acknowledge. */ 2460 spin_lock(&vortex->lock); 2461 for (i = 0; i < NR_ADB; i++) { 2462 if (vortex->dma_adb[i].fifo_status == FIFO_START) { 2463 if (!vortex_adbdma_bufshift(vortex, i)) 2464 continue; 2465 spin_unlock(&vortex->lock); 2466 snd_pcm_period_elapsed(vortex->dma_adb[i]. 2467 substream); 2468 spin_lock(&vortex->lock); 2469 } 2470 } 2471 #ifndef CHIP_AU8810 2472 for (i = 0; i < NR_WT; i++) { 2473 if (vortex->dma_wt[i].fifo_status == FIFO_START) { 2474 /* FIXME: we ignore the return value from 2475 * vortex_wtdma_bufshift() below as the delta 2476 * calculation seems not working for wavetable 2477 * by some reason 2478 */ 2479 vortex_wtdma_bufshift(vortex, i); 2480 spin_unlock(&vortex->lock); 2481 snd_pcm_period_elapsed(vortex->dma_wt[i]. 2482 substream); 2483 spin_lock(&vortex->lock); 2484 } 2485 } 2486 #endif 2487 spin_unlock(&vortex->lock); 2488 handled = 1; 2489 } 2490 //Acknowledge the Timer interrupt 2491 if (source & IRQ_TIMER) { 2492 hwread(vortex->mmio, VORTEX_IRQ_STAT); 2493 handled = 1; 2494 } 2495 if ((source & IRQ_MIDI) && vortex->rmidi) { 2496 snd_mpu401_uart_interrupt(vortex->irq, 2497 vortex->rmidi->private_data); 2498 handled = 1; 2499 } 2500 2501 if (!handled) { 2502 dev_err(vortex->card->dev, "unknown irq source %x\n", source); 2503 } 2504 return IRQ_RETVAL(handled); 2505 } 2506 2507 /* Codec */ 2508 2509 #define POLL_COUNT 1000 2510 static void vortex_codec_init(vortex_t * vortex) 2511 { 2512 int i; 2513 2514 for (i = 0; i < 32; i++) { 2515 /* the windows driver writes -i, so we write -i */ 2516 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i); 2517 msleep(2); 2518 } 2519 if (0) { 2520 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068); 2521 msleep(1); 2522 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8); 2523 msleep(1); 2524 } else { 2525 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8); 2526 msleep(2); 2527 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8); 2528 msleep(2); 2529 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8); 2530 msleep(2); 2531 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8); 2532 msleep(2); 2533 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8); 2534 msleep(2); 2535 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8); 2536 } 2537 for (i = 0; i < 32; i++) { 2538 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i); 2539 msleep(5); 2540 } 2541 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8); 2542 msleep(1); 2543 /* Enable codec channels 0 and 1. */ 2544 hwwrite(vortex->mmio, VORTEX_CODEC_EN, 2545 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC); 2546 } 2547 2548 static void 2549 vortex_codec_write(struct snd_ac97 * codec, unsigned short addr, unsigned short data) 2550 { 2551 2552 vortex_t *card = (vortex_t *) codec->private_data; 2553 unsigned int lifeboat = 0; 2554 2555 /* wait for transactions to clear */ 2556 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { 2557 udelay(100); 2558 if (lifeboat++ > POLL_COUNT) { 2559 dev_err(card->card->dev, "ac97 codec stuck busy\n"); 2560 return; 2561 } 2562 } 2563 /* write register */ 2564 hwwrite(card->mmio, VORTEX_CODEC_IO, 2565 ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) | 2566 ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) | 2567 VORTEX_CODEC_WRITE | 2568 (codec->num << VORTEX_CODEC_ID_SHIFT) ); 2569 2570 /* Flush Caches. */ 2571 hwread(card->mmio, VORTEX_CODEC_IO); 2572 } 2573 2574 static unsigned short vortex_codec_read(struct snd_ac97 * codec, unsigned short addr) 2575 { 2576 2577 vortex_t *card = (vortex_t *) codec->private_data; 2578 u32 read_addr, data; 2579 unsigned lifeboat = 0; 2580 2581 /* wait for transactions to clear */ 2582 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) { 2583 udelay(100); 2584 if (lifeboat++ > POLL_COUNT) { 2585 dev_err(card->card->dev, "ac97 codec stuck busy\n"); 2586 return 0xffff; 2587 } 2588 } 2589 /* set up read address */ 2590 read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) | 2591 (codec->num << VORTEX_CODEC_ID_SHIFT) ; 2592 hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr); 2593 2594 /* wait for address */ 2595 do { 2596 udelay(100); 2597 data = hwread(card->mmio, VORTEX_CODEC_IO); 2598 if (lifeboat++ > POLL_COUNT) { 2599 dev_err(card->card->dev, 2600 "ac97 address never arrived\n"); 2601 return 0xffff; 2602 } 2603 } while ((data & VORTEX_CODEC_ADDMASK) != 2604 (addr << VORTEX_CODEC_ADDSHIFT)); 2605 2606 /* return data. */ 2607 return (u16) (data & VORTEX_CODEC_DATMASK); 2608 } 2609 2610 /* SPDIF support */ 2611 2612 static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode) 2613 { 2614 int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0; 2615 2616 /* CAsp4Spdif::InitializeSpdifHardware(void) */ 2617 hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS, 2618 hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd); 2619 //for (i=0x291D4; i<0x29200; i+=4) 2620 for (i = 0; i < 11; i++) 2621 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0); 2622 //hwwrite(vortex->mmio, 0x29190, hwread(vortex->mmio, 0x29190) | 0xc0000); 2623 hwwrite(vortex->mmio, VORTEX_CODEC_EN, 2624 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF); 2625 2626 /* CAsp4Spdif::ProgramSRCInHardware(enum SPDIF_SR,enum SPDIFMODE) */ 2627 if (this_04 && this_08) { 2628 int edi; 2629 2630 i = (((0x5DC00000 / spdif_sr) + 1) >> 1); 2631 if (i > 0x800) { 2632 if (i < 0x1ffff) 2633 edi = (i >> 1); 2634 else 2635 edi = 0x1ffff; 2636 } else { 2637 edi = 0x800; 2638 } 2639 /* this_04 and this_08 are the CASp4Src's (samplerate converters) */ 2640 vortex_src_setupchannel(vortex, this_04, edi, 0, 1, 2641 this_0c, 1, 0, edi, 1); 2642 vortex_src_setupchannel(vortex, this_08, edi, 0, 1, 2643 this_0c, 1, 0, edi, 1); 2644 } 2645 2646 i = spdif_sr; 2647 spdif_sr |= 0x8c; 2648 switch (i) { 2649 case 32000: 2650 this_38 &= 0xFFFFFFFE; 2651 this_38 &= 0xFFFFFFFD; 2652 this_38 &= 0xF3FFFFFF; 2653 this_38 |= 0x03000000; /* set 32khz samplerate */ 2654 this_38 &= 0xFFFFFF3F; 2655 spdif_sr &= 0xFFFFFFFD; 2656 spdif_sr |= 1; 2657 break; 2658 case 44100: 2659 this_38 &= 0xFFFFFFFE; 2660 this_38 &= 0xFFFFFFFD; 2661 this_38 &= 0xF0FFFFFF; 2662 this_38 |= 0x03000000; 2663 this_38 &= 0xFFFFFF3F; 2664 spdif_sr &= 0xFFFFFFFC; 2665 break; 2666 case 48000: 2667 if (spdif_mode == 1) { 2668 this_38 &= 0xFFFFFFFE; 2669 this_38 &= 0xFFFFFFFD; 2670 this_38 &= 0xF2FFFFFF; 2671 this_38 |= 0x02000000; /* set 48khz samplerate */ 2672 this_38 &= 0xFFFFFF3F; 2673 } else { 2674 /* J. Gordon Wolfe: I think this stuff is for AC3 */ 2675 this_38 |= 0x00000003; 2676 this_38 &= 0xFFFFFFBF; 2677 this_38 |= 0x80; 2678 } 2679 spdif_sr |= 2; 2680 spdif_sr &= 0xFFFFFFFE; 2681 break; 2682 2683 } 2684 /* looks like the next 2 lines transfer a 16-bit value into 2 8-bit 2685 registers. seems to be for the standard IEC/SPDIF initialization 2686 stuff */ 2687 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff); 2688 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10); 2689 hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr); 2690 } 2691 2692 /* Initialization */ 2693 2694 static int vortex_core_init(vortex_t *vortex) 2695 { 2696 2697 dev_info(vortex->card->dev, "init started\n"); 2698 /* Hardware Init. */ 2699 hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff); 2700 msleep(5); 2701 hwwrite(vortex->mmio, VORTEX_CTRL, 2702 hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff); 2703 msleep(5); 2704 /* Reset IRQ flags */ 2705 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff); 2706 hwread(vortex->mmio, VORTEX_IRQ_STAT); 2707 2708 vortex_codec_init(vortex); 2709 2710 #ifdef CHIP_AU8830 2711 hwwrite(vortex->mmio, VORTEX_CTRL, 2712 hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000); 2713 #endif 2714 2715 /* Init audio engine. */ 2716 vortex_adbdma_init(vortex); 2717 hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58 2718 vortex_adb_init(vortex); 2719 /* Init processing blocks. */ 2720 vortex_fifo_init(vortex); 2721 vortex_mixer_init(vortex); 2722 vortex_srcblock_init(vortex); 2723 #ifndef CHIP_AU8820 2724 vortex_eq_init(vortex); 2725 vortex_spdif_init(vortex, 48000, 1); 2726 vortex_Vort3D_enable(vortex); 2727 #endif 2728 #ifndef CHIP_AU8810 2729 vortex_wt_init(vortex); 2730 #endif 2731 // Moved to au88x0.c 2732 //vortex_connect_default(vortex, 1); 2733 2734 vortex_settimer(vortex, 0x90); 2735 // Enable Interrupts. 2736 // vortex_enable_int() must be first !! 2737 // hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0); 2738 // vortex_enable_int(vortex); 2739 //vortex_enable_timer_int(vortex); 2740 //vortex_disable_timer_int(vortex); 2741 2742 dev_info(vortex->card->dev, "init.... done.\n"); 2743 spin_lock_init(&vortex->lock); 2744 2745 return 0; 2746 } 2747 2748 static int vortex_core_shutdown(vortex_t * vortex) 2749 { 2750 2751 dev_info(vortex->card->dev, "shutdown started\n"); 2752 #ifndef CHIP_AU8820 2753 vortex_eq_free(vortex); 2754 vortex_Vort3D_disable(vortex); 2755 #endif 2756 //vortex_disable_timer_int(vortex); 2757 vortex_disable_int(vortex); 2758 vortex_connect_default(vortex, 0); 2759 /* Reset all DMA fifos. */ 2760 vortex_fifo_init(vortex); 2761 /* Erase all audio routes. */ 2762 vortex_adb_init(vortex); 2763 2764 /* Disable MPU401 */ 2765 //hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI); 2766 //hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN); 2767 2768 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0); 2769 hwwrite(vortex->mmio, VORTEX_CTRL, 0); 2770 msleep(5); 2771 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff); 2772 2773 dev_info(vortex->card->dev, "shutdown.... done.\n"); 2774 return 0; 2775 } 2776 2777 /* Alsa support. */ 2778 2779 static int vortex_alsafmt_aspfmt(snd_pcm_format_t alsafmt, vortex_t *v) 2780 { 2781 int fmt; 2782 2783 switch (alsafmt) { 2784 case SNDRV_PCM_FORMAT_U8: 2785 fmt = 0x1; 2786 break; 2787 case SNDRV_PCM_FORMAT_MU_LAW: 2788 fmt = 0x2; 2789 break; 2790 case SNDRV_PCM_FORMAT_A_LAW: 2791 fmt = 0x3; 2792 break; 2793 case SNDRV_PCM_FORMAT_SPECIAL: 2794 fmt = 0x4; /* guess. */ 2795 break; 2796 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 2797 fmt = 0x5; /* guess. */ 2798 break; 2799 case SNDRV_PCM_FORMAT_S16_LE: 2800 fmt = 0x8; 2801 break; 2802 case SNDRV_PCM_FORMAT_S16_BE: 2803 fmt = 0x9; /* check this... */ 2804 break; 2805 default: 2806 fmt = 0x8; 2807 dev_err(v->card->dev, 2808 "format unsupported %d\n", alsafmt); 2809 break; 2810 } 2811 return fmt; 2812 } 2813 2814 /* Some not yet useful translations. */ 2815 #if 0 2816 typedef enum { 2817 ASPFMTLINEAR16 = 0, /* 0x8 */ 2818 ASPFMTLINEAR8, /* 0x1 */ 2819 ASPFMTULAW, /* 0x2 */ 2820 ASPFMTALAW, /* 0x3 */ 2821 ASPFMTSPORT, /* ? */ 2822 ASPFMTSPDIF, /* ? */ 2823 } ASPENCODING; 2824 2825 static int 2826 vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod) 2827 { 2828 int a, this_194; 2829 2830 if ((bits != 8) && (bits != 16)) 2831 return -1; 2832 2833 switch (encod) { 2834 case 0: 2835 if (bits == 0x10) 2836 a = 8; // 16 bit 2837 break; 2838 case 1: 2839 if (bits == 8) 2840 a = 1; // 8 bit 2841 break; 2842 case 2: 2843 a = 2; // U_LAW 2844 break; 2845 case 3: 2846 a = 3; // A_LAW 2847 break; 2848 } 2849 switch (nch) { 2850 case 1: 2851 this_194 = 0; 2852 break; 2853 case 2: 2854 this_194 = 1; 2855 break; 2856 case 4: 2857 this_194 = 1; 2858 break; 2859 case 6: 2860 this_194 = 1; 2861 break; 2862 } 2863 return (a); 2864 } 2865 2866 static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch) 2867 { 2868 short int d, this_148; 2869 2870 d = ((bits >> 3) * nch); 2871 this_148 = 0xbb80 / d; 2872 } 2873 #endif 2874