1 /* 2 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers 3 * 4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 #include <linux/io.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/pci.h> 27 #include <linux/slab.h> 28 #include <linux/module.h> 29 #include <linux/mutex.h> 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/info.h> 34 #include <sound/ac97_codec.h> 35 #include <sound/initval.h> 36 37 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 38 MODULE_DESCRIPTION("ATI IXP AC97 controller"); 39 MODULE_LICENSE("GPL"); 40 MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400/600}}"); 41 42 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 43 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 44 static int ac97_clock = 48000; 45 static char *ac97_quirk; 46 static bool spdif_aclink = 1; 47 static int ac97_codec = -1; 48 49 module_param(index, int, 0444); 50 MODULE_PARM_DESC(index, "Index value for ATI IXP controller."); 51 module_param(id, charp, 0444); 52 MODULE_PARM_DESC(id, "ID string for ATI IXP controller."); 53 module_param(ac97_clock, int, 0444); 54 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz)."); 55 module_param(ac97_quirk, charp, 0444); 56 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 57 module_param(ac97_codec, int, 0444); 58 MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing."); 59 module_param(spdif_aclink, bool, 0444); 60 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 61 62 /* just for backward compatibility */ 63 static bool enable; 64 module_param(enable, bool, 0444); 65 66 67 /* 68 */ 69 70 #define ATI_REG_ISR 0x00 /* interrupt source */ 71 #define ATI_REG_ISR_IN_XRUN (1U<<0) 72 #define ATI_REG_ISR_IN_STATUS (1U<<1) 73 #define ATI_REG_ISR_OUT_XRUN (1U<<2) 74 #define ATI_REG_ISR_OUT_STATUS (1U<<3) 75 #define ATI_REG_ISR_SPDF_XRUN (1U<<4) 76 #define ATI_REG_ISR_SPDF_STATUS (1U<<5) 77 #define ATI_REG_ISR_PHYS_INTR (1U<<8) 78 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) 79 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) 80 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) 81 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) 82 #define ATI_REG_ISR_NEW_FRAME (1U<<13) 83 84 #define ATI_REG_IER 0x04 /* interrupt enable */ 85 #define ATI_REG_IER_IN_XRUN_EN (1U<<0) 86 #define ATI_REG_IER_IO_STATUS_EN (1U<<1) 87 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2) 88 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3) 89 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4) 90 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5) 91 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8) 92 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) 93 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) 94 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) 95 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) 96 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */ 97 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */ 98 99 #define ATI_REG_CMD 0x08 /* command */ 100 #define ATI_REG_CMD_POWERDOWN (1U<<0) 101 #define ATI_REG_CMD_RECEIVE_EN (1U<<1) 102 #define ATI_REG_CMD_SEND_EN (1U<<2) 103 #define ATI_REG_CMD_STATUS_MEM (1U<<3) 104 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4) 105 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5) 106 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6) 107 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6 108 #define ATI_REG_CMD_IN_DMA_EN (1U<<8) 109 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9) 110 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10) 111 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11) 112 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12) 113 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12) 114 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12) 115 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12) 116 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12) 117 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16) 118 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) 119 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21) 120 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22) 121 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23) 122 #define ATI_REG_CMD_PACKED_DIS (1U<<24) 123 #define ATI_REG_CMD_BURST_EN (1U<<25) 124 #define ATI_REG_CMD_PANIC_EN (1U<<26) 125 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27) 126 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) 127 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) 128 #define ATI_REG_CMD_AC_SYNC (1U<<30) 129 #define ATI_REG_CMD_AC_RESET (1U<<31) 130 131 #define ATI_REG_PHYS_OUT_ADDR 0x0c 132 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) 133 #define ATI_REG_PHYS_OUT_RW (1U<<2) 134 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) 135 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 136 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16 137 138 #define ATI_REG_PHYS_IN_ADDR 0x10 139 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) 140 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9 141 #define ATI_REG_PHYS_IN_DATA_SHIFT 16 142 143 #define ATI_REG_SLOTREQ 0x14 144 145 #define ATI_REG_COUNTER 0x18 146 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ 147 #define ATI_REG_COUNTER_BITCLOCK (31U<<8) 148 149 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c 150 151 #define ATI_REG_IN_DMA_LINKPTR 0x20 152 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */ 153 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */ 154 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */ 155 #define ATI_REG_IN_DMA_DT_SIZE 0x30 156 157 #define ATI_REG_OUT_DMA_SLOT 0x34 158 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3)) 159 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff 160 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800 161 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11 162 163 #define ATI_REG_OUT_DMA_LINKPTR 0x38 164 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */ 165 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */ 166 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */ 167 #define ATI_REG_OUT_DMA_DT_SIZE 0x48 168 169 #define ATI_REG_SPDF_CMD 0x4c 170 #define ATI_REG_SPDF_CMD_LFSR (1U<<4) 171 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5) 172 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */ 173 174 #define ATI_REG_SPDF_DMA_LINKPTR 0x50 175 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */ 176 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */ 177 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */ 178 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60 179 180 #define ATI_REG_MODEM_MIRROR 0x7c 181 #define ATI_REG_AUDIO_MIRROR 0x80 182 183 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */ 184 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */ 185 186 #define ATI_REG_FIFO_FLUSH 0x88 187 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0) 188 #define ATI_REG_FIFO_IN_FLUSH (1U<<1) 189 190 /* LINKPTR */ 191 #define ATI_REG_LINKPTR_EN (1U<<0) 192 193 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */ 194 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0) 195 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16) 196 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21) 197 #define ATI_REG_DMA_STATE (7U<<26) 198 199 200 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */ 201 202 203 struct atiixp; 204 205 /* 206 * DMA packate descriptor 207 */ 208 209 struct atiixp_dma_desc { 210 u32 addr; /* DMA buffer address */ 211 u16 status; /* status bits */ 212 u16 size; /* size of the packet in dwords */ 213 u32 next; /* address of the next packet descriptor */ 214 }; 215 216 /* 217 * stream enum 218 */ 219 enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */ 220 enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */ 221 enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */ 222 223 #define NUM_ATI_CODECS 3 224 225 226 /* 227 * constants and callbacks for each DMA type 228 */ 229 struct atiixp_dma_ops { 230 int type; /* ATI_DMA_XXX */ 231 unsigned int llp_offset; /* LINKPTR offset */ 232 unsigned int dt_cur; /* DT_CUR offset */ 233 /* called from open callback */ 234 void (*enable_dma)(struct atiixp *chip, int on); 235 /* called from trigger (START/STOP) */ 236 void (*enable_transfer)(struct atiixp *chip, int on); 237 /* called from trigger (STOP only) */ 238 void (*flush_dma)(struct atiixp *chip); 239 }; 240 241 /* 242 * DMA stream 243 */ 244 struct atiixp_dma { 245 const struct atiixp_dma_ops *ops; 246 struct snd_dma_buffer desc_buf; 247 struct snd_pcm_substream *substream; /* assigned PCM substream */ 248 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */ 249 unsigned int period_bytes, periods; 250 int opened; 251 int running; 252 int suspended; 253 int pcm_open_flag; 254 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */ 255 unsigned int saved_curptr; 256 }; 257 258 /* 259 * ATI IXP chip 260 */ 261 struct atiixp { 262 struct snd_card *card; 263 struct pci_dev *pci; 264 265 unsigned long addr; 266 void __iomem *remap_addr; 267 int irq; 268 269 struct snd_ac97_bus *ac97_bus; 270 struct snd_ac97 *ac97[NUM_ATI_CODECS]; 271 272 spinlock_t reg_lock; 273 274 struct atiixp_dma dmas[NUM_ATI_DMAS]; 275 struct ac97_pcm *pcms[NUM_ATI_PCMS]; 276 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS]; 277 278 int max_channels; /* max. channels for PCM out */ 279 280 unsigned int codec_not_ready_bits; /* for codec detection */ 281 282 int spdif_over_aclink; /* passed from the module option */ 283 struct mutex open_mutex; /* playback open mutex */ 284 }; 285 286 287 /* 288 */ 289 static const struct pci_device_id snd_atiixp_ids[] = { 290 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */ 291 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */ 292 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */ 293 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */ 294 { 0, } 295 }; 296 297 MODULE_DEVICE_TABLE(pci, snd_atiixp_ids); 298 299 static struct snd_pci_quirk atiixp_quirks[] = { 300 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0), 301 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0), 302 { } /* terminator */ 303 }; 304 305 /* 306 * lowlevel functions 307 */ 308 309 /* 310 * update the bits of the given register. 311 * return 1 if the bits changed. 312 */ 313 static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg, 314 unsigned int mask, unsigned int value) 315 { 316 void __iomem *addr = chip->remap_addr + reg; 317 unsigned int data, old_data; 318 old_data = data = readl(addr); 319 data &= ~mask; 320 data |= value; 321 if (old_data == data) 322 return 0; 323 writel(data, addr); 324 return 1; 325 } 326 327 /* 328 * macros for easy use 329 */ 330 #define atiixp_write(chip,reg,value) \ 331 writel(value, chip->remap_addr + ATI_REG_##reg) 332 #define atiixp_read(chip,reg) \ 333 readl(chip->remap_addr + ATI_REG_##reg) 334 #define atiixp_update(chip,reg,mask,val) \ 335 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) 336 337 /* 338 * handling DMA packets 339 * 340 * we allocate a linear buffer for the DMA, and split it to each packet. 341 * in a future version, a scatter-gather buffer should be implemented. 342 */ 343 344 #define ATI_DESC_LIST_SIZE \ 345 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc)) 346 347 /* 348 * build packets ring for the given buffer size. 349 * 350 * IXP handles the buffer descriptors, which are connected as a linked 351 * list. although we can change the list dynamically, in this version, 352 * a static RING of buffer descriptors is used. 353 * 354 * the ring is built in this function, and is set up to the hardware. 355 */ 356 static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma, 357 struct snd_pcm_substream *substream, 358 unsigned int periods, 359 unsigned int period_bytes) 360 { 361 unsigned int i; 362 u32 addr, desc_addr; 363 unsigned long flags; 364 365 if (periods > ATI_MAX_DESCRIPTORS) 366 return -ENOMEM; 367 368 if (dma->desc_buf.area == NULL) { 369 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 370 snd_dma_pci_data(chip->pci), 371 ATI_DESC_LIST_SIZE, 372 &dma->desc_buf) < 0) 373 return -ENOMEM; 374 dma->period_bytes = dma->periods = 0; /* clear */ 375 } 376 377 if (dma->periods == periods && dma->period_bytes == period_bytes) 378 return 0; 379 380 /* reset DMA before changing the descriptor table */ 381 spin_lock_irqsave(&chip->reg_lock, flags); 382 writel(0, chip->remap_addr + dma->ops->llp_offset); 383 dma->ops->enable_dma(chip, 0); 384 dma->ops->enable_dma(chip, 1); 385 spin_unlock_irqrestore(&chip->reg_lock, flags); 386 387 /* fill the entries */ 388 addr = (u32)substream->runtime->dma_addr; 389 desc_addr = (u32)dma->desc_buf.addr; 390 for (i = 0; i < periods; i++) { 391 struct atiixp_dma_desc *desc; 392 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i]; 393 desc->addr = cpu_to_le32(addr); 394 desc->status = 0; 395 desc->size = period_bytes >> 2; /* in dwords */ 396 desc_addr += sizeof(struct atiixp_dma_desc); 397 if (i == periods - 1) 398 desc->next = cpu_to_le32((u32)dma->desc_buf.addr); 399 else 400 desc->next = cpu_to_le32(desc_addr); 401 addr += period_bytes; 402 } 403 404 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, 405 chip->remap_addr + dma->ops->llp_offset); 406 407 dma->period_bytes = period_bytes; 408 dma->periods = periods; 409 410 return 0; 411 } 412 413 /* 414 * remove the ring buffer and release it if assigned 415 */ 416 static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma, 417 struct snd_pcm_substream *substream) 418 { 419 if (dma->desc_buf.area) { 420 writel(0, chip->remap_addr + dma->ops->llp_offset); 421 snd_dma_free_pages(&dma->desc_buf); 422 dma->desc_buf.area = NULL; 423 } 424 } 425 426 /* 427 * AC97 interface 428 */ 429 static int snd_atiixp_acquire_codec(struct atiixp *chip) 430 { 431 int timeout = 1000; 432 433 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) { 434 if (! timeout--) { 435 dev_warn(chip->card->dev, "codec acquire timeout\n"); 436 return -EBUSY; 437 } 438 udelay(1); 439 } 440 return 0; 441 } 442 443 static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg) 444 { 445 unsigned int data; 446 int timeout; 447 448 if (snd_atiixp_acquire_codec(chip) < 0) 449 return 0xffff; 450 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 451 ATI_REG_PHYS_OUT_ADDR_EN | 452 ATI_REG_PHYS_OUT_RW | 453 codec; 454 atiixp_write(chip, PHYS_OUT_ADDR, data); 455 if (snd_atiixp_acquire_codec(chip) < 0) 456 return 0xffff; 457 timeout = 1000; 458 do { 459 data = atiixp_read(chip, PHYS_IN_ADDR); 460 if (data & ATI_REG_PHYS_IN_READ_FLAG) 461 return data >> ATI_REG_PHYS_IN_DATA_SHIFT; 462 udelay(1); 463 } while (--timeout); 464 /* time out may happen during reset */ 465 if (reg < 0x7c) 466 dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg); 467 return 0xffff; 468 } 469 470 471 static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec, 472 unsigned short reg, unsigned short val) 473 { 474 unsigned int data; 475 476 if (snd_atiixp_acquire_codec(chip) < 0) 477 return; 478 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | 479 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 480 ATI_REG_PHYS_OUT_ADDR_EN | codec; 481 atiixp_write(chip, PHYS_OUT_ADDR, data); 482 } 483 484 485 static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97, 486 unsigned short reg) 487 { 488 struct atiixp *chip = ac97->private_data; 489 return snd_atiixp_codec_read(chip, ac97->num, reg); 490 491 } 492 493 static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 494 unsigned short val) 495 { 496 struct atiixp *chip = ac97->private_data; 497 snd_atiixp_codec_write(chip, ac97->num, reg, val); 498 } 499 500 /* 501 * reset AC link 502 */ 503 static int snd_atiixp_aclink_reset(struct atiixp *chip) 504 { 505 int timeout; 506 507 /* reset powerdoewn */ 508 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0)) 509 udelay(10); 510 511 /* perform a software reset */ 512 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET); 513 atiixp_read(chip, CMD); 514 udelay(10); 515 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0); 516 517 timeout = 10; 518 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) { 519 /* do a hard reset */ 520 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, 521 ATI_REG_CMD_AC_SYNC); 522 atiixp_read(chip, CMD); 523 mdelay(1); 524 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET); 525 if (!--timeout) { 526 dev_err(chip->card->dev, "codec reset timeout\n"); 527 break; 528 } 529 } 530 531 /* deassert RESET and assert SYNC to make sure */ 532 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, 533 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET); 534 535 return 0; 536 } 537 538 #ifdef CONFIG_PM_SLEEP 539 static int snd_atiixp_aclink_down(struct atiixp *chip) 540 { 541 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */ 542 // return -EBUSY; 543 atiixp_update(chip, CMD, 544 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET, 545 ATI_REG_CMD_POWERDOWN); 546 return 0; 547 } 548 #endif 549 550 /* 551 * auto-detection of codecs 552 * 553 * the IXP chip can generate interrupts for the non-existing codecs. 554 * NEW_FRAME interrupt is used to make sure that the interrupt is generated 555 * even if all three codecs are connected. 556 */ 557 558 #define ALL_CODEC_NOT_READY \ 559 (ATI_REG_ISR_CODEC0_NOT_READY |\ 560 ATI_REG_ISR_CODEC1_NOT_READY |\ 561 ATI_REG_ISR_CODEC2_NOT_READY) 562 #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME) 563 564 static int ac97_probing_bugs(struct pci_dev *pci) 565 { 566 const struct snd_pci_quirk *q; 567 568 q = snd_pci_quirk_lookup(pci, atiixp_quirks); 569 if (q) { 570 dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n", 571 snd_pci_quirk_name(q), q->value); 572 return q->value; 573 } 574 /* this hardware doesn't need workarounds. Probe for codec */ 575 return -1; 576 } 577 578 static int snd_atiixp_codec_detect(struct atiixp *chip) 579 { 580 int timeout; 581 582 chip->codec_not_ready_bits = 0; 583 if (ac97_codec == -1) 584 ac97_codec = ac97_probing_bugs(chip->pci); 585 if (ac97_codec >= 0) { 586 chip->codec_not_ready_bits |= 587 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10)); 588 return 0; 589 } 590 591 atiixp_write(chip, IER, CODEC_CHECK_BITS); 592 /* wait for the interrupts */ 593 timeout = 50; 594 while (timeout-- > 0) { 595 mdelay(1); 596 if (chip->codec_not_ready_bits) 597 break; 598 } 599 atiixp_write(chip, IER, 0); /* disable irqs */ 600 601 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) { 602 dev_err(chip->card->dev, "no codec detected!\n"); 603 return -ENXIO; 604 } 605 return 0; 606 } 607 608 609 /* 610 * enable DMA and irqs 611 */ 612 static int snd_atiixp_chip_start(struct atiixp *chip) 613 { 614 unsigned int reg; 615 616 /* set up spdif, enable burst mode */ 617 reg = atiixp_read(chip, CMD); 618 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT; 619 reg |= ATI_REG_CMD_BURST_EN; 620 atiixp_write(chip, CMD, reg); 621 622 reg = atiixp_read(chip, SPDF_CMD); 623 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH); 624 atiixp_write(chip, SPDF_CMD, reg); 625 626 /* clear all interrupt source */ 627 atiixp_write(chip, ISR, 0xffffffff); 628 /* enable irqs */ 629 atiixp_write(chip, IER, 630 ATI_REG_IER_IO_STATUS_EN | 631 ATI_REG_IER_IN_XRUN_EN | 632 ATI_REG_IER_OUT_XRUN_EN | 633 ATI_REG_IER_SPDF_XRUN_EN | 634 ATI_REG_IER_SPDF_STATUS_EN); 635 return 0; 636 } 637 638 639 /* 640 * disable DMA and IRQs 641 */ 642 static int snd_atiixp_chip_stop(struct atiixp *chip) 643 { 644 /* clear interrupt source */ 645 atiixp_write(chip, ISR, atiixp_read(chip, ISR)); 646 /* disable irqs */ 647 atiixp_write(chip, IER, 0); 648 return 0; 649 } 650 651 652 /* 653 * PCM section 654 */ 655 656 /* 657 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current 658 * position. when SG-buffer is implemented, the offset must be calculated 659 * correctly... 660 */ 661 static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream) 662 { 663 struct atiixp *chip = snd_pcm_substream_chip(substream); 664 struct snd_pcm_runtime *runtime = substream->runtime; 665 struct atiixp_dma *dma = runtime->private_data; 666 unsigned int curptr; 667 int timeout = 1000; 668 669 while (timeout--) { 670 curptr = readl(chip->remap_addr + dma->ops->dt_cur); 671 if (curptr < dma->buf_addr) 672 continue; 673 curptr -= dma->buf_addr; 674 if (curptr >= dma->buf_bytes) 675 continue; 676 return bytes_to_frames(runtime, curptr); 677 } 678 dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n", 679 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr); 680 return 0; 681 } 682 683 /* 684 * XRUN detected, and stop the PCM substream 685 */ 686 static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma) 687 { 688 if (! dma->substream || ! dma->running) 689 return; 690 dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type); 691 snd_pcm_stop_xrun(dma->substream); 692 } 693 694 /* 695 * the period ack. update the substream. 696 */ 697 static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma) 698 { 699 if (! dma->substream || ! dma->running) 700 return; 701 snd_pcm_period_elapsed(dma->substream); 702 } 703 704 /* set BUS_BUSY interrupt bit if any DMA is running */ 705 /* call with spinlock held */ 706 static void snd_atiixp_check_bus_busy(struct atiixp *chip) 707 { 708 unsigned int bus_busy; 709 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN | 710 ATI_REG_CMD_RECEIVE_EN | 711 ATI_REG_CMD_SPDF_OUT_EN)) 712 bus_busy = ATI_REG_IER_SET_BUS_BUSY; 713 else 714 bus_busy = 0; 715 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy); 716 } 717 718 /* common trigger callback 719 * calling the lowlevel callbacks in it 720 */ 721 static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 722 { 723 struct atiixp *chip = snd_pcm_substream_chip(substream); 724 struct atiixp_dma *dma = substream->runtime->private_data; 725 int err = 0; 726 727 if (snd_BUG_ON(!dma->ops->enable_transfer || 728 !dma->ops->flush_dma)) 729 return -EINVAL; 730 731 spin_lock(&chip->reg_lock); 732 switch (cmd) { 733 case SNDRV_PCM_TRIGGER_START: 734 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 735 case SNDRV_PCM_TRIGGER_RESUME: 736 dma->ops->enable_transfer(chip, 1); 737 dma->running = 1; 738 dma->suspended = 0; 739 break; 740 case SNDRV_PCM_TRIGGER_STOP: 741 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 742 case SNDRV_PCM_TRIGGER_SUSPEND: 743 dma->ops->enable_transfer(chip, 0); 744 dma->running = 0; 745 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND; 746 break; 747 default: 748 err = -EINVAL; 749 break; 750 } 751 if (! err) { 752 snd_atiixp_check_bus_busy(chip); 753 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 754 dma->ops->flush_dma(chip); 755 snd_atiixp_check_bus_busy(chip); 756 } 757 } 758 spin_unlock(&chip->reg_lock); 759 return err; 760 } 761 762 763 /* 764 * lowlevel callbacks for each DMA type 765 * 766 * every callback is supposed to be called in chip->reg_lock spinlock 767 */ 768 769 /* flush FIFO of analog OUT DMA */ 770 static void atiixp_out_flush_dma(struct atiixp *chip) 771 { 772 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH); 773 } 774 775 /* enable/disable analog OUT DMA */ 776 static void atiixp_out_enable_dma(struct atiixp *chip, int on) 777 { 778 unsigned int data; 779 data = atiixp_read(chip, CMD); 780 if (on) { 781 if (data & ATI_REG_CMD_OUT_DMA_EN) 782 return; 783 atiixp_out_flush_dma(chip); 784 data |= ATI_REG_CMD_OUT_DMA_EN; 785 } else 786 data &= ~ATI_REG_CMD_OUT_DMA_EN; 787 atiixp_write(chip, CMD, data); 788 } 789 790 /* start/stop transfer over OUT DMA */ 791 static void atiixp_out_enable_transfer(struct atiixp *chip, int on) 792 { 793 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN, 794 on ? ATI_REG_CMD_SEND_EN : 0); 795 } 796 797 /* enable/disable analog IN DMA */ 798 static void atiixp_in_enable_dma(struct atiixp *chip, int on) 799 { 800 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN, 801 on ? ATI_REG_CMD_IN_DMA_EN : 0); 802 } 803 804 /* start/stop analog IN DMA */ 805 static void atiixp_in_enable_transfer(struct atiixp *chip, int on) 806 { 807 if (on) { 808 unsigned int data = atiixp_read(chip, CMD); 809 if (! (data & ATI_REG_CMD_RECEIVE_EN)) { 810 data |= ATI_REG_CMD_RECEIVE_EN; 811 #if 0 /* FIXME: this causes the endless loop */ 812 /* wait until slot 3/4 are finished */ 813 while ((atiixp_read(chip, COUNTER) & 814 ATI_REG_COUNTER_SLOT) != 5) 815 ; 816 #endif 817 atiixp_write(chip, CMD, data); 818 } 819 } else 820 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0); 821 } 822 823 /* flush FIFO of analog IN DMA */ 824 static void atiixp_in_flush_dma(struct atiixp *chip) 825 { 826 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH); 827 } 828 829 /* enable/disable SPDIF OUT DMA */ 830 static void atiixp_spdif_enable_dma(struct atiixp *chip, int on) 831 { 832 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN, 833 on ? ATI_REG_CMD_SPDF_DMA_EN : 0); 834 } 835 836 /* start/stop SPDIF OUT DMA */ 837 static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on) 838 { 839 unsigned int data; 840 data = atiixp_read(chip, CMD); 841 if (on) 842 data |= ATI_REG_CMD_SPDF_OUT_EN; 843 else 844 data &= ~ATI_REG_CMD_SPDF_OUT_EN; 845 atiixp_write(chip, CMD, data); 846 } 847 848 /* flush FIFO of SPDIF OUT DMA */ 849 static void atiixp_spdif_flush_dma(struct atiixp *chip) 850 { 851 int timeout; 852 853 /* DMA off, transfer on */ 854 atiixp_spdif_enable_dma(chip, 0); 855 atiixp_spdif_enable_transfer(chip, 1); 856 857 timeout = 100; 858 do { 859 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED)) 860 break; 861 udelay(1); 862 } while (timeout-- > 0); 863 864 atiixp_spdif_enable_transfer(chip, 0); 865 } 866 867 /* set up slots and formats for SPDIF OUT */ 868 static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream) 869 { 870 struct atiixp *chip = snd_pcm_substream_chip(substream); 871 872 spin_lock_irq(&chip->reg_lock); 873 if (chip->spdif_over_aclink) { 874 unsigned int data; 875 /* enable slots 10/11 */ 876 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 877 ATI_REG_CMD_SPDF_CONFIG_01); 878 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; 879 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | 880 ATI_REG_OUT_DMA_SLOT_BIT(11); 881 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 882 atiixp_write(chip, OUT_DMA_SLOT, data); 883 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, 884 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 885 ATI_REG_CMD_INTERLEAVE_OUT : 0); 886 } else { 887 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0); 888 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0); 889 } 890 spin_unlock_irq(&chip->reg_lock); 891 return 0; 892 } 893 894 /* set up slots and formats for analog OUT */ 895 static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream) 896 { 897 struct atiixp *chip = snd_pcm_substream_chip(substream); 898 unsigned int data; 899 900 spin_lock_irq(&chip->reg_lock); 901 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; 902 switch (substream->runtime->channels) { 903 case 8: 904 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | 905 ATI_REG_OUT_DMA_SLOT_BIT(11); 906 /* fallthru */ 907 case 6: 908 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) | 909 ATI_REG_OUT_DMA_SLOT_BIT(8); 910 /* fallthru */ 911 case 4: 912 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) | 913 ATI_REG_OUT_DMA_SLOT_BIT(9); 914 /* fallthru */ 915 default: 916 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 917 ATI_REG_OUT_DMA_SLOT_BIT(4); 918 break; 919 } 920 921 /* set output threshold */ 922 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 923 atiixp_write(chip, OUT_DMA_SLOT, data); 924 925 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, 926 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 927 ATI_REG_CMD_INTERLEAVE_OUT : 0); 928 929 /* 930 * enable 6 channel re-ordering bit if needed 931 */ 932 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN, 933 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0); 934 935 spin_unlock_irq(&chip->reg_lock); 936 return 0; 937 } 938 939 /* set up slots and formats for analog IN */ 940 static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream) 941 { 942 struct atiixp *chip = snd_pcm_substream_chip(substream); 943 944 spin_lock_irq(&chip->reg_lock); 945 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN, 946 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 947 ATI_REG_CMD_INTERLEAVE_IN : 0); 948 spin_unlock_irq(&chip->reg_lock); 949 return 0; 950 } 951 952 /* 953 * hw_params - allocate the buffer and set up buffer descriptors 954 */ 955 static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream, 956 struct snd_pcm_hw_params *hw_params) 957 { 958 struct atiixp *chip = snd_pcm_substream_chip(substream); 959 struct atiixp_dma *dma = substream->runtime->private_data; 960 int err; 961 962 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 963 if (err < 0) 964 return err; 965 dma->buf_addr = substream->runtime->dma_addr; 966 dma->buf_bytes = params_buffer_bytes(hw_params); 967 968 err = atiixp_build_dma_packets(chip, dma, substream, 969 params_periods(hw_params), 970 params_period_bytes(hw_params)); 971 if (err < 0) 972 return err; 973 974 if (dma->ac97_pcm_type >= 0) { 975 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; 976 /* PCM is bound to AC97 codec(s) 977 * set up the AC97 codecs 978 */ 979 if (dma->pcm_open_flag) { 980 snd_ac97_pcm_close(pcm); 981 dma->pcm_open_flag = 0; 982 } 983 err = snd_ac97_pcm_open(pcm, params_rate(hw_params), 984 params_channels(hw_params), 985 pcm->r[0].slots); 986 if (err >= 0) 987 dma->pcm_open_flag = 1; 988 } 989 990 return err; 991 } 992 993 static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream) 994 { 995 struct atiixp *chip = snd_pcm_substream_chip(substream); 996 struct atiixp_dma *dma = substream->runtime->private_data; 997 998 if (dma->pcm_open_flag) { 999 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; 1000 snd_ac97_pcm_close(pcm); 1001 dma->pcm_open_flag = 0; 1002 } 1003 atiixp_clear_dma_packets(chip, dma, substream); 1004 snd_pcm_lib_free_pages(substream); 1005 return 0; 1006 } 1007 1008 1009 /* 1010 * pcm hardware definition, identical for all DMA types 1011 */ 1012 static struct snd_pcm_hardware snd_atiixp_pcm_hw = 1013 { 1014 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1015 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1016 SNDRV_PCM_INFO_PAUSE | 1017 SNDRV_PCM_INFO_RESUME | 1018 SNDRV_PCM_INFO_MMAP_VALID), 1019 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1020 .rates = SNDRV_PCM_RATE_48000, 1021 .rate_min = 48000, 1022 .rate_max = 48000, 1023 .channels_min = 2, 1024 .channels_max = 2, 1025 .buffer_bytes_max = 256 * 1024, 1026 .period_bytes_min = 32, 1027 .period_bytes_max = 128 * 1024, 1028 .periods_min = 2, 1029 .periods_max = ATI_MAX_DESCRIPTORS, 1030 }; 1031 1032 static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream, 1033 struct atiixp_dma *dma, int pcm_type) 1034 { 1035 struct atiixp *chip = snd_pcm_substream_chip(substream); 1036 struct snd_pcm_runtime *runtime = substream->runtime; 1037 int err; 1038 1039 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) 1040 return -EINVAL; 1041 1042 if (dma->opened) 1043 return -EBUSY; 1044 dma->substream = substream; 1045 runtime->hw = snd_atiixp_pcm_hw; 1046 dma->ac97_pcm_type = pcm_type; 1047 if (pcm_type >= 0) { 1048 runtime->hw.rates = chip->pcms[pcm_type]->rates; 1049 snd_pcm_limit_hw_rates(runtime); 1050 } else { 1051 /* direct SPDIF */ 1052 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 1053 } 1054 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1055 return err; 1056 runtime->private_data = dma; 1057 1058 /* enable DMA bits */ 1059 spin_lock_irq(&chip->reg_lock); 1060 dma->ops->enable_dma(chip, 1); 1061 spin_unlock_irq(&chip->reg_lock); 1062 dma->opened = 1; 1063 1064 return 0; 1065 } 1066 1067 static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream, 1068 struct atiixp_dma *dma) 1069 { 1070 struct atiixp *chip = snd_pcm_substream_chip(substream); 1071 /* disable DMA bits */ 1072 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) 1073 return -EINVAL; 1074 spin_lock_irq(&chip->reg_lock); 1075 dma->ops->enable_dma(chip, 0); 1076 spin_unlock_irq(&chip->reg_lock); 1077 dma->substream = NULL; 1078 dma->opened = 0; 1079 return 0; 1080 } 1081 1082 /* 1083 */ 1084 static int snd_atiixp_playback_open(struct snd_pcm_substream *substream) 1085 { 1086 struct atiixp *chip = snd_pcm_substream_chip(substream); 1087 int err; 1088 1089 mutex_lock(&chip->open_mutex); 1090 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0); 1091 mutex_unlock(&chip->open_mutex); 1092 if (err < 0) 1093 return err; 1094 substream->runtime->hw.channels_max = chip->max_channels; 1095 if (chip->max_channels > 2) 1096 /* channels must be even */ 1097 snd_pcm_hw_constraint_step(substream->runtime, 0, 1098 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1099 return 0; 1100 } 1101 1102 static int snd_atiixp_playback_close(struct snd_pcm_substream *substream) 1103 { 1104 struct atiixp *chip = snd_pcm_substream_chip(substream); 1105 int err; 1106 mutex_lock(&chip->open_mutex); 1107 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); 1108 mutex_unlock(&chip->open_mutex); 1109 return err; 1110 } 1111 1112 static int snd_atiixp_capture_open(struct snd_pcm_substream *substream) 1113 { 1114 struct atiixp *chip = snd_pcm_substream_chip(substream); 1115 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1); 1116 } 1117 1118 static int snd_atiixp_capture_close(struct snd_pcm_substream *substream) 1119 { 1120 struct atiixp *chip = snd_pcm_substream_chip(substream); 1121 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]); 1122 } 1123 1124 static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream) 1125 { 1126 struct atiixp *chip = snd_pcm_substream_chip(substream); 1127 int err; 1128 mutex_lock(&chip->open_mutex); 1129 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */ 1130 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2); 1131 else 1132 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1); 1133 mutex_unlock(&chip->open_mutex); 1134 return err; 1135 } 1136 1137 static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream) 1138 { 1139 struct atiixp *chip = snd_pcm_substream_chip(substream); 1140 int err; 1141 mutex_lock(&chip->open_mutex); 1142 if (chip->spdif_over_aclink) 1143 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); 1144 else 1145 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]); 1146 mutex_unlock(&chip->open_mutex); 1147 return err; 1148 } 1149 1150 /* AC97 playback */ 1151 static struct snd_pcm_ops snd_atiixp_playback_ops = { 1152 .open = snd_atiixp_playback_open, 1153 .close = snd_atiixp_playback_close, 1154 .ioctl = snd_pcm_lib_ioctl, 1155 .hw_params = snd_atiixp_pcm_hw_params, 1156 .hw_free = snd_atiixp_pcm_hw_free, 1157 .prepare = snd_atiixp_playback_prepare, 1158 .trigger = snd_atiixp_pcm_trigger, 1159 .pointer = snd_atiixp_pcm_pointer, 1160 }; 1161 1162 /* AC97 capture */ 1163 static struct snd_pcm_ops snd_atiixp_capture_ops = { 1164 .open = snd_atiixp_capture_open, 1165 .close = snd_atiixp_capture_close, 1166 .ioctl = snd_pcm_lib_ioctl, 1167 .hw_params = snd_atiixp_pcm_hw_params, 1168 .hw_free = snd_atiixp_pcm_hw_free, 1169 .prepare = snd_atiixp_capture_prepare, 1170 .trigger = snd_atiixp_pcm_trigger, 1171 .pointer = snd_atiixp_pcm_pointer, 1172 }; 1173 1174 /* SPDIF playback */ 1175 static struct snd_pcm_ops snd_atiixp_spdif_ops = { 1176 .open = snd_atiixp_spdif_open, 1177 .close = snd_atiixp_spdif_close, 1178 .ioctl = snd_pcm_lib_ioctl, 1179 .hw_params = snd_atiixp_pcm_hw_params, 1180 .hw_free = snd_atiixp_pcm_hw_free, 1181 .prepare = snd_atiixp_spdif_prepare, 1182 .trigger = snd_atiixp_pcm_trigger, 1183 .pointer = snd_atiixp_pcm_pointer, 1184 }; 1185 1186 static struct ac97_pcm atiixp_pcm_defs[] = { 1187 /* front PCM */ 1188 { 1189 .exclusive = 1, 1190 .r = { { 1191 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1192 (1 << AC97_SLOT_PCM_RIGHT) | 1193 (1 << AC97_SLOT_PCM_CENTER) | 1194 (1 << AC97_SLOT_PCM_SLEFT) | 1195 (1 << AC97_SLOT_PCM_SRIGHT) | 1196 (1 << AC97_SLOT_LFE) 1197 } 1198 } 1199 }, 1200 /* PCM IN #1 */ 1201 { 1202 .stream = 1, 1203 .exclusive = 1, 1204 .r = { { 1205 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1206 (1 << AC97_SLOT_PCM_RIGHT) 1207 } 1208 } 1209 }, 1210 /* S/PDIF OUT (optional) */ 1211 { 1212 .exclusive = 1, 1213 .spdif = 1, 1214 .r = { { 1215 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1216 (1 << AC97_SLOT_SPDIF_RIGHT2) 1217 } 1218 } 1219 }, 1220 }; 1221 1222 static struct atiixp_dma_ops snd_atiixp_playback_dma_ops = { 1223 .type = ATI_DMA_PLAYBACK, 1224 .llp_offset = ATI_REG_OUT_DMA_LINKPTR, 1225 .dt_cur = ATI_REG_OUT_DMA_DT_CUR, 1226 .enable_dma = atiixp_out_enable_dma, 1227 .enable_transfer = atiixp_out_enable_transfer, 1228 .flush_dma = atiixp_out_flush_dma, 1229 }; 1230 1231 static struct atiixp_dma_ops snd_atiixp_capture_dma_ops = { 1232 .type = ATI_DMA_CAPTURE, 1233 .llp_offset = ATI_REG_IN_DMA_LINKPTR, 1234 .dt_cur = ATI_REG_IN_DMA_DT_CUR, 1235 .enable_dma = atiixp_in_enable_dma, 1236 .enable_transfer = atiixp_in_enable_transfer, 1237 .flush_dma = atiixp_in_flush_dma, 1238 }; 1239 1240 static struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = { 1241 .type = ATI_DMA_SPDIF, 1242 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR, 1243 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR, 1244 .enable_dma = atiixp_spdif_enable_dma, 1245 .enable_transfer = atiixp_spdif_enable_transfer, 1246 .flush_dma = atiixp_spdif_flush_dma, 1247 }; 1248 1249 1250 static int snd_atiixp_pcm_new(struct atiixp *chip) 1251 { 1252 struct snd_pcm *pcm; 1253 struct snd_pcm_chmap *chmap; 1254 struct snd_ac97_bus *pbus = chip->ac97_bus; 1255 int err, i, num_pcms; 1256 1257 /* initialize constants */ 1258 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops; 1259 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops; 1260 if (! chip->spdif_over_aclink) 1261 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops; 1262 1263 /* assign AC97 pcm */ 1264 if (chip->spdif_over_aclink) 1265 num_pcms = 3; 1266 else 1267 num_pcms = 2; 1268 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs); 1269 if (err < 0) 1270 return err; 1271 for (i = 0; i < num_pcms; i++) 1272 chip->pcms[i] = &pbus->pcms[i]; 1273 1274 chip->max_channels = 2; 1275 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 1276 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE)) 1277 chip->max_channels = 6; 1278 else 1279 chip->max_channels = 4; 1280 } 1281 1282 /* PCM #0: analog I/O */ 1283 err = snd_pcm_new(chip->card, "ATI IXP AC97", 1284 ATI_PCMDEV_ANALOG, 1, 1, &pcm); 1285 if (err < 0) 1286 return err; 1287 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops); 1288 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops); 1289 pcm->private_data = chip; 1290 strcpy(pcm->name, "ATI IXP AC97"); 1291 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm; 1292 1293 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1294 snd_dma_pci_data(chip->pci), 1295 64*1024, 128*1024); 1296 1297 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1298 snd_pcm_alt_chmaps, chip->max_channels, 0, 1299 &chmap); 1300 if (err < 0) 1301 return err; 1302 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; 1303 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; 1304 1305 /* no SPDIF support on codec? */ 1306 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates) 1307 return 0; 1308 1309 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */ 1310 if (chip->pcms[ATI_PCM_SPDIF]) 1311 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000; 1312 1313 /* PCM #1: spdif playback */ 1314 err = snd_pcm_new(chip->card, "ATI IXP IEC958", 1315 ATI_PCMDEV_DIGITAL, 1, 0, &pcm); 1316 if (err < 0) 1317 return err; 1318 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops); 1319 pcm->private_data = chip; 1320 if (chip->spdif_over_aclink) 1321 strcpy(pcm->name, "ATI IXP IEC958 (AC97)"); 1322 else 1323 strcpy(pcm->name, "ATI IXP IEC958 (Direct)"); 1324 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm; 1325 1326 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1327 snd_dma_pci_data(chip->pci), 1328 64*1024, 128*1024); 1329 1330 /* pre-select AC97 SPDIF slots 10/11 */ 1331 for (i = 0; i < NUM_ATI_CODECS; i++) { 1332 if (chip->ac97[i]) 1333 snd_ac97_update_bits(chip->ac97[i], 1334 AC97_EXTENDED_STATUS, 1335 0x03 << 4, 0x03 << 4); 1336 } 1337 1338 return 0; 1339 } 1340 1341 1342 1343 /* 1344 * interrupt handler 1345 */ 1346 static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id) 1347 { 1348 struct atiixp *chip = dev_id; 1349 unsigned int status; 1350 1351 status = atiixp_read(chip, ISR); 1352 1353 if (! status) 1354 return IRQ_NONE; 1355 1356 /* process audio DMA */ 1357 if (status & ATI_REG_ISR_OUT_XRUN) 1358 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); 1359 else if (status & ATI_REG_ISR_OUT_STATUS) 1360 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); 1361 if (status & ATI_REG_ISR_IN_XRUN) 1362 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); 1363 else if (status & ATI_REG_ISR_IN_STATUS) 1364 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); 1365 if (! chip->spdif_over_aclink) { 1366 if (status & ATI_REG_ISR_SPDF_XRUN) 1367 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); 1368 else if (status & ATI_REG_ISR_SPDF_STATUS) 1369 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); 1370 } 1371 1372 /* for codec detection */ 1373 if (status & CODEC_CHECK_BITS) { 1374 unsigned int detected; 1375 detected = status & CODEC_CHECK_BITS; 1376 spin_lock(&chip->reg_lock); 1377 chip->codec_not_ready_bits |= detected; 1378 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */ 1379 spin_unlock(&chip->reg_lock); 1380 } 1381 1382 /* ack */ 1383 atiixp_write(chip, ISR, status); 1384 1385 return IRQ_HANDLED; 1386 } 1387 1388 1389 /* 1390 * ac97 mixer section 1391 */ 1392 1393 static const struct ac97_quirk ac97_quirks[] = { 1394 { 1395 .subvendor = 0x103c, 1396 .subdevice = 0x006b, 1397 .name = "HP Pavilion ZV5030US", 1398 .type = AC97_TUNE_MUTE_LED 1399 }, 1400 { 1401 .subvendor = 0x103c, 1402 .subdevice = 0x308b, 1403 .name = "HP nx6125", 1404 .type = AC97_TUNE_MUTE_LED 1405 }, 1406 { 1407 .subvendor = 0x103c, 1408 .subdevice = 0x3091, 1409 .name = "unknown HP", 1410 .type = AC97_TUNE_MUTE_LED 1411 }, 1412 { } /* terminator */ 1413 }; 1414 1415 static int snd_atiixp_mixer_new(struct atiixp *chip, int clock, 1416 const char *quirk_override) 1417 { 1418 struct snd_ac97_bus *pbus; 1419 struct snd_ac97_template ac97; 1420 int i, err; 1421 int codec_count; 1422 static struct snd_ac97_bus_ops ops = { 1423 .write = snd_atiixp_ac97_write, 1424 .read = snd_atiixp_ac97_read, 1425 }; 1426 static unsigned int codec_skip[NUM_ATI_CODECS] = { 1427 ATI_REG_ISR_CODEC0_NOT_READY, 1428 ATI_REG_ISR_CODEC1_NOT_READY, 1429 ATI_REG_ISR_CODEC2_NOT_READY, 1430 }; 1431 1432 if (snd_atiixp_codec_detect(chip) < 0) 1433 return -ENXIO; 1434 1435 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) 1436 return err; 1437 pbus->clock = clock; 1438 chip->ac97_bus = pbus; 1439 1440 codec_count = 0; 1441 for (i = 0; i < NUM_ATI_CODECS; i++) { 1442 if (chip->codec_not_ready_bits & codec_skip[i]) 1443 continue; 1444 memset(&ac97, 0, sizeof(ac97)); 1445 ac97.private_data = chip; 1446 ac97.pci = chip->pci; 1447 ac97.num = i; 1448 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 1449 if (! chip->spdif_over_aclink) 1450 ac97.scaps |= AC97_SCAP_NO_SPDIF; 1451 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 1452 chip->ac97[i] = NULL; /* to be sure */ 1453 dev_dbg(chip->card->dev, 1454 "codec %d not available for audio\n", i); 1455 continue; 1456 } 1457 codec_count++; 1458 } 1459 1460 if (! codec_count) { 1461 dev_err(chip->card->dev, "no codec available\n"); 1462 return -ENODEV; 1463 } 1464 1465 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 1466 1467 return 0; 1468 } 1469 1470 1471 #ifdef CONFIG_PM_SLEEP 1472 /* 1473 * power management 1474 */ 1475 static int snd_atiixp_suspend(struct device *dev) 1476 { 1477 struct snd_card *card = dev_get_drvdata(dev); 1478 struct atiixp *chip = card->private_data; 1479 int i; 1480 1481 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1482 for (i = 0; i < NUM_ATI_PCMDEVS; i++) 1483 if (chip->pcmdevs[i]) { 1484 struct atiixp_dma *dma = &chip->dmas[i]; 1485 if (dma->substream && dma->running) 1486 dma->saved_curptr = readl(chip->remap_addr + 1487 dma->ops->dt_cur); 1488 snd_pcm_suspend_all(chip->pcmdevs[i]); 1489 } 1490 for (i = 0; i < NUM_ATI_CODECS; i++) 1491 snd_ac97_suspend(chip->ac97[i]); 1492 snd_atiixp_aclink_down(chip); 1493 snd_atiixp_chip_stop(chip); 1494 return 0; 1495 } 1496 1497 static int snd_atiixp_resume(struct device *dev) 1498 { 1499 struct snd_card *card = dev_get_drvdata(dev); 1500 struct atiixp *chip = card->private_data; 1501 int i; 1502 1503 snd_atiixp_aclink_reset(chip); 1504 snd_atiixp_chip_start(chip); 1505 1506 for (i = 0; i < NUM_ATI_CODECS; i++) 1507 snd_ac97_resume(chip->ac97[i]); 1508 1509 for (i = 0; i < NUM_ATI_PCMDEVS; i++) 1510 if (chip->pcmdevs[i]) { 1511 struct atiixp_dma *dma = &chip->dmas[i]; 1512 if (dma->substream && dma->suspended) { 1513 dma->ops->enable_dma(chip, 1); 1514 dma->substream->ops->prepare(dma->substream); 1515 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, 1516 chip->remap_addr + dma->ops->llp_offset); 1517 writel(dma->saved_curptr, chip->remap_addr + 1518 dma->ops->dt_cur); 1519 } 1520 } 1521 1522 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1523 return 0; 1524 } 1525 1526 static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume); 1527 #define SND_ATIIXP_PM_OPS &snd_atiixp_pm 1528 #else 1529 #define SND_ATIIXP_PM_OPS NULL 1530 #endif /* CONFIG_PM_SLEEP */ 1531 1532 1533 /* 1534 * proc interface for register dump 1535 */ 1536 1537 static void snd_atiixp_proc_read(struct snd_info_entry *entry, 1538 struct snd_info_buffer *buffer) 1539 { 1540 struct atiixp *chip = entry->private_data; 1541 int i; 1542 1543 for (i = 0; i < 256; i += 4) 1544 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i)); 1545 } 1546 1547 static void snd_atiixp_proc_init(struct atiixp *chip) 1548 { 1549 struct snd_info_entry *entry; 1550 1551 if (! snd_card_proc_new(chip->card, "atiixp", &entry)) 1552 snd_info_set_text_ops(entry, chip, snd_atiixp_proc_read); 1553 } 1554 1555 1556 /* 1557 * destructor 1558 */ 1559 1560 static int snd_atiixp_free(struct atiixp *chip) 1561 { 1562 if (chip->irq < 0) 1563 goto __hw_end; 1564 snd_atiixp_chip_stop(chip); 1565 1566 __hw_end: 1567 if (chip->irq >= 0) 1568 free_irq(chip->irq, chip); 1569 iounmap(chip->remap_addr); 1570 pci_release_regions(chip->pci); 1571 pci_disable_device(chip->pci); 1572 kfree(chip); 1573 return 0; 1574 } 1575 1576 static int snd_atiixp_dev_free(struct snd_device *device) 1577 { 1578 struct atiixp *chip = device->device_data; 1579 return snd_atiixp_free(chip); 1580 } 1581 1582 /* 1583 * constructor for chip instance 1584 */ 1585 static int snd_atiixp_create(struct snd_card *card, 1586 struct pci_dev *pci, 1587 struct atiixp **r_chip) 1588 { 1589 static struct snd_device_ops ops = { 1590 .dev_free = snd_atiixp_dev_free, 1591 }; 1592 struct atiixp *chip; 1593 int err; 1594 1595 if ((err = pci_enable_device(pci)) < 0) 1596 return err; 1597 1598 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1599 if (chip == NULL) { 1600 pci_disable_device(pci); 1601 return -ENOMEM; 1602 } 1603 1604 spin_lock_init(&chip->reg_lock); 1605 mutex_init(&chip->open_mutex); 1606 chip->card = card; 1607 chip->pci = pci; 1608 chip->irq = -1; 1609 if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) { 1610 pci_disable_device(pci); 1611 kfree(chip); 1612 return err; 1613 } 1614 chip->addr = pci_resource_start(pci, 0); 1615 chip->remap_addr = pci_ioremap_bar(pci, 0); 1616 if (chip->remap_addr == NULL) { 1617 dev_err(card->dev, "AC'97 space ioremap problem\n"); 1618 snd_atiixp_free(chip); 1619 return -EIO; 1620 } 1621 1622 if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED, 1623 KBUILD_MODNAME, chip)) { 1624 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 1625 snd_atiixp_free(chip); 1626 return -EBUSY; 1627 } 1628 chip->irq = pci->irq; 1629 pci_set_master(pci); 1630 synchronize_irq(chip->irq); 1631 1632 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1633 snd_atiixp_free(chip); 1634 return err; 1635 } 1636 1637 *r_chip = chip; 1638 return 0; 1639 } 1640 1641 1642 static int snd_atiixp_probe(struct pci_dev *pci, 1643 const struct pci_device_id *pci_id) 1644 { 1645 struct snd_card *card; 1646 struct atiixp *chip; 1647 int err; 1648 1649 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); 1650 if (err < 0) 1651 return err; 1652 1653 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA"); 1654 strcpy(card->shortname, "ATI IXP"); 1655 if ((err = snd_atiixp_create(card, pci, &chip)) < 0) 1656 goto __error; 1657 card->private_data = chip; 1658 1659 if ((err = snd_atiixp_aclink_reset(chip)) < 0) 1660 goto __error; 1661 1662 chip->spdif_over_aclink = spdif_aclink; 1663 1664 if ((err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk)) < 0) 1665 goto __error; 1666 1667 if ((err = snd_atiixp_pcm_new(chip)) < 0) 1668 goto __error; 1669 1670 snd_atiixp_proc_init(chip); 1671 1672 snd_atiixp_chip_start(chip); 1673 1674 snprintf(card->longname, sizeof(card->longname), 1675 "%s rev %x with %s at %#lx, irq %i", card->shortname, 1676 pci->revision, 1677 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?", 1678 chip->addr, chip->irq); 1679 1680 if ((err = snd_card_register(card)) < 0) 1681 goto __error; 1682 1683 pci_set_drvdata(pci, card); 1684 return 0; 1685 1686 __error: 1687 snd_card_free(card); 1688 return err; 1689 } 1690 1691 static void snd_atiixp_remove(struct pci_dev *pci) 1692 { 1693 snd_card_free(pci_get_drvdata(pci)); 1694 } 1695 1696 static struct pci_driver atiixp_driver = { 1697 .name = KBUILD_MODNAME, 1698 .id_table = snd_atiixp_ids, 1699 .probe = snd_atiixp_probe, 1700 .remove = snd_atiixp_remove, 1701 .driver = { 1702 .pm = SND_ATIIXP_PM_OPS, 1703 }, 1704 }; 1705 1706 module_pci_driver(atiixp_driver); 1707