1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers 4 * 5 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 6 */ 7 8 #include <linux/io.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/init.h> 12 #include <linux/pci.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/info.h> 20 #include <sound/ac97_codec.h> 21 #include <sound/initval.h> 22 23 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 24 MODULE_DESCRIPTION("ATI IXP AC97 controller"); 25 MODULE_LICENSE("GPL"); 26 27 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 28 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 29 static int ac97_clock = 48000; 30 static char *ac97_quirk; 31 static bool spdif_aclink = 1; 32 static int ac97_codec = -1; 33 34 module_param(index, int, 0444); 35 MODULE_PARM_DESC(index, "Index value for ATI IXP controller."); 36 module_param(id, charp, 0444); 37 MODULE_PARM_DESC(id, "ID string for ATI IXP controller."); 38 module_param(ac97_clock, int, 0444); 39 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz)."); 40 module_param(ac97_quirk, charp, 0444); 41 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 42 module_param(ac97_codec, int, 0444); 43 MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing."); 44 module_param(spdif_aclink, bool, 0444); 45 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 46 47 /* just for backward compatibility */ 48 static bool enable; 49 module_param(enable, bool, 0444); 50 51 52 /* 53 */ 54 55 #define ATI_REG_ISR 0x00 /* interrupt source */ 56 #define ATI_REG_ISR_IN_XRUN (1U<<0) 57 #define ATI_REG_ISR_IN_STATUS (1U<<1) 58 #define ATI_REG_ISR_OUT_XRUN (1U<<2) 59 #define ATI_REG_ISR_OUT_STATUS (1U<<3) 60 #define ATI_REG_ISR_SPDF_XRUN (1U<<4) 61 #define ATI_REG_ISR_SPDF_STATUS (1U<<5) 62 #define ATI_REG_ISR_PHYS_INTR (1U<<8) 63 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) 64 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) 65 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) 66 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) 67 #define ATI_REG_ISR_NEW_FRAME (1U<<13) 68 69 #define ATI_REG_IER 0x04 /* interrupt enable */ 70 #define ATI_REG_IER_IN_XRUN_EN (1U<<0) 71 #define ATI_REG_IER_IO_STATUS_EN (1U<<1) 72 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2) 73 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3) 74 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4) 75 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5) 76 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8) 77 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) 78 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) 79 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) 80 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) 81 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */ 82 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */ 83 84 #define ATI_REG_CMD 0x08 /* command */ 85 #define ATI_REG_CMD_POWERDOWN (1U<<0) 86 #define ATI_REG_CMD_RECEIVE_EN (1U<<1) 87 #define ATI_REG_CMD_SEND_EN (1U<<2) 88 #define ATI_REG_CMD_STATUS_MEM (1U<<3) 89 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4) 90 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5) 91 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6) 92 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6 93 #define ATI_REG_CMD_IN_DMA_EN (1U<<8) 94 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9) 95 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10) 96 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11) 97 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12) 98 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12) 99 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12) 100 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12) 101 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12) 102 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16) 103 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) 104 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21) 105 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22) 106 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23) 107 #define ATI_REG_CMD_PACKED_DIS (1U<<24) 108 #define ATI_REG_CMD_BURST_EN (1U<<25) 109 #define ATI_REG_CMD_PANIC_EN (1U<<26) 110 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27) 111 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) 112 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) 113 #define ATI_REG_CMD_AC_SYNC (1U<<30) 114 #define ATI_REG_CMD_AC_RESET (1U<<31) 115 116 #define ATI_REG_PHYS_OUT_ADDR 0x0c 117 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) 118 #define ATI_REG_PHYS_OUT_RW (1U<<2) 119 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) 120 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 121 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16 122 123 #define ATI_REG_PHYS_IN_ADDR 0x10 124 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) 125 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9 126 #define ATI_REG_PHYS_IN_DATA_SHIFT 16 127 128 #define ATI_REG_SLOTREQ 0x14 129 130 #define ATI_REG_COUNTER 0x18 131 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ 132 #define ATI_REG_COUNTER_BITCLOCK (31U<<8) 133 134 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c 135 136 #define ATI_REG_IN_DMA_LINKPTR 0x20 137 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */ 138 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */ 139 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */ 140 #define ATI_REG_IN_DMA_DT_SIZE 0x30 141 142 #define ATI_REG_OUT_DMA_SLOT 0x34 143 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3)) 144 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff 145 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800 146 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11 147 148 #define ATI_REG_OUT_DMA_LINKPTR 0x38 149 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */ 150 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */ 151 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */ 152 #define ATI_REG_OUT_DMA_DT_SIZE 0x48 153 154 #define ATI_REG_SPDF_CMD 0x4c 155 #define ATI_REG_SPDF_CMD_LFSR (1U<<4) 156 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5) 157 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */ 158 159 #define ATI_REG_SPDF_DMA_LINKPTR 0x50 160 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */ 161 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */ 162 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */ 163 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60 164 165 #define ATI_REG_MODEM_MIRROR 0x7c 166 #define ATI_REG_AUDIO_MIRROR 0x80 167 168 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */ 169 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */ 170 171 #define ATI_REG_FIFO_FLUSH 0x88 172 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0) 173 #define ATI_REG_FIFO_IN_FLUSH (1U<<1) 174 175 /* LINKPTR */ 176 #define ATI_REG_LINKPTR_EN (1U<<0) 177 178 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */ 179 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0) 180 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16) 181 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21) 182 #define ATI_REG_DMA_STATE (7U<<26) 183 184 185 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */ 186 187 188 struct atiixp; 189 190 /* 191 * DMA packate descriptor 192 */ 193 194 struct atiixp_dma_desc { 195 __le32 addr; /* DMA buffer address */ 196 u16 status; /* status bits */ 197 u16 size; /* size of the packet in dwords */ 198 __le32 next; /* address of the next packet descriptor */ 199 }; 200 201 /* 202 * stream enum 203 */ 204 enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */ 205 enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */ 206 enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */ 207 208 #define NUM_ATI_CODECS 3 209 210 211 /* 212 * constants and callbacks for each DMA type 213 */ 214 struct atiixp_dma_ops { 215 int type; /* ATI_DMA_XXX */ 216 unsigned int llp_offset; /* LINKPTR offset */ 217 unsigned int dt_cur; /* DT_CUR offset */ 218 /* called from open callback */ 219 void (*enable_dma)(struct atiixp *chip, int on); 220 /* called from trigger (START/STOP) */ 221 void (*enable_transfer)(struct atiixp *chip, int on); 222 /* called from trigger (STOP only) */ 223 void (*flush_dma)(struct atiixp *chip); 224 }; 225 226 /* 227 * DMA stream 228 */ 229 struct atiixp_dma { 230 const struct atiixp_dma_ops *ops; 231 struct snd_dma_buffer desc_buf; 232 struct snd_pcm_substream *substream; /* assigned PCM substream */ 233 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */ 234 unsigned int period_bytes, periods; 235 int opened; 236 int running; 237 int suspended; 238 int pcm_open_flag; 239 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */ 240 unsigned int saved_curptr; 241 }; 242 243 /* 244 * ATI IXP chip 245 */ 246 struct atiixp { 247 struct snd_card *card; 248 struct pci_dev *pci; 249 250 unsigned long addr; 251 void __iomem *remap_addr; 252 int irq; 253 254 struct snd_ac97_bus *ac97_bus; 255 struct snd_ac97 *ac97[NUM_ATI_CODECS]; 256 257 spinlock_t reg_lock; 258 259 struct atiixp_dma dmas[NUM_ATI_DMAS]; 260 struct ac97_pcm *pcms[NUM_ATI_PCMS]; 261 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS]; 262 263 int max_channels; /* max. channels for PCM out */ 264 265 unsigned int codec_not_ready_bits; /* for codec detection */ 266 267 int spdif_over_aclink; /* passed from the module option */ 268 struct mutex open_mutex; /* playback open mutex */ 269 }; 270 271 272 /* 273 */ 274 static const struct pci_device_id snd_atiixp_ids[] = { 275 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */ 276 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */ 277 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */ 278 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */ 279 { 0, } 280 }; 281 282 MODULE_DEVICE_TABLE(pci, snd_atiixp_ids); 283 284 static const struct snd_pci_quirk atiixp_quirks[] = { 285 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0), 286 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0), 287 { } /* terminator */ 288 }; 289 290 /* 291 * lowlevel functions 292 */ 293 294 /* 295 * update the bits of the given register. 296 * return 1 if the bits changed. 297 */ 298 static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg, 299 unsigned int mask, unsigned int value) 300 { 301 void __iomem *addr = chip->remap_addr + reg; 302 unsigned int data, old_data; 303 old_data = data = readl(addr); 304 data &= ~mask; 305 data |= value; 306 if (old_data == data) 307 return 0; 308 writel(data, addr); 309 return 1; 310 } 311 312 /* 313 * macros for easy use 314 */ 315 #define atiixp_write(chip,reg,value) \ 316 writel(value, chip->remap_addr + ATI_REG_##reg) 317 #define atiixp_read(chip,reg) \ 318 readl(chip->remap_addr + ATI_REG_##reg) 319 #define atiixp_update(chip,reg,mask,val) \ 320 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) 321 322 /* 323 * handling DMA packets 324 * 325 * we allocate a linear buffer for the DMA, and split it to each packet. 326 * in a future version, a scatter-gather buffer should be implemented. 327 */ 328 329 #define ATI_DESC_LIST_SIZE \ 330 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc)) 331 332 /* 333 * build packets ring for the given buffer size. 334 * 335 * IXP handles the buffer descriptors, which are connected as a linked 336 * list. although we can change the list dynamically, in this version, 337 * a static RING of buffer descriptors is used. 338 * 339 * the ring is built in this function, and is set up to the hardware. 340 */ 341 static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma, 342 struct snd_pcm_substream *substream, 343 unsigned int periods, 344 unsigned int period_bytes) 345 { 346 unsigned int i; 347 u32 addr, desc_addr; 348 unsigned long flags; 349 350 if (periods > ATI_MAX_DESCRIPTORS) 351 return -ENOMEM; 352 353 if (dma->desc_buf.area == NULL) { 354 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 355 &chip->pci->dev, 356 ATI_DESC_LIST_SIZE, 357 &dma->desc_buf) < 0) 358 return -ENOMEM; 359 dma->period_bytes = dma->periods = 0; /* clear */ 360 } 361 362 if (dma->periods == periods && dma->period_bytes == period_bytes) 363 return 0; 364 365 /* reset DMA before changing the descriptor table */ 366 spin_lock_irqsave(&chip->reg_lock, flags); 367 writel(0, chip->remap_addr + dma->ops->llp_offset); 368 dma->ops->enable_dma(chip, 0); 369 dma->ops->enable_dma(chip, 1); 370 spin_unlock_irqrestore(&chip->reg_lock, flags); 371 372 /* fill the entries */ 373 addr = (u32)substream->runtime->dma_addr; 374 desc_addr = (u32)dma->desc_buf.addr; 375 for (i = 0; i < periods; i++) { 376 struct atiixp_dma_desc *desc; 377 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i]; 378 desc->addr = cpu_to_le32(addr); 379 desc->status = 0; 380 desc->size = period_bytes >> 2; /* in dwords */ 381 desc_addr += sizeof(struct atiixp_dma_desc); 382 if (i == periods - 1) 383 desc->next = cpu_to_le32((u32)dma->desc_buf.addr); 384 else 385 desc->next = cpu_to_le32(desc_addr); 386 addr += period_bytes; 387 } 388 389 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, 390 chip->remap_addr + dma->ops->llp_offset); 391 392 dma->period_bytes = period_bytes; 393 dma->periods = periods; 394 395 return 0; 396 } 397 398 /* 399 * remove the ring buffer and release it if assigned 400 */ 401 static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma, 402 struct snd_pcm_substream *substream) 403 { 404 if (dma->desc_buf.area) { 405 writel(0, chip->remap_addr + dma->ops->llp_offset); 406 snd_dma_free_pages(&dma->desc_buf); 407 dma->desc_buf.area = NULL; 408 } 409 } 410 411 /* 412 * AC97 interface 413 */ 414 static int snd_atiixp_acquire_codec(struct atiixp *chip) 415 { 416 int timeout = 1000; 417 418 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) { 419 if (! timeout--) { 420 dev_warn(chip->card->dev, "codec acquire timeout\n"); 421 return -EBUSY; 422 } 423 udelay(1); 424 } 425 return 0; 426 } 427 428 static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg) 429 { 430 unsigned int data; 431 int timeout; 432 433 if (snd_atiixp_acquire_codec(chip) < 0) 434 return 0xffff; 435 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 436 ATI_REG_PHYS_OUT_ADDR_EN | 437 ATI_REG_PHYS_OUT_RW | 438 codec; 439 atiixp_write(chip, PHYS_OUT_ADDR, data); 440 if (snd_atiixp_acquire_codec(chip) < 0) 441 return 0xffff; 442 timeout = 1000; 443 do { 444 data = atiixp_read(chip, PHYS_IN_ADDR); 445 if (data & ATI_REG_PHYS_IN_READ_FLAG) 446 return data >> ATI_REG_PHYS_IN_DATA_SHIFT; 447 udelay(1); 448 } while (--timeout); 449 /* time out may happen during reset */ 450 if (reg < 0x7c) 451 dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg); 452 return 0xffff; 453 } 454 455 456 static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec, 457 unsigned short reg, unsigned short val) 458 { 459 unsigned int data; 460 461 if (snd_atiixp_acquire_codec(chip) < 0) 462 return; 463 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | 464 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 465 ATI_REG_PHYS_OUT_ADDR_EN | codec; 466 atiixp_write(chip, PHYS_OUT_ADDR, data); 467 } 468 469 470 static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97, 471 unsigned short reg) 472 { 473 struct atiixp *chip = ac97->private_data; 474 return snd_atiixp_codec_read(chip, ac97->num, reg); 475 476 } 477 478 static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 479 unsigned short val) 480 { 481 struct atiixp *chip = ac97->private_data; 482 snd_atiixp_codec_write(chip, ac97->num, reg, val); 483 } 484 485 /* 486 * reset AC link 487 */ 488 static int snd_atiixp_aclink_reset(struct atiixp *chip) 489 { 490 int timeout; 491 492 /* reset powerdoewn */ 493 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0)) 494 udelay(10); 495 496 /* perform a software reset */ 497 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET); 498 atiixp_read(chip, CMD); 499 udelay(10); 500 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0); 501 502 timeout = 10; 503 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) { 504 /* do a hard reset */ 505 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, 506 ATI_REG_CMD_AC_SYNC); 507 atiixp_read(chip, CMD); 508 mdelay(1); 509 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET); 510 if (!--timeout) { 511 dev_err(chip->card->dev, "codec reset timeout\n"); 512 break; 513 } 514 } 515 516 /* deassert RESET and assert SYNC to make sure */ 517 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, 518 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET); 519 520 return 0; 521 } 522 523 #ifdef CONFIG_PM_SLEEP 524 static int snd_atiixp_aclink_down(struct atiixp *chip) 525 { 526 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */ 527 // return -EBUSY; 528 atiixp_update(chip, CMD, 529 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET, 530 ATI_REG_CMD_POWERDOWN); 531 return 0; 532 } 533 #endif 534 535 /* 536 * auto-detection of codecs 537 * 538 * the IXP chip can generate interrupts for the non-existing codecs. 539 * NEW_FRAME interrupt is used to make sure that the interrupt is generated 540 * even if all three codecs are connected. 541 */ 542 543 #define ALL_CODEC_NOT_READY \ 544 (ATI_REG_ISR_CODEC0_NOT_READY |\ 545 ATI_REG_ISR_CODEC1_NOT_READY |\ 546 ATI_REG_ISR_CODEC2_NOT_READY) 547 #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME) 548 549 static int ac97_probing_bugs(struct pci_dev *pci) 550 { 551 const struct snd_pci_quirk *q; 552 553 q = snd_pci_quirk_lookup(pci, atiixp_quirks); 554 if (q) { 555 dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n", 556 snd_pci_quirk_name(q), q->value); 557 return q->value; 558 } 559 /* this hardware doesn't need workarounds. Probe for codec */ 560 return -1; 561 } 562 563 static int snd_atiixp_codec_detect(struct atiixp *chip) 564 { 565 int timeout; 566 567 chip->codec_not_ready_bits = 0; 568 if (ac97_codec == -1) 569 ac97_codec = ac97_probing_bugs(chip->pci); 570 if (ac97_codec >= 0) { 571 chip->codec_not_ready_bits |= 572 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10)); 573 return 0; 574 } 575 576 atiixp_write(chip, IER, CODEC_CHECK_BITS); 577 /* wait for the interrupts */ 578 timeout = 50; 579 while (timeout-- > 0) { 580 mdelay(1); 581 if (chip->codec_not_ready_bits) 582 break; 583 } 584 atiixp_write(chip, IER, 0); /* disable irqs */ 585 586 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) { 587 dev_err(chip->card->dev, "no codec detected!\n"); 588 return -ENXIO; 589 } 590 return 0; 591 } 592 593 594 /* 595 * enable DMA and irqs 596 */ 597 static int snd_atiixp_chip_start(struct atiixp *chip) 598 { 599 unsigned int reg; 600 601 /* set up spdif, enable burst mode */ 602 reg = atiixp_read(chip, CMD); 603 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT; 604 reg |= ATI_REG_CMD_BURST_EN; 605 atiixp_write(chip, CMD, reg); 606 607 reg = atiixp_read(chip, SPDF_CMD); 608 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH); 609 atiixp_write(chip, SPDF_CMD, reg); 610 611 /* clear all interrupt source */ 612 atiixp_write(chip, ISR, 0xffffffff); 613 /* enable irqs */ 614 atiixp_write(chip, IER, 615 ATI_REG_IER_IO_STATUS_EN | 616 ATI_REG_IER_IN_XRUN_EN | 617 ATI_REG_IER_OUT_XRUN_EN | 618 ATI_REG_IER_SPDF_XRUN_EN | 619 ATI_REG_IER_SPDF_STATUS_EN); 620 return 0; 621 } 622 623 624 /* 625 * disable DMA and IRQs 626 */ 627 static int snd_atiixp_chip_stop(struct atiixp *chip) 628 { 629 /* clear interrupt source */ 630 atiixp_write(chip, ISR, atiixp_read(chip, ISR)); 631 /* disable irqs */ 632 atiixp_write(chip, IER, 0); 633 return 0; 634 } 635 636 637 /* 638 * PCM section 639 */ 640 641 /* 642 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current 643 * position. when SG-buffer is implemented, the offset must be calculated 644 * correctly... 645 */ 646 static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream) 647 { 648 struct atiixp *chip = snd_pcm_substream_chip(substream); 649 struct snd_pcm_runtime *runtime = substream->runtime; 650 struct atiixp_dma *dma = runtime->private_data; 651 unsigned int curptr; 652 int timeout = 1000; 653 654 while (timeout--) { 655 curptr = readl(chip->remap_addr + dma->ops->dt_cur); 656 if (curptr < dma->buf_addr) 657 continue; 658 curptr -= dma->buf_addr; 659 if (curptr >= dma->buf_bytes) 660 continue; 661 return bytes_to_frames(runtime, curptr); 662 } 663 dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n", 664 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr); 665 return 0; 666 } 667 668 /* 669 * XRUN detected, and stop the PCM substream 670 */ 671 static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma) 672 { 673 if (! dma->substream || ! dma->running) 674 return; 675 dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type); 676 snd_pcm_stop_xrun(dma->substream); 677 } 678 679 /* 680 * the period ack. update the substream. 681 */ 682 static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma) 683 { 684 if (! dma->substream || ! dma->running) 685 return; 686 snd_pcm_period_elapsed(dma->substream); 687 } 688 689 /* set BUS_BUSY interrupt bit if any DMA is running */ 690 /* call with spinlock held */ 691 static void snd_atiixp_check_bus_busy(struct atiixp *chip) 692 { 693 unsigned int bus_busy; 694 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN | 695 ATI_REG_CMD_RECEIVE_EN | 696 ATI_REG_CMD_SPDF_OUT_EN)) 697 bus_busy = ATI_REG_IER_SET_BUS_BUSY; 698 else 699 bus_busy = 0; 700 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy); 701 } 702 703 /* common trigger callback 704 * calling the lowlevel callbacks in it 705 */ 706 static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 707 { 708 struct atiixp *chip = snd_pcm_substream_chip(substream); 709 struct atiixp_dma *dma = substream->runtime->private_data; 710 int err = 0; 711 712 if (snd_BUG_ON(!dma->ops->enable_transfer || 713 !dma->ops->flush_dma)) 714 return -EINVAL; 715 716 spin_lock(&chip->reg_lock); 717 switch (cmd) { 718 case SNDRV_PCM_TRIGGER_START: 719 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 720 case SNDRV_PCM_TRIGGER_RESUME: 721 if (dma->running && dma->suspended && 722 cmd == SNDRV_PCM_TRIGGER_RESUME) 723 writel(dma->saved_curptr, chip->remap_addr + 724 dma->ops->dt_cur); 725 dma->ops->enable_transfer(chip, 1); 726 dma->running = 1; 727 dma->suspended = 0; 728 break; 729 case SNDRV_PCM_TRIGGER_STOP: 730 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 731 case SNDRV_PCM_TRIGGER_SUSPEND: 732 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND; 733 if (dma->running && dma->suspended) 734 dma->saved_curptr = readl(chip->remap_addr + 735 dma->ops->dt_cur); 736 dma->ops->enable_transfer(chip, 0); 737 dma->running = 0; 738 break; 739 default: 740 err = -EINVAL; 741 break; 742 } 743 if (! err) { 744 snd_atiixp_check_bus_busy(chip); 745 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 746 dma->ops->flush_dma(chip); 747 snd_atiixp_check_bus_busy(chip); 748 } 749 } 750 spin_unlock(&chip->reg_lock); 751 return err; 752 } 753 754 755 /* 756 * lowlevel callbacks for each DMA type 757 * 758 * every callback is supposed to be called in chip->reg_lock spinlock 759 */ 760 761 /* flush FIFO of analog OUT DMA */ 762 static void atiixp_out_flush_dma(struct atiixp *chip) 763 { 764 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH); 765 } 766 767 /* enable/disable analog OUT DMA */ 768 static void atiixp_out_enable_dma(struct atiixp *chip, int on) 769 { 770 unsigned int data; 771 data = atiixp_read(chip, CMD); 772 if (on) { 773 if (data & ATI_REG_CMD_OUT_DMA_EN) 774 return; 775 atiixp_out_flush_dma(chip); 776 data |= ATI_REG_CMD_OUT_DMA_EN; 777 } else 778 data &= ~ATI_REG_CMD_OUT_DMA_EN; 779 atiixp_write(chip, CMD, data); 780 } 781 782 /* start/stop transfer over OUT DMA */ 783 static void atiixp_out_enable_transfer(struct atiixp *chip, int on) 784 { 785 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN, 786 on ? ATI_REG_CMD_SEND_EN : 0); 787 } 788 789 /* enable/disable analog IN DMA */ 790 static void atiixp_in_enable_dma(struct atiixp *chip, int on) 791 { 792 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN, 793 on ? ATI_REG_CMD_IN_DMA_EN : 0); 794 } 795 796 /* start/stop analog IN DMA */ 797 static void atiixp_in_enable_transfer(struct atiixp *chip, int on) 798 { 799 if (on) { 800 unsigned int data = atiixp_read(chip, CMD); 801 if (! (data & ATI_REG_CMD_RECEIVE_EN)) { 802 data |= ATI_REG_CMD_RECEIVE_EN; 803 #if 0 /* FIXME: this causes the endless loop */ 804 /* wait until slot 3/4 are finished */ 805 while ((atiixp_read(chip, COUNTER) & 806 ATI_REG_COUNTER_SLOT) != 5) 807 ; 808 #endif 809 atiixp_write(chip, CMD, data); 810 } 811 } else 812 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0); 813 } 814 815 /* flush FIFO of analog IN DMA */ 816 static void atiixp_in_flush_dma(struct atiixp *chip) 817 { 818 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH); 819 } 820 821 /* enable/disable SPDIF OUT DMA */ 822 static void atiixp_spdif_enable_dma(struct atiixp *chip, int on) 823 { 824 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN, 825 on ? ATI_REG_CMD_SPDF_DMA_EN : 0); 826 } 827 828 /* start/stop SPDIF OUT DMA */ 829 static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on) 830 { 831 unsigned int data; 832 data = atiixp_read(chip, CMD); 833 if (on) 834 data |= ATI_REG_CMD_SPDF_OUT_EN; 835 else 836 data &= ~ATI_REG_CMD_SPDF_OUT_EN; 837 atiixp_write(chip, CMD, data); 838 } 839 840 /* flush FIFO of SPDIF OUT DMA */ 841 static void atiixp_spdif_flush_dma(struct atiixp *chip) 842 { 843 int timeout; 844 845 /* DMA off, transfer on */ 846 atiixp_spdif_enable_dma(chip, 0); 847 atiixp_spdif_enable_transfer(chip, 1); 848 849 timeout = 100; 850 do { 851 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED)) 852 break; 853 udelay(1); 854 } while (timeout-- > 0); 855 856 atiixp_spdif_enable_transfer(chip, 0); 857 } 858 859 /* set up slots and formats for SPDIF OUT */ 860 static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream) 861 { 862 struct atiixp *chip = snd_pcm_substream_chip(substream); 863 864 spin_lock_irq(&chip->reg_lock); 865 if (chip->spdif_over_aclink) { 866 unsigned int data; 867 /* enable slots 10/11 */ 868 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 869 ATI_REG_CMD_SPDF_CONFIG_01); 870 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; 871 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | 872 ATI_REG_OUT_DMA_SLOT_BIT(11); 873 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 874 atiixp_write(chip, OUT_DMA_SLOT, data); 875 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, 876 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 877 ATI_REG_CMD_INTERLEAVE_OUT : 0); 878 } else { 879 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0); 880 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0); 881 } 882 spin_unlock_irq(&chip->reg_lock); 883 return 0; 884 } 885 886 /* set up slots and formats for analog OUT */ 887 static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream) 888 { 889 struct atiixp *chip = snd_pcm_substream_chip(substream); 890 unsigned int data; 891 892 spin_lock_irq(&chip->reg_lock); 893 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; 894 switch (substream->runtime->channels) { 895 case 8: 896 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | 897 ATI_REG_OUT_DMA_SLOT_BIT(11); 898 fallthrough; 899 case 6: 900 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) | 901 ATI_REG_OUT_DMA_SLOT_BIT(8); 902 fallthrough; 903 case 4: 904 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) | 905 ATI_REG_OUT_DMA_SLOT_BIT(9); 906 fallthrough; 907 default: 908 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 909 ATI_REG_OUT_DMA_SLOT_BIT(4); 910 break; 911 } 912 913 /* set output threshold */ 914 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 915 atiixp_write(chip, OUT_DMA_SLOT, data); 916 917 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, 918 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 919 ATI_REG_CMD_INTERLEAVE_OUT : 0); 920 921 /* 922 * enable 6 channel re-ordering bit if needed 923 */ 924 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN, 925 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0); 926 927 spin_unlock_irq(&chip->reg_lock); 928 return 0; 929 } 930 931 /* set up slots and formats for analog IN */ 932 static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream) 933 { 934 struct atiixp *chip = snd_pcm_substream_chip(substream); 935 936 spin_lock_irq(&chip->reg_lock); 937 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN, 938 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 939 ATI_REG_CMD_INTERLEAVE_IN : 0); 940 spin_unlock_irq(&chip->reg_lock); 941 return 0; 942 } 943 944 /* 945 * hw_params - allocate the buffer and set up buffer descriptors 946 */ 947 static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream, 948 struct snd_pcm_hw_params *hw_params) 949 { 950 struct atiixp *chip = snd_pcm_substream_chip(substream); 951 struct atiixp_dma *dma = substream->runtime->private_data; 952 int err; 953 954 dma->buf_addr = substream->runtime->dma_addr; 955 dma->buf_bytes = params_buffer_bytes(hw_params); 956 957 err = atiixp_build_dma_packets(chip, dma, substream, 958 params_periods(hw_params), 959 params_period_bytes(hw_params)); 960 if (err < 0) 961 return err; 962 963 if (dma->ac97_pcm_type >= 0) { 964 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; 965 /* PCM is bound to AC97 codec(s) 966 * set up the AC97 codecs 967 */ 968 if (dma->pcm_open_flag) { 969 snd_ac97_pcm_close(pcm); 970 dma->pcm_open_flag = 0; 971 } 972 err = snd_ac97_pcm_open(pcm, params_rate(hw_params), 973 params_channels(hw_params), 974 pcm->r[0].slots); 975 if (err >= 0) 976 dma->pcm_open_flag = 1; 977 } 978 979 return err; 980 } 981 982 static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream) 983 { 984 struct atiixp *chip = snd_pcm_substream_chip(substream); 985 struct atiixp_dma *dma = substream->runtime->private_data; 986 987 if (dma->pcm_open_flag) { 988 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; 989 snd_ac97_pcm_close(pcm); 990 dma->pcm_open_flag = 0; 991 } 992 atiixp_clear_dma_packets(chip, dma, substream); 993 return 0; 994 } 995 996 997 /* 998 * pcm hardware definition, identical for all DMA types 999 */ 1000 static const struct snd_pcm_hardware snd_atiixp_pcm_hw = 1001 { 1002 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1003 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1004 SNDRV_PCM_INFO_PAUSE | 1005 SNDRV_PCM_INFO_RESUME | 1006 SNDRV_PCM_INFO_MMAP_VALID), 1007 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1008 .rates = SNDRV_PCM_RATE_48000, 1009 .rate_min = 48000, 1010 .rate_max = 48000, 1011 .channels_min = 2, 1012 .channels_max = 2, 1013 .buffer_bytes_max = 256 * 1024, 1014 .period_bytes_min = 32, 1015 .period_bytes_max = 128 * 1024, 1016 .periods_min = 2, 1017 .periods_max = ATI_MAX_DESCRIPTORS, 1018 }; 1019 1020 static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream, 1021 struct atiixp_dma *dma, int pcm_type) 1022 { 1023 struct atiixp *chip = snd_pcm_substream_chip(substream); 1024 struct snd_pcm_runtime *runtime = substream->runtime; 1025 int err; 1026 1027 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) 1028 return -EINVAL; 1029 1030 if (dma->opened) 1031 return -EBUSY; 1032 dma->substream = substream; 1033 runtime->hw = snd_atiixp_pcm_hw; 1034 dma->ac97_pcm_type = pcm_type; 1035 if (pcm_type >= 0) { 1036 runtime->hw.rates = chip->pcms[pcm_type]->rates; 1037 snd_pcm_limit_hw_rates(runtime); 1038 } else { 1039 /* direct SPDIF */ 1040 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 1041 } 1042 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1043 if (err < 0) 1044 return err; 1045 runtime->private_data = dma; 1046 1047 /* enable DMA bits */ 1048 spin_lock_irq(&chip->reg_lock); 1049 dma->ops->enable_dma(chip, 1); 1050 spin_unlock_irq(&chip->reg_lock); 1051 dma->opened = 1; 1052 1053 return 0; 1054 } 1055 1056 static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream, 1057 struct atiixp_dma *dma) 1058 { 1059 struct atiixp *chip = snd_pcm_substream_chip(substream); 1060 /* disable DMA bits */ 1061 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) 1062 return -EINVAL; 1063 spin_lock_irq(&chip->reg_lock); 1064 dma->ops->enable_dma(chip, 0); 1065 spin_unlock_irq(&chip->reg_lock); 1066 dma->substream = NULL; 1067 dma->opened = 0; 1068 return 0; 1069 } 1070 1071 /* 1072 */ 1073 static int snd_atiixp_playback_open(struct snd_pcm_substream *substream) 1074 { 1075 struct atiixp *chip = snd_pcm_substream_chip(substream); 1076 int err; 1077 1078 mutex_lock(&chip->open_mutex); 1079 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0); 1080 mutex_unlock(&chip->open_mutex); 1081 if (err < 0) 1082 return err; 1083 substream->runtime->hw.channels_max = chip->max_channels; 1084 if (chip->max_channels > 2) 1085 /* channels must be even */ 1086 snd_pcm_hw_constraint_step(substream->runtime, 0, 1087 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1088 return 0; 1089 } 1090 1091 static int snd_atiixp_playback_close(struct snd_pcm_substream *substream) 1092 { 1093 struct atiixp *chip = snd_pcm_substream_chip(substream); 1094 int err; 1095 mutex_lock(&chip->open_mutex); 1096 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); 1097 mutex_unlock(&chip->open_mutex); 1098 return err; 1099 } 1100 1101 static int snd_atiixp_capture_open(struct snd_pcm_substream *substream) 1102 { 1103 struct atiixp *chip = snd_pcm_substream_chip(substream); 1104 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1); 1105 } 1106 1107 static int snd_atiixp_capture_close(struct snd_pcm_substream *substream) 1108 { 1109 struct atiixp *chip = snd_pcm_substream_chip(substream); 1110 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]); 1111 } 1112 1113 static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream) 1114 { 1115 struct atiixp *chip = snd_pcm_substream_chip(substream); 1116 int err; 1117 mutex_lock(&chip->open_mutex); 1118 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */ 1119 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2); 1120 else 1121 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1); 1122 mutex_unlock(&chip->open_mutex); 1123 return err; 1124 } 1125 1126 static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream) 1127 { 1128 struct atiixp *chip = snd_pcm_substream_chip(substream); 1129 int err; 1130 mutex_lock(&chip->open_mutex); 1131 if (chip->spdif_over_aclink) 1132 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); 1133 else 1134 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]); 1135 mutex_unlock(&chip->open_mutex); 1136 return err; 1137 } 1138 1139 /* AC97 playback */ 1140 static const struct snd_pcm_ops snd_atiixp_playback_ops = { 1141 .open = snd_atiixp_playback_open, 1142 .close = snd_atiixp_playback_close, 1143 .hw_params = snd_atiixp_pcm_hw_params, 1144 .hw_free = snd_atiixp_pcm_hw_free, 1145 .prepare = snd_atiixp_playback_prepare, 1146 .trigger = snd_atiixp_pcm_trigger, 1147 .pointer = snd_atiixp_pcm_pointer, 1148 }; 1149 1150 /* AC97 capture */ 1151 static const struct snd_pcm_ops snd_atiixp_capture_ops = { 1152 .open = snd_atiixp_capture_open, 1153 .close = snd_atiixp_capture_close, 1154 .hw_params = snd_atiixp_pcm_hw_params, 1155 .hw_free = snd_atiixp_pcm_hw_free, 1156 .prepare = snd_atiixp_capture_prepare, 1157 .trigger = snd_atiixp_pcm_trigger, 1158 .pointer = snd_atiixp_pcm_pointer, 1159 }; 1160 1161 /* SPDIF playback */ 1162 static const struct snd_pcm_ops snd_atiixp_spdif_ops = { 1163 .open = snd_atiixp_spdif_open, 1164 .close = snd_atiixp_spdif_close, 1165 .hw_params = snd_atiixp_pcm_hw_params, 1166 .hw_free = snd_atiixp_pcm_hw_free, 1167 .prepare = snd_atiixp_spdif_prepare, 1168 .trigger = snd_atiixp_pcm_trigger, 1169 .pointer = snd_atiixp_pcm_pointer, 1170 }; 1171 1172 static const struct ac97_pcm atiixp_pcm_defs[] = { 1173 /* front PCM */ 1174 { 1175 .exclusive = 1, 1176 .r = { { 1177 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1178 (1 << AC97_SLOT_PCM_RIGHT) | 1179 (1 << AC97_SLOT_PCM_CENTER) | 1180 (1 << AC97_SLOT_PCM_SLEFT) | 1181 (1 << AC97_SLOT_PCM_SRIGHT) | 1182 (1 << AC97_SLOT_LFE) 1183 } 1184 } 1185 }, 1186 /* PCM IN #1 */ 1187 { 1188 .stream = 1, 1189 .exclusive = 1, 1190 .r = { { 1191 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1192 (1 << AC97_SLOT_PCM_RIGHT) 1193 } 1194 } 1195 }, 1196 /* S/PDIF OUT (optional) */ 1197 { 1198 .exclusive = 1, 1199 .spdif = 1, 1200 .r = { { 1201 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1202 (1 << AC97_SLOT_SPDIF_RIGHT2) 1203 } 1204 } 1205 }, 1206 }; 1207 1208 static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = { 1209 .type = ATI_DMA_PLAYBACK, 1210 .llp_offset = ATI_REG_OUT_DMA_LINKPTR, 1211 .dt_cur = ATI_REG_OUT_DMA_DT_CUR, 1212 .enable_dma = atiixp_out_enable_dma, 1213 .enable_transfer = atiixp_out_enable_transfer, 1214 .flush_dma = atiixp_out_flush_dma, 1215 }; 1216 1217 static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = { 1218 .type = ATI_DMA_CAPTURE, 1219 .llp_offset = ATI_REG_IN_DMA_LINKPTR, 1220 .dt_cur = ATI_REG_IN_DMA_DT_CUR, 1221 .enable_dma = atiixp_in_enable_dma, 1222 .enable_transfer = atiixp_in_enable_transfer, 1223 .flush_dma = atiixp_in_flush_dma, 1224 }; 1225 1226 static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = { 1227 .type = ATI_DMA_SPDIF, 1228 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR, 1229 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR, 1230 .enable_dma = atiixp_spdif_enable_dma, 1231 .enable_transfer = atiixp_spdif_enable_transfer, 1232 .flush_dma = atiixp_spdif_flush_dma, 1233 }; 1234 1235 1236 static int snd_atiixp_pcm_new(struct atiixp *chip) 1237 { 1238 struct snd_pcm *pcm; 1239 struct snd_pcm_chmap *chmap; 1240 struct snd_ac97_bus *pbus = chip->ac97_bus; 1241 int err, i, num_pcms; 1242 1243 /* initialize constants */ 1244 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops; 1245 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops; 1246 if (! chip->spdif_over_aclink) 1247 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops; 1248 1249 /* assign AC97 pcm */ 1250 if (chip->spdif_over_aclink) 1251 num_pcms = 3; 1252 else 1253 num_pcms = 2; 1254 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs); 1255 if (err < 0) 1256 return err; 1257 for (i = 0; i < num_pcms; i++) 1258 chip->pcms[i] = &pbus->pcms[i]; 1259 1260 chip->max_channels = 2; 1261 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 1262 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE)) 1263 chip->max_channels = 6; 1264 else 1265 chip->max_channels = 4; 1266 } 1267 1268 /* PCM #0: analog I/O */ 1269 err = snd_pcm_new(chip->card, "ATI IXP AC97", 1270 ATI_PCMDEV_ANALOG, 1, 1, &pcm); 1271 if (err < 0) 1272 return err; 1273 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops); 1274 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops); 1275 pcm->private_data = chip; 1276 strcpy(pcm->name, "ATI IXP AC97"); 1277 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm; 1278 1279 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1280 &chip->pci->dev, 64*1024, 128*1024); 1281 1282 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1283 snd_pcm_alt_chmaps, chip->max_channels, 0, 1284 &chmap); 1285 if (err < 0) 1286 return err; 1287 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; 1288 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; 1289 1290 /* no SPDIF support on codec? */ 1291 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates) 1292 return 0; 1293 1294 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */ 1295 if (chip->pcms[ATI_PCM_SPDIF]) 1296 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000; 1297 1298 /* PCM #1: spdif playback */ 1299 err = snd_pcm_new(chip->card, "ATI IXP IEC958", 1300 ATI_PCMDEV_DIGITAL, 1, 0, &pcm); 1301 if (err < 0) 1302 return err; 1303 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops); 1304 pcm->private_data = chip; 1305 if (chip->spdif_over_aclink) 1306 strcpy(pcm->name, "ATI IXP IEC958 (AC97)"); 1307 else 1308 strcpy(pcm->name, "ATI IXP IEC958 (Direct)"); 1309 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm; 1310 1311 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1312 &chip->pci->dev, 64*1024, 128*1024); 1313 1314 /* pre-select AC97 SPDIF slots 10/11 */ 1315 for (i = 0; i < NUM_ATI_CODECS; i++) { 1316 if (chip->ac97[i]) 1317 snd_ac97_update_bits(chip->ac97[i], 1318 AC97_EXTENDED_STATUS, 1319 0x03 << 4, 0x03 << 4); 1320 } 1321 1322 return 0; 1323 } 1324 1325 1326 1327 /* 1328 * interrupt handler 1329 */ 1330 static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id) 1331 { 1332 struct atiixp *chip = dev_id; 1333 unsigned int status; 1334 1335 status = atiixp_read(chip, ISR); 1336 1337 if (! status) 1338 return IRQ_NONE; 1339 1340 /* process audio DMA */ 1341 if (status & ATI_REG_ISR_OUT_XRUN) 1342 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); 1343 else if (status & ATI_REG_ISR_OUT_STATUS) 1344 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); 1345 if (status & ATI_REG_ISR_IN_XRUN) 1346 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); 1347 else if (status & ATI_REG_ISR_IN_STATUS) 1348 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); 1349 if (! chip->spdif_over_aclink) { 1350 if (status & ATI_REG_ISR_SPDF_XRUN) 1351 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); 1352 else if (status & ATI_REG_ISR_SPDF_STATUS) 1353 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); 1354 } 1355 1356 /* for codec detection */ 1357 if (status & CODEC_CHECK_BITS) { 1358 unsigned int detected; 1359 detected = status & CODEC_CHECK_BITS; 1360 spin_lock(&chip->reg_lock); 1361 chip->codec_not_ready_bits |= detected; 1362 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */ 1363 spin_unlock(&chip->reg_lock); 1364 } 1365 1366 /* ack */ 1367 atiixp_write(chip, ISR, status); 1368 1369 return IRQ_HANDLED; 1370 } 1371 1372 1373 /* 1374 * ac97 mixer section 1375 */ 1376 1377 static const struct ac97_quirk ac97_quirks[] = { 1378 { 1379 .subvendor = 0x103c, 1380 .subdevice = 0x006b, 1381 .name = "HP Pavilion ZV5030US", 1382 .type = AC97_TUNE_MUTE_LED 1383 }, 1384 { 1385 .subvendor = 0x103c, 1386 .subdevice = 0x308b, 1387 .name = "HP nx6125", 1388 .type = AC97_TUNE_MUTE_LED 1389 }, 1390 { 1391 .subvendor = 0x103c, 1392 .subdevice = 0x3091, 1393 .name = "unknown HP", 1394 .type = AC97_TUNE_MUTE_LED 1395 }, 1396 { } /* terminator */ 1397 }; 1398 1399 static int snd_atiixp_mixer_new(struct atiixp *chip, int clock, 1400 const char *quirk_override) 1401 { 1402 struct snd_ac97_bus *pbus; 1403 struct snd_ac97_template ac97; 1404 int i, err; 1405 int codec_count; 1406 static const struct snd_ac97_bus_ops ops = { 1407 .write = snd_atiixp_ac97_write, 1408 .read = snd_atiixp_ac97_read, 1409 }; 1410 static const unsigned int codec_skip[NUM_ATI_CODECS] = { 1411 ATI_REG_ISR_CODEC0_NOT_READY, 1412 ATI_REG_ISR_CODEC1_NOT_READY, 1413 ATI_REG_ISR_CODEC2_NOT_READY, 1414 }; 1415 1416 if (snd_atiixp_codec_detect(chip) < 0) 1417 return -ENXIO; 1418 1419 err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus); 1420 if (err < 0) 1421 return err; 1422 pbus->clock = clock; 1423 chip->ac97_bus = pbus; 1424 1425 codec_count = 0; 1426 for (i = 0; i < NUM_ATI_CODECS; i++) { 1427 if (chip->codec_not_ready_bits & codec_skip[i]) 1428 continue; 1429 memset(&ac97, 0, sizeof(ac97)); 1430 ac97.private_data = chip; 1431 ac97.pci = chip->pci; 1432 ac97.num = i; 1433 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 1434 if (! chip->spdif_over_aclink) 1435 ac97.scaps |= AC97_SCAP_NO_SPDIF; 1436 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]); 1437 if (err < 0) { 1438 chip->ac97[i] = NULL; /* to be sure */ 1439 dev_dbg(chip->card->dev, 1440 "codec %d not available for audio\n", i); 1441 continue; 1442 } 1443 codec_count++; 1444 } 1445 1446 if (! codec_count) { 1447 dev_err(chip->card->dev, "no codec available\n"); 1448 return -ENODEV; 1449 } 1450 1451 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 1452 1453 return 0; 1454 } 1455 1456 1457 #ifdef CONFIG_PM_SLEEP 1458 /* 1459 * power management 1460 */ 1461 static int snd_atiixp_suspend(struct device *dev) 1462 { 1463 struct snd_card *card = dev_get_drvdata(dev); 1464 struct atiixp *chip = card->private_data; 1465 int i; 1466 1467 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1468 for (i = 0; i < NUM_ATI_CODECS; i++) 1469 snd_ac97_suspend(chip->ac97[i]); 1470 snd_atiixp_aclink_down(chip); 1471 snd_atiixp_chip_stop(chip); 1472 return 0; 1473 } 1474 1475 static int snd_atiixp_resume(struct device *dev) 1476 { 1477 struct snd_card *card = dev_get_drvdata(dev); 1478 struct atiixp *chip = card->private_data; 1479 int i; 1480 1481 snd_atiixp_aclink_reset(chip); 1482 snd_atiixp_chip_start(chip); 1483 1484 for (i = 0; i < NUM_ATI_CODECS; i++) 1485 snd_ac97_resume(chip->ac97[i]); 1486 1487 for (i = 0; i < NUM_ATI_PCMDEVS; i++) 1488 if (chip->pcmdevs[i]) { 1489 struct atiixp_dma *dma = &chip->dmas[i]; 1490 if (dma->substream && dma->suspended) { 1491 dma->ops->enable_dma(chip, 1); 1492 dma->substream->ops->prepare(dma->substream); 1493 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, 1494 chip->remap_addr + dma->ops->llp_offset); 1495 } 1496 } 1497 1498 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1499 return 0; 1500 } 1501 1502 static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume); 1503 #define SND_ATIIXP_PM_OPS &snd_atiixp_pm 1504 #else 1505 #define SND_ATIIXP_PM_OPS NULL 1506 #endif /* CONFIG_PM_SLEEP */ 1507 1508 1509 /* 1510 * proc interface for register dump 1511 */ 1512 1513 static void snd_atiixp_proc_read(struct snd_info_entry *entry, 1514 struct snd_info_buffer *buffer) 1515 { 1516 struct atiixp *chip = entry->private_data; 1517 int i; 1518 1519 for (i = 0; i < 256; i += 4) 1520 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i)); 1521 } 1522 1523 static void snd_atiixp_proc_init(struct atiixp *chip) 1524 { 1525 snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read); 1526 } 1527 1528 1529 /* 1530 * destructor 1531 */ 1532 1533 static int snd_atiixp_free(struct atiixp *chip) 1534 { 1535 if (chip->irq < 0) 1536 goto __hw_end; 1537 snd_atiixp_chip_stop(chip); 1538 1539 __hw_end: 1540 if (chip->irq >= 0) 1541 free_irq(chip->irq, chip); 1542 iounmap(chip->remap_addr); 1543 pci_release_regions(chip->pci); 1544 pci_disable_device(chip->pci); 1545 kfree(chip); 1546 return 0; 1547 } 1548 1549 static int snd_atiixp_dev_free(struct snd_device *device) 1550 { 1551 struct atiixp *chip = device->device_data; 1552 return snd_atiixp_free(chip); 1553 } 1554 1555 /* 1556 * constructor for chip instance 1557 */ 1558 static int snd_atiixp_create(struct snd_card *card, 1559 struct pci_dev *pci, 1560 struct atiixp **r_chip) 1561 { 1562 static const struct snd_device_ops ops = { 1563 .dev_free = snd_atiixp_dev_free, 1564 }; 1565 struct atiixp *chip; 1566 int err; 1567 1568 err = pci_enable_device(pci); 1569 if (err < 0) 1570 return err; 1571 1572 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1573 if (chip == NULL) { 1574 pci_disable_device(pci); 1575 return -ENOMEM; 1576 } 1577 1578 spin_lock_init(&chip->reg_lock); 1579 mutex_init(&chip->open_mutex); 1580 chip->card = card; 1581 chip->pci = pci; 1582 chip->irq = -1; 1583 err = pci_request_regions(pci, "ATI IXP AC97"); 1584 if (err < 0) { 1585 pci_disable_device(pci); 1586 kfree(chip); 1587 return err; 1588 } 1589 chip->addr = pci_resource_start(pci, 0); 1590 chip->remap_addr = pci_ioremap_bar(pci, 0); 1591 if (chip->remap_addr == NULL) { 1592 dev_err(card->dev, "AC'97 space ioremap problem\n"); 1593 snd_atiixp_free(chip); 1594 return -EIO; 1595 } 1596 1597 if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED, 1598 KBUILD_MODNAME, chip)) { 1599 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 1600 snd_atiixp_free(chip); 1601 return -EBUSY; 1602 } 1603 chip->irq = pci->irq; 1604 card->sync_irq = chip->irq; 1605 pci_set_master(pci); 1606 1607 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1608 if (err < 0) { 1609 snd_atiixp_free(chip); 1610 return err; 1611 } 1612 1613 *r_chip = chip; 1614 return 0; 1615 } 1616 1617 1618 static int snd_atiixp_probe(struct pci_dev *pci, 1619 const struct pci_device_id *pci_id) 1620 { 1621 struct snd_card *card; 1622 struct atiixp *chip; 1623 int err; 1624 1625 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); 1626 if (err < 0) 1627 return err; 1628 1629 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA"); 1630 strcpy(card->shortname, "ATI IXP"); 1631 err = snd_atiixp_create(card, pci, &chip); 1632 if (err < 0) 1633 goto __error; 1634 card->private_data = chip; 1635 1636 err = snd_atiixp_aclink_reset(chip); 1637 if (err < 0) 1638 goto __error; 1639 1640 chip->spdif_over_aclink = spdif_aclink; 1641 1642 err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk); 1643 if (err < 0) 1644 goto __error; 1645 1646 err = snd_atiixp_pcm_new(chip); 1647 if (err < 0) 1648 goto __error; 1649 1650 snd_atiixp_proc_init(chip); 1651 1652 snd_atiixp_chip_start(chip); 1653 1654 snprintf(card->longname, sizeof(card->longname), 1655 "%s rev %x with %s at %#lx, irq %i", card->shortname, 1656 pci->revision, 1657 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?", 1658 chip->addr, chip->irq); 1659 1660 err = snd_card_register(card); 1661 if (err < 0) 1662 goto __error; 1663 1664 pci_set_drvdata(pci, card); 1665 return 0; 1666 1667 __error: 1668 snd_card_free(card); 1669 return err; 1670 } 1671 1672 static void snd_atiixp_remove(struct pci_dev *pci) 1673 { 1674 snd_card_free(pci_get_drvdata(pci)); 1675 } 1676 1677 static struct pci_driver atiixp_driver = { 1678 .name = KBUILD_MODNAME, 1679 .id_table = snd_atiixp_ids, 1680 .probe = snd_atiixp_probe, 1681 .remove = snd_atiixp_remove, 1682 .driver = { 1683 .pm = SND_ATIIXP_PM_OPS, 1684 }, 1685 }; 1686 1687 module_pci_driver(atiixp_driver); 1688