1 /****************************************************************************** 2 3 AudioScience HPI driver 4 Copyright (C) 1997-2011 AudioScience Inc. <support@audioscience.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of version 2 of the GNU General Public License as 8 published by the Free Software Foundation; 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 19 Hardware Programming Interface (HPI) for AudioScience 20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters. 21 These PCI and PCIe bus adapters are based on a 22 TMS320C6205 PCI bus mastering DSP, 23 and (except ASI50xx) TI TMS320C6xxx floating point DSP 24 25 Exported function: 26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) 27 28 (C) Copyright AudioScience Inc. 1998-2010 29 *******************************************************************************/ 30 #define SOURCEFILE_NAME "hpi6205.c" 31 32 #include "hpi_internal.h" 33 #include "hpimsginit.h" 34 #include "hpidebug.h" 35 #include "hpi6205.h" 36 #include "hpidspcd.h" 37 #include "hpicmn.h" 38 39 /*****************************************************************************/ 40 /* HPI6205 specific error codes */ 41 #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */ 42 43 /* operational/messaging errors */ 44 #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015 45 #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016 46 47 /* initialization/bootload errors */ 48 #define HPI6205_ERROR_6205_NO_IRQ 1002 49 #define HPI6205_ERROR_6205_INIT_FAILED 1003 50 #define HPI6205_ERROR_6205_REG 1006 51 #define HPI6205_ERROR_6205_DSPPAGE 1007 52 #define HPI6205_ERROR_C6713_HPIC 1009 53 #define HPI6205_ERROR_C6713_HPIA 1010 54 #define HPI6205_ERROR_C6713_PLL 1011 55 #define HPI6205_ERROR_DSP_INTMEM 1012 56 #define HPI6205_ERROR_DSP_EXTMEM 1013 57 #define HPI6205_ERROR_DSP_PLD 1014 58 #define HPI6205_ERROR_6205_EEPROM 1017 59 #define HPI6205_ERROR_DSP_EMIF1 1018 60 #define HPI6205_ERROR_DSP_EMIF2 1019 61 #define HPI6205_ERROR_DSP_EMIF3 1020 62 #define HPI6205_ERROR_DSP_EMIF4 1021 63 64 /*****************************************************************************/ 65 /* for C6205 PCI i/f */ 66 /* Host Status Register (HSR) bitfields */ 67 #define C6205_HSR_INTSRC 0x01 68 #define C6205_HSR_INTAVAL 0x02 69 #define C6205_HSR_INTAM 0x04 70 #define C6205_HSR_CFGERR 0x08 71 #define C6205_HSR_EEREAD 0x10 72 /* Host-to-DSP Control Register (HDCR) bitfields */ 73 #define C6205_HDCR_WARMRESET 0x01 74 #define C6205_HDCR_DSPINT 0x02 75 #define C6205_HDCR_PCIBOOT 0x04 76 /* DSP Page Register (DSPP) bitfields, */ 77 /* defines 4 Mbyte page that BAR0 points to */ 78 #define C6205_DSPP_MAP1 0x400 79 80 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP. 81 * BAR1 maps to non-prefetchable 8 Mbyte memory block 82 * of DSP memory mapped registers (starting at 0x01800000). 83 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this 84 * needs to be added to the BAR1 base address set in the PCI config reg 85 */ 86 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L) 87 #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET) 88 #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4) 89 #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8) 90 91 /* used to control LED (revA) and reset C6713 (revB) */ 92 #define C6205_BAR0_TIMER1_CTL (0x01980000L) 93 94 /* For first 6713 in CE1 space, using DA17,16,2 */ 95 #define HPICL_ADDR 0x01400000L 96 #define HPICH_ADDR 0x01400004L 97 #define HPIAL_ADDR 0x01410000L 98 #define HPIAH_ADDR 0x01410004L 99 #define HPIDIL_ADDR 0x01420000L 100 #define HPIDIH_ADDR 0x01420004L 101 #define HPIDL_ADDR 0x01430000L 102 #define HPIDH_ADDR 0x01430004L 103 104 #define C6713_EMIF_GCTL 0x01800000 105 #define C6713_EMIF_CE1 0x01800004 106 #define C6713_EMIF_CE0 0x01800008 107 #define C6713_EMIF_CE2 0x01800010 108 #define C6713_EMIF_CE3 0x01800014 109 #define C6713_EMIF_SDRAMCTL 0x01800018 110 #define C6713_EMIF_SDRAMTIMING 0x0180001C 111 #define C6713_EMIF_SDRAMEXT 0x01800020 112 113 struct hpi_hw_obj { 114 /* PCI registers */ 115 __iomem u32 *prHSR; 116 __iomem u32 *prHDCR; 117 __iomem u32 *prDSPP; 118 119 u32 dsp_page; 120 121 struct consistent_dma_area h_locked_mem; 122 struct bus_master_interface *p_interface_buffer; 123 124 u16 flag_outstream_just_reset[HPI_MAX_STREAMS]; 125 /* a non-NULL handle means there is an HPI allocated buffer */ 126 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS]; 127 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS]; 128 /* non-zero size means a buffer exists, may be external */ 129 u32 instream_host_buffer_size[HPI_MAX_STREAMS]; 130 u32 outstream_host_buffer_size[HPI_MAX_STREAMS]; 131 132 struct consistent_dma_area h_control_cache; 133 struct hpi_control_cache *p_cache; 134 }; 135 136 /*****************************************************************************/ 137 /* local prototypes */ 138 139 #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write) 140 141 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us); 142 143 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd); 144 145 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 146 u32 *pos_error_code); 147 148 static u16 message_response_sequence(struct hpi_adapter_obj *pao, 149 struct hpi_message *phm, struct hpi_response *phr); 150 151 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 152 struct hpi_response *phr); 153 154 #define HPI6205_TIMEOUT 1000000 155 156 static void subsys_create_adapter(struct hpi_message *phm, 157 struct hpi_response *phr); 158 static void adapter_delete(struct hpi_adapter_obj *pao, 159 struct hpi_message *phm, struct hpi_response *phr); 160 161 static u16 create_adapter_obj(struct hpi_adapter_obj *pao, 162 u32 *pos_error_code); 163 164 static void delete_adapter_obj(struct hpi_adapter_obj *pao); 165 166 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, 167 struct hpi_message *phm, struct hpi_response *phr); 168 169 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, 170 struct hpi_message *phm, struct hpi_response *phr); 171 172 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, 173 struct hpi_message *phm, struct hpi_response *phr); 174 static void outstream_write(struct hpi_adapter_obj *pao, 175 struct hpi_message *phm, struct hpi_response *phr); 176 177 static void outstream_get_info(struct hpi_adapter_obj *pao, 178 struct hpi_message *phm, struct hpi_response *phr); 179 180 static void outstream_start(struct hpi_adapter_obj *pao, 181 struct hpi_message *phm, struct hpi_response *phr); 182 183 static void outstream_open(struct hpi_adapter_obj *pao, 184 struct hpi_message *phm, struct hpi_response *phr); 185 186 static void outstream_reset(struct hpi_adapter_obj *pao, 187 struct hpi_message *phm, struct hpi_response *phr); 188 189 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, 190 struct hpi_message *phm, struct hpi_response *phr); 191 192 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, 193 struct hpi_message *phm, struct hpi_response *phr); 194 195 static void instream_host_buffer_free(struct hpi_adapter_obj *pao, 196 struct hpi_message *phm, struct hpi_response *phr); 197 198 static void instream_read(struct hpi_adapter_obj *pao, 199 struct hpi_message *phm, struct hpi_response *phr); 200 201 static void instream_get_info(struct hpi_adapter_obj *pao, 202 struct hpi_message *phm, struct hpi_response *phr); 203 204 static void instream_start(struct hpi_adapter_obj *pao, 205 struct hpi_message *phm, struct hpi_response *phr); 206 207 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, 208 u32 address); 209 210 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, 211 int dsp_index, u32 address, u32 data); 212 213 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, 214 int dsp_index); 215 216 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, 217 u32 address, u32 length); 218 219 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, 220 int dsp_index); 221 222 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, 223 int dsp_index); 224 225 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index); 226 227 /*****************************************************************************/ 228 229 static void subsys_message(struct hpi_adapter_obj *pao, 230 struct hpi_message *phm, struct hpi_response *phr) 231 { 232 switch (phm->function) { 233 case HPI_SUBSYS_CREATE_ADAPTER: 234 subsys_create_adapter(phm, phr); 235 break; 236 default: 237 phr->error = HPI_ERROR_INVALID_FUNC; 238 break; 239 } 240 } 241 242 static void control_message(struct hpi_adapter_obj *pao, 243 struct hpi_message *phm, struct hpi_response *phr) 244 { 245 246 struct hpi_hw_obj *phw = pao->priv; 247 u16 pending_cache_error = 0; 248 249 switch (phm->function) { 250 case HPI_CONTROL_GET_STATE: 251 if (pao->has_control_cache) { 252 rmb(); /* make sure we see updates DMAed from DSP */ 253 if (hpi_check_control_cache(phw->p_cache, phm, phr)) { 254 break; 255 } else if (phm->u.c.attribute == HPI_METER_PEAK) { 256 pending_cache_error = 257 HPI_ERROR_CONTROL_CACHING; 258 } 259 } 260 hw_message(pao, phm, phr); 261 if (pending_cache_error && !phr->error) 262 phr->error = pending_cache_error; 263 break; 264 case HPI_CONTROL_GET_INFO: 265 hw_message(pao, phm, phr); 266 break; 267 case HPI_CONTROL_SET_STATE: 268 hw_message(pao, phm, phr); 269 if (pao->has_control_cache) 270 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, 271 phr); 272 break; 273 default: 274 phr->error = HPI_ERROR_INVALID_FUNC; 275 break; 276 } 277 } 278 279 static void adapter_message(struct hpi_adapter_obj *pao, 280 struct hpi_message *phm, struct hpi_response *phr) 281 { 282 switch (phm->function) { 283 case HPI_ADAPTER_DELETE: 284 adapter_delete(pao, phm, phr); 285 break; 286 287 default: 288 hw_message(pao, phm, phr); 289 break; 290 } 291 } 292 293 static void outstream_message(struct hpi_adapter_obj *pao, 294 struct hpi_message *phm, struct hpi_response *phr) 295 { 296 297 if (phm->obj_index >= HPI_MAX_STREAMS) { 298 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 299 HPI_DEBUG_LOG(WARNING, 300 "Message referencing invalid stream %d " 301 "on adapter index %d\n", phm->obj_index, 302 phm->adapter_index); 303 return; 304 } 305 306 switch (phm->function) { 307 case HPI_OSTREAM_WRITE: 308 outstream_write(pao, phm, phr); 309 break; 310 case HPI_OSTREAM_GET_INFO: 311 outstream_get_info(pao, phm, phr); 312 break; 313 case HPI_OSTREAM_HOSTBUFFER_ALLOC: 314 outstream_host_buffer_allocate(pao, phm, phr); 315 break; 316 case HPI_OSTREAM_HOSTBUFFER_GET_INFO: 317 outstream_host_buffer_get_info(pao, phm, phr); 318 break; 319 case HPI_OSTREAM_HOSTBUFFER_FREE: 320 outstream_host_buffer_free(pao, phm, phr); 321 break; 322 case HPI_OSTREAM_START: 323 outstream_start(pao, phm, phr); 324 break; 325 case HPI_OSTREAM_OPEN: 326 outstream_open(pao, phm, phr); 327 break; 328 case HPI_OSTREAM_RESET: 329 outstream_reset(pao, phm, phr); 330 break; 331 default: 332 hw_message(pao, phm, phr); 333 break; 334 } 335 } 336 337 static void instream_message(struct hpi_adapter_obj *pao, 338 struct hpi_message *phm, struct hpi_response *phr) 339 { 340 341 if (phm->obj_index >= HPI_MAX_STREAMS) { 342 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 343 HPI_DEBUG_LOG(WARNING, 344 "Message referencing invalid stream %d " 345 "on adapter index %d\n", phm->obj_index, 346 phm->adapter_index); 347 return; 348 } 349 350 switch (phm->function) { 351 case HPI_ISTREAM_READ: 352 instream_read(pao, phm, phr); 353 break; 354 case HPI_ISTREAM_GET_INFO: 355 instream_get_info(pao, phm, phr); 356 break; 357 case HPI_ISTREAM_HOSTBUFFER_ALLOC: 358 instream_host_buffer_allocate(pao, phm, phr); 359 break; 360 case HPI_ISTREAM_HOSTBUFFER_GET_INFO: 361 instream_host_buffer_get_info(pao, phm, phr); 362 break; 363 case HPI_ISTREAM_HOSTBUFFER_FREE: 364 instream_host_buffer_free(pao, phm, phr); 365 break; 366 case HPI_ISTREAM_START: 367 instream_start(pao, phm, phr); 368 break; 369 default: 370 hw_message(pao, phm, phr); 371 break; 372 } 373 } 374 375 /*****************************************************************************/ 376 /** Entry point to this HPI backend 377 * All calls to the HPI start here 378 */ 379 static 380 void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm, 381 struct hpi_response *phr) 382 { 383 if (pao && (pao->dsp_crashed >= 10) 384 && (phm->function != HPI_ADAPTER_DEBUG_READ)) { 385 /* allow last resort debug read even after crash */ 386 hpi_init_response(phr, phm->object, phm->function, 387 HPI_ERROR_DSP_HARDWARE); 388 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object, 389 phm->function); 390 return; 391 } 392 393 /* Init default response */ 394 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) 395 phr->error = HPI_ERROR_PROCESSING_MESSAGE; 396 397 HPI_DEBUG_LOG(VERBOSE, "start of switch\n"); 398 switch (phm->type) { 399 case HPI_TYPE_REQUEST: 400 switch (phm->object) { 401 case HPI_OBJ_SUBSYSTEM: 402 subsys_message(pao, phm, phr); 403 break; 404 405 case HPI_OBJ_ADAPTER: 406 adapter_message(pao, phm, phr); 407 break; 408 409 case HPI_OBJ_CONTROL: 410 control_message(pao, phm, phr); 411 break; 412 413 case HPI_OBJ_OSTREAM: 414 outstream_message(pao, phm, phr); 415 break; 416 417 case HPI_OBJ_ISTREAM: 418 instream_message(pao, phm, phr); 419 break; 420 421 default: 422 hw_message(pao, phm, phr); 423 break; 424 } 425 break; 426 427 default: 428 phr->error = HPI_ERROR_INVALID_TYPE; 429 break; 430 } 431 } 432 433 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) 434 { 435 struct hpi_adapter_obj *pao = NULL; 436 437 if (phm->object != HPI_OBJ_SUBSYSTEM) { 438 /* normal messages must have valid adapter index */ 439 pao = hpi_find_adapter(phm->adapter_index); 440 } else { 441 /* subsys messages don't address an adapter */ 442 _HPI_6205(NULL, phm, phr); 443 return; 444 } 445 446 if (pao) 447 _HPI_6205(pao, phm, phr); 448 else 449 hpi_init_response(phr, phm->object, phm->function, 450 HPI_ERROR_BAD_ADAPTER_NUMBER); 451 } 452 453 /*****************************************************************************/ 454 /* SUBSYSTEM */ 455 456 /** Create an adapter object and initialise it based on resource information 457 * passed in in the message 458 * *** NOTE - you cannot use this function AND the FindAdapters function at the 459 * same time, the application must use only one of them to get the adapters *** 460 */ 461 static void subsys_create_adapter(struct hpi_message *phm, 462 struct hpi_response *phr) 463 { 464 /* create temp adapter obj, because we don't know what index yet */ 465 struct hpi_adapter_obj ao; 466 u32 os_error_code; 467 u16 err; 468 469 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n"); 470 471 memset(&ao, 0, sizeof(ao)); 472 473 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); 474 if (!ao.priv) { 475 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n"); 476 phr->error = HPI_ERROR_MEMORY_ALLOC; 477 return; 478 } 479 480 ao.pci = *phm->u.s.resource.r.pci; 481 err = create_adapter_obj(&ao, &os_error_code); 482 if (err) { 483 delete_adapter_obj(&ao); 484 if (err >= HPI_ERROR_BACKEND_BASE) { 485 phr->error = HPI_ERROR_DSP_BOOTLOAD; 486 phr->specific_error = err; 487 } else { 488 phr->error = err; 489 } 490 phr->u.s.data = os_error_code; 491 return; 492 } 493 494 phr->u.s.adapter_type = ao.type; 495 phr->u.s.adapter_index = ao.index; 496 phr->error = 0; 497 } 498 499 /** delete an adapter - required by WDM driver */ 500 static void adapter_delete(struct hpi_adapter_obj *pao, 501 struct hpi_message *phm, struct hpi_response *phr) 502 { 503 struct hpi_hw_obj *phw; 504 505 if (!pao) { 506 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 507 return; 508 } 509 phw = pao->priv; 510 /* reset adapter h/w */ 511 /* Reset C6713 #1 */ 512 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); 513 /* reset C6205 */ 514 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR); 515 516 delete_adapter_obj(pao); 517 hpi_delete_adapter(pao); 518 phr->error = 0; 519 } 520 521 /** Create adapter object 522 allocate buffers, bootload DSPs, initialise control cache 523 */ 524 static u16 create_adapter_obj(struct hpi_adapter_obj *pao, 525 u32 *pos_error_code) 526 { 527 struct hpi_hw_obj *phw = pao->priv; 528 struct bus_master_interface *interface; 529 u32 phys_addr; 530 int i; 531 u16 err; 532 533 /* init error reporting */ 534 pao->dsp_crashed = 0; 535 536 for (i = 0; i < HPI_MAX_STREAMS; i++) 537 phw->flag_outstream_just_reset[i] = 1; 538 539 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */ 540 phw->prHSR = 541 pao->pci.ap_mem_base[1] + 542 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]); 543 phw->prHDCR = 544 pao->pci.ap_mem_base[1] + 545 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]); 546 phw->prDSPP = 547 pao->pci.ap_mem_base[1] + 548 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]); 549 550 pao->has_control_cache = 0; 551 552 if (hpios_locked_mem_alloc(&phw->h_locked_mem, 553 sizeof(struct bus_master_interface), 554 pao->pci.pci_dev)) 555 phw->p_interface_buffer = NULL; 556 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem, 557 (void *)&phw->p_interface_buffer)) 558 phw->p_interface_buffer = NULL; 559 560 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n", 561 phw->p_interface_buffer); 562 563 if (phw->p_interface_buffer) { 564 memset((void *)phw->p_interface_buffer, 0, 565 sizeof(struct bus_master_interface)); 566 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN; 567 } 568 569 err = adapter_boot_load_dsp(pao, pos_error_code); 570 if (err) { 571 HPI_DEBUG_LOG(ERROR, "DSP code load failed\n"); 572 /* no need to clean up as SubSysCreateAdapter */ 573 /* calls DeleteAdapter on error. */ 574 return err; 575 } 576 HPI_DEBUG_LOG(INFO, "load DSP code OK\n"); 577 578 /* allow boot load even if mem alloc wont work */ 579 if (!phw->p_interface_buffer) 580 return HPI_ERROR_MEMORY_ALLOC; 581 582 interface = phw->p_interface_buffer; 583 584 /* make sure the DSP has started ok */ 585 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) { 586 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n"); 587 return HPI6205_ERROR_6205_INIT_FAILED; 588 } 589 /* Note that *pao, *phw are zeroed after allocation, 590 * so pointers and flags are NULL by default. 591 * Allocate bus mastering control cache buffer and tell the DSP about it 592 */ 593 if (interface->control_cache.number_of_controls) { 594 u8 *p_control_cache_virtual; 595 596 err = hpios_locked_mem_alloc(&phw->h_control_cache, 597 interface->control_cache.size_in_bytes, 598 pao->pci.pci_dev); 599 if (!err) 600 err = hpios_locked_mem_get_virt_addr(&phw-> 601 h_control_cache, 602 (void *)&p_control_cache_virtual); 603 if (!err) { 604 memset(p_control_cache_virtual, 0, 605 interface->control_cache.size_in_bytes); 606 607 phw->p_cache = 608 hpi_alloc_control_cache(interface-> 609 control_cache.number_of_controls, 610 interface->control_cache.size_in_bytes, 611 p_control_cache_virtual); 612 613 if (!phw->p_cache) 614 err = HPI_ERROR_MEMORY_ALLOC; 615 } 616 if (!err) { 617 err = hpios_locked_mem_get_phys_addr(&phw-> 618 h_control_cache, &phys_addr); 619 interface->control_cache.physical_address32 = 620 phys_addr; 621 } 622 623 if (!err) 624 pao->has_control_cache = 1; 625 else { 626 if (hpios_locked_mem_valid(&phw->h_control_cache)) 627 hpios_locked_mem_free(&phw->h_control_cache); 628 pao->has_control_cache = 0; 629 } 630 } 631 send_dsp_command(phw, H620_HIF_IDLE); 632 633 { 634 struct hpi_message hm; 635 struct hpi_response hr; 636 u32 max_streams; 637 638 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n"); 639 memset(&hm, 0, sizeof(hm)); 640 /* wAdapterIndex == version == 0 */ 641 hm.type = HPI_TYPE_REQUEST; 642 hm.size = sizeof(hm); 643 hm.object = HPI_OBJ_ADAPTER; 644 hm.function = HPI_ADAPTER_GET_INFO; 645 646 memset(&hr, 0, sizeof(hr)); 647 hr.size = sizeof(hr); 648 649 err = message_response_sequence(pao, &hm, &hr); 650 if (err) { 651 HPI_DEBUG_LOG(ERROR, "message transport error %d\n", 652 err); 653 return err; 654 } 655 if (hr.error) 656 return hr.error; 657 658 pao->type = hr.u.ax.info.adapter_type; 659 pao->index = hr.u.ax.info.adapter_index; 660 661 max_streams = 662 hr.u.ax.info.num_outstreams + 663 hr.u.ax.info.num_instreams; 664 665 HPI_DEBUG_LOG(VERBOSE, 666 "got adapter info type %x index %d serial %d\n", 667 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index, 668 hr.u.ax.info.serial_number); 669 } 670 671 if (phw->p_cache) 672 phw->p_cache->adap_idx = pao->index; 673 674 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); 675 676 return hpi_add_adapter(pao); 677 } 678 679 /** Free memory areas allocated by adapter 680 * this routine is called from AdapterDelete, 681 * and SubSysCreateAdapter if duplicate index 682 */ 683 static void delete_adapter_obj(struct hpi_adapter_obj *pao) 684 { 685 struct hpi_hw_obj *phw = pao->priv; 686 int i; 687 688 if (hpios_locked_mem_valid(&phw->h_control_cache)) { 689 hpios_locked_mem_free(&phw->h_control_cache); 690 hpi_free_control_cache(phw->p_cache); 691 } 692 693 if (hpios_locked_mem_valid(&phw->h_locked_mem)) { 694 hpios_locked_mem_free(&phw->h_locked_mem); 695 phw->p_interface_buffer = NULL; 696 } 697 698 for (i = 0; i < HPI_MAX_STREAMS; i++) 699 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) { 700 hpios_locked_mem_free(&phw->instream_host_buffers[i]); 701 /*?phw->InStreamHostBuffers[i] = NULL; */ 702 phw->instream_host_buffer_size[i] = 0; 703 } 704 705 for (i = 0; i < HPI_MAX_STREAMS; i++) 706 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) { 707 hpios_locked_mem_free(&phw->outstream_host_buffers 708 [i]); 709 phw->outstream_host_buffer_size[i] = 0; 710 } 711 kfree(phw); 712 } 713 714 /*****************************************************************************/ 715 /* Adapter functions */ 716 717 /*****************************************************************************/ 718 /* OutStream Host buffer functions */ 719 720 /** Allocate or attach buffer for busmastering 721 */ 722 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, 723 struct hpi_message *phm, struct hpi_response *phr) 724 { 725 u16 err = 0; 726 u32 command = phm->u.d.u.buffer.command; 727 struct hpi_hw_obj *phw = pao->priv; 728 struct bus_master_interface *interface = phw->p_interface_buffer; 729 730 hpi_init_response(phr, phm->object, phm->function, 0); 731 732 if (command == HPI_BUFFER_CMD_EXTERNAL 733 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { 734 /* ALLOC phase, allocate a buffer with power of 2 size, 735 get its bus address for PCI bus mastering 736 */ 737 phm->u.d.u.buffer.buffer_size = 738 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); 739 /* return old size and allocated size, 740 so caller can detect change */ 741 phr->u.d.u.stream_info.data_available = 742 phw->outstream_host_buffer_size[phm->obj_index]; 743 phr->u.d.u.stream_info.buffer_size = 744 phm->u.d.u.buffer.buffer_size; 745 746 if (phw->outstream_host_buffer_size[phm->obj_index] == 747 phm->u.d.u.buffer.buffer_size) { 748 /* Same size, no action required */ 749 return; 750 } 751 752 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 753 obj_index])) 754 hpios_locked_mem_free(&phw->outstream_host_buffers 755 [phm->obj_index]); 756 757 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers 758 [phm->obj_index], phm->u.d.u.buffer.buffer_size, 759 pao->pci.pci_dev); 760 761 if (err) { 762 phr->error = HPI_ERROR_INVALID_DATASIZE; 763 phw->outstream_host_buffer_size[phm->obj_index] = 0; 764 return; 765 } 766 767 err = hpios_locked_mem_get_phys_addr 768 (&phw->outstream_host_buffers[phm->obj_index], 769 &phm->u.d.u.buffer.pci_address); 770 /* get the phys addr into msg for single call alloc caller 771 * needs to do this for split alloc (or use the same message) 772 * return the phy address for split alloc in the respose too 773 */ 774 phr->u.d.u.stream_info.auxiliary_data_available = 775 phm->u.d.u.buffer.pci_address; 776 777 if (err) { 778 hpios_locked_mem_free(&phw->outstream_host_buffers 779 [phm->obj_index]); 780 phw->outstream_host_buffer_size[phm->obj_index] = 0; 781 phr->error = HPI_ERROR_MEMORY_ALLOC; 782 return; 783 } 784 } 785 786 if (command == HPI_BUFFER_CMD_EXTERNAL 787 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { 788 /* GRANT phase. Set up the BBM status, tell the DSP about 789 the buffer so it can start using BBM. 790 */ 791 struct hpi_hostbuffer_status *status; 792 793 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. 794 buffer_size - 1)) { 795 HPI_DEBUG_LOG(ERROR, 796 "Buffer size must be 2^N not %d\n", 797 phm->u.d.u.buffer.buffer_size); 798 phr->error = HPI_ERROR_INVALID_DATASIZE; 799 return; 800 } 801 phw->outstream_host_buffer_size[phm->obj_index] = 802 phm->u.d.u.buffer.buffer_size; 803 status = &interface->outstream_host_buffer_status[phm-> 804 obj_index]; 805 status->samples_processed = 0; 806 status->stream_state = HPI_STATE_STOPPED; 807 status->dsp_index = 0; 808 status->host_index = status->dsp_index; 809 status->size_in_bytes = phm->u.d.u.buffer.buffer_size; 810 status->auxiliary_data_available = 0; 811 812 hw_message(pao, phm, phr); 813 814 if (phr->error 815 && hpios_locked_mem_valid(&phw-> 816 outstream_host_buffers[phm->obj_index])) { 817 hpios_locked_mem_free(&phw->outstream_host_buffers 818 [phm->obj_index]); 819 phw->outstream_host_buffer_size[phm->obj_index] = 0; 820 } 821 } 822 } 823 824 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, 825 struct hpi_message *phm, struct hpi_response *phr) 826 { 827 struct hpi_hw_obj *phw = pao->priv; 828 struct bus_master_interface *interface = phw->p_interface_buffer; 829 struct hpi_hostbuffer_status *status; 830 u8 *p_bbm_data; 831 832 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 833 obj_index])) { 834 if (hpios_locked_mem_get_virt_addr(&phw-> 835 outstream_host_buffers[phm->obj_index], 836 (void *)&p_bbm_data)) { 837 phr->error = HPI_ERROR_INVALID_OPERATION; 838 return; 839 } 840 status = &interface->outstream_host_buffer_status[phm-> 841 obj_index]; 842 hpi_init_response(phr, HPI_OBJ_OSTREAM, 843 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0); 844 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; 845 phr->u.d.u.hostbuffer_info.p_status = status; 846 } else { 847 hpi_init_response(phr, HPI_OBJ_OSTREAM, 848 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 849 HPI_ERROR_INVALID_OPERATION); 850 } 851 } 852 853 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, 854 struct hpi_message *phm, struct hpi_response *phr) 855 { 856 struct hpi_hw_obj *phw = pao->priv; 857 u32 command = phm->u.d.u.buffer.command; 858 859 if (phw->outstream_host_buffer_size[phm->obj_index]) { 860 if (command == HPI_BUFFER_CMD_EXTERNAL 861 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { 862 phw->outstream_host_buffer_size[phm->obj_index] = 0; 863 hw_message(pao, phm, phr); 864 /* Tell adapter to stop using the host buffer. */ 865 } 866 if (command == HPI_BUFFER_CMD_EXTERNAL 867 || command == HPI_BUFFER_CMD_INTERNAL_FREE) 868 hpios_locked_mem_free(&phw->outstream_host_buffers 869 [phm->obj_index]); 870 } 871 /* Should HPI_ERROR_INVALID_OPERATION be returned 872 if no host buffer is allocated? */ 873 else 874 hpi_init_response(phr, HPI_OBJ_OSTREAM, 875 HPI_OSTREAM_HOSTBUFFER_FREE, 0); 876 877 } 878 879 static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status) 880 { 881 return status->size_in_bytes - (status->host_index - 882 status->dsp_index); 883 } 884 885 static void outstream_write(struct hpi_adapter_obj *pao, 886 struct hpi_message *phm, struct hpi_response *phr) 887 { 888 struct hpi_hw_obj *phw = pao->priv; 889 struct bus_master_interface *interface = phw->p_interface_buffer; 890 struct hpi_hostbuffer_status *status; 891 u32 space_available; 892 893 if (!phw->outstream_host_buffer_size[phm->obj_index]) { 894 /* there is no BBM buffer, write via message */ 895 hw_message(pao, phm, phr); 896 return; 897 } 898 899 hpi_init_response(phr, phm->object, phm->function, 0); 900 status = &interface->outstream_host_buffer_status[phm->obj_index]; 901 902 space_available = outstream_get_space_available(status); 903 if (space_available < phm->u.d.u.data.data_size) { 904 phr->error = HPI_ERROR_INVALID_DATASIZE; 905 return; 906 } 907 908 /* HostBuffers is used to indicate host buffer is internally allocated. 909 otherwise, assumed external, data written externally */ 910 if (phm->u.d.u.data.pb_data 911 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 912 obj_index])) { 913 u8 *p_bbm_data; 914 u32 l_first_write; 915 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; 916 917 if (hpios_locked_mem_get_virt_addr(&phw-> 918 outstream_host_buffers[phm->obj_index], 919 (void *)&p_bbm_data)) { 920 phr->error = HPI_ERROR_INVALID_OPERATION; 921 return; 922 } 923 924 /* either all data, 925 or enough to fit from current to end of BBM buffer */ 926 l_first_write = 927 min(phm->u.d.u.data.data_size, 928 status->size_in_bytes - 929 (status->host_index & (status->size_in_bytes - 1))); 930 931 memcpy(p_bbm_data + 932 (status->host_index & (status->size_in_bytes - 1)), 933 p_app_data, l_first_write); 934 /* remaining data if any */ 935 memcpy(p_bbm_data, p_app_data + l_first_write, 936 phm->u.d.u.data.data_size - l_first_write); 937 } 938 939 /* 940 * This version relies on the DSP code triggering an OStream buffer 941 * update immediately following a SET_FORMAT call. The host has 942 * already written data into the BBM buffer, but the DSP won't know 943 * about it until dwHostIndex is adjusted. 944 */ 945 if (phw->flag_outstream_just_reset[phm->obj_index]) { 946 /* Format can only change after reset. Must tell DSP. */ 947 u16 function = phm->function; 948 phw->flag_outstream_just_reset[phm->obj_index] = 0; 949 phm->function = HPI_OSTREAM_SET_FORMAT; 950 hw_message(pao, phm, phr); /* send the format to the DSP */ 951 phm->function = function; 952 if (phr->error) 953 return; 954 } 955 956 status->host_index += phm->u.d.u.data.data_size; 957 } 958 959 static void outstream_get_info(struct hpi_adapter_obj *pao, 960 struct hpi_message *phm, struct hpi_response *phr) 961 { 962 struct hpi_hw_obj *phw = pao->priv; 963 struct bus_master_interface *interface = phw->p_interface_buffer; 964 struct hpi_hostbuffer_status *status; 965 966 if (!phw->outstream_host_buffer_size[phm->obj_index]) { 967 hw_message(pao, phm, phr); 968 return; 969 } 970 971 hpi_init_response(phr, phm->object, phm->function, 0); 972 973 status = &interface->outstream_host_buffer_status[phm->obj_index]; 974 975 phr->u.d.u.stream_info.state = (u16)status->stream_state; 976 phr->u.d.u.stream_info.samples_transferred = 977 status->samples_processed; 978 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; 979 phr->u.d.u.stream_info.data_available = 980 status->size_in_bytes - outstream_get_space_available(status); 981 phr->u.d.u.stream_info.auxiliary_data_available = 982 status->auxiliary_data_available; 983 } 984 985 static void outstream_start(struct hpi_adapter_obj *pao, 986 struct hpi_message *phm, struct hpi_response *phr) 987 { 988 hw_message(pao, phm, phr); 989 } 990 991 static void outstream_reset(struct hpi_adapter_obj *pao, 992 struct hpi_message *phm, struct hpi_response *phr) 993 { 994 struct hpi_hw_obj *phw = pao->priv; 995 phw->flag_outstream_just_reset[phm->obj_index] = 1; 996 hw_message(pao, phm, phr); 997 } 998 999 static void outstream_open(struct hpi_adapter_obj *pao, 1000 struct hpi_message *phm, struct hpi_response *phr) 1001 { 1002 outstream_reset(pao, phm, phr); 1003 } 1004 1005 /*****************************************************************************/ 1006 /* InStream Host buffer functions */ 1007 1008 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, 1009 struct hpi_message *phm, struct hpi_response *phr) 1010 { 1011 u16 err = 0; 1012 u32 command = phm->u.d.u.buffer.command; 1013 struct hpi_hw_obj *phw = pao->priv; 1014 struct bus_master_interface *interface = phw->p_interface_buffer; 1015 1016 hpi_init_response(phr, phm->object, phm->function, 0); 1017 1018 if (command == HPI_BUFFER_CMD_EXTERNAL 1019 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { 1020 1021 phm->u.d.u.buffer.buffer_size = 1022 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); 1023 phr->u.d.u.stream_info.data_available = 1024 phw->instream_host_buffer_size[phm->obj_index]; 1025 phr->u.d.u.stream_info.buffer_size = 1026 phm->u.d.u.buffer.buffer_size; 1027 1028 if (phw->instream_host_buffer_size[phm->obj_index] == 1029 phm->u.d.u.buffer.buffer_size) { 1030 /* Same size, no action required */ 1031 return; 1032 } 1033 1034 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1035 obj_index])) 1036 hpios_locked_mem_free(&phw->instream_host_buffers 1037 [phm->obj_index]); 1038 1039 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm-> 1040 obj_index], phm->u.d.u.buffer.buffer_size, 1041 pao->pci.pci_dev); 1042 1043 if (err) { 1044 phr->error = HPI_ERROR_INVALID_DATASIZE; 1045 phw->instream_host_buffer_size[phm->obj_index] = 0; 1046 return; 1047 } 1048 1049 err = hpios_locked_mem_get_phys_addr 1050 (&phw->instream_host_buffers[phm->obj_index], 1051 &phm->u.d.u.buffer.pci_address); 1052 /* get the phys addr into msg for single call alloc. Caller 1053 needs to do this for split alloc so return the phy address */ 1054 phr->u.d.u.stream_info.auxiliary_data_available = 1055 phm->u.d.u.buffer.pci_address; 1056 if (err) { 1057 hpios_locked_mem_free(&phw->instream_host_buffers 1058 [phm->obj_index]); 1059 phw->instream_host_buffer_size[phm->obj_index] = 0; 1060 phr->error = HPI_ERROR_MEMORY_ALLOC; 1061 return; 1062 } 1063 } 1064 1065 if (command == HPI_BUFFER_CMD_EXTERNAL 1066 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { 1067 struct hpi_hostbuffer_status *status; 1068 1069 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. 1070 buffer_size - 1)) { 1071 HPI_DEBUG_LOG(ERROR, 1072 "Buffer size must be 2^N not %d\n", 1073 phm->u.d.u.buffer.buffer_size); 1074 phr->error = HPI_ERROR_INVALID_DATASIZE; 1075 return; 1076 } 1077 1078 phw->instream_host_buffer_size[phm->obj_index] = 1079 phm->u.d.u.buffer.buffer_size; 1080 status = &interface->instream_host_buffer_status[phm-> 1081 obj_index]; 1082 status->samples_processed = 0; 1083 status->stream_state = HPI_STATE_STOPPED; 1084 status->dsp_index = 0; 1085 status->host_index = status->dsp_index; 1086 status->size_in_bytes = phm->u.d.u.buffer.buffer_size; 1087 status->auxiliary_data_available = 0; 1088 1089 hw_message(pao, phm, phr); 1090 1091 if (phr->error 1092 && hpios_locked_mem_valid(&phw-> 1093 instream_host_buffers[phm->obj_index])) { 1094 hpios_locked_mem_free(&phw->instream_host_buffers 1095 [phm->obj_index]); 1096 phw->instream_host_buffer_size[phm->obj_index] = 0; 1097 } 1098 } 1099 } 1100 1101 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, 1102 struct hpi_message *phm, struct hpi_response *phr) 1103 { 1104 struct hpi_hw_obj *phw = pao->priv; 1105 struct bus_master_interface *interface = phw->p_interface_buffer; 1106 struct hpi_hostbuffer_status *status; 1107 u8 *p_bbm_data; 1108 1109 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1110 obj_index])) { 1111 if (hpios_locked_mem_get_virt_addr(&phw-> 1112 instream_host_buffers[phm->obj_index], 1113 (void *)&p_bbm_data)) { 1114 phr->error = HPI_ERROR_INVALID_OPERATION; 1115 return; 1116 } 1117 status = &interface->instream_host_buffer_status[phm-> 1118 obj_index]; 1119 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1120 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0); 1121 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; 1122 phr->u.d.u.hostbuffer_info.p_status = status; 1123 } else { 1124 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1125 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 1126 HPI_ERROR_INVALID_OPERATION); 1127 } 1128 } 1129 1130 static void instream_host_buffer_free(struct hpi_adapter_obj *pao, 1131 struct hpi_message *phm, struct hpi_response *phr) 1132 { 1133 struct hpi_hw_obj *phw = pao->priv; 1134 u32 command = phm->u.d.u.buffer.command; 1135 1136 if (phw->instream_host_buffer_size[phm->obj_index]) { 1137 if (command == HPI_BUFFER_CMD_EXTERNAL 1138 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { 1139 phw->instream_host_buffer_size[phm->obj_index] = 0; 1140 hw_message(pao, phm, phr); 1141 } 1142 1143 if (command == HPI_BUFFER_CMD_EXTERNAL 1144 || command == HPI_BUFFER_CMD_INTERNAL_FREE) 1145 hpios_locked_mem_free(&phw->instream_host_buffers 1146 [phm->obj_index]); 1147 1148 } else { 1149 /* Should HPI_ERROR_INVALID_OPERATION be returned 1150 if no host buffer is allocated? */ 1151 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1152 HPI_ISTREAM_HOSTBUFFER_FREE, 0); 1153 1154 } 1155 1156 } 1157 1158 static void instream_start(struct hpi_adapter_obj *pao, 1159 struct hpi_message *phm, struct hpi_response *phr) 1160 { 1161 hw_message(pao, phm, phr); 1162 } 1163 1164 static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status) 1165 { 1166 return status->dsp_index - status->host_index; 1167 } 1168 1169 static void instream_read(struct hpi_adapter_obj *pao, 1170 struct hpi_message *phm, struct hpi_response *phr) 1171 { 1172 struct hpi_hw_obj *phw = pao->priv; 1173 struct bus_master_interface *interface = phw->p_interface_buffer; 1174 struct hpi_hostbuffer_status *status; 1175 u32 data_available; 1176 u8 *p_bbm_data; 1177 u32 l_first_read; 1178 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; 1179 1180 if (!phw->instream_host_buffer_size[phm->obj_index]) { 1181 hw_message(pao, phm, phr); 1182 return; 1183 } 1184 hpi_init_response(phr, phm->object, phm->function, 0); 1185 1186 status = &interface->instream_host_buffer_status[phm->obj_index]; 1187 data_available = instream_get_bytes_available(status); 1188 if (data_available < phm->u.d.u.data.data_size) { 1189 phr->error = HPI_ERROR_INVALID_DATASIZE; 1190 return; 1191 } 1192 1193 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1194 obj_index])) { 1195 if (hpios_locked_mem_get_virt_addr(&phw-> 1196 instream_host_buffers[phm->obj_index], 1197 (void *)&p_bbm_data)) { 1198 phr->error = HPI_ERROR_INVALID_OPERATION; 1199 return; 1200 } 1201 1202 /* either all data, 1203 or enough to fit from current to end of BBM buffer */ 1204 l_first_read = 1205 min(phm->u.d.u.data.data_size, 1206 status->size_in_bytes - 1207 (status->host_index & (status->size_in_bytes - 1))); 1208 1209 memcpy(p_app_data, 1210 p_bbm_data + 1211 (status->host_index & (status->size_in_bytes - 1)), 1212 l_first_read); 1213 /* remaining data if any */ 1214 memcpy(p_app_data + l_first_read, p_bbm_data, 1215 phm->u.d.u.data.data_size - l_first_read); 1216 } 1217 status->host_index += phm->u.d.u.data.data_size; 1218 } 1219 1220 static void instream_get_info(struct hpi_adapter_obj *pao, 1221 struct hpi_message *phm, struct hpi_response *phr) 1222 { 1223 struct hpi_hw_obj *phw = pao->priv; 1224 struct bus_master_interface *interface = phw->p_interface_buffer; 1225 struct hpi_hostbuffer_status *status; 1226 if (!phw->instream_host_buffer_size[phm->obj_index]) { 1227 hw_message(pao, phm, phr); 1228 return; 1229 } 1230 1231 status = &interface->instream_host_buffer_status[phm->obj_index]; 1232 1233 hpi_init_response(phr, phm->object, phm->function, 0); 1234 1235 phr->u.d.u.stream_info.state = (u16)status->stream_state; 1236 phr->u.d.u.stream_info.samples_transferred = 1237 status->samples_processed; 1238 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; 1239 phr->u.d.u.stream_info.data_available = 1240 instream_get_bytes_available(status); 1241 phr->u.d.u.stream_info.auxiliary_data_available = 1242 status->auxiliary_data_available; 1243 } 1244 1245 /*****************************************************************************/ 1246 /* LOW-LEVEL */ 1247 #define HPI6205_MAX_FILES_TO_LOAD 2 1248 1249 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 1250 u32 *pos_error_code) 1251 { 1252 struct hpi_hw_obj *phw = pao->priv; 1253 struct dsp_code dsp_code; 1254 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD]; 1255 u32 temp; 1256 int dsp = 0, i = 0; 1257 u16 err = 0; 1258 1259 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205); 1260 1261 boot_code_id[1] = pao->pci.pci_dev->subsystem_device; 1262 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]); 1263 1264 /* fix up cases where bootcode id[1] != subsys id */ 1265 switch (boot_code_id[1]) { 1266 case HPI_ADAPTER_FAMILY_ASI(0x5000): 1267 boot_code_id[0] = boot_code_id[1]; 1268 boot_code_id[1] = 0; 1269 break; 1270 case HPI_ADAPTER_FAMILY_ASI(0x5300): 1271 case HPI_ADAPTER_FAMILY_ASI(0x5400): 1272 case HPI_ADAPTER_FAMILY_ASI(0x6300): 1273 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400); 1274 break; 1275 case HPI_ADAPTER_FAMILY_ASI(0x5500): 1276 case HPI_ADAPTER_FAMILY_ASI(0x5600): 1277 case HPI_ADAPTER_FAMILY_ASI(0x6500): 1278 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600); 1279 break; 1280 case HPI_ADAPTER_FAMILY_ASI(0x8800): 1281 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900); 1282 break; 1283 default: 1284 break; 1285 } 1286 1287 /* reset DSP by writing a 1 to the WARMRESET bit */ 1288 temp = C6205_HDCR_WARMRESET; 1289 iowrite32(temp, phw->prHDCR); 1290 hpios_delay_micro_seconds(1000); 1291 1292 /* check that PCI i/f was configured by EEPROM */ 1293 temp = ioread32(phw->prHSR); 1294 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) != 1295 C6205_HSR_EEREAD) 1296 return HPI6205_ERROR_6205_EEPROM; 1297 temp |= 0x04; 1298 /* disable PINTA interrupt */ 1299 iowrite32(temp, phw->prHSR); 1300 1301 /* check control register reports PCI boot mode */ 1302 temp = ioread32(phw->prHDCR); 1303 if (!(temp & C6205_HDCR_PCIBOOT)) 1304 return HPI6205_ERROR_6205_REG; 1305 1306 /* try writing a few numbers to the DSP page register */ 1307 /* and reading them back. */ 1308 temp = 3; 1309 iowrite32(temp, phw->prDSPP); 1310 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1311 return HPI6205_ERROR_6205_DSPPAGE; 1312 temp = 2; 1313 iowrite32(temp, phw->prDSPP); 1314 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1315 return HPI6205_ERROR_6205_DSPPAGE; 1316 temp = 1; 1317 iowrite32(temp, phw->prDSPP); 1318 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1319 return HPI6205_ERROR_6205_DSPPAGE; 1320 /* reset DSP page to the correct number */ 1321 temp = 0; 1322 iowrite32(temp, phw->prDSPP); 1323 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1324 return HPI6205_ERROR_6205_DSPPAGE; 1325 phw->dsp_page = 0; 1326 1327 /* release 6713 from reset before 6205 is bootloaded. 1328 This ensures that the EMIF is inactive, 1329 and the 6713 HPI gets the correct bootmode etc 1330 */ 1331 if (boot_code_id[1] != 0) { 1332 /* DSP 1 is a C6713 */ 1333 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */ 1334 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202); 1335 hpios_delay_micro_seconds(100); 1336 /* Reset the 6713 #1 - revB */ 1337 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); 1338 1339 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1340 boot_loader_read_mem32(pao, 0, 0); 1341 1342 hpios_delay_micro_seconds(100); 1343 /* Release C6713 from reset - revB */ 1344 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4); 1345 hpios_delay_micro_seconds(100); 1346 } 1347 1348 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) { 1349 /* is there a DSP to load? */ 1350 if (boot_code_id[dsp] == 0) 1351 continue; 1352 1353 err = boot_loader_config_emif(pao, dsp); 1354 if (err) 1355 return err; 1356 1357 err = boot_loader_test_internal_memory(pao, dsp); 1358 if (err) 1359 return err; 1360 1361 err = boot_loader_test_external_memory(pao, dsp); 1362 if (err) 1363 return err; 1364 1365 err = boot_loader_test_pld(pao, dsp); 1366 if (err) 1367 return err; 1368 1369 /* write the DSP code down into the DSPs memory */ 1370 err = hpi_dsp_code_open(boot_code_id[dsp], pao->pci.pci_dev, 1371 &dsp_code, pos_error_code); 1372 if (err) 1373 return err; 1374 1375 while (1) { 1376 u32 length; 1377 u32 address; 1378 u32 type; 1379 u32 *pcode; 1380 1381 err = hpi_dsp_code_read_word(&dsp_code, &length); 1382 if (err) 1383 break; 1384 if (length == 0xFFFFFFFF) 1385 break; /* end of code */ 1386 1387 err = hpi_dsp_code_read_word(&dsp_code, &address); 1388 if (err) 1389 break; 1390 err = hpi_dsp_code_read_word(&dsp_code, &type); 1391 if (err) 1392 break; 1393 err = hpi_dsp_code_read_block(length, &dsp_code, 1394 &pcode); 1395 if (err) 1396 break; 1397 for (i = 0; i < (int)length; i++) { 1398 boot_loader_write_mem32(pao, dsp, address, 1399 *pcode); 1400 /* dummy read every 4 words */ 1401 /* for 6205 advisory 1.4.4 */ 1402 if (i % 4 == 0) 1403 boot_loader_read_mem32(pao, dsp, 1404 address); 1405 pcode++; 1406 address += 4; 1407 } 1408 1409 } 1410 if (err) { 1411 hpi_dsp_code_close(&dsp_code); 1412 return err; 1413 } 1414 1415 /* verify code */ 1416 hpi_dsp_code_rewind(&dsp_code); 1417 while (1) { 1418 u32 length = 0; 1419 u32 address = 0; 1420 u32 type = 0; 1421 u32 *pcode = NULL; 1422 u32 data = 0; 1423 1424 hpi_dsp_code_read_word(&dsp_code, &length); 1425 if (length == 0xFFFFFFFF) 1426 break; /* end of code */ 1427 1428 hpi_dsp_code_read_word(&dsp_code, &address); 1429 hpi_dsp_code_read_word(&dsp_code, &type); 1430 hpi_dsp_code_read_block(length, &dsp_code, &pcode); 1431 1432 for (i = 0; i < (int)length; i++) { 1433 data = boot_loader_read_mem32(pao, dsp, 1434 address); 1435 if (data != *pcode) { 1436 err = 0; 1437 break; 1438 } 1439 pcode++; 1440 address += 4; 1441 } 1442 if (err) 1443 break; 1444 } 1445 hpi_dsp_code_close(&dsp_code); 1446 if (err) 1447 return err; 1448 } 1449 1450 /* After bootloading all DSPs, start DSP0 running 1451 * The DSP0 code will handle starting and synchronizing with its slaves 1452 */ 1453 if (phw->p_interface_buffer) { 1454 /* we need to tell the card the physical PCI address */ 1455 u32 physicalPC_iaddress; 1456 struct bus_master_interface *interface = 1457 phw->p_interface_buffer; 1458 u32 host_mailbox_address_on_dsp; 1459 u32 physicalPC_iaddress_verify = 0; 1460 int time_out = 10; 1461 /* set ack so we know when DSP is ready to go */ 1462 /* (dwDspAck will be changed to HIF_RESET) */ 1463 interface->dsp_ack = H620_HIF_UNKNOWN; 1464 wmb(); /* ensure ack is written before dsp writes back */ 1465 1466 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem, 1467 &physicalPC_iaddress); 1468 1469 /* locate the host mailbox on the DSP. */ 1470 host_mailbox_address_on_dsp = 0x80000000; 1471 while ((physicalPC_iaddress != physicalPC_iaddress_verify) 1472 && time_out--) { 1473 boot_loader_write_mem32(pao, 0, 1474 host_mailbox_address_on_dsp, 1475 physicalPC_iaddress); 1476 physicalPC_iaddress_verify = 1477 boot_loader_read_mem32(pao, 0, 1478 host_mailbox_address_on_dsp); 1479 } 1480 } 1481 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n"); 1482 /* enable interrupts */ 1483 temp = ioread32(phw->prHSR); 1484 temp &= ~(u32)C6205_HSR_INTAM; 1485 iowrite32(temp, phw->prHSR); 1486 1487 /* start code running... */ 1488 temp = ioread32(phw->prHDCR); 1489 temp |= (u32)C6205_HDCR_DSPINT; 1490 iowrite32(temp, phw->prHDCR); 1491 1492 /* give the DSP 10ms to start up */ 1493 hpios_delay_micro_seconds(10000); 1494 return err; 1495 1496 } 1497 1498 /*****************************************************************************/ 1499 /* Bootloader utility functions */ 1500 1501 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, 1502 u32 address) 1503 { 1504 struct hpi_hw_obj *phw = pao->priv; 1505 u32 data = 0; 1506 __iomem u32 *p_data; 1507 1508 if (dsp_index == 0) { 1509 /* DSP 0 is always C6205 */ 1510 if ((address >= 0x01800000) & (address < 0x02000000)) { 1511 /* BAR1 register access */ 1512 p_data = pao->pci.ap_mem_base[1] + 1513 (address & 0x007fffff) / 1514 sizeof(*pao->pci.ap_mem_base[1]); 1515 /* HPI_DEBUG_LOG(WARNING, 1516 "BAR1 access %08x\n", dwAddress); */ 1517 } else { 1518 u32 dw4M_page = address >> 22L; 1519 if (dw4M_page != phw->dsp_page) { 1520 phw->dsp_page = dw4M_page; 1521 /* *INDENT OFF* */ 1522 iowrite32(phw->dsp_page, phw->prDSPP); 1523 /* *INDENT-ON* */ 1524 } 1525 address &= 0x3fffff; /* address within 4M page */ 1526 /* BAR0 memory access */ 1527 p_data = pao->pci.ap_mem_base[0] + 1528 address / sizeof(u32); 1529 } 1530 data = ioread32(p_data); 1531 } else if (dsp_index == 1) { 1532 /* DSP 1 is a C6713 */ 1533 u32 lsb; 1534 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); 1535 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); 1536 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR); 1537 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR); 1538 data = (data << 16) | (lsb & 0xFFFF); 1539 } 1540 return data; 1541 } 1542 1543 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, 1544 int dsp_index, u32 address, u32 data) 1545 { 1546 struct hpi_hw_obj *phw = pao->priv; 1547 __iomem u32 *p_data; 1548 /* u32 dwVerifyData=0; */ 1549 1550 if (dsp_index == 0) { 1551 /* DSP 0 is always C6205 */ 1552 if ((address >= 0x01800000) & (address < 0x02000000)) { 1553 /* BAR1 - DSP register access using */ 1554 /* Non-prefetchable PCI access */ 1555 p_data = pao->pci.ap_mem_base[1] + 1556 (address & 0x007fffff) / 1557 sizeof(*pao->pci.ap_mem_base[1]); 1558 } else { 1559 /* BAR0 access - all of DSP memory using */ 1560 /* pre-fetchable PCI access */ 1561 u32 dw4M_page = address >> 22L; 1562 if (dw4M_page != phw->dsp_page) { 1563 phw->dsp_page = dw4M_page; 1564 /* *INDENT-OFF* */ 1565 iowrite32(phw->dsp_page, phw->prDSPP); 1566 /* *INDENT-ON* */ 1567 } 1568 address &= 0x3fffff; /* address within 4M page */ 1569 p_data = pao->pci.ap_mem_base[0] + 1570 address / sizeof(u32); 1571 } 1572 iowrite32(data, p_data); 1573 } else if (dsp_index == 1) { 1574 /* DSP 1 is a C6713 */ 1575 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); 1576 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); 1577 1578 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1579 boot_loader_read_mem32(pao, 0, 0); 1580 1581 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data); 1582 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16); 1583 1584 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1585 boot_loader_read_mem32(pao, 0, 0); 1586 } 1587 } 1588 1589 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index) 1590 { 1591 if (dsp_index == 0) { 1592 u32 setting; 1593 1594 /* DSP 0 is always C6205 */ 1595 1596 /* Set the EMIF */ 1597 /* memory map of C6205 */ 1598 /* 00000000-0000FFFF 16Kx32 internal program */ 1599 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */ 1600 1601 /* EMIF config */ 1602 /*------------ */ 1603 /* Global EMIF control */ 1604 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779); 1605 #define WS_OFS 28 1606 #define WST_OFS 22 1607 #define WH_OFS 20 1608 #define RS_OFS 16 1609 #define RST_OFS 8 1610 #define MTYPE_OFS 4 1611 #define RH_OFS 0 1612 1613 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */ 1614 setting = 0x00000030; 1615 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting); 1616 if (setting != boot_loader_read_mem32(pao, dsp_index, 1617 0x01800008)) 1618 return HPI6205_ERROR_DSP_EMIF1; 1619 1620 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */ 1621 /* which occupies D15..0. 6713 starts at 27MHz, so need */ 1622 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */ 1623 /* WST should be 71, but 63 is max possible */ 1624 setting = 1625 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) | 1626 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | 1627 (2L << MTYPE_OFS); 1628 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting); 1629 if (setting != boot_loader_read_mem32(pao, dsp_index, 1630 0x01800004)) 1631 return HPI6205_ERROR_DSP_EMIF2; 1632 1633 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */ 1634 /* which occupies D15..0. 6713 starts at 27MHz, so need */ 1635 /* plenty of wait states */ 1636 setting = 1637 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) | 1638 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | 1639 (2L << MTYPE_OFS); 1640 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting); 1641 if (setting != boot_loader_read_mem32(pao, dsp_index, 1642 0x01800010)) 1643 return HPI6205_ERROR_DSP_EMIF3; 1644 1645 /* EMIF CE3 setup - 32 bit async. */ 1646 /* This is the PLD on the ASI5000 cards only */ 1647 setting = 1648 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) | 1649 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) | 1650 (2L << MTYPE_OFS); 1651 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting); 1652 if (setting != boot_loader_read_mem32(pao, dsp_index, 1653 0x01800014)) 1654 return HPI6205_ERROR_DSP_EMIF4; 1655 1656 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */ 1657 /* need to use this else DSP code crashes? */ 1658 boot_loader_write_mem32(pao, dsp_index, 0x01800018, 1659 0x07117000); 1660 1661 /* EMIF SDRAM Refresh Timing */ 1662 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */ 1663 boot_loader_write_mem32(pao, dsp_index, 0x0180001C, 1664 0x00000410); 1665 1666 } else if (dsp_index == 1) { 1667 /* test access to the C6713s HPI registers */ 1668 u32 write_data = 0, read_data = 0, i = 0; 1669 1670 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */ 1671 write_data = 1; 1672 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data); 1673 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data); 1674 /* C67 HPI is on lower 16bits of 32bit EMIF */ 1675 read_data = 1676 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR); 1677 if (write_data != read_data) { 1678 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data, 1679 read_data); 1680 return HPI6205_ERROR_C6713_HPIC; 1681 } 1682 /* HPIA - walking ones test */ 1683 write_data = 1; 1684 for (i = 0; i < 32; i++) { 1685 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, 1686 write_data); 1687 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, 1688 (write_data >> 16)); 1689 read_data = 1690 0xFFFF & boot_loader_read_mem32(pao, 0, 1691 HPIAL_ADDR); 1692 read_data = 1693 read_data | ((0xFFFF & 1694 boot_loader_read_mem32(pao, 0, 1695 HPIAH_ADDR)) 1696 << 16); 1697 if (read_data != write_data) { 1698 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n", 1699 write_data, read_data); 1700 return HPI6205_ERROR_C6713_HPIA; 1701 } 1702 write_data = write_data << 1; 1703 } 1704 1705 /* setup C67x PLL 1706 * ** C6713 datasheet says we cannot program PLL from HPI, 1707 * and indeed if we try to set the PLL multiply from the HPI, 1708 * the PLL does not seem to lock, so we enable the PLL and 1709 * use the default multiply of x 7, which for a 27MHz clock 1710 * gives a DSP speed of 189MHz 1711 */ 1712 /* bypass PLL */ 1713 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000); 1714 hpios_delay_micro_seconds(1000); 1715 /* EMIF = 189/3=63MHz */ 1716 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002); 1717 /* peri = 189/2 */ 1718 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001); 1719 /* cpu = 189/1 */ 1720 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000); 1721 hpios_delay_micro_seconds(1000); 1722 /* ** SGT test to take GPO3 high when we start the PLL */ 1723 /* and low when the delay is completed */ 1724 /* FSX0 <- '1' (GPO3) */ 1725 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A); 1726 /* PLL not bypassed */ 1727 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001); 1728 hpios_delay_micro_seconds(1000); 1729 /* FSX0 <- '0' (GPO3) */ 1730 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02); 1731 1732 /* 6205 EMIF CE1 resetup - 32 bit async. */ 1733 /* Now 6713 #1 is running at 189MHz can reduce waitstates */ 1734 boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */ 1735 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) | 1736 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) | 1737 (2L << MTYPE_OFS)); 1738 1739 hpios_delay_micro_seconds(1000); 1740 1741 /* check that we can read one of the PLL registers */ 1742 /* PLL should not be bypassed! */ 1743 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF) 1744 != 0x0001) { 1745 return HPI6205_ERROR_C6713_PLL; 1746 } 1747 /* setup C67x EMIF (note this is the only use of 1748 BAR1 via BootLoader_WriteMem32) */ 1749 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL, 1750 0x000034A8); 1751 1752 /* EMIF CE0 setup - 2Mx32 Sync DRAM 1753 31..28 Wr setup 1754 27..22 Wr strobe 1755 21..20 Wr hold 1756 19..16 Rd setup 1757 15..14 - 1758 13..8 Rd strobe 1759 7..4 MTYPE 0011 Sync DRAM 32bits 1760 3 Wr hold MSB 1761 2..0 Rd hold 1762 */ 1763 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0, 1764 0x00000030); 1765 1766 /* EMIF SDRAM Extension 1767 0x00 1768 31-21 0000b 0000b 000b 1769 20 WR2RD = 2cycles-1 = 1b 1770 1771 19-18 WR2DEAC = 3cycle-1 = 10b 1772 17 WR2WR = 2cycle-1 = 1b 1773 16-15 R2WDQM = 4cycle-1 = 11b 1774 14-12 RD2WR = 6cycles-1 = 101b 1775 1776 11-10 RD2DEAC = 4cycle-1 = 11b 1777 9 RD2RD = 2cycle-1 = 1b 1778 8-7 THZP = 3cycle-1 = 10b 1779 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns) 1780 4 TRRD = 2cycle = 0b (tRRD = 14ns) 1781 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns) 1782 1 CAS latency = 3cyc = 1b 1783 (for Micron 2M32-7 operating at 100MHz) 1784 */ 1785 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT, 1786 0x001BDF29); 1787 1788 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 1789 31 - 0b - 1790 30 SDBSZ 1b 4 bank 1791 29..28 SDRSZ 00b 11 row address pins 1792 1793 27..26 SDCSZ 01b 8 column address pins 1794 25 RFEN 1b refersh enabled 1795 24 INIT 1b init SDRAM! 1796 1797 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1 1798 1799 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1 1800 1801 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6 1802 1803 11..0 - 0000b 0000b 0000b 1804 */ 1805 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL, 1806 0x47116000); 1807 1808 /* SDRAM refresh timing 1809 Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A 1810 */ 1811 boot_loader_write_mem32(pao, dsp_index, 1812 C6713_EMIF_SDRAMTIMING, 0x00000410); 1813 1814 hpios_delay_micro_seconds(1000); 1815 } else if (dsp_index == 2) { 1816 /* DSP 2 is a C6713 */ 1817 } 1818 1819 return 0; 1820 } 1821 1822 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, 1823 u32 start_address, u32 length) 1824 { 1825 u32 i = 0, j = 0; 1826 u32 test_addr = 0; 1827 u32 test_data = 0, data = 0; 1828 1829 length = 1000; 1830 1831 /* for 1st word, test each bit in the 32bit word, */ 1832 /* dwLength specifies number of 32bit words to test */ 1833 /*for(i=0; i<dwLength; i++) */ 1834 i = 0; 1835 { 1836 test_addr = start_address + i * 4; 1837 test_data = 0x00000001; 1838 for (j = 0; j < 32; j++) { 1839 boot_loader_write_mem32(pao, dsp_index, test_addr, 1840 test_data); 1841 data = boot_loader_read_mem32(pao, dsp_index, 1842 test_addr); 1843 if (data != test_data) { 1844 HPI_DEBUG_LOG(VERBOSE, 1845 "Memtest error details " 1846 "%08x %08x %08x %i\n", test_addr, 1847 test_data, data, dsp_index); 1848 return 1; /* error */ 1849 } 1850 test_data = test_data << 1; 1851 } /* for(j) */ 1852 } /* for(i) */ 1853 1854 /* for the next 100 locations test each location, leaving it as zero */ 1855 /* write a zero to the next word in memory before we read */ 1856 /* the previous write to make sure every memory location is unique */ 1857 for (i = 0; i < 100; i++) { 1858 test_addr = start_address + i * 4; 1859 test_data = 0xA5A55A5A; 1860 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data); 1861 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0); 1862 data = boot_loader_read_mem32(pao, dsp_index, test_addr); 1863 if (data != test_data) { 1864 HPI_DEBUG_LOG(VERBOSE, 1865 "Memtest error details " 1866 "%08x %08x %08x %i\n", test_addr, test_data, 1867 data, dsp_index); 1868 return 1; /* error */ 1869 } 1870 /* leave location as zero */ 1871 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); 1872 } 1873 1874 /* zero out entire memory block */ 1875 for (i = 0; i < length; i++) { 1876 test_addr = start_address + i * 4; 1877 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); 1878 } 1879 return 0; 1880 } 1881 1882 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, 1883 int dsp_index) 1884 { 1885 int err = 0; 1886 if (dsp_index == 0) { 1887 /* DSP 0 is a C6205 */ 1888 /* 64K prog mem */ 1889 err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 1890 0x10000); 1891 if (!err) 1892 /* 64K data mem */ 1893 err = boot_loader_test_memory(pao, dsp_index, 1894 0x80000000, 0x10000); 1895 } else if (dsp_index == 1) { 1896 /* DSP 1 is a C6713 */ 1897 /* 192K internal mem */ 1898 err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 1899 0x30000); 1900 if (!err) 1901 /* 64K internal mem / L2 cache */ 1902 err = boot_loader_test_memory(pao, dsp_index, 1903 0x00030000, 0x10000); 1904 } 1905 1906 if (err) 1907 return HPI6205_ERROR_DSP_INTMEM; 1908 else 1909 return 0; 1910 } 1911 1912 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, 1913 int dsp_index) 1914 { 1915 u32 dRAM_start_address = 0; 1916 u32 dRAM_size = 0; 1917 1918 if (dsp_index == 0) { 1919 /* only test for SDRAM if an ASI5000 card */ 1920 if (pao->pci.pci_dev->subsystem_device == 0x5000) { 1921 /* DSP 0 is always C6205 */ 1922 dRAM_start_address = 0x00400000; 1923 dRAM_size = 0x200000; 1924 /*dwDRAMinc=1024; */ 1925 } else 1926 return 0; 1927 } else if (dsp_index == 1) { 1928 /* DSP 1 is a C6713 */ 1929 dRAM_start_address = 0x80000000; 1930 dRAM_size = 0x200000; 1931 /*dwDRAMinc=1024; */ 1932 } 1933 1934 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address, 1935 dRAM_size)) 1936 return HPI6205_ERROR_DSP_EXTMEM; 1937 return 0; 1938 } 1939 1940 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index) 1941 { 1942 u32 data = 0; 1943 if (dsp_index == 0) { 1944 /* only test for DSP0 PLD on ASI5000 card */ 1945 if (pao->pci.pci_dev->subsystem_device == 0x5000) { 1946 /* PLD is located at CE3=0x03000000 */ 1947 data = boot_loader_read_mem32(pao, dsp_index, 1948 0x03000008); 1949 if ((data & 0xF) != 0x5) 1950 return HPI6205_ERROR_DSP_PLD; 1951 data = boot_loader_read_mem32(pao, dsp_index, 1952 0x0300000C); 1953 if ((data & 0xF) != 0xA) 1954 return HPI6205_ERROR_DSP_PLD; 1955 } 1956 } else if (dsp_index == 1) { 1957 /* DSP 1 is a C6713 */ 1958 if (pao->pci.pci_dev->subsystem_device == 0x8700) { 1959 /* PLD is located at CE1=0x90000000 */ 1960 data = boot_loader_read_mem32(pao, dsp_index, 1961 0x90000010); 1962 if ((data & 0xFF) != 0xAA) 1963 return HPI6205_ERROR_DSP_PLD; 1964 /* 8713 - LED on */ 1965 boot_loader_write_mem32(pao, dsp_index, 0x90000000, 1966 0x02); 1967 } 1968 } 1969 return 0; 1970 } 1971 1972 /** Transfer data to or from DSP 1973 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA 1974 */ 1975 static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data, 1976 u32 data_size, int operation) 1977 { 1978 struct hpi_hw_obj *phw = pao->priv; 1979 u32 data_transferred = 0; 1980 u16 err = 0; 1981 u32 temp2; 1982 struct bus_master_interface *interface = phw->p_interface_buffer; 1983 1984 if (!p_data) 1985 return HPI_ERROR_INVALID_DATA_POINTER; 1986 1987 data_size &= ~3L; /* round data_size down to nearest 4 bytes */ 1988 1989 /* make sure state is IDLE */ 1990 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) 1991 return HPI_ERROR_DSP_HARDWARE; 1992 1993 while (data_transferred < data_size) { 1994 u32 this_copy = data_size - data_transferred; 1995 1996 if (this_copy > HPI6205_SIZEOF_DATA) 1997 this_copy = HPI6205_SIZEOF_DATA; 1998 1999 if (operation == H620_HIF_SEND_DATA) 2000 memcpy((void *)&interface->u.b_data[0], 2001 &p_data[data_transferred], this_copy); 2002 2003 interface->transfer_size_in_bytes = this_copy; 2004 2005 /* DSP must change this back to nOperation */ 2006 interface->dsp_ack = H620_HIF_IDLE; 2007 send_dsp_command(phw, operation); 2008 2009 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT); 2010 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n", 2011 HPI6205_TIMEOUT - temp2, this_copy); 2012 2013 if (!temp2) { 2014 /* timed out */ 2015 HPI_DEBUG_LOG(ERROR, 2016 "Timed out waiting for " "state %d got %d\n", 2017 operation, interface->dsp_ack); 2018 2019 break; 2020 } 2021 if (operation == H620_HIF_GET_DATA) 2022 memcpy(&p_data[data_transferred], 2023 (void *)&interface->u.b_data[0], this_copy); 2024 2025 data_transferred += this_copy; 2026 } 2027 if (interface->dsp_ack != operation) 2028 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n", 2029 interface->dsp_ack, operation); 2030 /* err=HPI_ERROR_DSP_HARDWARE; */ 2031 2032 send_dsp_command(phw, H620_HIF_IDLE); 2033 2034 return err; 2035 } 2036 2037 /* wait for up to timeout_us microseconds for the DSP 2038 to signal state by DMA into dwDspAck 2039 */ 2040 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us) 2041 { 2042 struct bus_master_interface *interface = phw->p_interface_buffer; 2043 int t = timeout_us / 4; 2044 2045 rmb(); /* ensure interface->dsp_ack is up to date */ 2046 while ((interface->dsp_ack != state) && --t) { 2047 hpios_delay_micro_seconds(4); 2048 rmb(); /* DSP changes dsp_ack by DMA */ 2049 } 2050 2051 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */ 2052 return t * 4; 2053 } 2054 2055 /* set the busmaster interface to cmd, then interrupt the DSP */ 2056 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd) 2057 { 2058 struct bus_master_interface *interface = phw->p_interface_buffer; 2059 u32 r; 2060 2061 interface->host_cmd = cmd; 2062 wmb(); /* DSP gets state by DMA, make sure it is written to memory */ 2063 /* before we interrupt the DSP */ 2064 r = ioread32(phw->prHDCR); 2065 r |= (u32)C6205_HDCR_DSPINT; 2066 iowrite32(r, phw->prHDCR); 2067 r &= ~(u32)C6205_HDCR_DSPINT; 2068 iowrite32(r, phw->prHDCR); 2069 } 2070 2071 static unsigned int message_count; 2072 2073 static u16 message_response_sequence(struct hpi_adapter_obj *pao, 2074 struct hpi_message *phm, struct hpi_response *phr) 2075 { 2076 u32 time_out, time_out2; 2077 struct hpi_hw_obj *phw = pao->priv; 2078 struct bus_master_interface *interface = phw->p_interface_buffer; 2079 u16 err = 0; 2080 2081 message_count++; 2082 if (phm->size > sizeof(interface->u.message_buffer)) { 2083 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL; 2084 phr->specific_error = sizeof(interface->u.message_buffer); 2085 phr->size = sizeof(struct hpi_response_header); 2086 HPI_DEBUG_LOG(ERROR, 2087 "message len %d too big for buffer %zd \n", phm->size, 2088 sizeof(interface->u.message_buffer)); 2089 return 0; 2090 } 2091 2092 /* Assume buffer of type struct bus_master_interface 2093 is allocated "noncacheable" */ 2094 2095 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { 2096 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n"); 2097 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; 2098 } 2099 2100 memcpy(&interface->u.message_buffer, phm, phm->size); 2101 /* signal we want a response */ 2102 send_dsp_command(phw, H620_HIF_GET_RESP); 2103 2104 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT); 2105 2106 if (!time_out2) { 2107 HPI_DEBUG_LOG(ERROR, 2108 "(%u) Timed out waiting for " "GET_RESP state [%x]\n", 2109 message_count, interface->dsp_ack); 2110 } else { 2111 HPI_DEBUG_LOG(VERBOSE, 2112 "(%u) transition to GET_RESP after %u\n", 2113 message_count, HPI6205_TIMEOUT - time_out2); 2114 } 2115 /* spin waiting on HIF interrupt flag (end of msg process) */ 2116 time_out = HPI6205_TIMEOUT; 2117 2118 /* read the result */ 2119 if (time_out) { 2120 if (interface->u.response_buffer.response.size <= phr->size) 2121 memcpy(phr, &interface->u.response_buffer, 2122 interface->u.response_buffer.response.size); 2123 else { 2124 HPI_DEBUG_LOG(ERROR, 2125 "response len %d too big for buffer %d\n", 2126 interface->u.response_buffer.response.size, 2127 phr->size); 2128 memcpy(phr, &interface->u.response_buffer, 2129 sizeof(struct hpi_response_header)); 2130 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; 2131 phr->specific_error = 2132 interface->u.response_buffer.response.size; 2133 phr->size = sizeof(struct hpi_response_header); 2134 } 2135 } 2136 /* set interface back to idle */ 2137 send_dsp_command(phw, H620_HIF_IDLE); 2138 2139 if (!time_out || !time_out2) { 2140 HPI_DEBUG_LOG(DEBUG, "something timed out!\n"); 2141 return HPI6205_ERROR_MSG_RESP_TIMEOUT; 2142 } 2143 /* special case for adapter close - */ 2144 /* wait for the DSP to indicate it is idle */ 2145 if (phm->function == HPI_ADAPTER_CLOSE) { 2146 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { 2147 HPI_DEBUG_LOG(DEBUG, 2148 "Timeout waiting for idle " 2149 "(on adapter_close)\n"); 2150 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; 2151 } 2152 } 2153 err = hpi_validate_response(phm, phr); 2154 return err; 2155 } 2156 2157 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 2158 struct hpi_response *phr) 2159 { 2160 2161 u16 err = 0; 2162 2163 hpios_dsplock_lock(pao); 2164 2165 err = message_response_sequence(pao, phm, phr); 2166 2167 /* maybe an error response */ 2168 if (err) { 2169 /* something failed in the HPI/DSP interface */ 2170 if (err >= HPI_ERROR_BACKEND_BASE) { 2171 phr->error = HPI_ERROR_DSP_COMMUNICATION; 2172 phr->specific_error = err; 2173 } else { 2174 phr->error = err; 2175 } 2176 2177 pao->dsp_crashed++; 2178 2179 /* just the header of the response is valid */ 2180 phr->size = sizeof(struct hpi_response_header); 2181 goto err; 2182 } else 2183 pao->dsp_crashed = 0; 2184 2185 if (phr->error != 0) /* something failed in the DSP */ 2186 goto err; 2187 2188 switch (phm->function) { 2189 case HPI_OSTREAM_WRITE: 2190 case HPI_ISTREAM_ANC_WRITE: 2191 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, 2192 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA); 2193 break; 2194 2195 case HPI_ISTREAM_READ: 2196 case HPI_OSTREAM_ANC_READ: 2197 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, 2198 phm->u.d.u.data.data_size, H620_HIF_GET_DATA); 2199 break; 2200 2201 } 2202 phr->error = err; 2203 2204 err: 2205 hpios_dsplock_unlock(pao); 2206 2207 return; 2208 } 2209