1 /****************************************************************************** 2 3 AudioScience HPI driver 4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of version 2 of the GNU General Public License as 8 published by the Free Software Foundation; 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 19 Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters. 20 These PCI bus adapters are based on the TI C6711 DSP. 21 22 Exported functions: 23 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr) 24 25 #defines 26 HIDE_PCI_ASSERTS to show the PCI asserts 27 PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1) 28 29 (C) Copyright AudioScience Inc. 1998-2003 30 *******************************************************************************/ 31 #define SOURCEFILE_NAME "hpi6000.c" 32 33 #include "hpi_internal.h" 34 #include "hpimsginit.h" 35 #include "hpidebug.h" 36 #include "hpi6000.h" 37 #include "hpidspcd.h" 38 #include "hpicmn.h" 39 40 #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */ 41 #define HPI_HIF_ADDR(member) \ 42 (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member)) 43 #define HPI_HIF_ERROR_MASK 0x4000 44 45 /* HPI6000 specific error codes */ 46 #define HPI6000_ERROR_BASE 900 /* not actually used anywhere */ 47 48 /* operational/messaging errors */ 49 #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901 50 51 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903 52 #define HPI6000_ERROR_MSG_GET_ADR 904 53 #define HPI6000_ERROR_RESP_GET_ADR 905 54 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906 55 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907 56 57 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909 58 59 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911 60 #define HPI6000_ERROR_SEND_DATA_ACK 912 61 #define HPI6000_ERROR_SEND_DATA_ADR 913 62 #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914 63 #define HPI6000_ERROR_SEND_DATA_CMD 915 64 #define HPI6000_ERROR_SEND_DATA_WRITE 916 65 #define HPI6000_ERROR_SEND_DATA_IDLECMD 917 66 67 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921 68 #define HPI6000_ERROR_GET_DATA_ACK 922 69 #define HPI6000_ERROR_GET_DATA_CMD 923 70 #define HPI6000_ERROR_GET_DATA_READ 924 71 #define HPI6000_ERROR_GET_DATA_IDLECMD 925 72 73 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951 74 #define HPI6000_ERROR_CONTROL_CACHE_READ 952 75 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953 76 77 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961 78 #define HPI6000_ERROR_MSG_RESP_IDLECMD 962 79 80 /* Initialisation/bootload errors */ 81 #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930 82 83 /* can't access PCI2040 */ 84 #define HPI6000_ERROR_INIT_PCI2040 931 85 /* can't access DSP HPI i/f */ 86 #define HPI6000_ERROR_INIT_DSPHPI 932 87 /* can't access internal DSP memory */ 88 #define HPI6000_ERROR_INIT_DSPINTMEM 933 89 /* can't access SDRAM - test#1 */ 90 #define HPI6000_ERROR_INIT_SDRAM1 934 91 /* can't access SDRAM - test#2 */ 92 #define HPI6000_ERROR_INIT_SDRAM2 935 93 94 #define HPI6000_ERROR_INIT_VERIFY 938 95 96 #define HPI6000_ERROR_INIT_NOACK 939 97 98 #define HPI6000_ERROR_INIT_PLDTEST1 941 99 #define HPI6000_ERROR_INIT_PLDTEST2 942 100 101 /* local defines */ 102 103 #define HIDE_PCI_ASSERTS 104 #define PROFILE_DSP2 105 106 /* for PCI2040 i/f chip */ 107 /* HPI CSR registers */ 108 /* word offsets from CSR base */ 109 /* use when io addresses defined as u32 * */ 110 111 #define INTERRUPT_EVENT_SET 0 112 #define INTERRUPT_EVENT_CLEAR 1 113 #define INTERRUPT_MASK_SET 2 114 #define INTERRUPT_MASK_CLEAR 3 115 #define HPI_ERROR_REPORT 4 116 #define HPI_RESET 5 117 #define HPI_DATA_WIDTH 6 118 119 #define MAX_DSPS 2 120 /* HPI registers, spaced 8K bytes = 2K words apart */ 121 #define DSP_SPACING 0x800 122 123 #define CONTROL 0x0000 124 #define ADDRESS 0x0200 125 #define DATA_AUTOINC 0x0400 126 #define DATA 0x0600 127 128 #define TIMEOUT 500000 129 130 struct dsp_obj { 131 __iomem u32 *prHPI_control; 132 __iomem u32 *prHPI_address; 133 __iomem u32 *prHPI_data; 134 __iomem u32 *prHPI_data_auto_inc; 135 char c_dsp_rev; /*A, B */ 136 u32 control_cache_address_on_dsp; 137 u32 control_cache_length_on_dsp; 138 struct hpi_adapter_obj *pa_parent_adapter; 139 }; 140 141 struct hpi_hw_obj { 142 __iomem u32 *dw2040_HPICSR; 143 __iomem u32 *dw2040_HPIDSP; 144 145 u16 num_dsp; 146 struct dsp_obj ado[MAX_DSPS]; 147 148 u32 message_buffer_address_on_dsp; 149 u32 response_buffer_address_on_dsp; 150 u32 pCI2040HPI_error_count; 151 152 struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS]; 153 struct hpi_control_cache *p_cache; 154 }; 155 156 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao, 157 u16 dsp_index, u32 hpi_address, u32 *source, u32 count); 158 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao, 159 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count); 160 161 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 162 u32 *pos_error_code); 163 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao, 164 u16 read_or_write); 165 #define H6READ 1 166 #define H6WRITE 0 167 168 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao, 169 struct hpi_message *phm); 170 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao, 171 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr); 172 173 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 174 struct hpi_response *phr); 175 176 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index, 177 u32 ack_value); 178 179 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao, 180 u16 dsp_index, u32 host_cmd); 181 182 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo); 183 184 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index, 185 struct hpi_message *phm, struct hpi_response *phr); 186 187 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index, 188 struct hpi_message *phm, struct hpi_response *phr); 189 190 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data); 191 192 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address); 193 194 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata, 195 u32 length); 196 197 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata, 198 u32 length); 199 200 static void subsys_create_adapter(struct hpi_message *phm, 201 struct hpi_response *phr); 202 203 static void adapter_delete(struct hpi_adapter_obj *pao, 204 struct hpi_message *phm, struct hpi_response *phr); 205 206 static void adapter_get_asserts(struct hpi_adapter_obj *pao, 207 struct hpi_message *phm, struct hpi_response *phr); 208 209 static short create_adapter_obj(struct hpi_adapter_obj *pao, 210 u32 *pos_error_code); 211 212 static void delete_adapter_obj(struct hpi_adapter_obj *pao); 213 214 /* local globals */ 215 216 static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */ 217 static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */ 218 219 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr) 220 { 221 switch (phm->function) { 222 case HPI_SUBSYS_CREATE_ADAPTER: 223 subsys_create_adapter(phm, phr); 224 break; 225 default: 226 phr->error = HPI_ERROR_INVALID_FUNC; 227 break; 228 } 229 } 230 231 static void control_message(struct hpi_adapter_obj *pao, 232 struct hpi_message *phm, struct hpi_response *phr) 233 { 234 switch (phm->function) { 235 case HPI_CONTROL_GET_STATE: 236 if (pao->has_control_cache) { 237 u16 err; 238 err = hpi6000_update_control_cache(pao, phm); 239 240 if (err) { 241 if (err >= HPI_ERROR_BACKEND_BASE) { 242 phr->error = 243 HPI_ERROR_CONTROL_CACHING; 244 phr->specific_error = err; 245 } else { 246 phr->error = err; 247 } 248 break; 249 } 250 251 if (hpi_check_control_cache(((struct hpi_hw_obj *) 252 pao->priv)->p_cache, phm, 253 phr)) 254 break; 255 } 256 hw_message(pao, phm, phr); 257 break; 258 case HPI_CONTROL_SET_STATE: 259 hw_message(pao, phm, phr); 260 hpi_cmn_control_cache_sync_to_msg(((struct hpi_hw_obj *)pao-> 261 priv)->p_cache, phm, phr); 262 break; 263 264 case HPI_CONTROL_GET_INFO: 265 default: 266 hw_message(pao, phm, phr); 267 break; 268 } 269 } 270 271 static void adapter_message(struct hpi_adapter_obj *pao, 272 struct hpi_message *phm, struct hpi_response *phr) 273 { 274 switch (phm->function) { 275 case HPI_ADAPTER_GET_ASSERT: 276 adapter_get_asserts(pao, phm, phr); 277 break; 278 279 case HPI_ADAPTER_DELETE: 280 adapter_delete(pao, phm, phr); 281 break; 282 283 default: 284 hw_message(pao, phm, phr); 285 break; 286 } 287 } 288 289 static void outstream_message(struct hpi_adapter_obj *pao, 290 struct hpi_message *phm, struct hpi_response *phr) 291 { 292 switch (phm->function) { 293 case HPI_OSTREAM_HOSTBUFFER_ALLOC: 294 case HPI_OSTREAM_HOSTBUFFER_FREE: 295 /* Don't let these messages go to the HW function because 296 * they're called without locking the spinlock. 297 * For the HPI6000 adapters the HW would return 298 * HPI_ERROR_INVALID_FUNC anyway. 299 */ 300 phr->error = HPI_ERROR_INVALID_FUNC; 301 break; 302 default: 303 hw_message(pao, phm, phr); 304 return; 305 } 306 } 307 308 static void instream_message(struct hpi_adapter_obj *pao, 309 struct hpi_message *phm, struct hpi_response *phr) 310 { 311 312 switch (phm->function) { 313 case HPI_ISTREAM_HOSTBUFFER_ALLOC: 314 case HPI_ISTREAM_HOSTBUFFER_FREE: 315 /* Don't let these messages go to the HW function because 316 * they're called without locking the spinlock. 317 * For the HPI6000 adapters the HW would return 318 * HPI_ERROR_INVALID_FUNC anyway. 319 */ 320 phr->error = HPI_ERROR_INVALID_FUNC; 321 break; 322 default: 323 hw_message(pao, phm, phr); 324 return; 325 } 326 } 327 328 /************************************************************************/ 329 /** HPI_6000() 330 * Entry point from HPIMAN 331 * All calls to the HPI start here 332 */ 333 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr) 334 { 335 struct hpi_adapter_obj *pao = NULL; 336 337 if (phm->object != HPI_OBJ_SUBSYSTEM) { 338 pao = hpi_find_adapter(phm->adapter_index); 339 if (!pao) { 340 hpi_init_response(phr, phm->object, phm->function, 341 HPI_ERROR_BAD_ADAPTER_NUMBER); 342 HPI_DEBUG_LOG(DEBUG, "invalid adapter index: %d \n", 343 phm->adapter_index); 344 return; 345 } 346 347 /* Don't even try to communicate with crashed DSP */ 348 if (pao->dsp_crashed >= 10) { 349 hpi_init_response(phr, phm->object, phm->function, 350 HPI_ERROR_DSP_HARDWARE); 351 HPI_DEBUG_LOG(DEBUG, "adapter %d dsp crashed\n", 352 phm->adapter_index); 353 return; 354 } 355 } 356 /* Init default response including the size field */ 357 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) 358 hpi_init_response(phr, phm->object, phm->function, 359 HPI_ERROR_PROCESSING_MESSAGE); 360 361 switch (phm->type) { 362 case HPI_TYPE_REQUEST: 363 switch (phm->object) { 364 case HPI_OBJ_SUBSYSTEM: 365 subsys_message(phm, phr); 366 break; 367 368 case HPI_OBJ_ADAPTER: 369 phr->size = 370 sizeof(struct hpi_response_header) + 371 sizeof(struct hpi_adapter_res); 372 adapter_message(pao, phm, phr); 373 break; 374 375 case HPI_OBJ_CONTROL: 376 control_message(pao, phm, phr); 377 break; 378 379 case HPI_OBJ_OSTREAM: 380 outstream_message(pao, phm, phr); 381 break; 382 383 case HPI_OBJ_ISTREAM: 384 instream_message(pao, phm, phr); 385 break; 386 387 default: 388 hw_message(pao, phm, phr); 389 break; 390 } 391 break; 392 393 default: 394 phr->error = HPI_ERROR_INVALID_TYPE; 395 break; 396 } 397 } 398 399 /************************************************************************/ 400 /* SUBSYSTEM */ 401 402 /* create an adapter object and initialise it based on resource information 403 * passed in in the message 404 * NOTE - you cannot use this function AND the FindAdapters function at the 405 * same time, the application must use only one of them to get the adapters 406 */ 407 static void subsys_create_adapter(struct hpi_message *phm, 408 struct hpi_response *phr) 409 { 410 /* create temp adapter obj, because we don't know what index yet */ 411 struct hpi_adapter_obj ao; 412 struct hpi_adapter_obj *pao; 413 u32 os_error_code; 414 u16 err = 0; 415 u32 dsp_index = 0; 416 417 HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n"); 418 419 memset(&ao, 0, sizeof(ao)); 420 421 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); 422 if (!ao.priv) { 423 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n"); 424 phr->error = HPI_ERROR_MEMORY_ALLOC; 425 return; 426 } 427 428 /* create the adapter object based on the resource information */ 429 ao.pci = *phm->u.s.resource.r.pci; 430 431 err = create_adapter_obj(&ao, &os_error_code); 432 if (err) { 433 delete_adapter_obj(&ao); 434 if (err >= HPI_ERROR_BACKEND_BASE) { 435 phr->error = HPI_ERROR_DSP_BOOTLOAD; 436 phr->specific_error = err; 437 } else { 438 phr->error = err; 439 } 440 441 phr->u.s.data = os_error_code; 442 return; 443 } 444 /* need to update paParentAdapter */ 445 pao = hpi_find_adapter(ao.index); 446 if (!pao) { 447 /* We just added this adapter, why can't we find it!? */ 448 HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n"); 449 phr->error = HPI_ERROR_BAD_ADAPTER; 450 return; 451 } 452 453 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) { 454 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; 455 phw->ado[dsp_index].pa_parent_adapter = pao; 456 } 457 458 phr->u.s.adapter_type = ao.adapter_type; 459 phr->u.s.adapter_index = ao.index; 460 phr->error = 0; 461 } 462 463 static void adapter_delete(struct hpi_adapter_obj *pao, 464 struct hpi_message *phm, struct hpi_response *phr) 465 { 466 delete_adapter_obj(pao); 467 hpi_delete_adapter(pao); 468 phr->error = 0; 469 } 470 471 /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */ 472 static short create_adapter_obj(struct hpi_adapter_obj *pao, 473 u32 *pos_error_code) 474 { 475 short boot_error = 0; 476 u32 dsp_index = 0; 477 u32 control_cache_size = 0; 478 u32 control_cache_count = 0; 479 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; 480 481 /* The PCI2040 has the following address map */ 482 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */ 483 /* BAR1 - 32K = HPI registers on DSP */ 484 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0]; 485 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1]; 486 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR, 487 phw->dw2040_HPIDSP); 488 489 /* set addresses for the possible DSP HPI interfaces */ 490 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) { 491 phw->ado[dsp_index].prHPI_control = 492 phw->dw2040_HPIDSP + (CONTROL + 493 DSP_SPACING * dsp_index); 494 495 phw->ado[dsp_index].prHPI_address = 496 phw->dw2040_HPIDSP + (ADDRESS + 497 DSP_SPACING * dsp_index); 498 phw->ado[dsp_index].prHPI_data = 499 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index); 500 501 phw->ado[dsp_index].prHPI_data_auto_inc = 502 phw->dw2040_HPIDSP + (DATA_AUTOINC + 503 DSP_SPACING * dsp_index); 504 505 HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n", 506 phw->ado[dsp_index].prHPI_control, 507 phw->ado[dsp_index].prHPI_address, 508 phw->ado[dsp_index].prHPI_data, 509 phw->ado[dsp_index].prHPI_data_auto_inc); 510 511 phw->ado[dsp_index].pa_parent_adapter = pao; 512 } 513 514 phw->pCI2040HPI_error_count = 0; 515 pao->has_control_cache = 0; 516 517 /* Set the default number of DSPs on this card */ 518 /* This is (conditionally) adjusted after bootloading */ 519 /* of the first DSP in the bootload section. */ 520 phw->num_dsp = 1; 521 522 boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code); 523 if (boot_error) 524 return boot_error; 525 526 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); 527 528 phw->message_buffer_address_on_dsp = 0L; 529 phw->response_buffer_address_on_dsp = 0L; 530 531 /* get info about the adapter by asking the adapter */ 532 /* send a HPI_ADAPTER_GET_INFO message */ 533 { 534 struct hpi_message hm; 535 struct hpi_response hr0; /* response from DSP 0 */ 536 struct hpi_response hr1; /* response from DSP 1 */ 537 u16 error = 0; 538 539 HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n"); 540 memset(&hm, 0, sizeof(hm)); 541 hm.type = HPI_TYPE_REQUEST; 542 hm.size = sizeof(struct hpi_message); 543 hm.object = HPI_OBJ_ADAPTER; 544 hm.function = HPI_ADAPTER_GET_INFO; 545 hm.adapter_index = 0; 546 memset(&hr0, 0, sizeof(hr0)); 547 memset(&hr1, 0, sizeof(hr1)); 548 hr0.size = sizeof(hr0); 549 hr1.size = sizeof(hr1); 550 551 error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0); 552 if (hr0.error) { 553 HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error); 554 return hr0.error; 555 } 556 if (phw->num_dsp == 2) { 557 error = hpi6000_message_response_sequence(pao, 1, &hm, 558 &hr1); 559 if (error) 560 return error; 561 } 562 pao->adapter_type = hr0.u.ax.info.adapter_type; 563 pao->index = hr0.u.ax.info.adapter_index; 564 } 565 566 memset(&phw->control_cache[0], 0, 567 sizeof(struct hpi_control_cache_single) * 568 HPI_NMIXER_CONTROLS); 569 /* Read the control cache length to figure out if it is turned on */ 570 control_cache_size = 571 hpi_read_word(&phw->ado[0], 572 HPI_HIF_ADDR(control_cache_size_in_bytes)); 573 if (control_cache_size) { 574 control_cache_count = 575 hpi_read_word(&phw->ado[0], 576 HPI_HIF_ADDR(control_cache_count)); 577 578 phw->p_cache = 579 hpi_alloc_control_cache(control_cache_count, 580 control_cache_size, (unsigned char *) 581 &phw->control_cache[0] 582 ); 583 if (phw->p_cache) 584 pao->has_control_cache = 1; 585 } 586 587 HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n", 588 pao->adapter_type, pao->index); 589 pao->open = 0; /* upon creation the adapter is closed */ 590 591 if (phw->p_cache) 592 phw->p_cache->adap_idx = pao->index; 593 594 return hpi_add_adapter(pao); 595 } 596 597 static void delete_adapter_obj(struct hpi_adapter_obj *pao) 598 { 599 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; 600 601 if (pao->has_control_cache) 602 hpi_free_control_cache(phw->p_cache); 603 604 /* reset DSPs on adapter */ 605 iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET); 606 607 kfree(phw); 608 } 609 610 /************************************************************************/ 611 /* ADAPTER */ 612 613 static void adapter_get_asserts(struct hpi_adapter_obj *pao, 614 struct hpi_message *phm, struct hpi_response *phr) 615 { 616 #ifndef HIDE_PCI_ASSERTS 617 /* if we have PCI2040 asserts then collect them */ 618 if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) { 619 phr->u.ax.assert.p1 = 620 gw_pci_read_asserts * 100 + gw_pci_write_asserts; 621 phr->u.ax.assert.p2 = 0; 622 phr->u.ax.assert.count = 1; /* assert count */ 623 phr->u.ax.assert.dsp_index = -1; /* "dsp index" */ 624 strcpy(phr->u.ax.assert.sz_message, "PCI2040 error"); 625 phr->u.ax.assert.dsp_msg_addr = 0; 626 gw_pci_read_asserts = 0; 627 gw_pci_write_asserts = 0; 628 phr->error = 0; 629 } else 630 #endif 631 hw_message(pao, phm, phr); /*get DSP asserts */ 632 633 return; 634 } 635 636 /************************************************************************/ 637 /* LOW-LEVEL */ 638 639 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 640 u32 *pos_error_code) 641 { 642 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; 643 short error; 644 u32 timeout; 645 u32 read = 0; 646 u32 i = 0; 647 u32 data = 0; 648 u32 j = 0; 649 u32 test_addr = 0x80000000; 650 u32 test_data = 0x00000001; 651 u32 dw2040_reset = 0; 652 u32 dsp_index = 0; 653 u32 endian = 0; 654 u32 adapter_info = 0; 655 u32 delay = 0; 656 657 struct dsp_code dsp_code; 658 u16 boot_load_family = 0; 659 660 /* NOTE don't use wAdapterType in this routine. It is not setup yet */ 661 662 switch (pao->pci.pci_dev->subsystem_device) { 663 case 0x5100: 664 case 0x5110: /* ASI5100 revB or higher with C6711D */ 665 case 0x5200: /* ASI5200 PCIe version of ASI5100 */ 666 case 0x6100: 667 case 0x6200: 668 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200); 669 break; 670 default: 671 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID; 672 } 673 674 /* reset all DSPs, indicate two DSPs are present 675 * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode 676 */ 677 endian = 0; 678 dw2040_reset = 0x0003000F; 679 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 680 681 /* read back register to make sure PCI2040 chip is functioning 682 * note that bits 4..15 are read-only and so should always return zero, 683 * even though we wrote 1 to them 684 */ 685 hpios_delay_micro_seconds(1000); 686 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET); 687 688 if (delay != dw2040_reset) { 689 HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset, 690 delay); 691 return HPI6000_ERROR_INIT_PCI2040; 692 } 693 694 /* Indicate that DSP#0,1 is a C6X */ 695 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH); 696 /* set Bit30 and 29 - which will prevent Target aborts from being 697 * issued upon HPI or GP error 698 */ 699 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET); 700 701 /* isolate DSP HAD8 line from PCI2040 so that 702 * Little endian can be set by pullup 703 */ 704 dw2040_reset = dw2040_reset & (~(endian << 3)); 705 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 706 707 phw->ado[0].c_dsp_rev = 'B'; /* revB */ 708 phw->ado[1].c_dsp_rev = 'B'; /* revB */ 709 710 /*Take both DSPs out of reset, setting HAD8 to the correct Endian */ 711 dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */ 712 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 713 dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */ 714 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 715 716 /* set HAD8 back to PCI2040, now that DSP set to little endian mode */ 717 dw2040_reset = dw2040_reset & (~0x00000008); 718 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); 719 /*delay to allow DSP to get going */ 720 hpios_delay_micro_seconds(100); 721 722 /* loop through all DSPs, downloading DSP code */ 723 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) { 724 struct dsp_obj *pdo = &phw->ado[dsp_index]; 725 726 /* configure DSP so that we download code into the SRAM */ 727 /* set control reg for little endian, HWOB=1 */ 728 iowrite32(0x00010001, pdo->prHPI_control); 729 730 /* test access to the HPI address register (HPIA) */ 731 test_data = 0x00000001; 732 for (j = 0; j < 32; j++) { 733 iowrite32(test_data, pdo->prHPI_address); 734 data = ioread32(pdo->prHPI_address); 735 if (data != test_data) { 736 HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n", 737 test_data, data, dsp_index); 738 return HPI6000_ERROR_INIT_DSPHPI; 739 } 740 test_data = test_data << 1; 741 } 742 743 /* if C6713 the setup PLL to generate 225MHz from 25MHz. 744 * Since the PLLDIV1 read is sometimes wrong, even on a C6713, 745 * we're going to do this unconditionally 746 */ 747 /* PLLDIV1 should have a value of 8000 after reset */ 748 /* 749 if (HpiReadWord(pdo,0x01B7C118) == 0x8000) 750 */ 751 { 752 /* C6713 datasheet says we cannot program PLL from HPI, 753 * and indeed if we try to set the PLL multiply from the 754 * HPI, the PLL does not seem to lock, 755 * so we enable the PLL and use the default of x 7 756 */ 757 /* bypass PLL */ 758 hpi_write_word(pdo, 0x01B7C100, 0x0000); 759 hpios_delay_micro_seconds(100); 760 761 /* ** use default of PLL x7 ** */ 762 /* EMIF = 225/3=75MHz */ 763 hpi_write_word(pdo, 0x01B7C120, 0x8002); 764 hpios_delay_micro_seconds(100); 765 766 /* peri = 225/2 */ 767 hpi_write_word(pdo, 0x01B7C11C, 0x8001); 768 hpios_delay_micro_seconds(100); 769 770 /* cpu = 225/1 */ 771 hpi_write_word(pdo, 0x01B7C118, 0x8000); 772 773 /* ~2ms delay */ 774 hpios_delay_micro_seconds(2000); 775 776 /* PLL not bypassed */ 777 hpi_write_word(pdo, 0x01B7C100, 0x0001); 778 /* ~2ms delay */ 779 hpios_delay_micro_seconds(2000); 780 } 781 782 /* test r/w to internal DSP memory 783 * C6711 has L2 cache mapped to 0x0 when reset 784 * 785 * revB - because of bug 3.0.1 last HPI read 786 * (before HPI address issued) must be non-autoinc 787 */ 788 /* test each bit in the 32bit word */ 789 for (i = 0; i < 100; i++) { 790 test_addr = 0x00000000; 791 test_data = 0x00000001; 792 for (j = 0; j < 32; j++) { 793 hpi_write_word(pdo, test_addr + i, test_data); 794 data = hpi_read_word(pdo, test_addr + i); 795 if (data != test_data) { 796 HPI_DEBUG_LOG(ERROR, 797 "DSP mem %x %x %x %x\n", 798 test_addr + i, test_data, 799 data, dsp_index); 800 801 return HPI6000_ERROR_INIT_DSPINTMEM; 802 } 803 test_data = test_data << 1; 804 } 805 } 806 807 /* memory map of ASI6200 808 00000000-0000FFFF 16Kx32 internal program 809 01800000-019FFFFF Internal peripheral 810 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz 811 90000000-9000FFFF CE1 Async peripherals: 812 813 EMIF config 814 ------------ 815 Global EMIF control 816 0 - 817 1 - 818 2 - 819 3 CLK2EN = 1 CLKOUT2 enabled 820 4 CLK1EN = 0 CLKOUT1 disabled 821 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT 822 6 - 823 7 NOHOLD = 1 external HOLD disabled 824 8 HOLDA = 0 HOLDA output is low 825 9 HOLD = 0 HOLD input is low 826 10 ARDY = 1 ARDY input is high 827 11 BUSREQ = 0 BUSREQ output is low 828 12,13 Reserved = 1 829 */ 830 hpi_write_word(pdo, 0x01800000, 0x34A8); 831 832 /* EMIF CE0 setup - 2Mx32 Sync DRAM 833 31..28 Wr setup 834 27..22 Wr strobe 835 21..20 Wr hold 836 19..16 Rd setup 837 15..14 - 838 13..8 Rd strobe 839 7..4 MTYPE 0011 Sync DRAM 32bits 840 3 Wr hold MSB 841 2..0 Rd hold 842 */ 843 hpi_write_word(pdo, 0x01800008, 0x00000030); 844 845 /* EMIF SDRAM Extension 846 31-21 0 847 20 WR2RD = 0 848 19-18 WR2DEAC = 1 849 17 WR2WR = 0 850 16-15 R2WDQM = 2 851 14-12 RD2WR = 4 852 11-10 RD2DEAC = 1 853 9 RD2RD = 1 854 8-7 THZP = 10b 855 6-5 TWR = 2-1 = 01b (tWR = 10ns) 856 4 TRRD = 0b = 2 ECLK (tRRD = 14ns) 857 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK) 858 1 CAS latency = 3 ECLK 859 (for Micron 2M32-7 operating at 100Mhz) 860 */ 861 862 /* need to use this else DSP code crashes */ 863 hpi_write_word(pdo, 0x01800020, 0x001BDF29); 864 865 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 866 31 - - 867 30 SDBSZ 1 4 bank 868 29..28 SDRSZ 00 11 row address pins 869 27..26 SDCSZ 01 8 column address pins 870 25 RFEN 1 refersh enabled 871 24 INIT 1 init SDRAM 872 23..20 TRCD 0001 873 19..16 TRP 0001 874 15..12 TRC 0110 875 11..0 - - 876 */ 877 /* need to use this else DSP code crashes */ 878 hpi_write_word(pdo, 0x01800018, 0x47117000); 879 880 /* EMIF SDRAM Refresh Timing */ 881 hpi_write_word(pdo, 0x0180001C, 0x00000410); 882 883 /*MIF CE1 setup - Async peripherals 884 @100MHz bus speed, each cycle is 10ns, 885 31..28 Wr setup = 1 886 27..22 Wr strobe = 3 30ns 887 21..20 Wr hold = 1 888 19..16 Rd setup =1 889 15..14 Ta = 2 890 13..8 Rd strobe = 3 30ns 891 7..4 MTYPE 0010 Async 32bits 892 3 Wr hold MSB =0 893 2..0 Rd hold = 1 894 */ 895 { 896 u32 cE1 = 897 (1L << 28) | (3L << 22) | (1L << 20) | (1L << 898 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L; 899 hpi_write_word(pdo, 0x01800004, cE1); 900 } 901 902 /* delay a little to allow SDRAM and DSP to "get going" */ 903 hpios_delay_micro_seconds(1000); 904 905 /* test access to SDRAM */ 906 { 907 test_addr = 0x80000000; 908 test_data = 0x00000001; 909 /* test each bit in the 32bit word */ 910 for (j = 0; j < 32; j++) { 911 hpi_write_word(pdo, test_addr, test_data); 912 data = hpi_read_word(pdo, test_addr); 913 if (data != test_data) { 914 HPI_DEBUG_LOG(ERROR, 915 "DSP dram %x %x %x %x\n", 916 test_addr, test_data, data, 917 dsp_index); 918 919 return HPI6000_ERROR_INIT_SDRAM1; 920 } 921 test_data = test_data << 1; 922 } 923 /* test every Nth address in the DRAM */ 924 #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */ 925 #define DRAM_INC 1024 926 test_addr = 0x80000000; 927 test_data = 0x0; 928 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { 929 hpi_write_word(pdo, test_addr + i, test_data); 930 test_data++; 931 } 932 test_addr = 0x80000000; 933 test_data = 0x0; 934 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { 935 data = hpi_read_word(pdo, test_addr + i); 936 if (data != test_data) { 937 HPI_DEBUG_LOG(ERROR, 938 "DSP dram %x %x %x %x\n", 939 test_addr + i, test_data, 940 data, dsp_index); 941 return HPI6000_ERROR_INIT_SDRAM2; 942 } 943 test_data++; 944 } 945 946 } 947 948 /* write the DSP code down into the DSPs memory */ 949 error = hpi_dsp_code_open(boot_load_family, pao->pci.pci_dev, 950 &dsp_code, pos_error_code); 951 952 if (error) 953 return error; 954 955 while (1) { 956 u32 length; 957 u32 address; 958 u32 type; 959 u32 *pcode; 960 961 error = hpi_dsp_code_read_word(&dsp_code, &length); 962 if (error) 963 break; 964 if (length == 0xFFFFFFFF) 965 break; /* end of code */ 966 967 error = hpi_dsp_code_read_word(&dsp_code, &address); 968 if (error) 969 break; 970 error = hpi_dsp_code_read_word(&dsp_code, &type); 971 if (error) 972 break; 973 error = hpi_dsp_code_read_block(length, &dsp_code, 974 &pcode); 975 if (error) 976 break; 977 error = hpi6000_dsp_block_write32(pao, (u16)dsp_index, 978 address, pcode, length); 979 if (error) 980 break; 981 } 982 983 if (error) { 984 hpi_dsp_code_close(&dsp_code); 985 return error; 986 } 987 /* verify that code was written correctly */ 988 /* this time through, assume no errors in DSP code file/array */ 989 hpi_dsp_code_rewind(&dsp_code); 990 while (1) { 991 u32 length; 992 u32 address; 993 u32 type; 994 u32 *pcode; 995 996 hpi_dsp_code_read_word(&dsp_code, &length); 997 if (length == 0xFFFFFFFF) 998 break; /* end of code */ 999 1000 hpi_dsp_code_read_word(&dsp_code, &address); 1001 hpi_dsp_code_read_word(&dsp_code, &type); 1002 hpi_dsp_code_read_block(length, &dsp_code, &pcode); 1003 1004 for (i = 0; i < length; i++) { 1005 data = hpi_read_word(pdo, address); 1006 if (data != *pcode) { 1007 error = HPI6000_ERROR_INIT_VERIFY; 1008 HPI_DEBUG_LOG(ERROR, 1009 "DSP verify %x %x %x %x\n", 1010 address, *pcode, data, 1011 dsp_index); 1012 break; 1013 } 1014 pcode++; 1015 address += 4; 1016 } 1017 if (error) 1018 break; 1019 } 1020 hpi_dsp_code_close(&dsp_code); 1021 if (error) 1022 return error; 1023 1024 /* zero out the hostmailbox */ 1025 { 1026 u32 address = HPI_HIF_ADDR(host_cmd); 1027 for (i = 0; i < 4; i++) { 1028 hpi_write_word(pdo, address, 0); 1029 address += 4; 1030 } 1031 } 1032 /* write the DSP number into the hostmailbox */ 1033 /* structure before starting the DSP */ 1034 hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index); 1035 1036 /* write the DSP adapter Info into the */ 1037 /* hostmailbox before starting the DSP */ 1038 if (dsp_index > 0) 1039 hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info), 1040 adapter_info); 1041 1042 /* step 3. Start code by sending interrupt */ 1043 iowrite32(0x00030003, pdo->prHPI_control); 1044 hpios_delay_micro_seconds(10000); 1045 1046 /* wait for a non-zero value in hostcmd - 1047 * indicating initialization is complete 1048 * 1049 * Init could take a while if DSP checks SDRAM memory 1050 * Was 200000. Increased to 2000000 for ASI8801 so we 1051 * don't get 938 errors. 1052 */ 1053 timeout = 2000000; 1054 while (timeout) { 1055 do { 1056 read = hpi_read_word(pdo, 1057 HPI_HIF_ADDR(host_cmd)); 1058 } while (--timeout 1059 && hpi6000_check_PCI2040_error_flag(pao, 1060 H6READ)); 1061 1062 if (read) 1063 break; 1064 /* The following is a workaround for bug #94: 1065 * Bluescreen on install and subsequent boots on a 1066 * DELL PowerEdge 600SC PC with 1.8GHz P4 and 1067 * ServerWorks chipset. Without this delay the system 1068 * locks up with a bluescreen (NOT GPF or pagefault). 1069 */ 1070 else 1071 hpios_delay_micro_seconds(10000); 1072 } 1073 if (timeout == 0) 1074 return HPI6000_ERROR_INIT_NOACK; 1075 1076 /* read the DSP adapter Info from the */ 1077 /* hostmailbox structure after starting the DSP */ 1078 if (dsp_index == 0) { 1079 /*u32 dwTestData=0; */ 1080 u32 mask = 0; 1081 1082 adapter_info = 1083 hpi_read_word(pdo, 1084 HPI_HIF_ADDR(adapter_info)); 1085 if (HPI_ADAPTER_FAMILY_ASI 1086 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER 1087 (adapter_info)) == 1088 HPI_ADAPTER_FAMILY_ASI(0x6200)) 1089 /* all 6200 cards have this many DSPs */ 1090 phw->num_dsp = 2; 1091 1092 /* test that the PLD is programmed */ 1093 /* and we can read/write 24bits */ 1094 #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */ 1095 1096 switch (boot_load_family) { 1097 case HPI_ADAPTER_FAMILY_ASI(0x6200): 1098 /* ASI6100/6200 has 24bit path to FPGA */ 1099 mask = 0xFFFFFF00L; 1100 /* ASI5100 uses AX6 code, */ 1101 /* but has no PLD r/w register to test */ 1102 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> 1103 subsystem_device) == 1104 HPI_ADAPTER_FAMILY_ASI(0x5100)) 1105 mask = 0x00000000L; 1106 /* ASI5200 uses AX6 code, */ 1107 /* but has no PLD r/w register to test */ 1108 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> 1109 subsystem_device) == 1110 HPI_ADAPTER_FAMILY_ASI(0x5200)) 1111 mask = 0x00000000L; 1112 break; 1113 case HPI_ADAPTER_FAMILY_ASI(0x8800): 1114 /* ASI8800 has 16bit path to FPGA */ 1115 mask = 0xFFFF0000L; 1116 break; 1117 } 1118 test_data = 0xAAAAAA00L & mask; 1119 /* write to 24 bit Debug register (D31-D8) */ 1120 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); 1121 read = hpi_read_word(pdo, 1122 PLD_BASE_ADDRESS + 4L) & mask; 1123 if (read != test_data) { 1124 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, 1125 read); 1126 return HPI6000_ERROR_INIT_PLDTEST1; 1127 } 1128 test_data = 0x55555500L & mask; 1129 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); 1130 read = hpi_read_word(pdo, 1131 PLD_BASE_ADDRESS + 4L) & mask; 1132 if (read != test_data) { 1133 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, 1134 read); 1135 return HPI6000_ERROR_INIT_PLDTEST2; 1136 } 1137 } 1138 } /* for numDSP */ 1139 return 0; 1140 } 1141 1142 #define PCI_TIMEOUT 100 1143 1144 static int hpi_set_address(struct dsp_obj *pdo, u32 address) 1145 { 1146 u32 timeout = PCI_TIMEOUT; 1147 1148 do { 1149 iowrite32(address, pdo->prHPI_address); 1150 } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter, 1151 H6WRITE) 1152 && --timeout); 1153 1154 if (timeout) 1155 return 0; 1156 1157 return 1; 1158 } 1159 1160 /* write one word to the HPI port */ 1161 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data) 1162 { 1163 if (hpi_set_address(pdo, address)) 1164 return; 1165 iowrite32(data, pdo->prHPI_data); 1166 } 1167 1168 /* read one word from the HPI port */ 1169 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address) 1170 { 1171 u32 data = 0; 1172 1173 if (hpi_set_address(pdo, address)) 1174 return 0; /*? No way to return error */ 1175 1176 /* take care of errata in revB DSP (2.0.1) */ 1177 data = ioread32(pdo->prHPI_data); 1178 return data; 1179 } 1180 1181 /* write a block of 32bit words to the DSP HPI port using auto-inc mode */ 1182 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata, 1183 u32 length) 1184 { 1185 u16 length16 = length - 1; 1186 1187 if (length == 0) 1188 return; 1189 1190 if (hpi_set_address(pdo, address)) 1191 return; 1192 1193 iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16); 1194 1195 /* take care of errata in revB DSP (2.0.1) */ 1196 /* must end with non auto-inc */ 1197 iowrite32(*(pdata + length - 1), pdo->prHPI_data); 1198 } 1199 1200 /** read a block of 32bit words from the DSP HPI port using auto-inc mode 1201 */ 1202 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata, 1203 u32 length) 1204 { 1205 u16 length16 = length - 1; 1206 1207 if (length == 0) 1208 return; 1209 1210 if (hpi_set_address(pdo, address)) 1211 return; 1212 1213 ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16); 1214 1215 /* take care of errata in revB DSP (2.0.1) */ 1216 /* must end with non auto-inc */ 1217 *(pdata + length - 1) = ioread32(pdo->prHPI_data); 1218 } 1219 1220 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao, 1221 u16 dsp_index, u32 hpi_address, u32 *source, u32 count) 1222 { 1223 struct dsp_obj *pdo = 1224 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index]; 1225 u32 time_out = PCI_TIMEOUT; 1226 int c6711_burst_size = 128; 1227 u32 local_hpi_address = hpi_address; 1228 int local_count = count; 1229 int xfer_size; 1230 u32 *pdata = source; 1231 1232 while (local_count) { 1233 if (local_count > c6711_burst_size) 1234 xfer_size = c6711_burst_size; 1235 else 1236 xfer_size = local_count; 1237 1238 time_out = PCI_TIMEOUT; 1239 do { 1240 hpi_write_block(pdo, local_hpi_address, pdata, 1241 xfer_size); 1242 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) 1243 && --time_out); 1244 1245 if (!time_out) 1246 break; 1247 pdata += xfer_size; 1248 local_hpi_address += sizeof(u32) * xfer_size; 1249 local_count -= xfer_size; 1250 } 1251 1252 if (time_out) 1253 return 0; 1254 else 1255 return 1; 1256 } 1257 1258 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao, 1259 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count) 1260 { 1261 struct dsp_obj *pdo = 1262 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index]; 1263 u32 time_out = PCI_TIMEOUT; 1264 int c6711_burst_size = 16; 1265 u32 local_hpi_address = hpi_address; 1266 int local_count = count; 1267 int xfer_size; 1268 u32 *pdata = dest; 1269 u32 loop_count = 0; 1270 1271 while (local_count) { 1272 if (local_count > c6711_burst_size) 1273 xfer_size = c6711_burst_size; 1274 else 1275 xfer_size = local_count; 1276 1277 time_out = PCI_TIMEOUT; 1278 do { 1279 hpi_read_block(pdo, local_hpi_address, pdata, 1280 xfer_size); 1281 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) 1282 && --time_out); 1283 if (!time_out) 1284 break; 1285 1286 pdata += xfer_size; 1287 local_hpi_address += sizeof(u32) * xfer_size; 1288 local_count -= xfer_size; 1289 loop_count++; 1290 } 1291 1292 if (time_out) 1293 return 0; 1294 else 1295 return 1; 1296 } 1297 1298 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao, 1299 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr) 1300 { 1301 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; 1302 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1303 u32 timeout; 1304 u16 ack; 1305 u32 address; 1306 u32 length; 1307 u32 *p_data; 1308 u16 error = 0; 1309 1310 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); 1311 if (ack & HPI_HIF_ERROR_MASK) { 1312 pao->dsp_crashed++; 1313 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT; 1314 } 1315 pao->dsp_crashed = 0; 1316 1317 /* get the message address and size */ 1318 if (phw->message_buffer_address_on_dsp == 0) { 1319 timeout = TIMEOUT; 1320 do { 1321 address = 1322 hpi_read_word(pdo, 1323 HPI_HIF_ADDR(message_buffer_address)); 1324 phw->message_buffer_address_on_dsp = address; 1325 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) 1326 && --timeout); 1327 if (!timeout) 1328 return HPI6000_ERROR_MSG_GET_ADR; 1329 } else 1330 address = phw->message_buffer_address_on_dsp; 1331 1332 length = phm->size; 1333 1334 /* send the message */ 1335 p_data = (u32 *)phm; 1336 if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data, 1337 (u16)length / 4)) 1338 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32; 1339 1340 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP)) 1341 return HPI6000_ERROR_MSG_RESP_GETRESPCMD; 1342 hpi6000_send_dsp_interrupt(pdo); 1343 1344 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP); 1345 if (ack & HPI_HIF_ERROR_MASK) 1346 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK; 1347 1348 /* get the response address */ 1349 if (phw->response_buffer_address_on_dsp == 0) { 1350 timeout = TIMEOUT; 1351 do { 1352 address = 1353 hpi_read_word(pdo, 1354 HPI_HIF_ADDR(response_buffer_address)); 1355 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) 1356 && --timeout); 1357 phw->response_buffer_address_on_dsp = address; 1358 1359 if (!timeout) 1360 return HPI6000_ERROR_RESP_GET_ADR; 1361 } else 1362 address = phw->response_buffer_address_on_dsp; 1363 1364 /* read the length of the response back from the DSP */ 1365 timeout = TIMEOUT; 1366 do { 1367 length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); 1368 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); 1369 if (!timeout) 1370 length = sizeof(struct hpi_response); 1371 1372 /* get the response */ 1373 p_data = (u32 *)phr; 1374 if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data, 1375 (u16)length / 4)) 1376 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32; 1377 1378 /* set i/f back to idle */ 1379 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) 1380 return HPI6000_ERROR_MSG_RESP_IDLECMD; 1381 hpi6000_send_dsp_interrupt(pdo); 1382 1383 error = hpi_validate_response(phm, phr); 1384 return error; 1385 } 1386 1387 /* have to set up the below defines to match stuff in the MAP file */ 1388 1389 #define MSG_ADDRESS (HPI_HIF_BASE+0x18) 1390 #define MSG_LENGTH 11 1391 #define RESP_ADDRESS (HPI_HIF_BASE+0x44) 1392 #define RESP_LENGTH 16 1393 #define QUEUE_START (HPI_HIF_BASE+0x88) 1394 #define QUEUE_SIZE 0x8000 1395 1396 static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords) 1397 { 1398 /*#define CHECKING // comment this line in to enable checking */ 1399 #ifdef CHECKING 1400 if (address < (u32)MSG_ADDRESS) 1401 return 0; 1402 if (address > (u32)(QUEUE_START + QUEUE_SIZE)) 1403 return 0; 1404 if ((address + (length_in_dwords << 2)) > 1405 (u32)(QUEUE_START + QUEUE_SIZE)) 1406 return 0; 1407 #else 1408 (void)address; 1409 (void)length_in_dwords; 1410 return 1; 1411 #endif 1412 } 1413 1414 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index, 1415 struct hpi_message *phm, struct hpi_response *phr) 1416 { 1417 struct dsp_obj *pdo = 1418 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index]; 1419 u32 data_sent = 0; 1420 u16 ack; 1421 u32 length, address; 1422 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data; 1423 u16 time_out = 8; 1424 1425 (void)phr; 1426 1427 /* round dwDataSize down to nearest 4 bytes */ 1428 while ((data_sent < (phm->u.d.u.data.data_size & ~3L)) 1429 && --time_out) { 1430 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); 1431 if (ack & HPI_HIF_ERROR_MASK) 1432 return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT; 1433 1434 if (hpi6000_send_host_command(pao, dsp_index, 1435 HPI_HIF_SEND_DATA)) 1436 return HPI6000_ERROR_SEND_DATA_CMD; 1437 1438 hpi6000_send_dsp_interrupt(pdo); 1439 1440 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA); 1441 1442 if (ack & HPI_HIF_ERROR_MASK) 1443 return HPI6000_ERROR_SEND_DATA_ACK; 1444 1445 do { 1446 /* get the address and size */ 1447 address = hpi_read_word(pdo, HPI_HIF_ADDR(address)); 1448 /* DSP returns number of DWORDS */ 1449 length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); 1450 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)); 1451 1452 if (!hpi6000_send_data_check_adr(address, length)) 1453 return HPI6000_ERROR_SEND_DATA_ADR; 1454 1455 /* send the data. break data into 512 DWORD blocks (2K bytes) 1456 * and send using block write. 2Kbytes is the max as this is the 1457 * memory window given to the HPI data register by the PCI2040 1458 */ 1459 1460 { 1461 u32 len = length; 1462 u32 blk_len = 512; 1463 while (len) { 1464 if (len < blk_len) 1465 blk_len = len; 1466 if (hpi6000_dsp_block_write32(pao, dsp_index, 1467 address, p_data, blk_len)) 1468 return HPI6000_ERROR_SEND_DATA_WRITE; 1469 address += blk_len * 4; 1470 p_data += blk_len; 1471 len -= blk_len; 1472 } 1473 } 1474 1475 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) 1476 return HPI6000_ERROR_SEND_DATA_IDLECMD; 1477 1478 hpi6000_send_dsp_interrupt(pdo); 1479 1480 data_sent += length * 4; 1481 } 1482 if (!time_out) 1483 return HPI6000_ERROR_SEND_DATA_TIMEOUT; 1484 return 0; 1485 } 1486 1487 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index, 1488 struct hpi_message *phm, struct hpi_response *phr) 1489 { 1490 struct dsp_obj *pdo = 1491 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index]; 1492 u32 data_got = 0; 1493 u16 ack; 1494 u32 length, address; 1495 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data; 1496 1497 (void)phr; /* this parameter not used! */ 1498 1499 /* round dwDataSize down to nearest 4 bytes */ 1500 while (data_got < (phm->u.d.u.data.data_size & ~3L)) { 1501 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); 1502 if (ack & HPI_HIF_ERROR_MASK) 1503 return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT; 1504 1505 if (hpi6000_send_host_command(pao, dsp_index, 1506 HPI_HIF_GET_DATA)) 1507 return HPI6000_ERROR_GET_DATA_CMD; 1508 hpi6000_send_dsp_interrupt(pdo); 1509 1510 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA); 1511 1512 if (ack & HPI_HIF_ERROR_MASK) 1513 return HPI6000_ERROR_GET_DATA_ACK; 1514 1515 /* get the address and size */ 1516 do { 1517 address = hpi_read_word(pdo, HPI_HIF_ADDR(address)); 1518 length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); 1519 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)); 1520 1521 /* read the data */ 1522 { 1523 u32 len = length; 1524 u32 blk_len = 512; 1525 while (len) { 1526 if (len < blk_len) 1527 blk_len = len; 1528 if (hpi6000_dsp_block_read32(pao, dsp_index, 1529 address, p_data, blk_len)) 1530 return HPI6000_ERROR_GET_DATA_READ; 1531 address += blk_len * 4; 1532 p_data += blk_len; 1533 len -= blk_len; 1534 } 1535 } 1536 1537 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) 1538 return HPI6000_ERROR_GET_DATA_IDLECMD; 1539 hpi6000_send_dsp_interrupt(pdo); 1540 1541 data_got += length * 4; 1542 } 1543 return 0; 1544 } 1545 1546 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo) 1547 { 1548 iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */ 1549 } 1550 1551 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao, 1552 u16 dsp_index, u32 host_cmd) 1553 { 1554 struct dsp_obj *pdo = 1555 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index]; 1556 u32 timeout = TIMEOUT; 1557 1558 /* set command */ 1559 do { 1560 hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd); 1561 /* flush the FIFO */ 1562 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); 1563 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout); 1564 1565 /* reset the interrupt bit */ 1566 iowrite32(0x00040004, pdo->prHPI_control); 1567 1568 if (timeout) 1569 return 0; 1570 else 1571 return 1; 1572 } 1573 1574 /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */ 1575 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao, 1576 u16 read_or_write) 1577 { 1578 u32 hPI_error; 1579 1580 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; 1581 1582 /* read the error bits from the PCI2040 */ 1583 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT); 1584 if (hPI_error) { 1585 /* reset the error flag */ 1586 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT); 1587 phw->pCI2040HPI_error_count++; 1588 if (read_or_write == 1) 1589 gw_pci_read_asserts++; /************* inc global */ 1590 else 1591 gw_pci_write_asserts++; 1592 return 1; 1593 } else 1594 return 0; 1595 } 1596 1597 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index, 1598 u32 ack_value) 1599 { 1600 struct dsp_obj *pdo = 1601 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index]; 1602 u32 ack = 0L; 1603 u32 timeout; 1604 u32 hPIC = 0L; 1605 1606 /* wait for host interrupt to signal ack is ready */ 1607 timeout = TIMEOUT; 1608 while (--timeout) { 1609 hPIC = ioread32(pdo->prHPI_control); 1610 if (hPIC & 0x04) /* 0x04 = HINT from DSP */ 1611 break; 1612 } 1613 if (timeout == 0) 1614 return HPI_HIF_ERROR_MASK; 1615 1616 /* wait for dwAckValue */ 1617 timeout = TIMEOUT; 1618 while (--timeout) { 1619 /* read the ack mailbox */ 1620 ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack)); 1621 if (ack == ack_value) 1622 break; 1623 if ((ack & HPI_HIF_ERROR_MASK) 1624 && !hpi6000_check_PCI2040_error_flag(pao, H6READ)) 1625 break; 1626 /*for (i=0;i<1000;i++) */ 1627 /* dwPause=i+1; */ 1628 } 1629 if (ack & HPI_HIF_ERROR_MASK) 1630 /* indicates bad read from DSP - 1631 typically 0xffffff is read for some reason */ 1632 ack = HPI_HIF_ERROR_MASK; 1633 1634 if (timeout == 0) 1635 ack = HPI_HIF_ERROR_MASK; 1636 return (short)ack; 1637 } 1638 1639 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao, 1640 struct hpi_message *phm) 1641 { 1642 const u16 dsp_index = 0; 1643 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; 1644 struct dsp_obj *pdo = &phw->ado[dsp_index]; 1645 u32 timeout; 1646 u32 cache_dirty_flag; 1647 u16 err; 1648 1649 hpios_dsplock_lock(pao); 1650 1651 timeout = TIMEOUT; 1652 do { 1653 cache_dirty_flag = 1654 hpi_read_word((struct dsp_obj *)pdo, 1655 HPI_HIF_ADDR(control_cache_is_dirty)); 1656 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); 1657 if (!timeout) { 1658 err = HPI6000_ERROR_CONTROL_CACHE_PARAMS; 1659 goto unlock; 1660 } 1661 1662 if (cache_dirty_flag) { 1663 /* read the cached controls */ 1664 u32 address; 1665 u32 length; 1666 1667 timeout = TIMEOUT; 1668 if (pdo->control_cache_address_on_dsp == 0) { 1669 do { 1670 address = 1671 hpi_read_word((struct dsp_obj *)pdo, 1672 HPI_HIF_ADDR(control_cache_address)); 1673 1674 length = hpi_read_word((struct dsp_obj *)pdo, 1675 HPI_HIF_ADDR 1676 (control_cache_size_in_bytes)); 1677 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) 1678 && --timeout); 1679 if (!timeout) { 1680 err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN; 1681 goto unlock; 1682 } 1683 pdo->control_cache_address_on_dsp = address; 1684 pdo->control_cache_length_on_dsp = length; 1685 } else { 1686 address = pdo->control_cache_address_on_dsp; 1687 length = pdo->control_cache_length_on_dsp; 1688 } 1689 1690 if (hpi6000_dsp_block_read32(pao, dsp_index, address, 1691 (u32 *)&phw->control_cache[0], 1692 length / sizeof(u32))) { 1693 err = HPI6000_ERROR_CONTROL_CACHE_READ; 1694 goto unlock; 1695 } 1696 do { 1697 hpi_write_word((struct dsp_obj *)pdo, 1698 HPI_HIF_ADDR(control_cache_is_dirty), 0); 1699 /* flush the FIFO */ 1700 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); 1701 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) 1702 && --timeout); 1703 if (!timeout) { 1704 err = HPI6000_ERROR_CONTROL_CACHE_FLUSH; 1705 goto unlock; 1706 } 1707 1708 } 1709 err = 0; 1710 1711 unlock: 1712 hpios_dsplock_unlock(pao); 1713 return err; 1714 } 1715 1716 /** Get dsp index for multi DSP adapters only */ 1717 static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm) 1718 { 1719 u16 ret = 0; 1720 switch (phm->object) { 1721 case HPI_OBJ_ISTREAM: 1722 if (phm->obj_index < 2) 1723 ret = 1; 1724 break; 1725 case HPI_OBJ_PROFILE: 1726 ret = phm->obj_index; 1727 break; 1728 default: 1729 break; 1730 } 1731 return ret; 1732 } 1733 1734 /** Complete transaction with DSP 1735 1736 Send message, get response, send or get stream data if any. 1737 */ 1738 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 1739 struct hpi_response *phr) 1740 { 1741 u16 error = 0; 1742 u16 dsp_index = 0; 1743 u16 num_dsp = ((struct hpi_hw_obj *)pao->priv)->num_dsp; 1744 1745 if (num_dsp < 2) 1746 dsp_index = 0; 1747 else { 1748 dsp_index = get_dsp_index(pao, phm); 1749 1750 /* is this checked on the DSP anyway? */ 1751 if ((phm->function == HPI_ISTREAM_GROUP_ADD) 1752 || (phm->function == HPI_OSTREAM_GROUP_ADD)) { 1753 struct hpi_message hm; 1754 u16 add_index; 1755 hm.obj_index = phm->u.d.u.stream.stream_index; 1756 hm.object = phm->u.d.u.stream.object_type; 1757 add_index = get_dsp_index(pao, &hm); 1758 if (add_index != dsp_index) { 1759 phr->error = HPI_ERROR_NO_INTERDSP_GROUPS; 1760 return; 1761 } 1762 } 1763 } 1764 1765 hpios_dsplock_lock(pao); 1766 error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr); 1767 1768 if (error) /* something failed in the HPI/DSP interface */ 1769 goto err; 1770 1771 if (phr->error) /* something failed in the DSP */ 1772 goto out; 1773 1774 switch (phm->function) { 1775 case HPI_OSTREAM_WRITE: 1776 case HPI_ISTREAM_ANC_WRITE: 1777 error = hpi6000_send_data(pao, dsp_index, phm, phr); 1778 break; 1779 case HPI_ISTREAM_READ: 1780 case HPI_OSTREAM_ANC_READ: 1781 error = hpi6000_get_data(pao, dsp_index, phm, phr); 1782 break; 1783 case HPI_ADAPTER_GET_ASSERT: 1784 phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */ 1785 if (num_dsp == 2) { 1786 if (!phr->u.ax.assert.count) { 1787 /* no assert from dsp 0, check dsp 1 */ 1788 error = hpi6000_message_response_sequence(pao, 1789 1, phm, phr); 1790 phr->u.ax.assert.dsp_index = 1; 1791 } 1792 } 1793 } 1794 1795 err: 1796 if (error) { 1797 if (error >= HPI_ERROR_BACKEND_BASE) { 1798 phr->error = HPI_ERROR_DSP_COMMUNICATION; 1799 phr->specific_error = error; 1800 } else { 1801 phr->error = error; 1802 } 1803 1804 /* just the header of the response is valid */ 1805 phr->size = sizeof(struct hpi_response_header); 1806 } 1807 out: 1808 hpios_dsplock_unlock(pao); 1809 return; 1810 } 1811