1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HD-audio stream operations 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/export.h> 9 #include <linux/clocksource.h> 10 #include <sound/compress_driver.h> 11 #include <sound/core.h> 12 #include <sound/pcm.h> 13 #include <sound/hdaudio.h> 14 #include <sound/hda_register.h> 15 #include "trace.h" 16 17 /* 18 * the hdac_stream library is intended to be used with the following 19 * transitions. The states are not formally defined in the code but loosely 20 * inspired by boolean variables. Note that the 'prepared' field is not used 21 * in this library but by the callers during the hw_params/prepare transitions 22 * 23 * | 24 * stream_init() | 25 * v 26 * +--+-------+ 27 * | unused | 28 * +--+----+--+ 29 * | ^ 30 * stream_assign() | | stream_release() 31 * v | 32 * +--+----+--+ 33 * | opened | 34 * +--+----+--+ 35 * | ^ 36 * stream_reset() | | 37 * stream_setup() | | stream_cleanup() 38 * v | 39 * +--+----+--+ 40 * | prepared | 41 * +--+----+--+ 42 * | ^ 43 * stream_start() | | stream_stop() 44 * v | 45 * +--+----+--+ 46 * | running | 47 * +----------+ 48 */ 49 50 /** 51 * snd_hdac_get_stream_stripe_ctl - get stripe control value 52 * @bus: HD-audio core bus 53 * @substream: PCM substream 54 */ 55 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, 56 struct snd_pcm_substream *substream) 57 { 58 struct snd_pcm_runtime *runtime = substream->runtime; 59 unsigned int channels = runtime->channels, 60 rate = runtime->rate, 61 bits_per_sample = runtime->sample_bits, 62 max_sdo_lines, value, sdo_line; 63 64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */ 65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO; 66 67 /* following is from HD audio spec */ 68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) { 69 if (rate > 48000) 70 value = (channels * bits_per_sample * 71 (rate / 48000)) / sdo_line; 72 else 73 value = (channels * bits_per_sample) / sdo_line; 74 75 if (value >= bus->sdo_limit) 76 break; 77 } 78 79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */ 80 return sdo_line >> 1; 81 } 82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl); 83 84 /** 85 * snd_hdac_stream_init - initialize each stream (aka device) 86 * @bus: HD-audio core bus 87 * @azx_dev: HD-audio core stream object to initialize 88 * @idx: stream index number 89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) 90 * @tag: the tag id to assign 91 * 92 * Assign the starting bdl address to each stream (device) and initialize. 93 */ 94 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, 95 int idx, int direction, int tag) 96 { 97 azx_dev->bus = bus; 98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); 100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 101 azx_dev->sd_int_sta_mask = 1 << idx; 102 azx_dev->index = idx; 103 azx_dev->direction = direction; 104 azx_dev->stream_tag = tag; 105 snd_hdac_dsp_lock_init(azx_dev); 106 list_add_tail(&azx_dev->list, &bus->stream_list); 107 108 if (bus->spbcap) { 109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE + 110 AZX_SPB_INTERVAL * idx + 111 AZX_SPB_SPIB; 112 113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE + 114 AZX_SPB_INTERVAL * idx + 115 AZX_SPB_MAXFIFO; 116 } 117 118 if (bus->drsmcap) 119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE + 120 AZX_DRSM_INTERVAL * idx; 121 } 122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init); 123 124 /** 125 * snd_hdac_stream_start - start a stream 126 * @azx_dev: HD-audio core stream to start 127 * 128 * Start a stream, set start_wallclk and set the running flag. 129 */ 130 void snd_hdac_stream_start(struct hdac_stream *azx_dev) 131 { 132 struct hdac_bus *bus = azx_dev->bus; 133 int stripe_ctl; 134 135 trace_snd_hdac_stream_start(bus, azx_dev); 136 137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); 138 139 /* enable SIE */ 140 snd_hdac_chip_updatel(bus, INTCTL, 141 1 << azx_dev->index, 142 1 << azx_dev->index); 143 /* set stripe control */ 144 if (azx_dev->stripe) { 145 if (azx_dev->substream) 146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream); 147 else 148 stripe_ctl = 0; 149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 150 stripe_ctl); 151 } 152 /* set DMA start and interrupt mask */ 153 if (bus->access_sdnctl_in_dword) 154 snd_hdac_stream_updatel(azx_dev, SD_CTL, 155 0, SD_CTL_DMA_START | SD_INT_MASK); 156 else 157 snd_hdac_stream_updateb(azx_dev, SD_CTL, 158 0, SD_CTL_DMA_START | SD_INT_MASK); 159 azx_dev->running = true; 160 } 161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start); 162 163 /** 164 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers 165 * @azx_dev: HD-audio core stream to stop 166 */ 167 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev) 168 { 169 snd_hdac_stream_updateb(azx_dev, SD_CTL, 170 SD_CTL_DMA_START | SD_INT_MASK, 0); 171 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 172 if (azx_dev->stripe) 173 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); 174 azx_dev->running = false; 175 } 176 177 /** 178 * snd_hdac_stream_stop - stop a stream 179 * @azx_dev: HD-audio core stream to stop 180 * 181 * Stop a stream DMA and disable stream interrupt 182 */ 183 void snd_hdac_stream_stop(struct hdac_stream *azx_dev) 184 { 185 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev); 186 187 snd_hdac_stream_clear(azx_dev); 188 /* disable SIE */ 189 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); 190 } 191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); 192 193 /** 194 * snd_hdac_stop_streams - stop all streams 195 * @bus: HD-audio core bus 196 */ 197 void snd_hdac_stop_streams(struct hdac_bus *bus) 198 { 199 struct hdac_stream *stream; 200 201 list_for_each_entry(stream, &bus->stream_list, list) 202 snd_hdac_stream_stop(stream); 203 } 204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); 205 206 /** 207 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running 208 * @bus: HD-audio core bus 209 */ 210 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus) 211 { 212 213 if (bus->chip_init) { 214 snd_hdac_stop_streams(bus); 215 snd_hdac_bus_stop_chip(bus); 216 } 217 } 218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip); 219 220 /** 221 * snd_hdac_stream_reset - reset a stream 222 * @azx_dev: HD-audio core stream to reset 223 */ 224 void snd_hdac_stream_reset(struct hdac_stream *azx_dev) 225 { 226 unsigned char val; 227 int dma_run_state; 228 229 snd_hdac_stream_clear(azx_dev); 230 231 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; 232 233 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); 234 235 /* wait for hardware to report that the stream entered reset */ 236 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300); 237 238 if (azx_dev->bus->dma_stop_delay && dma_run_state) 239 udelay(azx_dev->bus->dma_stop_delay); 240 241 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0); 242 243 /* wait for hardware to report that the stream is out of reset */ 244 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300); 245 246 /* reset first position - may not be synced with hw at this time */ 247 if (azx_dev->posbuf) 248 *azx_dev->posbuf = 0; 249 } 250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); 251 252 /** 253 * snd_hdac_stream_setup - set up the SD for streaming 254 * @azx_dev: HD-audio core stream to set up 255 */ 256 int snd_hdac_stream_setup(struct hdac_stream *azx_dev) 257 { 258 struct hdac_bus *bus = azx_dev->bus; 259 struct snd_pcm_runtime *runtime; 260 unsigned int val; 261 262 if (azx_dev->substream) 263 runtime = azx_dev->substream->runtime; 264 else 265 runtime = NULL; 266 /* make sure the run bit is zero for SD */ 267 snd_hdac_stream_clear(azx_dev); 268 /* program the stream_tag */ 269 val = snd_hdac_stream_readl(azx_dev, SD_CTL); 270 val = (val & ~SD_CTL_STREAM_TAG_MASK) | 271 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); 272 if (!bus->snoop) 273 val |= SD_CTL_TRAFFIC_PRIO; 274 snd_hdac_stream_writel(azx_dev, SD_CTL, val); 275 276 /* program the length of samples in cyclic buffer */ 277 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); 278 279 /* program the stream format */ 280 /* this value needs to be the same as the one programmed */ 281 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 282 283 /* program the stream LVI (last valid index) of the BDL */ 284 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 285 286 /* program the BDL address */ 287 /* lower BDL address */ 288 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 289 /* upper BDL address */ 290 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 291 upper_32_bits(azx_dev->bdl.addr)); 292 293 /* enable the position buffer */ 294 if (bus->use_posbuf && bus->posbuf.addr) { 295 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) 296 snd_hdac_chip_writel(bus, DPLBASE, 297 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); 298 } 299 300 /* set the interrupt enable bits in the descriptor control register */ 301 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); 302 303 azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1; 304 305 /* when LPIB delay correction gives a small negative value, 306 * we ignore it; currently set the threshold statically to 307 * 64 frames 308 */ 309 if (runtime && runtime->period_size > 64) 310 azx_dev->delay_negative_threshold = 311 -frames_to_bytes(runtime, 64); 312 else 313 azx_dev->delay_negative_threshold = 0; 314 315 /* wallclk has 24Mhz clock source */ 316 if (runtime) 317 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 318 runtime->rate) * 1000); 319 320 return 0; 321 } 322 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); 323 324 /** 325 * snd_hdac_stream_cleanup - cleanup a stream 326 * @azx_dev: HD-audio core stream to clean up 327 */ 328 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) 329 { 330 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 331 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 332 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 333 azx_dev->bufsize = 0; 334 azx_dev->period_bytes = 0; 335 azx_dev->format_val = 0; 336 } 337 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); 338 339 /** 340 * snd_hdac_stream_assign - assign a stream for the PCM 341 * @bus: HD-audio core bus 342 * @substream: PCM substream to assign 343 * 344 * Look for an unused stream for the given PCM substream, assign it 345 * and return the stream object. If no stream is free, returns NULL. 346 * The function tries to keep using the same stream object when it's used 347 * beforehand. Also, when bus->reverse_assign flag is set, the last free 348 * or matching entry is returned. This is needed for some strange codecs. 349 */ 350 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, 351 struct snd_pcm_substream *substream) 352 { 353 struct hdac_stream *azx_dev; 354 struct hdac_stream *res = NULL; 355 356 /* make a non-zero unique key for the substream */ 357 int key = (substream->pcm->device << 16) | (substream->number << 2) | 358 (substream->stream + 1); 359 360 spin_lock_irq(&bus->reg_lock); 361 list_for_each_entry(azx_dev, &bus->stream_list, list) { 362 if (azx_dev->direction != substream->stream) 363 continue; 364 if (azx_dev->opened) 365 continue; 366 if (azx_dev->assigned_key == key) { 367 res = azx_dev; 368 break; 369 } 370 if (!res || bus->reverse_assign) 371 res = azx_dev; 372 } 373 if (res) { 374 res->opened = 1; 375 res->running = 0; 376 res->assigned_key = key; 377 res->substream = substream; 378 } 379 spin_unlock_irq(&bus->reg_lock); 380 return res; 381 } 382 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); 383 384 /** 385 * snd_hdac_stream_release_locked - release the assigned stream 386 * @azx_dev: HD-audio core stream to release 387 * 388 * Release the stream that has been assigned by snd_hdac_stream_assign(). 389 * The bus->reg_lock needs to be taken at a higher level 390 */ 391 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev) 392 { 393 azx_dev->opened = 0; 394 azx_dev->running = 0; 395 azx_dev->substream = NULL; 396 } 397 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked); 398 399 /** 400 * snd_hdac_stream_release - release the assigned stream 401 * @azx_dev: HD-audio core stream to release 402 * 403 * Release the stream that has been assigned by snd_hdac_stream_assign(). 404 */ 405 void snd_hdac_stream_release(struct hdac_stream *azx_dev) 406 { 407 struct hdac_bus *bus = azx_dev->bus; 408 409 spin_lock_irq(&bus->reg_lock); 410 snd_hdac_stream_release_locked(azx_dev); 411 spin_unlock_irq(&bus->reg_lock); 412 } 413 EXPORT_SYMBOL_GPL(snd_hdac_stream_release); 414 415 /** 416 * snd_hdac_get_stream - return hdac_stream based on stream_tag and 417 * direction 418 * 419 * @bus: HD-audio core bus 420 * @dir: direction for the stream to be found 421 * @stream_tag: stream tag for stream to be found 422 */ 423 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, 424 int dir, int stream_tag) 425 { 426 struct hdac_stream *s; 427 428 list_for_each_entry(s, &bus->stream_list, list) { 429 if (s->direction == dir && s->stream_tag == stream_tag) 430 return s; 431 } 432 433 return NULL; 434 } 435 EXPORT_SYMBOL_GPL(snd_hdac_get_stream); 436 437 /* 438 * set up a BDL entry 439 */ 440 static int setup_bdle(struct hdac_bus *bus, 441 struct snd_dma_buffer *dmab, 442 struct hdac_stream *azx_dev, __le32 **bdlp, 443 int ofs, int size, int with_ioc) 444 { 445 __le32 *bdl = *bdlp; 446 447 while (size > 0) { 448 dma_addr_t addr; 449 int chunk; 450 451 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 452 return -EINVAL; 453 454 addr = snd_sgbuf_get_addr(dmab, ofs); 455 /* program the address field of the BDL entry */ 456 bdl[0] = cpu_to_le32((u32)addr); 457 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 458 /* program the size field of the BDL entry */ 459 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); 460 /* one BDLE cannot cross 4K boundary on CTHDA chips */ 461 if (bus->align_bdle_4k) { 462 u32 remain = 0x1000 - (ofs & 0xfff); 463 464 if (chunk > remain) 465 chunk = remain; 466 } 467 bdl[2] = cpu_to_le32(chunk); 468 /* program the IOC to enable interrupt 469 * only when the whole fragment is processed 470 */ 471 size -= chunk; 472 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 473 bdl += 4; 474 azx_dev->frags++; 475 ofs += chunk; 476 } 477 *bdlp = bdl; 478 return ofs; 479 } 480 481 /** 482 * snd_hdac_stream_setup_periods - set up BDL entries 483 * @azx_dev: HD-audio core stream to set up 484 * 485 * Set up the buffer descriptor table of the given stream based on the 486 * period and buffer sizes of the assigned PCM substream. 487 */ 488 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) 489 { 490 struct hdac_bus *bus = azx_dev->bus; 491 struct snd_pcm_substream *substream = azx_dev->substream; 492 struct snd_compr_stream *cstream = azx_dev->cstream; 493 struct snd_pcm_runtime *runtime = NULL; 494 struct snd_dma_buffer *dmab; 495 __le32 *bdl; 496 int i, ofs, periods, period_bytes; 497 int pos_adj, pos_align; 498 499 if (substream) { 500 runtime = substream->runtime; 501 dmab = snd_pcm_get_dma_buf(substream); 502 } else if (cstream) { 503 dmab = snd_pcm_get_dma_buf(cstream); 504 } else { 505 WARN(1, "No substream or cstream assigned\n"); 506 return -EINVAL; 507 } 508 509 /* reset BDL address */ 510 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 511 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 512 513 period_bytes = azx_dev->period_bytes; 514 periods = azx_dev->bufsize / period_bytes; 515 516 /* program the initial BDL entries */ 517 bdl = (__le32 *)azx_dev->bdl.area; 518 ofs = 0; 519 azx_dev->frags = 0; 520 521 pos_adj = bus->bdl_pos_adj; 522 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) { 523 pos_align = pos_adj; 524 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000); 525 if (!pos_adj) 526 pos_adj = pos_align; 527 else 528 pos_adj = roundup(pos_adj, pos_align); 529 pos_adj = frames_to_bytes(runtime, pos_adj); 530 if (pos_adj >= period_bytes) { 531 dev_warn(bus->dev, "Too big adjustment %d\n", 532 pos_adj); 533 pos_adj = 0; 534 } else { 535 ofs = setup_bdle(bus, dmab, azx_dev, 536 &bdl, ofs, pos_adj, true); 537 if (ofs < 0) 538 goto error; 539 } 540 } else 541 pos_adj = 0; 542 543 for (i = 0; i < periods; i++) { 544 if (i == periods - 1 && pos_adj) 545 ofs = setup_bdle(bus, dmab, azx_dev, 546 &bdl, ofs, period_bytes - pos_adj, 0); 547 else 548 ofs = setup_bdle(bus, dmab, azx_dev, 549 &bdl, ofs, period_bytes, 550 !azx_dev->no_period_wakeup); 551 if (ofs < 0) 552 goto error; 553 } 554 return 0; 555 556 error: 557 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", 558 azx_dev->bufsize, period_bytes); 559 return -EINVAL; 560 } 561 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); 562 563 /** 564 * snd_hdac_stream_set_params - set stream parameters 565 * @azx_dev: HD-audio core stream for which parameters are to be set 566 * @format_val: format value parameter 567 * 568 * Setup the HD-audio core stream parameters from substream of the stream 569 * and passed format value 570 */ 571 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, 572 unsigned int format_val) 573 { 574 struct snd_pcm_substream *substream = azx_dev->substream; 575 struct snd_compr_stream *cstream = azx_dev->cstream; 576 unsigned int bufsize, period_bytes; 577 unsigned int no_period_wakeup; 578 int err; 579 580 if (substream) { 581 bufsize = snd_pcm_lib_buffer_bytes(substream); 582 period_bytes = snd_pcm_lib_period_bytes(substream); 583 no_period_wakeup = substream->runtime->no_period_wakeup; 584 } else if (cstream) { 585 bufsize = cstream->runtime->buffer_size; 586 period_bytes = cstream->runtime->fragment_size; 587 no_period_wakeup = 0; 588 } else { 589 return -EINVAL; 590 } 591 592 if (bufsize != azx_dev->bufsize || 593 period_bytes != azx_dev->period_bytes || 594 format_val != azx_dev->format_val || 595 no_period_wakeup != azx_dev->no_period_wakeup) { 596 azx_dev->bufsize = bufsize; 597 azx_dev->period_bytes = period_bytes; 598 azx_dev->format_val = format_val; 599 azx_dev->no_period_wakeup = no_period_wakeup; 600 err = snd_hdac_stream_setup_periods(azx_dev); 601 if (err < 0) 602 return err; 603 } 604 return 0; 605 } 606 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); 607 608 static u64 azx_cc_read(const struct cyclecounter *cc) 609 { 610 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); 611 612 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); 613 } 614 615 static void azx_timecounter_init(struct hdac_stream *azx_dev, 616 bool force, u64 last) 617 { 618 struct timecounter *tc = &azx_dev->tc; 619 struct cyclecounter *cc = &azx_dev->cc; 620 u64 nsec; 621 622 cc->read = azx_cc_read; 623 cc->mask = CLOCKSOURCE_MASK(32); 624 625 /* 626 * Calculate the optimal mult/shift values. The counter wraps 627 * around after ~178.9 seconds. 628 */ 629 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000, 630 NSEC_PER_SEC, 178); 631 632 nsec = 0; /* audio time is elapsed time since trigger */ 633 timecounter_init(tc, cc, nsec); 634 if (force) { 635 /* 636 * force timecounter to use predefined value, 637 * used for synchronized starts 638 */ 639 tc->cycle_last = last; 640 } 641 } 642 643 /** 644 * snd_hdac_stream_timecounter_init - initialize time counter 645 * @azx_dev: HD-audio core stream (master stream) 646 * @streams: bit flags of streams to set up 647 * 648 * Initializes the time counter of streams marked by the bit flags (each 649 * bit corresponds to the stream index). 650 * The trigger timestamp of PCM substream assigned to the given stream is 651 * updated accordingly, too. 652 */ 653 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, 654 unsigned int streams) 655 { 656 struct hdac_bus *bus = azx_dev->bus; 657 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; 658 struct hdac_stream *s; 659 bool inited = false; 660 u64 cycle_last = 0; 661 int i = 0; 662 663 list_for_each_entry(s, &bus->stream_list, list) { 664 if (streams & (1 << i)) { 665 azx_timecounter_init(s, inited, cycle_last); 666 if (!inited) { 667 inited = true; 668 cycle_last = s->tc.cycle_last; 669 } 670 } 671 i++; 672 } 673 674 snd_pcm_gettime(runtime, &runtime->trigger_tstamp); 675 runtime->trigger_tstamp_latched = true; 676 } 677 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); 678 679 /** 680 * snd_hdac_stream_sync_trigger - turn on/off stream sync register 681 * @azx_dev: HD-audio core stream (master stream) 682 * @set: true = set, false = clear 683 * @streams: bit flags of streams to sync 684 * @reg: the stream sync register address 685 */ 686 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, 687 unsigned int streams, unsigned int reg) 688 { 689 struct hdac_bus *bus = azx_dev->bus; 690 unsigned int val; 691 692 if (!reg) 693 reg = AZX_REG_SSYNC; 694 val = _snd_hdac_chip_readl(bus, reg); 695 if (set) 696 val |= streams; 697 else 698 val &= ~streams; 699 _snd_hdac_chip_writel(bus, reg, val); 700 } 701 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); 702 703 /** 704 * snd_hdac_stream_sync - sync with start/stop trigger operation 705 * @azx_dev: HD-audio core stream (master stream) 706 * @start: true = start, false = stop 707 * @streams: bit flags of streams to sync 708 * 709 * For @start = true, wait until all FIFOs get ready. 710 * For @start = false, wait until all RUN bits are cleared. 711 */ 712 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, 713 unsigned int streams) 714 { 715 struct hdac_bus *bus = azx_dev->bus; 716 int i, nwait, timeout; 717 struct hdac_stream *s; 718 719 for (timeout = 5000; timeout; timeout--) { 720 nwait = 0; 721 i = 0; 722 list_for_each_entry(s, &bus->stream_list, list) { 723 if (!(streams & (1 << i++))) 724 continue; 725 726 if (start) { 727 /* check FIFO gets ready */ 728 if (!(snd_hdac_stream_readb(s, SD_STS) & 729 SD_STS_FIFO_READY)) 730 nwait++; 731 } else { 732 /* check RUN bit is cleared */ 733 if (snd_hdac_stream_readb(s, SD_CTL) & 734 SD_CTL_DMA_START) { 735 nwait++; 736 /* 737 * Perform stream reset if DMA RUN 738 * bit not cleared within given timeout 739 */ 740 if (timeout == 1) 741 snd_hdac_stream_reset(s); 742 } 743 } 744 } 745 if (!nwait) 746 break; 747 cpu_relax(); 748 } 749 } 750 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); 751 752 /** 753 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream 754 * @bus: HD-audio core bus 755 * @enable: flag to enable/disable SPIB 756 * @index: stream index for which SPIB need to be enabled 757 */ 758 void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus, 759 bool enable, int index) 760 { 761 u32 mask = 0; 762 763 if (!bus->spbcap) { 764 dev_err(bus->dev, "Address of SPB capability is NULL\n"); 765 return; 766 } 767 768 mask |= (1 << index); 769 770 if (enable) 771 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask); 772 else 773 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0); 774 } 775 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable); 776 777 /** 778 * snd_hdac_stream_set_spib - sets the spib value of a stream 779 * @bus: HD-audio core bus 780 * @azx_dev: hdac_stream 781 * @value: spib value to set 782 */ 783 int snd_hdac_stream_set_spib(struct hdac_bus *bus, 784 struct hdac_stream *azx_dev, u32 value) 785 { 786 if (!bus->spbcap) { 787 dev_err(bus->dev, "Address of SPB capability is NULL\n"); 788 return -EINVAL; 789 } 790 791 writel(value, azx_dev->spib_addr); 792 793 return 0; 794 } 795 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib); 796 797 /** 798 * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream 799 * @bus: HD-audio core bus 800 * @azx_dev: hdac_stream 801 * 802 * Return maxfifo for the stream 803 */ 804 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus, 805 struct hdac_stream *azx_dev) 806 { 807 if (!bus->spbcap) { 808 dev_err(bus->dev, "Address of SPB capability is NULL\n"); 809 return -EINVAL; 810 } 811 812 return readl(azx_dev->fifo_addr); 813 } 814 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo); 815 816 /** 817 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream 818 * @bus: HD-audio core bus 819 * @enable: flag to enable/disable DRSM 820 * @index: stream index for which DRSM need to be enabled 821 */ 822 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, 823 bool enable, int index) 824 { 825 u32 mask = 0; 826 827 if (!bus->drsmcap) { 828 dev_err(bus->dev, "Address of DRSM capability is NULL\n"); 829 return; 830 } 831 832 mask |= (1 << index); 833 834 if (enable) 835 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask); 836 else 837 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0); 838 } 839 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable); 840 841 /* 842 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream 843 * @azx_dev: HD-audio core stream to await RSM for 844 * 845 * Returns 0 on success and -ETIMEDOUT upon a timeout. 846 */ 847 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev) 848 { 849 struct hdac_bus *bus = azx_dev->bus; 850 u32 mask, reg; 851 int ret; 852 853 mask = 1 << azx_dev->index; 854 855 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus, 856 bus->drsmcap + AZX_REG_DRSM_CTL); 857 if (ret) 858 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret); 859 return ret; 860 } 861 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm); 862 863 /** 864 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream 865 * @bus: HD-audio core bus 866 * @azx_dev: hdac_stream 867 * @value: dpib value to set 868 */ 869 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, 870 struct hdac_stream *azx_dev, u32 value) 871 { 872 if (!bus->drsmcap) { 873 dev_err(bus->dev, "Address of DRSM capability is NULL\n"); 874 return -EINVAL; 875 } 876 877 writel(value, azx_dev->dpibr_addr); 878 879 return 0; 880 } 881 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr); 882 883 /** 884 * snd_hdac_stream_set_lpib - sets the lpib value of a stream 885 * @azx_dev: hdac_stream 886 * @value: lpib value to set 887 */ 888 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value) 889 { 890 snd_hdac_stream_writel(azx_dev, SD_LPIB, value); 891 892 return 0; 893 } 894 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib); 895 896 #ifdef CONFIG_SND_HDA_DSP_LOADER 897 /** 898 * snd_hdac_dsp_prepare - prepare for DSP loading 899 * @azx_dev: HD-audio core stream used for DSP loading 900 * @format: HD-audio stream format 901 * @byte_size: data chunk byte size 902 * @bufp: allocated buffer 903 * 904 * Allocate the buffer for the given size and set up the given stream for 905 * DSP loading. Returns the stream tag (>= 0), or a negative error code. 906 */ 907 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 908 unsigned int byte_size, struct snd_dma_buffer *bufp) 909 { 910 struct hdac_bus *bus = azx_dev->bus; 911 __le32 *bdl; 912 int err; 913 914 snd_hdac_dsp_lock(azx_dev); 915 spin_lock_irq(&bus->reg_lock); 916 if (azx_dev->running || azx_dev->locked) { 917 spin_unlock_irq(&bus->reg_lock); 918 err = -EBUSY; 919 goto unlock; 920 } 921 azx_dev->locked = true; 922 spin_unlock_irq(&bus->reg_lock); 923 924 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev, 925 byte_size, bufp); 926 if (err < 0) 927 goto err_alloc; 928 929 azx_dev->substream = NULL; 930 azx_dev->bufsize = byte_size; 931 azx_dev->period_bytes = byte_size; 932 azx_dev->format_val = format; 933 934 snd_hdac_stream_reset(azx_dev); 935 936 /* reset BDL address */ 937 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 938 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 939 940 azx_dev->frags = 0; 941 bdl = (__le32 *)azx_dev->bdl.area; 942 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0); 943 if (err < 0) 944 goto error; 945 946 snd_hdac_stream_setup(azx_dev); 947 snd_hdac_dsp_unlock(azx_dev); 948 return azx_dev->stream_tag; 949 950 error: 951 snd_dma_free_pages(bufp); 952 err_alloc: 953 spin_lock_irq(&bus->reg_lock); 954 azx_dev->locked = false; 955 spin_unlock_irq(&bus->reg_lock); 956 unlock: 957 snd_hdac_dsp_unlock(azx_dev); 958 return err; 959 } 960 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); 961 962 /** 963 * snd_hdac_dsp_trigger - start / stop DSP loading 964 * @azx_dev: HD-audio core stream used for DSP loading 965 * @start: trigger start or stop 966 */ 967 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) 968 { 969 if (start) 970 snd_hdac_stream_start(azx_dev); 971 else 972 snd_hdac_stream_stop(azx_dev); 973 } 974 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); 975 976 /** 977 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal 978 * @azx_dev: HD-audio core stream used for DSP loading 979 * @dmab: buffer used by DSP loading 980 */ 981 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 982 struct snd_dma_buffer *dmab) 983 { 984 struct hdac_bus *bus = azx_dev->bus; 985 986 if (!dmab->area || !azx_dev->locked) 987 return; 988 989 snd_hdac_dsp_lock(azx_dev); 990 /* reset BDL address */ 991 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 992 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 993 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 994 azx_dev->bufsize = 0; 995 azx_dev->period_bytes = 0; 996 azx_dev->format_val = 0; 997 998 snd_dma_free_pages(dmab); 999 dmab->area = NULL; 1000 1001 spin_lock_irq(&bus->reg_lock); 1002 azx_dev->locked = false; 1003 spin_unlock_irq(&bus->reg_lock); 1004 snd_hdac_dsp_unlock(azx_dev); 1005 } 1006 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); 1007 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 1008