1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HD-audio stream operations 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/export.h> 9 #include <linux/clocksource.h> 10 #include <sound/core.h> 11 #include <sound/pcm.h> 12 #include <sound/hdaudio.h> 13 #include <sound/hda_register.h> 14 #include "trace.h" 15 16 /** 17 * snd_hdac_get_stream_stripe_ctl - get stripe control value 18 * @bus: HD-audio core bus 19 * @substream: PCM substream 20 */ 21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, 22 struct snd_pcm_substream *substream) 23 { 24 struct snd_pcm_runtime *runtime = substream->runtime; 25 unsigned int channels = runtime->channels, 26 rate = runtime->rate, 27 bits_per_sample = runtime->sample_bits, 28 max_sdo_lines, value, sdo_line; 29 30 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */ 31 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO; 32 33 /* following is from HD audio spec */ 34 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) { 35 if (rate > 48000) 36 value = (channels * bits_per_sample * 37 (rate / 48000)) / sdo_line; 38 else 39 value = (channels * bits_per_sample) / sdo_line; 40 41 if (value >= 8) 42 break; 43 } 44 45 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */ 46 return sdo_line >> 1; 47 } 48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl); 49 50 /** 51 * snd_hdac_stream_init - initialize each stream (aka device) 52 * @bus: HD-audio core bus 53 * @azx_dev: HD-audio core stream object to initialize 54 * @idx: stream index number 55 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) 56 * @tag: the tag id to assign 57 * 58 * Assign the starting bdl address to each stream (device) and initialize. 59 */ 60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, 61 int idx, int direction, int tag) 62 { 63 azx_dev->bus = bus; 64 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 65 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); 66 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 67 azx_dev->sd_int_sta_mask = 1 << idx; 68 azx_dev->index = idx; 69 azx_dev->direction = direction; 70 azx_dev->stream_tag = tag; 71 snd_hdac_dsp_lock_init(azx_dev); 72 list_add_tail(&azx_dev->list, &bus->stream_list); 73 } 74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init); 75 76 /** 77 * snd_hdac_stream_start - start a stream 78 * @azx_dev: HD-audio core stream to start 79 * @fresh_start: false = wallclock timestamp relative to period wallclock 80 * 81 * Start a stream, set start_wallclk and set the running flag. 82 */ 83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start) 84 { 85 struct hdac_bus *bus = azx_dev->bus; 86 int stripe_ctl; 87 88 trace_snd_hdac_stream_start(bus, azx_dev); 89 90 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); 91 if (!fresh_start) 92 azx_dev->start_wallclk -= azx_dev->period_wallclk; 93 94 /* enable SIE */ 95 snd_hdac_chip_updatel(bus, INTCTL, 96 1 << azx_dev->index, 97 1 << azx_dev->index); 98 /* set stripe control */ 99 if (azx_dev->substream) 100 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream); 101 else 102 stripe_ctl = 0; 103 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 104 stripe_ctl); 105 /* set DMA start and interrupt mask */ 106 snd_hdac_stream_updateb(azx_dev, SD_CTL, 107 0, SD_CTL_DMA_START | SD_INT_MASK); 108 azx_dev->running = true; 109 } 110 EXPORT_SYMBOL_GPL(snd_hdac_stream_start); 111 112 /** 113 * snd_hdac_stream_clear - stop a stream DMA 114 * @azx_dev: HD-audio core stream to stop 115 */ 116 void snd_hdac_stream_clear(struct hdac_stream *azx_dev) 117 { 118 snd_hdac_stream_updateb(azx_dev, SD_CTL, 119 SD_CTL_DMA_START | SD_INT_MASK, 0); 120 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 121 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); 122 azx_dev->running = false; 123 } 124 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear); 125 126 /** 127 * snd_hdac_stream_stop - stop a stream 128 * @azx_dev: HD-audio core stream to stop 129 * 130 * Stop a stream DMA and disable stream interrupt 131 */ 132 void snd_hdac_stream_stop(struct hdac_stream *azx_dev) 133 { 134 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev); 135 136 snd_hdac_stream_clear(azx_dev); 137 /* disable SIE */ 138 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); 139 } 140 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); 141 142 /** 143 * snd_hdac_stream_reset - reset a stream 144 * @azx_dev: HD-audio core stream to reset 145 */ 146 void snd_hdac_stream_reset(struct hdac_stream *azx_dev) 147 { 148 unsigned char val; 149 int timeout; 150 151 snd_hdac_stream_clear(azx_dev); 152 153 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); 154 udelay(3); 155 timeout = 300; 156 do { 157 val = snd_hdac_stream_readb(azx_dev, SD_CTL) & 158 SD_CTL_STREAM_RESET; 159 if (val) 160 break; 161 } while (--timeout); 162 val &= ~SD_CTL_STREAM_RESET; 163 snd_hdac_stream_writeb(azx_dev, SD_CTL, val); 164 udelay(3); 165 166 timeout = 300; 167 /* waiting for hardware to report that the stream is out of reset */ 168 do { 169 val = snd_hdac_stream_readb(azx_dev, SD_CTL) & 170 SD_CTL_STREAM_RESET; 171 if (!val) 172 break; 173 } while (--timeout); 174 175 /* reset first position - may not be synced with hw at this time */ 176 if (azx_dev->posbuf) 177 *azx_dev->posbuf = 0; 178 } 179 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); 180 181 /** 182 * snd_hdac_stream_setup - set up the SD for streaming 183 * @azx_dev: HD-audio core stream to set up 184 */ 185 int snd_hdac_stream_setup(struct hdac_stream *azx_dev) 186 { 187 struct hdac_bus *bus = azx_dev->bus; 188 struct snd_pcm_runtime *runtime; 189 unsigned int val; 190 191 if (azx_dev->substream) 192 runtime = azx_dev->substream->runtime; 193 else 194 runtime = NULL; 195 /* make sure the run bit is zero for SD */ 196 snd_hdac_stream_clear(azx_dev); 197 /* program the stream_tag */ 198 val = snd_hdac_stream_readl(azx_dev, SD_CTL); 199 val = (val & ~SD_CTL_STREAM_TAG_MASK) | 200 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); 201 if (!bus->snoop) 202 val |= SD_CTL_TRAFFIC_PRIO; 203 snd_hdac_stream_writel(azx_dev, SD_CTL, val); 204 205 /* program the length of samples in cyclic buffer */ 206 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); 207 208 /* program the stream format */ 209 /* this value needs to be the same as the one programmed */ 210 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 211 212 /* program the stream LVI (last valid index) of the BDL */ 213 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 214 215 /* program the BDL address */ 216 /* lower BDL address */ 217 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 218 /* upper BDL address */ 219 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 220 upper_32_bits(azx_dev->bdl.addr)); 221 222 /* enable the position buffer */ 223 if (bus->use_posbuf && bus->posbuf.addr) { 224 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) 225 snd_hdac_chip_writel(bus, DPLBASE, 226 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); 227 } 228 229 /* set the interrupt enable bits in the descriptor control register */ 230 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); 231 232 if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK) 233 azx_dev->fifo_size = 234 snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1; 235 else 236 azx_dev->fifo_size = 0; 237 238 /* when LPIB delay correction gives a small negative value, 239 * we ignore it; currently set the threshold statically to 240 * 64 frames 241 */ 242 if (runtime && runtime->period_size > 64) 243 azx_dev->delay_negative_threshold = 244 -frames_to_bytes(runtime, 64); 245 else 246 azx_dev->delay_negative_threshold = 0; 247 248 /* wallclk has 24Mhz clock source */ 249 if (runtime) 250 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 251 runtime->rate) * 1000); 252 253 return 0; 254 } 255 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); 256 257 /** 258 * snd_hdac_stream_cleanup - cleanup a stream 259 * @azx_dev: HD-audio core stream to clean up 260 */ 261 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) 262 { 263 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 264 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 265 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 266 azx_dev->bufsize = 0; 267 azx_dev->period_bytes = 0; 268 azx_dev->format_val = 0; 269 } 270 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); 271 272 /** 273 * snd_hdac_stream_assign - assign a stream for the PCM 274 * @bus: HD-audio core bus 275 * @substream: PCM substream to assign 276 * 277 * Look for an unused stream for the given PCM substream, assign it 278 * and return the stream object. If no stream is free, returns NULL. 279 * The function tries to keep using the same stream object when it's used 280 * beforehand. Also, when bus->reverse_assign flag is set, the last free 281 * or matching entry is returned. This is needed for some strange codecs. 282 */ 283 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, 284 struct snd_pcm_substream *substream) 285 { 286 struct hdac_stream *azx_dev; 287 struct hdac_stream *res = NULL; 288 289 /* make a non-zero unique key for the substream */ 290 int key = (substream->pcm->device << 16) | (substream->number << 2) | 291 (substream->stream + 1); 292 293 list_for_each_entry(azx_dev, &bus->stream_list, list) { 294 if (azx_dev->direction != substream->stream) 295 continue; 296 if (azx_dev->opened) 297 continue; 298 if (azx_dev->assigned_key == key) { 299 res = azx_dev; 300 break; 301 } 302 if (!res || bus->reverse_assign) 303 res = azx_dev; 304 } 305 if (res) { 306 spin_lock_irq(&bus->reg_lock); 307 res->opened = 1; 308 res->running = 0; 309 res->assigned_key = key; 310 res->substream = substream; 311 spin_unlock_irq(&bus->reg_lock); 312 } 313 return res; 314 } 315 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); 316 317 /** 318 * snd_hdac_stream_release - release the assigned stream 319 * @azx_dev: HD-audio core stream to release 320 * 321 * Release the stream that has been assigned by snd_hdac_stream_assign(). 322 */ 323 void snd_hdac_stream_release(struct hdac_stream *azx_dev) 324 { 325 struct hdac_bus *bus = azx_dev->bus; 326 327 spin_lock_irq(&bus->reg_lock); 328 azx_dev->opened = 0; 329 azx_dev->running = 0; 330 azx_dev->substream = NULL; 331 spin_unlock_irq(&bus->reg_lock); 332 } 333 EXPORT_SYMBOL_GPL(snd_hdac_stream_release); 334 335 /** 336 * snd_hdac_get_stream - return hdac_stream based on stream_tag and 337 * direction 338 * 339 * @bus: HD-audio core bus 340 * @dir: direction for the stream to be found 341 * @stream_tag: stream tag for stream to be found 342 */ 343 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, 344 int dir, int stream_tag) 345 { 346 struct hdac_stream *s; 347 348 list_for_each_entry(s, &bus->stream_list, list) { 349 if (s->direction == dir && s->stream_tag == stream_tag) 350 return s; 351 } 352 353 return NULL; 354 } 355 EXPORT_SYMBOL_GPL(snd_hdac_get_stream); 356 357 /* 358 * set up a BDL entry 359 */ 360 static int setup_bdle(struct hdac_bus *bus, 361 struct snd_dma_buffer *dmab, 362 struct hdac_stream *azx_dev, __le32 **bdlp, 363 int ofs, int size, int with_ioc) 364 { 365 __le32 *bdl = *bdlp; 366 367 while (size > 0) { 368 dma_addr_t addr; 369 int chunk; 370 371 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 372 return -EINVAL; 373 374 addr = snd_sgbuf_get_addr(dmab, ofs); 375 /* program the address field of the BDL entry */ 376 bdl[0] = cpu_to_le32((u32)addr); 377 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 378 /* program the size field of the BDL entry */ 379 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); 380 /* one BDLE cannot cross 4K boundary on CTHDA chips */ 381 if (bus->align_bdle_4k) { 382 u32 remain = 0x1000 - (ofs & 0xfff); 383 384 if (chunk > remain) 385 chunk = remain; 386 } 387 bdl[2] = cpu_to_le32(chunk); 388 /* program the IOC to enable interrupt 389 * only when the whole fragment is processed 390 */ 391 size -= chunk; 392 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 393 bdl += 4; 394 azx_dev->frags++; 395 ofs += chunk; 396 } 397 *bdlp = bdl; 398 return ofs; 399 } 400 401 /** 402 * snd_hdac_stream_setup_periods - set up BDL entries 403 * @azx_dev: HD-audio core stream to set up 404 * 405 * Set up the buffer descriptor table of the given stream based on the 406 * period and buffer sizes of the assigned PCM substream. 407 */ 408 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) 409 { 410 struct hdac_bus *bus = azx_dev->bus; 411 struct snd_pcm_substream *substream = azx_dev->substream; 412 struct snd_pcm_runtime *runtime = substream->runtime; 413 __le32 *bdl; 414 int i, ofs, periods, period_bytes; 415 int pos_adj, pos_align; 416 417 /* reset BDL address */ 418 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 419 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 420 421 period_bytes = azx_dev->period_bytes; 422 periods = azx_dev->bufsize / period_bytes; 423 424 /* program the initial BDL entries */ 425 bdl = (__le32 *)azx_dev->bdl.area; 426 ofs = 0; 427 azx_dev->frags = 0; 428 429 pos_adj = bus->bdl_pos_adj; 430 if (!azx_dev->no_period_wakeup && pos_adj > 0) { 431 pos_align = pos_adj; 432 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 433 if (!pos_adj) 434 pos_adj = pos_align; 435 else 436 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 437 pos_align; 438 pos_adj = frames_to_bytes(runtime, pos_adj); 439 if (pos_adj >= period_bytes) { 440 dev_warn(bus->dev, "Too big adjustment %d\n", 441 pos_adj); 442 pos_adj = 0; 443 } else { 444 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), 445 azx_dev, 446 &bdl, ofs, pos_adj, true); 447 if (ofs < 0) 448 goto error; 449 } 450 } else 451 pos_adj = 0; 452 453 for (i = 0; i < periods; i++) { 454 if (i == periods - 1 && pos_adj) 455 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), 456 azx_dev, &bdl, ofs, 457 period_bytes - pos_adj, 0); 458 else 459 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream), 460 azx_dev, &bdl, ofs, 461 period_bytes, 462 !azx_dev->no_period_wakeup); 463 if (ofs < 0) 464 goto error; 465 } 466 return 0; 467 468 error: 469 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", 470 azx_dev->bufsize, period_bytes); 471 return -EINVAL; 472 } 473 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); 474 475 /** 476 * snd_hdac_stream_set_params - set stream parameters 477 * @azx_dev: HD-audio core stream for which parameters are to be set 478 * @format_val: format value parameter 479 * 480 * Setup the HD-audio core stream parameters from substream of the stream 481 * and passed format value 482 */ 483 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, 484 unsigned int format_val) 485 { 486 487 unsigned int bufsize, period_bytes; 488 struct snd_pcm_substream *substream = azx_dev->substream; 489 struct snd_pcm_runtime *runtime; 490 int err; 491 492 if (!substream) 493 return -EINVAL; 494 runtime = substream->runtime; 495 bufsize = snd_pcm_lib_buffer_bytes(substream); 496 period_bytes = snd_pcm_lib_period_bytes(substream); 497 498 if (bufsize != azx_dev->bufsize || 499 period_bytes != azx_dev->period_bytes || 500 format_val != azx_dev->format_val || 501 runtime->no_period_wakeup != azx_dev->no_period_wakeup) { 502 azx_dev->bufsize = bufsize; 503 azx_dev->period_bytes = period_bytes; 504 azx_dev->format_val = format_val; 505 azx_dev->no_period_wakeup = runtime->no_period_wakeup; 506 err = snd_hdac_stream_setup_periods(azx_dev); 507 if (err < 0) 508 return err; 509 } 510 return 0; 511 } 512 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); 513 514 static u64 azx_cc_read(const struct cyclecounter *cc) 515 { 516 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); 517 518 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); 519 } 520 521 static void azx_timecounter_init(struct hdac_stream *azx_dev, 522 bool force, u64 last) 523 { 524 struct timecounter *tc = &azx_dev->tc; 525 struct cyclecounter *cc = &azx_dev->cc; 526 u64 nsec; 527 528 cc->read = azx_cc_read; 529 cc->mask = CLOCKSOURCE_MASK(32); 530 531 /* 532 * Converting from 24 MHz to ns means applying a 125/3 factor. 533 * To avoid any saturation issues in intermediate operations, 534 * the 125 factor is applied first. The division is applied 535 * last after reading the timecounter value. 536 * Applying the 1/3 factor as part of the multiplication 537 * requires at least 20 bits for a decent precision, however 538 * overflows occur after about 4 hours or less, not a option. 539 */ 540 541 cc->mult = 125; /* saturation after 195 years */ 542 cc->shift = 0; 543 544 nsec = 0; /* audio time is elapsed time since trigger */ 545 timecounter_init(tc, cc, nsec); 546 if (force) { 547 /* 548 * force timecounter to use predefined value, 549 * used for synchronized starts 550 */ 551 tc->cycle_last = last; 552 } 553 } 554 555 /** 556 * snd_hdac_stream_timecounter_init - initialize time counter 557 * @azx_dev: HD-audio core stream (master stream) 558 * @streams: bit flags of streams to set up 559 * 560 * Initializes the time counter of streams marked by the bit flags (each 561 * bit corresponds to the stream index). 562 * The trigger timestamp of PCM substream assigned to the given stream is 563 * updated accordingly, too. 564 */ 565 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, 566 unsigned int streams) 567 { 568 struct hdac_bus *bus = azx_dev->bus; 569 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; 570 struct hdac_stream *s; 571 bool inited = false; 572 u64 cycle_last = 0; 573 int i = 0; 574 575 list_for_each_entry(s, &bus->stream_list, list) { 576 if (streams & (1 << i)) { 577 azx_timecounter_init(s, inited, cycle_last); 578 if (!inited) { 579 inited = true; 580 cycle_last = s->tc.cycle_last; 581 } 582 } 583 i++; 584 } 585 586 snd_pcm_gettime(runtime, &runtime->trigger_tstamp); 587 runtime->trigger_tstamp_latched = true; 588 } 589 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); 590 591 /** 592 * snd_hdac_stream_sync_trigger - turn on/off stream sync register 593 * @azx_dev: HD-audio core stream (master stream) 594 * @streams: bit flags of streams to sync 595 */ 596 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, 597 unsigned int streams, unsigned int reg) 598 { 599 struct hdac_bus *bus = azx_dev->bus; 600 unsigned int val; 601 602 if (!reg) 603 reg = AZX_REG_SSYNC; 604 val = _snd_hdac_chip_readl(bus, reg); 605 if (set) 606 val |= streams; 607 else 608 val &= ~streams; 609 _snd_hdac_chip_writel(bus, reg, val); 610 } 611 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); 612 613 /** 614 * snd_hdac_stream_sync - sync with start/strop trigger operation 615 * @azx_dev: HD-audio core stream (master stream) 616 * @start: true = start, false = stop 617 * @streams: bit flags of streams to sync 618 * 619 * For @start = true, wait until all FIFOs get ready. 620 * For @start = false, wait until all RUN bits are cleared. 621 */ 622 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, 623 unsigned int streams) 624 { 625 struct hdac_bus *bus = azx_dev->bus; 626 int i, nwait, timeout; 627 struct hdac_stream *s; 628 629 for (timeout = 5000; timeout; timeout--) { 630 nwait = 0; 631 i = 0; 632 list_for_each_entry(s, &bus->stream_list, list) { 633 if (streams & (1 << i)) { 634 if (start) { 635 /* check FIFO gets ready */ 636 if (!(snd_hdac_stream_readb(s, SD_STS) & 637 SD_STS_FIFO_READY)) 638 nwait++; 639 } else { 640 /* check RUN bit is cleared */ 641 if (snd_hdac_stream_readb(s, SD_CTL) & 642 SD_CTL_DMA_START) 643 nwait++; 644 } 645 } 646 i++; 647 } 648 if (!nwait) 649 break; 650 cpu_relax(); 651 } 652 } 653 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); 654 655 #ifdef CONFIG_SND_HDA_DSP_LOADER 656 /** 657 * snd_hdac_dsp_prepare - prepare for DSP loading 658 * @azx_dev: HD-audio core stream used for DSP loading 659 * @format: HD-audio stream format 660 * @byte_size: data chunk byte size 661 * @bufp: allocated buffer 662 * 663 * Allocate the buffer for the given size and set up the given stream for 664 * DSP loading. Returns the stream tag (>= 0), or a negative error code. 665 */ 666 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 667 unsigned int byte_size, struct snd_dma_buffer *bufp) 668 { 669 struct hdac_bus *bus = azx_dev->bus; 670 __le32 *bdl; 671 int err; 672 673 snd_hdac_dsp_lock(azx_dev); 674 spin_lock_irq(&bus->reg_lock); 675 if (azx_dev->running || azx_dev->locked) { 676 spin_unlock_irq(&bus->reg_lock); 677 err = -EBUSY; 678 goto unlock; 679 } 680 azx_dev->locked = true; 681 spin_unlock_irq(&bus->reg_lock); 682 683 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG, 684 byte_size, bufp); 685 if (err < 0) 686 goto err_alloc; 687 688 azx_dev->substream = NULL; 689 azx_dev->bufsize = byte_size; 690 azx_dev->period_bytes = byte_size; 691 azx_dev->format_val = format; 692 693 snd_hdac_stream_reset(azx_dev); 694 695 /* reset BDL address */ 696 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 697 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 698 699 azx_dev->frags = 0; 700 bdl = (__le32 *)azx_dev->bdl.area; 701 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0); 702 if (err < 0) 703 goto error; 704 705 snd_hdac_stream_setup(azx_dev); 706 snd_hdac_dsp_unlock(azx_dev); 707 return azx_dev->stream_tag; 708 709 error: 710 bus->io_ops->dma_free_pages(bus, bufp); 711 err_alloc: 712 spin_lock_irq(&bus->reg_lock); 713 azx_dev->locked = false; 714 spin_unlock_irq(&bus->reg_lock); 715 unlock: 716 snd_hdac_dsp_unlock(azx_dev); 717 return err; 718 } 719 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); 720 721 /** 722 * snd_hdac_dsp_trigger - start / stop DSP loading 723 * @azx_dev: HD-audio core stream used for DSP loading 724 * @start: trigger start or stop 725 */ 726 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) 727 { 728 if (start) 729 snd_hdac_stream_start(azx_dev, true); 730 else 731 snd_hdac_stream_stop(azx_dev); 732 } 733 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); 734 735 /** 736 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal 737 * @azx_dev: HD-audio core stream used for DSP loading 738 * @dmab: buffer used by DSP loading 739 */ 740 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 741 struct snd_dma_buffer *dmab) 742 { 743 struct hdac_bus *bus = azx_dev->bus; 744 745 if (!dmab->area || !azx_dev->locked) 746 return; 747 748 snd_hdac_dsp_lock(azx_dev); 749 /* reset BDL address */ 750 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 751 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 752 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 753 azx_dev->bufsize = 0; 754 azx_dev->period_bytes = 0; 755 azx_dev->format_val = 0; 756 757 bus->io_ops->dma_free_pages(bus, dmab); 758 dmab->area = NULL; 759 760 spin_lock_irq(&bus->reg_lock); 761 azx_dev->locked = false; 762 spin_unlock_irq(&bus->reg_lock); 763 snd_hdac_dsp_unlock(azx_dev); 764 } 765 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); 766 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 767