1 /* 2 * HD-audio controller helpers 3 */ 4 5 #include <linux/kernel.h> 6 #include <linux/delay.h> 7 #include <linux/export.h> 8 #include <sound/core.h> 9 #include <sound/hdaudio.h> 10 #include <sound/hda_register.h> 11 12 /* clear CORB read pointer properly */ 13 static void azx_clear_corbrp(struct hdac_bus *bus) 14 { 15 int timeout; 16 17 for (timeout = 1000; timeout > 0; timeout--) { 18 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST) 19 break; 20 udelay(1); 21 } 22 if (timeout <= 0) 23 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", 24 snd_hdac_chip_readw(bus, CORBRP)); 25 26 snd_hdac_chip_writew(bus, CORBRP, 0); 27 for (timeout = 1000; timeout > 0; timeout--) { 28 if (snd_hdac_chip_readw(bus, CORBRP) == 0) 29 break; 30 udelay(1); 31 } 32 if (timeout <= 0) 33 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", 34 snd_hdac_chip_readw(bus, CORBRP)); 35 } 36 37 /** 38 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers 39 * @bus: HD-audio core bus 40 */ 41 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus) 42 { 43 spin_lock_irq(&bus->reg_lock); 44 /* CORB set up */ 45 bus->corb.addr = bus->rb.addr; 46 bus->corb.buf = (__le32 *)bus->rb.area; 47 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr); 48 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr)); 49 50 /* set the corb size to 256 entries (ULI requires explicitly) */ 51 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02); 52 /* set the corb write pointer to 0 */ 53 snd_hdac_chip_writew(bus, CORBWP, 0); 54 55 /* reset the corb hw read pointer */ 56 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST); 57 if (!bus->corbrp_self_clear) 58 azx_clear_corbrp(bus); 59 60 /* enable corb dma */ 61 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN); 62 63 /* RIRB set up */ 64 bus->rirb.addr = bus->rb.addr + 2048; 65 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048); 66 bus->rirb.wp = bus->rirb.rp = 0; 67 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds)); 68 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr); 69 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr)); 70 71 /* set the rirb size to 256 entries (ULI requires explicitly) */ 72 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02); 73 /* reset the rirb hw write pointer */ 74 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST); 75 /* set N=1, get RIRB response interrupt for new entry */ 76 snd_hdac_chip_writew(bus, RINTCNT, 1); 77 /* enable rirb dma and response irq */ 78 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); 79 spin_unlock_irq(&bus->reg_lock); 80 } 81 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io); 82 83 /* wait for cmd dmas till they are stopped */ 84 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus) 85 { 86 unsigned long timeout; 87 88 timeout = jiffies + msecs_to_jiffies(100); 89 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN) 90 && time_before(jiffies, timeout)) 91 udelay(10); 92 93 timeout = jiffies + msecs_to_jiffies(100); 94 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN) 95 && time_before(jiffies, timeout)) 96 udelay(10); 97 } 98 99 /** 100 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers 101 * @bus: HD-audio core bus 102 */ 103 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus) 104 { 105 spin_lock_irq(&bus->reg_lock); 106 /* disable ringbuffer DMAs */ 107 snd_hdac_chip_writeb(bus, RIRBCTL, 0); 108 snd_hdac_chip_writeb(bus, CORBCTL, 0); 109 spin_unlock_irq(&bus->reg_lock); 110 111 hdac_wait_for_cmd_dmas(bus); 112 113 spin_lock_irq(&bus->reg_lock); 114 /* disable unsolicited responses */ 115 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0); 116 spin_unlock_irq(&bus->reg_lock); 117 } 118 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io); 119 120 static unsigned int azx_command_addr(u32 cmd) 121 { 122 unsigned int addr = cmd >> 28; 123 124 if (snd_BUG_ON(addr >= HDA_MAX_CODECS)) 125 addr = 0; 126 return addr; 127 } 128 129 /** 130 * snd_hdac_bus_send_cmd - send a command verb via CORB 131 * @bus: HD-audio core bus 132 * @val: encoded verb value to send 133 * 134 * Returns zero for success or a negative error code. 135 */ 136 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) 137 { 138 unsigned int addr = azx_command_addr(val); 139 unsigned int wp, rp; 140 141 spin_lock_irq(&bus->reg_lock); 142 143 bus->last_cmd[azx_command_addr(val)] = val; 144 145 /* add command to corb */ 146 wp = snd_hdac_chip_readw(bus, CORBWP); 147 if (wp == 0xffff) { 148 /* something wrong, controller likely turned to D3 */ 149 spin_unlock_irq(&bus->reg_lock); 150 return -EIO; 151 } 152 wp++; 153 wp %= AZX_MAX_CORB_ENTRIES; 154 155 rp = snd_hdac_chip_readw(bus, CORBRP); 156 if (wp == rp) { 157 /* oops, it's full */ 158 spin_unlock_irq(&bus->reg_lock); 159 return -EAGAIN; 160 } 161 162 bus->rirb.cmds[addr]++; 163 bus->corb.buf[wp] = cpu_to_le32(val); 164 snd_hdac_chip_writew(bus, CORBWP, wp); 165 166 spin_unlock_irq(&bus->reg_lock); 167 168 return 0; 169 } 170 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd); 171 172 #define AZX_RIRB_EX_UNSOL_EV (1<<4) 173 174 /** 175 * snd_hdac_bus_update_rirb - retrieve RIRB entries 176 * @bus: HD-audio core bus 177 * 178 * Usually called from interrupt handler. 179 */ 180 void snd_hdac_bus_update_rirb(struct hdac_bus *bus) 181 { 182 unsigned int rp, wp; 183 unsigned int addr; 184 u32 res, res_ex; 185 186 wp = snd_hdac_chip_readw(bus, RIRBWP); 187 if (wp == 0xffff) { 188 /* something wrong, controller likely turned to D3 */ 189 return; 190 } 191 192 if (wp == bus->rirb.wp) 193 return; 194 bus->rirb.wp = wp; 195 196 while (bus->rirb.rp != wp) { 197 bus->rirb.rp++; 198 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES; 199 200 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 201 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]); 202 res = le32_to_cpu(bus->rirb.buf[rp]); 203 addr = res_ex & 0xf; 204 if (addr >= HDA_MAX_CODECS) { 205 dev_err(bus->dev, 206 "spurious response %#x:%#x, rp = %d, wp = %d", 207 res, res_ex, bus->rirb.rp, wp); 208 snd_BUG(); 209 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV) 210 snd_hdac_bus_queue_event(bus, res, res_ex); 211 else if (bus->rirb.cmds[addr]) { 212 bus->rirb.res[addr] = res; 213 bus->rirb.cmds[addr]--; 214 } else { 215 dev_err_ratelimited(bus->dev, 216 "spurious response %#x:%#x, last cmd=%#08x\n", 217 res, res_ex, bus->last_cmd[addr]); 218 } 219 } 220 } 221 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb); 222 223 /** 224 * snd_hdac_bus_get_response - receive a response via RIRB 225 * @bus: HD-audio core bus 226 * @addr: codec address 227 * @res: pointer to store the value, NULL when not needed 228 * 229 * Returns zero if a value is read, or a negative error code. 230 */ 231 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, 232 unsigned int *res) 233 { 234 unsigned long timeout; 235 unsigned long loopcounter; 236 237 timeout = jiffies + msecs_to_jiffies(1000); 238 239 for (loopcounter = 0;; loopcounter++) { 240 spin_lock_irq(&bus->reg_lock); 241 if (!bus->rirb.cmds[addr]) { 242 if (res) 243 *res = bus->rirb.res[addr]; /* the last value */ 244 spin_unlock_irq(&bus->reg_lock); 245 return 0; 246 } 247 spin_unlock_irq(&bus->reg_lock); 248 if (time_after(jiffies, timeout)) 249 break; 250 if (loopcounter > 3000) 251 msleep(2); /* temporary workaround */ 252 else { 253 udelay(10); 254 cond_resched(); 255 } 256 } 257 258 return -EIO; 259 } 260 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response); 261 262 #define HDAC_MAX_CAPS 10 263 /** 264 * snd_hdac_bus_parse_capabilities - parse capability structure 265 * @bus: the pointer to bus object 266 * 267 * Returns 0 if successful, or a negative error code. 268 */ 269 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus) 270 { 271 unsigned int cur_cap; 272 unsigned int offset; 273 unsigned int counter = 0; 274 275 offset = snd_hdac_chip_readw(bus, LLCH); 276 277 /* Lets walk the linked capabilities list */ 278 do { 279 cur_cap = _snd_hdac_chip_readl(bus, offset); 280 281 dev_dbg(bus->dev, "Capability version: 0x%x\n", 282 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF); 283 284 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n", 285 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF); 286 287 if (cur_cap == -1) { 288 dev_dbg(bus->dev, "Invalid capability reg read\n"); 289 break; 290 } 291 292 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) { 293 case AZX_ML_CAP_ID: 294 dev_dbg(bus->dev, "Found ML capability\n"); 295 bus->mlcap = bus->remap_addr + offset; 296 break; 297 298 case AZX_GTS_CAP_ID: 299 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset); 300 bus->gtscap = bus->remap_addr + offset; 301 break; 302 303 case AZX_PP_CAP_ID: 304 /* PP capability found, the Audio DSP is present */ 305 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset); 306 bus->ppcap = bus->remap_addr + offset; 307 break; 308 309 case AZX_SPB_CAP_ID: 310 /* SPIB capability found, handler function */ 311 dev_dbg(bus->dev, "Found SPB capability\n"); 312 bus->spbcap = bus->remap_addr + offset; 313 break; 314 315 case AZX_DRSM_CAP_ID: 316 /* DMA resume capability found, handler function */ 317 dev_dbg(bus->dev, "Found DRSM capability\n"); 318 bus->drsmcap = bus->remap_addr + offset; 319 break; 320 321 default: 322 dev_err(bus->dev, "Unknown capability %d\n", cur_cap); 323 cur_cap = 0; 324 break; 325 } 326 327 counter++; 328 329 if (counter > HDAC_MAX_CAPS) { 330 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n"); 331 break; 332 } 333 334 /* read the offset of next capability */ 335 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK; 336 337 } while (offset); 338 339 return 0; 340 } 341 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities); 342 343 /* 344 * Lowlevel interface 345 */ 346 347 /** 348 * snd_hdac_bus_enter_link_reset - enter link reset 349 * @bus: HD-audio core bus 350 * 351 * Enter to the link reset state. 352 */ 353 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus) 354 { 355 unsigned long timeout; 356 357 /* reset controller */ 358 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0); 359 360 timeout = jiffies + msecs_to_jiffies(100); 361 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) && 362 time_before(jiffies, timeout)) 363 usleep_range(500, 1000); 364 } 365 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset); 366 367 /** 368 * snd_hdac_bus_exit_link_reset - exit link reset 369 * @bus: HD-audio core bus 370 * 371 * Exit from the link reset state. 372 */ 373 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus) 374 { 375 unsigned long timeout; 376 377 snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET); 378 379 timeout = jiffies + msecs_to_jiffies(100); 380 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout)) 381 usleep_range(500, 1000); 382 } 383 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset); 384 385 /* reset codec link */ 386 static int azx_reset(struct hdac_bus *bus, bool full_reset) 387 { 388 if (!full_reset) 389 goto skip_reset; 390 391 /* clear STATESTS */ 392 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); 393 394 /* reset controller */ 395 snd_hdac_bus_enter_link_reset(bus); 396 397 /* delay for >= 100us for codec PLL to settle per spec 398 * Rev 0.9 section 5.5.1 399 */ 400 usleep_range(500, 1000); 401 402 /* Bring controller out of reset */ 403 snd_hdac_bus_exit_link_reset(bus); 404 405 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 406 usleep_range(1000, 1200); 407 408 skip_reset: 409 /* check to see if controller is ready */ 410 if (!snd_hdac_chip_readb(bus, GCTL)) { 411 dev_dbg(bus->dev, "azx_reset: controller not ready!\n"); 412 return -EBUSY; 413 } 414 415 /* Accept unsolicited responses */ 416 snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL); 417 418 /* detect codecs */ 419 if (!bus->codec_mask) { 420 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS); 421 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask); 422 } 423 424 return 0; 425 } 426 427 /* enable interrupts */ 428 static void azx_int_enable(struct hdac_bus *bus) 429 { 430 /* enable controller CIE and GIE */ 431 snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN); 432 } 433 434 /* disable interrupts */ 435 static void azx_int_disable(struct hdac_bus *bus) 436 { 437 struct hdac_stream *azx_dev; 438 439 /* disable interrupts in stream descriptor */ 440 list_for_each_entry(azx_dev, &bus->stream_list, list) 441 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0); 442 443 /* disable SIE for all streams */ 444 snd_hdac_chip_writeb(bus, INTCTL, 0); 445 446 /* disable controller CIE and GIE */ 447 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0); 448 } 449 450 /* clear interrupts */ 451 static void azx_int_clear(struct hdac_bus *bus) 452 { 453 struct hdac_stream *azx_dev; 454 455 /* clear stream status */ 456 list_for_each_entry(azx_dev, &bus->stream_list, list) 457 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); 458 459 /* clear STATESTS */ 460 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); 461 462 /* clear rirb status */ 463 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 464 465 /* clear int status */ 466 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM); 467 } 468 469 /** 470 * snd_hdac_bus_init_chip - reset and start the controller registers 471 * @bus: HD-audio core bus 472 * @full_reset: Do full reset 473 */ 474 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset) 475 { 476 if (bus->chip_init) 477 return false; 478 479 /* reset controller */ 480 azx_reset(bus, full_reset); 481 482 /* initialize interrupts */ 483 azx_int_clear(bus); 484 azx_int_enable(bus); 485 486 /* initialize the codec command I/O */ 487 snd_hdac_bus_init_cmd_io(bus); 488 489 /* program the position buffer */ 490 if (bus->use_posbuf && bus->posbuf.addr) { 491 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr); 492 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr)); 493 } 494 495 bus->chip_init = true; 496 return true; 497 } 498 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip); 499 500 /** 501 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os 502 * @bus: HD-audio core bus 503 */ 504 void snd_hdac_bus_stop_chip(struct hdac_bus *bus) 505 { 506 if (!bus->chip_init) 507 return; 508 509 /* disable interrupts */ 510 azx_int_disable(bus); 511 azx_int_clear(bus); 512 513 /* disable CORB/RIRB */ 514 snd_hdac_bus_stop_cmd_io(bus); 515 516 /* disable position buffer */ 517 if (bus->posbuf.addr) { 518 snd_hdac_chip_writel(bus, DPLBASE, 0); 519 snd_hdac_chip_writel(bus, DPUBASE, 0); 520 } 521 522 bus->chip_init = false; 523 } 524 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip); 525 526 /** 527 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams 528 * @bus: HD-audio core bus 529 * @status: INTSTS register value 530 * @ask: callback to be called for woken streams 531 * 532 * Returns the bits of handled streams, or zero if no stream is handled. 533 */ 534 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, 535 void (*ack)(struct hdac_bus *, 536 struct hdac_stream *)) 537 { 538 struct hdac_stream *azx_dev; 539 u8 sd_status; 540 int handled = 0; 541 542 list_for_each_entry(azx_dev, &bus->stream_list, list) { 543 if (status & azx_dev->sd_int_sta_mask) { 544 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS); 545 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); 546 handled |= 1 << azx_dev->index; 547 if (!azx_dev->substream || !azx_dev->running || 548 !(sd_status & SD_INT_COMPLETE)) 549 continue; 550 if (ack) 551 ack(bus, azx_dev); 552 } 553 } 554 return handled; 555 } 556 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq); 557 558 /** 559 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers 560 * @bus: HD-audio core bus 561 * 562 * Call this after assigning the all streams. 563 * Returns zero for success, or a negative error code. 564 */ 565 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus) 566 { 567 struct hdac_stream *s; 568 int num_streams = 0; 569 int err; 570 571 list_for_each_entry(s, &bus->stream_list, list) { 572 /* allocate memory for the BDL for each stream */ 573 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, 574 BDL_SIZE, &s->bdl); 575 num_streams++; 576 if (err < 0) 577 return -ENOMEM; 578 } 579 580 if (WARN_ON(!num_streams)) 581 return -EINVAL; 582 /* allocate memory for the position buffer */ 583 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, 584 num_streams * 8, &bus->posbuf); 585 if (err < 0) 586 return -ENOMEM; 587 list_for_each_entry(s, &bus->stream_list, list) 588 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8); 589 590 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 591 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, 592 PAGE_SIZE, &bus->rb); 593 } 594 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages); 595 596 /** 597 * snd_hdac_bus_free_stream_pages - release BDL and other buffers 598 * @bus: HD-audio core bus 599 */ 600 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus) 601 { 602 struct hdac_stream *s; 603 604 list_for_each_entry(s, &bus->stream_list, list) { 605 if (s->bdl.area) 606 bus->io_ops->dma_free_pages(bus, &s->bdl); 607 } 608 609 if (bus->rb.area) 610 bus->io_ops->dma_free_pages(bus, &bus->rb); 611 if (bus->posbuf.area) 612 bus->io_ops->dma_free_pages(bus, &bus->posbuf); 613 } 614 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages); 615