1 /*
2  *  hdac-ext-controller.c - HD-audio extended controller functions.
3  *
4  *  Copyright (C) 2014-2015 Intel Corp
5  *  Author: Jeeja KP <jeeja.kp@intel.com>
6  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7  *
8  *  This program is free software; you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation; version 2 of the License.
11  *
12  *  This program is distributed in the hope that it will be useful, but
13  *  WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  *  General Public License for more details.
16  *
17  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18  */
19 
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <sound/hda_register.h>
23 #include <sound/hdaudio_ext.h>
24 
25 /*
26  * maximum HDAC capablities we should parse to avoid endless looping:
27  * currently we have 4 extended caps, so this is future proof for now.
28  * extend when this limit is seen meeting in real HW
29  */
30 #define HDAC_MAX_CAPS 10
31 
32 /**
33  * snd_hdac_ext_bus_parse_capabilities - parse capablity structure
34  * @ebus: the pointer to extended bus object
35  *
36  * Returns 0 if successful, or a negative error code.
37  */
38 int snd_hdac_ext_bus_parse_capabilities(struct hdac_ext_bus *ebus)
39 {
40 	unsigned int cur_cap;
41 	unsigned int offset;
42 	struct hdac_bus *bus = &ebus->bus;
43 	unsigned int counter = 0;
44 
45 	offset = snd_hdac_chip_readl(bus, LLCH);
46 
47 	/* Lets walk the linked capabilities list */
48 	do {
49 		cur_cap = _snd_hdac_chip_read(l, bus, offset);
50 
51 		dev_dbg(bus->dev, "Capability version: 0x%x\n",
52 				((cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF));
53 
54 		dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
55 				(cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
56 
57 		switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
58 		case AZX_ML_CAP_ID:
59 			dev_dbg(bus->dev, "Found ML capability\n");
60 			ebus->mlcap = bus->remap_addr + offset;
61 			break;
62 
63 		case AZX_GTS_CAP_ID:
64 			dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
65 			ebus->gtscap = bus->remap_addr + offset;
66 			break;
67 
68 		case AZX_PP_CAP_ID:
69 			/* PP capability found, the Audio DSP is present */
70 			dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
71 			ebus->ppcap = bus->remap_addr + offset;
72 			break;
73 
74 		case AZX_SPB_CAP_ID:
75 			/* SPIB capability found, handler function */
76 			dev_dbg(bus->dev, "Found SPB capability\n");
77 			ebus->spbcap = bus->remap_addr + offset;
78 			break;
79 
80 		case AZX_DRSM_CAP_ID:
81 			/* DMA resume  capability found, handler function */
82 			dev_dbg(bus->dev, "Found DRSM capability\n");
83 			ebus->drsmcap = bus->remap_addr + offset;
84 			break;
85 
86 		default:
87 			dev_dbg(bus->dev, "Unknown capability %d\n", cur_cap);
88 			break;
89 		}
90 
91 		counter++;
92 
93 		if (counter > HDAC_MAX_CAPS) {
94 			dev_err(bus->dev, "We exceeded HDAC Ext capablities!!!\n");
95 			break;
96 		}
97 
98 		/* read the offset of next capabiity */
99 		offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
100 
101 	} while (offset);
102 
103 	return 0;
104 }
105 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_parse_capabilities);
106 
107 /*
108  * processing pipe helpers - these helpers are useful for dealing with HDA
109  * new capability of processing pipelines
110  */
111 
112 /**
113  * snd_hdac_ext_bus_ppcap_enable - enable/disable processing pipe capability
114  * @ebus: HD-audio extended core bus
115  * @enable: flag to turn on/off the capability
116  */
117 void snd_hdac_ext_bus_ppcap_enable(struct hdac_ext_bus *ebus, bool enable)
118 {
119 	struct hdac_bus *bus = &ebus->bus;
120 
121 	if (!ebus->ppcap) {
122 		dev_err(bus->dev, "Address of PP capability is NULL");
123 		return;
124 	}
125 
126 	if (enable)
127 		snd_hdac_updatel(ebus->ppcap, AZX_REG_PP_PPCTL, 0, AZX_PPCTL_GPROCEN);
128 	else
129 		snd_hdac_updatel(ebus->ppcap, AZX_REG_PP_PPCTL, AZX_PPCTL_GPROCEN, 0);
130 }
131 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_ppcap_enable);
132 
133 /**
134  * snd_hdac_ext_bus_ppcap_int_enable - ppcap interrupt enable/disable
135  * @ebus: HD-audio extended core bus
136  * @enable: flag to enable/disable interrupt
137  */
138 void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_ext_bus *ebus, bool enable)
139 {
140 	struct hdac_bus *bus = &ebus->bus;
141 
142 	if (!ebus->ppcap) {
143 		dev_err(bus->dev, "Address of PP capability is NULL\n");
144 		return;
145 	}
146 
147 	if (enable)
148 		snd_hdac_updatel(ebus->ppcap, AZX_REG_PP_PPCTL, 0, AZX_PPCTL_PIE);
149 	else
150 		snd_hdac_updatel(ebus->ppcap, AZX_REG_PP_PPCTL, AZX_PPCTL_PIE, 0);
151 }
152 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_ppcap_int_enable);
153 
154 /*
155  * Multilink helpers - these helpers are useful for dealing with HDA
156  * new multilink capability
157  */
158 
159 /**
160  * snd_hdac_ext_bus_get_ml_capabilities - get multilink capability
161  * @ebus: HD-audio extended core bus
162  *
163  * This will parse all links and read the mlink capabilities and add them
164  * in hlink_list of extended hdac bus
165  * Note: this will be freed on bus exit by driver
166  */
167 int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_ext_bus *ebus)
168 {
169 	int idx;
170 	u32 link_count;
171 	struct hdac_ext_link *hlink;
172 	struct hdac_bus *bus = &ebus->bus;
173 
174 	link_count = readl(ebus->mlcap + AZX_REG_ML_MLCD) + 1;
175 
176 	dev_dbg(bus->dev, "In %s Link count: %d\n", __func__, link_count);
177 
178 	for (idx = 0; idx < link_count; idx++) {
179 		hlink  = kzalloc(sizeof(*hlink), GFP_KERNEL);
180 		if (!hlink)
181 			return -ENOMEM;
182 		hlink->index = idx;
183 		hlink->bus = bus;
184 		hlink->ml_addr = ebus->mlcap + AZX_ML_BASE +
185 					(AZX_ML_INTERVAL * idx);
186 		hlink->lcaps  = readl(hlink->ml_addr + AZX_REG_ML_LCAP);
187 		hlink->lsdiid = readw(hlink->ml_addr + AZX_REG_ML_LSDIID);
188 
189 		/* since link in On, update the ref */
190 		hlink->ref_count = 1;
191 
192 		list_add_tail(&hlink->list, &ebus->hlink_list);
193 	}
194 
195 	return 0;
196 }
197 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_get_ml_capabilities);
198 
199 /**
200  * snd_hdac_link_free_all- free hdac extended link objects
201  *
202  * @ebus: HD-audio ext core bus
203  */
204 
205 void snd_hdac_link_free_all(struct hdac_ext_bus *ebus)
206 {
207 	struct hdac_ext_link *l;
208 
209 	while (!list_empty(&ebus->hlink_list)) {
210 		l = list_first_entry(&ebus->hlink_list, struct hdac_ext_link, list);
211 		list_del(&l->list);
212 		kfree(l);
213 	}
214 }
215 EXPORT_SYMBOL_GPL(snd_hdac_link_free_all);
216 
217 /**
218  * snd_hdac_ext_bus_get_link_index - get link based on codec name
219  * @ebus: HD-audio extended core bus
220  * @codec_name: codec name
221  */
222 struct hdac_ext_link *snd_hdac_ext_bus_get_link(struct hdac_ext_bus *ebus,
223 						 const char *codec_name)
224 {
225 	int i;
226 	struct hdac_ext_link *hlink = NULL;
227 	int bus_idx, addr;
228 
229 	if (sscanf(codec_name, "ehdaudio%dD%d", &bus_idx, &addr) != 2)
230 		return NULL;
231 	if (ebus->idx != bus_idx)
232 		return NULL;
233 
234 	list_for_each_entry(hlink, &ebus->hlink_list, list) {
235 		for (i = 0; i < HDA_MAX_CODECS; i++) {
236 			if (hlink->lsdiid & (0x1 << addr))
237 				return hlink;
238 		}
239 	}
240 
241 	return NULL;
242 }
243 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_get_link);
244 
245 static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
246 {
247 	int timeout;
248 	u32 val;
249 	int mask = (1 << AZX_MLCTL_CPA);
250 
251 	udelay(3);
252 	timeout = 150;
253 
254 	do {
255 		val = readl(link->ml_addr + AZX_REG_ML_LCTL);
256 		if (enable) {
257 			if (((val & mask) >> AZX_MLCTL_CPA))
258 				return 0;
259 		} else {
260 			if (!((val & mask) >> AZX_MLCTL_CPA))
261 				return 0;
262 		}
263 		udelay(3);
264 	} while (--timeout);
265 
266 	return -EIO;
267 }
268 
269 /**
270  * snd_hdac_ext_bus_link_power_up -power up hda link
271  * @link: HD-audio extended link
272  */
273 int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *link)
274 {
275 	snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL, 0, AZX_MLCTL_SPA);
276 
277 	return check_hdac_link_power_active(link, true);
278 }
279 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_up);
280 
281 /**
282  * snd_hdac_ext_bus_link_power_down -power down hda link
283  * @link: HD-audio extended link
284  */
285 int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *link)
286 {
287 	snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL, AZX_MLCTL_SPA, 0);
288 
289 	return check_hdac_link_power_active(link, false);
290 }
291 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_down);
292 
293 /**
294  * snd_hdac_ext_bus_link_power_up_all -power up all hda link
295  * @ebus: HD-audio extended bus
296  */
297 int snd_hdac_ext_bus_link_power_up_all(struct hdac_ext_bus *ebus)
298 {
299 	struct hdac_ext_link *hlink = NULL;
300 	int ret;
301 
302 	list_for_each_entry(hlink, &ebus->hlink_list, list) {
303 		snd_hdac_updatel(hlink->ml_addr,
304 				AZX_REG_ML_LCTL, 0, AZX_MLCTL_SPA);
305 		ret = check_hdac_link_power_active(hlink, true);
306 		if (ret < 0)
307 			return ret;
308 	}
309 
310 	return 0;
311 }
312 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_up_all);
313 
314 /**
315  * snd_hdac_ext_bus_link_power_down_all -power down all hda link
316  * @ebus: HD-audio extended bus
317  */
318 int snd_hdac_ext_bus_link_power_down_all(struct hdac_ext_bus *ebus)
319 {
320 	struct hdac_ext_link *hlink = NULL;
321 	int ret;
322 
323 	list_for_each_entry(hlink, &ebus->hlink_list, list) {
324 		snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL, AZX_MLCTL_SPA, 0);
325 		ret = check_hdac_link_power_active(hlink, false);
326 		if (ret < 0)
327 			return ret;
328 	}
329 
330 	return 0;
331 }
332 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_down_all);
333 
334 int snd_hdac_ext_bus_link_get(struct hdac_ext_bus *ebus,
335 				struct hdac_ext_link *link)
336 {
337 	int ret = 0;
338 
339 	mutex_lock(&ebus->lock);
340 
341 	/*
342 	 * if we move from 0 to 1, count will be 1 so power up this link
343 	 * as well, also check the dma status and trigger that
344 	 */
345 	if (++link->ref_count == 1) {
346 		if (!ebus->cmd_dma_state) {
347 			snd_hdac_bus_init_cmd_io(&ebus->bus);
348 			ebus->cmd_dma_state = true;
349 		}
350 
351 		ret = snd_hdac_ext_bus_link_power_up(link);
352 	}
353 
354 	mutex_unlock(&ebus->lock);
355 	return ret;
356 }
357 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_get);
358 
359 int snd_hdac_ext_bus_link_put(struct hdac_ext_bus *ebus,
360 				struct hdac_ext_link *link)
361 {
362 	int ret = 0;
363 	struct hdac_ext_link *hlink;
364 	bool link_up = false;
365 
366 	mutex_lock(&ebus->lock);
367 
368 	/*
369 	 * if we move from 1 to 0, count will be 0
370 	 * so power down this link as well
371 	 */
372 	if (--link->ref_count == 0) {
373 		ret = snd_hdac_ext_bus_link_power_down(link);
374 
375 		/*
376 		 * now check if all links are off, if so turn off
377 		 * cmd dma as well
378 		 */
379 		list_for_each_entry(hlink, &ebus->hlink_list, list) {
380 			if (hlink->ref_count) {
381 				link_up = true;
382 				break;
383 			}
384 		}
385 
386 		if (!link_up) {
387 			snd_hdac_bus_stop_cmd_io(&ebus->bus);
388 			ebus->cmd_dma_state = false;
389 		}
390 	}
391 
392 	mutex_unlock(&ebus->lock);
393 	return ret;
394 }
395 EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_put);
396