1 /* 2 * motu-protocol-v3.c - a part of driver for MOTU FireWire series 3 * 4 * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp> 5 * 6 * Licensed under the terms of the GNU General Public License, version 2. 7 */ 8 9 #include <linux/delay.h> 10 #include "motu.h" 11 12 #define V3_CLOCK_STATUS_OFFSET 0x0b14 13 #define V3_FETCH_PCM_FRAMES 0x02000000 14 #define V3_CLOCK_RATE_MASK 0x0000ff00 15 #define V3_CLOCK_RATE_SHIFT 8 16 #define V3_CLOCK_SOURCE_MASK 0x000000ff 17 #define V3_CLOCK_SOURCE_SHIFT 8 18 19 #define V3_OPT_IFACE_MODE_OFFSET 0x0c94 20 #define V3_ENABLE_OPT_IN_IFACE_A 0x00000001 21 #define V3_ENABLE_OPT_IN_IFACE_B 0x00000002 22 #define V3_ENABLE_OPT_OUT_IFACE_A 0x00000100 23 #define V3_ENABLE_OPT_OUT_IFACE_B 0x00000200 24 #define V3_NO_ADAT_OPT_IN_IFACE_A 0x00010000 25 #define V3_NO_ADAT_OPT_IN_IFACE_B 0x00100000 26 #define V3_NO_ADAT_OPT_OUT_IFACE_A 0x00040000 27 #define V3_NO_ADAT_OPT_OUT_IFACE_B 0x00400000 28 29 static int v3_get_clock_rate(struct snd_motu *motu, unsigned int *rate) 30 { 31 __be32 reg; 32 u32 data; 33 int err; 34 35 err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, 36 sizeof(reg)); 37 if (err < 0) 38 return err; 39 data = be32_to_cpu(reg); 40 41 data = (data & V3_CLOCK_RATE_MASK) >> V3_CLOCK_RATE_SHIFT; 42 if (data >= ARRAY_SIZE(snd_motu_clock_rates)) 43 return -EIO; 44 45 *rate = snd_motu_clock_rates[data]; 46 47 return 0; 48 } 49 50 static int v3_set_clock_rate(struct snd_motu *motu, unsigned int rate) 51 { 52 __be32 reg; 53 u32 data; 54 bool need_to_wait; 55 int i, err; 56 57 for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) { 58 if (snd_motu_clock_rates[i] == rate) 59 break; 60 } 61 if (i == ARRAY_SIZE(snd_motu_clock_rates)) 62 return -EINVAL; 63 64 err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, 65 sizeof(reg)); 66 if (err < 0) 67 return err; 68 data = be32_to_cpu(reg); 69 70 data &= ~(V3_CLOCK_RATE_MASK | V3_FETCH_PCM_FRAMES); 71 data |= i << V3_CLOCK_RATE_SHIFT; 72 73 need_to_wait = data != be32_to_cpu(reg); 74 75 reg = cpu_to_be32(data); 76 err = snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®, 77 sizeof(reg)); 78 if (err < 0) 79 return err; 80 81 if (need_to_wait) { 82 /* Cost expensive. */ 83 if (msleep_interruptible(4000) > 0) 84 return -EINTR; 85 } 86 87 return 0; 88 } 89 90 static int v3_get_clock_source(struct snd_motu *motu, 91 enum snd_motu_clock_source *src) 92 { 93 __be32 reg; 94 u32 data; 95 unsigned int val; 96 int err; 97 98 err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, 99 sizeof(reg)); 100 if (err < 0) 101 return err; 102 data = be32_to_cpu(reg); 103 104 val = (data & V3_CLOCK_SOURCE_MASK) >> V3_CLOCK_SOURCE_SHIFT; 105 if (val == 0x00) { 106 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL; 107 } else if (val == 0x01) { 108 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC; 109 } else if (val == 0x10) { 110 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX; 111 } else if (val == 0x18 || val == 0x19) { 112 err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET, 113 ®, sizeof(reg)); 114 if (err < 0) 115 return err; 116 data = be32_to_cpu(reg); 117 118 if (val == 0x18) { 119 if (data & V3_NO_ADAT_OPT_IN_IFACE_A) 120 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_A; 121 else 122 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_A; 123 } else { 124 if (data & V3_NO_ADAT_OPT_IN_IFACE_B) 125 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_B; 126 else 127 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_B; 128 } 129 } else { 130 *src = SND_MOTU_CLOCK_SOURCE_UNKNOWN; 131 } 132 133 return 0; 134 } 135 136 static int v3_switch_fetching_mode(struct snd_motu *motu, bool enable) 137 { 138 __be32 reg; 139 u32 data; 140 int err; 141 142 err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, 143 sizeof(reg)); 144 if (err < 0) 145 return 0; 146 data = be32_to_cpu(reg); 147 148 if (enable) 149 data |= V3_FETCH_PCM_FRAMES; 150 else 151 data &= ~V3_FETCH_PCM_FRAMES; 152 153 reg = cpu_to_be32(data); 154 return snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®, 155 sizeof(reg)); 156 } 157 158 static void calculate_fixed_part(struct snd_motu_packet_format *formats, 159 enum amdtp_stream_direction dir, 160 enum snd_motu_spec_flags flags, 161 unsigned char analog_ports) 162 { 163 unsigned char pcm_chunks[3] = {0, 0, 0}; 164 165 formats->msg_chunks = 2; 166 167 pcm_chunks[0] = analog_ports; 168 pcm_chunks[1] = analog_ports; 169 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 170 pcm_chunks[2] = analog_ports; 171 172 if (dir == AMDTP_IN_STREAM) { 173 if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) { 174 pcm_chunks[0] += 2; 175 pcm_chunks[1] += 2; 176 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 177 pcm_chunks[2] += 2; 178 } 179 180 if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) { 181 pcm_chunks[0] += 2; 182 pcm_chunks[1] += 2; 183 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 184 pcm_chunks[2] += 2; 185 } 186 187 if (flags & SND_MOTU_SPEC_TX_REVERB_CHUNK) { 188 pcm_chunks[0] += 2; 189 pcm_chunks[1] += 2; 190 } 191 } else { 192 /* 193 * Packets to v2 units transfer main-out-1/2 and phone-out-1/2. 194 */ 195 pcm_chunks[0] += 4; 196 pcm_chunks[1] += 4; 197 } 198 199 /* 200 * At least, packets have two data chunks for S/PDIF on coaxial 201 * interface. 202 */ 203 pcm_chunks[0] += 2; 204 pcm_chunks[1] += 2; 205 206 /* 207 * Fixed part consists of PCM chunks multiple of 4, with msg chunks. As 208 * a result, this part can includes empty data chunks. 209 */ 210 formats->fixed_part_pcm_chunks[0] = round_up(2 + pcm_chunks[0], 4) - 2; 211 formats->fixed_part_pcm_chunks[1] = round_up(2 + pcm_chunks[1], 4) - 2; 212 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 213 formats->fixed_part_pcm_chunks[2] = 214 round_up(2 + pcm_chunks[2], 4) - 2; 215 } 216 217 static void calculate_differed_part(struct snd_motu_packet_format *formats, 218 enum snd_motu_spec_flags flags, u32 data, 219 u32 a_enable_mask, u32 a_no_adat_mask, 220 u32 b_enable_mask, u32 b_no_adat_mask) 221 { 222 unsigned char pcm_chunks[3] = {0, 0, 0}; 223 int i; 224 225 if ((flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) && (data & a_enable_mask)) { 226 if (data & a_no_adat_mask) { 227 /* 228 * Additional two data chunks for S/PDIF on optical 229 * interface A. This includes empty data chunks. 230 */ 231 pcm_chunks[0] += 4; 232 pcm_chunks[1] += 4; 233 } else { 234 /* 235 * Additional data chunks for ADAT on optical interface 236 * A. 237 */ 238 pcm_chunks[0] += 8; 239 pcm_chunks[1] += 4; 240 } 241 } 242 243 if ((flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) && (data & b_enable_mask)) { 244 if (data & b_no_adat_mask) { 245 /* 246 * Additional two data chunks for S/PDIF on optical 247 * interface B. This includes empty data chunks. 248 */ 249 pcm_chunks[0] += 4; 250 pcm_chunks[1] += 4; 251 } else { 252 /* 253 * Additional data chunks for ADAT on optical interface 254 * B. 255 */ 256 pcm_chunks[0] += 8; 257 pcm_chunks[1] += 4; 258 } 259 } 260 261 for (i = 0; i < 3; ++i) { 262 if (pcm_chunks[i] > 0) 263 pcm_chunks[i] = round_up(pcm_chunks[i], 4); 264 265 formats->differed_part_pcm_chunks[i] = pcm_chunks[i]; 266 } 267 } 268 269 static int v3_cache_packet_formats(struct snd_motu *motu) 270 { 271 __be32 reg; 272 u32 data; 273 int err; 274 275 err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET, ®, 276 sizeof(reg)); 277 if (err < 0) 278 return err; 279 data = be32_to_cpu(reg); 280 281 calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM, 282 motu->spec->flags, motu->spec->analog_in_ports); 283 calculate_differed_part(&motu->tx_packet_formats, 284 motu->spec->flags, data, 285 V3_ENABLE_OPT_IN_IFACE_A, V3_NO_ADAT_OPT_IN_IFACE_A, 286 V3_ENABLE_OPT_IN_IFACE_B, V3_NO_ADAT_OPT_IN_IFACE_B); 287 288 calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM, 289 motu->spec->flags, motu->spec->analog_out_ports); 290 calculate_differed_part(&motu->rx_packet_formats, 291 motu->spec->flags, data, 292 V3_ENABLE_OPT_OUT_IFACE_A, V3_NO_ADAT_OPT_OUT_IFACE_A, 293 V3_ENABLE_OPT_OUT_IFACE_B, V3_NO_ADAT_OPT_OUT_IFACE_B); 294 295 motu->tx_packet_formats.midi_flag_offset = 8; 296 motu->tx_packet_formats.midi_byte_offset = 7; 297 motu->tx_packet_formats.pcm_byte_offset = 10; 298 299 motu->rx_packet_formats.midi_flag_offset = 8; 300 motu->rx_packet_formats.midi_byte_offset = 7; 301 motu->rx_packet_formats.pcm_byte_offset = 10; 302 303 return 0; 304 } 305 306 const struct snd_motu_protocol snd_motu_protocol_v3 = { 307 .get_clock_rate = v3_get_clock_rate, 308 .set_clock_rate = v3_set_clock_rate, 309 .get_clock_source = v3_get_clock_source, 310 .switch_fetching_mode = v3_switch_fetching_mode, 311 .cache_packet_formats = v3_cache_packet_formats, 312 }; 313