1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * motu-protocol-v3.c - a part of driver for MOTU FireWire series 4 * 5 * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp> 6 */ 7 8 #include <linux/delay.h> 9 #include "motu.h" 10 11 #define V3_CLOCK_STATUS_OFFSET 0x0b14 12 #define V3_FETCH_PCM_FRAMES 0x02000000 13 #define V3_CLOCK_RATE_MASK 0x0000ff00 14 #define V3_CLOCK_RATE_SHIFT 8 15 #define V3_CLOCK_SOURCE_MASK 0x000000ff 16 17 #define V3_OPT_IFACE_MODE_OFFSET 0x0c94 18 #define V3_ENABLE_OPT_IN_IFACE_A 0x00000001 19 #define V3_ENABLE_OPT_IN_IFACE_B 0x00000002 20 #define V3_ENABLE_OPT_OUT_IFACE_A 0x00000100 21 #define V3_ENABLE_OPT_OUT_IFACE_B 0x00000200 22 #define V3_NO_ADAT_OPT_IN_IFACE_A 0x00010000 23 #define V3_NO_ADAT_OPT_IN_IFACE_B 0x00100000 24 #define V3_NO_ADAT_OPT_OUT_IFACE_A 0x00040000 25 #define V3_NO_ADAT_OPT_OUT_IFACE_B 0x00400000 26 27 int snd_motu_protocol_v3_get_clock_rate(struct snd_motu *motu, 28 unsigned int *rate) 29 { 30 __be32 reg; 31 u32 data; 32 int err; 33 34 err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, 35 sizeof(reg)); 36 if (err < 0) 37 return err; 38 data = be32_to_cpu(reg); 39 40 data = (data & V3_CLOCK_RATE_MASK) >> V3_CLOCK_RATE_SHIFT; 41 if (data >= ARRAY_SIZE(snd_motu_clock_rates)) 42 return -EIO; 43 44 *rate = snd_motu_clock_rates[data]; 45 46 return 0; 47 } 48 49 int snd_motu_protocol_v3_set_clock_rate(struct snd_motu *motu, 50 unsigned int rate) 51 { 52 __be32 reg; 53 u32 data; 54 bool need_to_wait; 55 int i, err; 56 57 for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) { 58 if (snd_motu_clock_rates[i] == rate) 59 break; 60 } 61 if (i == ARRAY_SIZE(snd_motu_clock_rates)) 62 return -EINVAL; 63 64 err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, 65 sizeof(reg)); 66 if (err < 0) 67 return err; 68 data = be32_to_cpu(reg); 69 70 data &= ~(V3_CLOCK_RATE_MASK | V3_FETCH_PCM_FRAMES); 71 data |= i << V3_CLOCK_RATE_SHIFT; 72 73 need_to_wait = data != be32_to_cpu(reg); 74 75 reg = cpu_to_be32(data); 76 err = snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®, 77 sizeof(reg)); 78 if (err < 0) 79 return err; 80 81 if (need_to_wait) { 82 /* Cost expensive. */ 83 if (msleep_interruptible(4000) > 0) 84 return -EINTR; 85 } 86 87 return 0; 88 } 89 90 int snd_motu_protocol_v3_get_clock_source(struct snd_motu *motu, 91 enum snd_motu_clock_source *src) 92 { 93 __be32 reg; 94 u32 data; 95 unsigned int val; 96 int err; 97 98 err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, 99 sizeof(reg)); 100 if (err < 0) 101 return err; 102 data = be32_to_cpu(reg); 103 104 val = data & V3_CLOCK_SOURCE_MASK; 105 if (val == 0x00) { 106 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL; 107 } else if (val == 0x01) { 108 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC; 109 } else if (val == 0x02) { 110 *src = SND_MOTU_CLOCK_SOURCE_SPH; 111 } else if (val == 0x10) { 112 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX; 113 } else if (val == 0x18 || val == 0x19) { 114 err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET, 115 ®, sizeof(reg)); 116 if (err < 0) 117 return err; 118 data = be32_to_cpu(reg); 119 120 if (val == 0x18) { 121 if (data & V3_NO_ADAT_OPT_IN_IFACE_A) 122 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_A; 123 else 124 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_A; 125 } else { 126 if (data & V3_NO_ADAT_OPT_IN_IFACE_B) 127 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_B; 128 else 129 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_B; 130 } 131 } else { 132 *src = SND_MOTU_CLOCK_SOURCE_UNKNOWN; 133 } 134 135 return 0; 136 } 137 138 int snd_motu_protocol_v3_switch_fetching_mode(struct snd_motu *motu, 139 bool enable) 140 { 141 __be32 reg; 142 u32 data; 143 int err; 144 145 err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, 146 sizeof(reg)); 147 if (err < 0) 148 return 0; 149 data = be32_to_cpu(reg); 150 151 if (enable) 152 data |= V3_FETCH_PCM_FRAMES; 153 else 154 data &= ~V3_FETCH_PCM_FRAMES; 155 156 reg = cpu_to_be32(data); 157 return snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®, 158 sizeof(reg)); 159 } 160 161 static void calculate_fixed_part(struct snd_motu_packet_format *formats, 162 enum amdtp_stream_direction dir, 163 enum snd_motu_spec_flags flags, 164 unsigned char analog_ports) 165 { 166 unsigned char pcm_chunks[3] = {0, 0, 0}; 167 168 pcm_chunks[0] = analog_ports; 169 pcm_chunks[1] = analog_ports; 170 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 171 pcm_chunks[2] = analog_ports; 172 173 if (dir == AMDTP_IN_STREAM) { 174 if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) { 175 pcm_chunks[0] += 2; 176 pcm_chunks[1] += 2; 177 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 178 pcm_chunks[2] += 2; 179 } 180 181 if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) { 182 pcm_chunks[0] += 2; 183 pcm_chunks[1] += 2; 184 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 185 pcm_chunks[2] += 2; 186 } 187 188 if (flags & SND_MOTU_SPEC_TX_REVERB_CHUNK) { 189 pcm_chunks[0] += 2; 190 pcm_chunks[1] += 2; 191 } 192 } else { 193 if (flags & SND_MOTU_SPEC_RX_SEPARATED_MAIN) { 194 pcm_chunks[0] += 2; 195 pcm_chunks[1] += 2; 196 } 197 198 // Packets to v3 units include 2 chunks for phone 1/2, except 199 // for 176.4/192.0 kHz. 200 pcm_chunks[0] += 2; 201 pcm_chunks[1] += 2; 202 } 203 204 if (flags & SND_MOTU_SPEC_HAS_AESEBU_IFACE) { 205 pcm_chunks[0] += 2; 206 pcm_chunks[1] += 2; 207 } 208 209 /* 210 * At least, packets have two data chunks for S/PDIF on coaxial 211 * interface. 212 */ 213 pcm_chunks[0] += 2; 214 pcm_chunks[1] += 2; 215 216 /* 217 * Fixed part consists of PCM chunks multiple of 4, with msg chunks. As 218 * a result, this part can includes empty data chunks. 219 */ 220 formats->fixed_part_pcm_chunks[0] = round_up(2 + pcm_chunks[0], 4) - 2; 221 formats->fixed_part_pcm_chunks[1] = round_up(2 + pcm_chunks[1], 4) - 2; 222 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) 223 formats->fixed_part_pcm_chunks[2] = 224 round_up(2 + pcm_chunks[2], 4) - 2; 225 } 226 227 static void calculate_differed_part(struct snd_motu_packet_format *formats, 228 enum snd_motu_spec_flags flags, u32 data, 229 u32 a_enable_mask, u32 a_no_adat_mask, 230 u32 b_enable_mask, u32 b_no_adat_mask) 231 { 232 unsigned char pcm_chunks[3] = {0, 0, 0}; 233 int i; 234 235 if ((flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) && (data & a_enable_mask)) { 236 if (data & a_no_adat_mask) { 237 /* 238 * Additional two data chunks for S/PDIF on optical 239 * interface A. This includes empty data chunks. 240 */ 241 pcm_chunks[0] += 4; 242 pcm_chunks[1] += 4; 243 } else { 244 /* 245 * Additional data chunks for ADAT on optical interface 246 * A. 247 */ 248 pcm_chunks[0] += 8; 249 pcm_chunks[1] += 4; 250 } 251 } 252 253 if ((flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) && (data & b_enable_mask)) { 254 if (data & b_no_adat_mask) { 255 /* 256 * Additional two data chunks for S/PDIF on optical 257 * interface B. This includes empty data chunks. 258 */ 259 pcm_chunks[0] += 4; 260 pcm_chunks[1] += 4; 261 } else { 262 /* 263 * Additional data chunks for ADAT on optical interface 264 * B. 265 */ 266 pcm_chunks[0] += 8; 267 pcm_chunks[1] += 4; 268 } 269 } 270 271 for (i = 0; i < 3; ++i) { 272 if (pcm_chunks[i] > 0) 273 pcm_chunks[i] = round_up(pcm_chunks[i], 4); 274 275 formats->differed_part_pcm_chunks[i] = pcm_chunks[i]; 276 } 277 } 278 279 static int detect_packet_formats_828mk3(struct snd_motu *motu, u32 data) 280 { 281 if (data & V3_ENABLE_OPT_IN_IFACE_A) { 282 if (data & V3_NO_ADAT_OPT_IN_IFACE_A) { 283 motu->tx_packet_formats.pcm_chunks[0] += 4; 284 motu->tx_packet_formats.pcm_chunks[1] += 4; 285 } else { 286 motu->tx_packet_formats.pcm_chunks[0] += 8; 287 motu->tx_packet_formats.pcm_chunks[1] += 4; 288 } 289 } 290 291 if (data & V3_ENABLE_OPT_IN_IFACE_B) { 292 if (data & V3_NO_ADAT_OPT_IN_IFACE_B) { 293 motu->tx_packet_formats.pcm_chunks[0] += 4; 294 motu->tx_packet_formats.pcm_chunks[1] += 4; 295 } else { 296 motu->tx_packet_formats.pcm_chunks[0] += 8; 297 motu->tx_packet_formats.pcm_chunks[1] += 4; 298 } 299 } 300 301 if (data & V3_ENABLE_OPT_OUT_IFACE_A) { 302 if (data & V3_NO_ADAT_OPT_OUT_IFACE_A) { 303 motu->rx_packet_formats.pcm_chunks[0] += 4; 304 motu->rx_packet_formats.pcm_chunks[1] += 4; 305 } else { 306 motu->rx_packet_formats.pcm_chunks[0] += 8; 307 motu->rx_packet_formats.pcm_chunks[1] += 4; 308 } 309 } 310 311 if (data & V3_ENABLE_OPT_OUT_IFACE_B) { 312 if (data & V3_NO_ADAT_OPT_OUT_IFACE_B) { 313 motu->rx_packet_formats.pcm_chunks[0] += 4; 314 motu->rx_packet_formats.pcm_chunks[1] += 4; 315 } else { 316 motu->rx_packet_formats.pcm_chunks[0] += 8; 317 motu->rx_packet_formats.pcm_chunks[1] += 4; 318 } 319 } 320 321 return 0; 322 } 323 324 int snd_motu_protocol_v3_cache_packet_formats(struct snd_motu *motu) 325 { 326 __be32 reg; 327 u32 data; 328 int err; 329 330 motu->tx_packet_formats.pcm_byte_offset = 10; 331 motu->rx_packet_formats.pcm_byte_offset = 10; 332 333 motu->tx_packet_formats.msg_chunks = 2; 334 motu->rx_packet_formats.msg_chunks = 2; 335 336 err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET, ®, 337 sizeof(reg)); 338 if (err < 0) 339 return err; 340 data = be32_to_cpu(reg); 341 342 calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM, 343 motu->spec->flags, motu->spec->analog_in_ports); 344 calculate_differed_part(&motu->tx_packet_formats, 345 motu->spec->flags, data, 346 V3_ENABLE_OPT_IN_IFACE_A, V3_NO_ADAT_OPT_IN_IFACE_A, 347 V3_ENABLE_OPT_IN_IFACE_B, V3_NO_ADAT_OPT_IN_IFACE_B); 348 349 calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM, 350 motu->spec->flags, motu->spec->analog_out_ports); 351 calculate_differed_part(&motu->rx_packet_formats, 352 motu->spec->flags, data, 353 V3_ENABLE_OPT_OUT_IFACE_A, V3_NO_ADAT_OPT_OUT_IFACE_A, 354 V3_ENABLE_OPT_OUT_IFACE_B, V3_NO_ADAT_OPT_OUT_IFACE_B); 355 356 memcpy(motu->tx_packet_formats.pcm_chunks, 357 motu->spec->tx_fixed_pcm_chunks, 358 sizeof(motu->tx_packet_formats.pcm_chunks)); 359 memcpy(motu->rx_packet_formats.pcm_chunks, 360 motu->spec->rx_fixed_pcm_chunks, 361 sizeof(motu->rx_packet_formats.pcm_chunks)); 362 363 if (motu->spec == &snd_motu_spec_828mk3) 364 return detect_packet_formats_828mk3(motu, data); 365 else 366 return 0; 367 } 368 369 370 const struct snd_motu_spec snd_motu_spec_828mk3 = { 371 .name = "828mk3", 372 .protocol_version = SND_MOTU_PROTOCOL_V3, 373 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 374 SND_MOTU_SPEC_SUPPORT_CLOCK_X4 | 375 SND_MOTU_SPEC_TX_MICINST_CHUNK | 376 SND_MOTU_SPEC_TX_RETURN_CHUNK | 377 SND_MOTU_SPEC_TX_REVERB_CHUNK | 378 SND_MOTU_SPEC_RX_SEPARATED_MAIN | 379 SND_MOTU_SPEC_HAS_OPT_IFACE_A | 380 SND_MOTU_SPEC_HAS_OPT_IFACE_B | 381 SND_MOTU_SPEC_RX_MIDI_3RD_Q | 382 SND_MOTU_SPEC_TX_MIDI_3RD_Q, 383 .tx_fixed_pcm_chunks = {18, 18, 14}, 384 .rx_fixed_pcm_chunks = {14, 14, 10}, 385 .analog_in_ports = 8, 386 .analog_out_ports = 8, 387 }; 388 389 const struct snd_motu_spec snd_motu_spec_audio_express = { 390 .name = "AudioExpress", 391 .protocol_version = SND_MOTU_PROTOCOL_V3, 392 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 393 SND_MOTU_SPEC_TX_MICINST_CHUNK | 394 SND_MOTU_SPEC_TX_RETURN_CHUNK | 395 SND_MOTU_SPEC_RX_SEPARATED_MAIN | 396 SND_MOTU_SPEC_RX_MIDI_2ND_Q | 397 SND_MOTU_SPEC_TX_MIDI_3RD_Q, 398 .tx_fixed_pcm_chunks = {10, 10, 0}, 399 .rx_fixed_pcm_chunks = {10, 10, 0}, 400 .analog_in_ports = 2, 401 .analog_out_ports = 4, 402 }; 403 404 const struct snd_motu_spec snd_motu_spec_4pre = { 405 .name = "4pre", 406 .protocol_version = SND_MOTU_PROTOCOL_V3, 407 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 | 408 SND_MOTU_SPEC_TX_MICINST_CHUNK | 409 SND_MOTU_SPEC_TX_RETURN_CHUNK | 410 SND_MOTU_SPEC_RX_SEPARATED_MAIN, 411 .tx_fixed_pcm_chunks = {10, 10, 0}, 412 .rx_fixed_pcm_chunks = {10, 10, 0}, 413 .analog_in_ports = 2, 414 .analog_out_ports = 2, 415 }; 416